1/* $NetBSD: vidc20config.c,v 1.31 2009/03/14 15:36:02 dsl Exp $ */ 2 3/* 4 * Copyright (c) 2001 Reinoud Zandijk 5 * Copyright (c) 1996 Mark Brinicombe 6 * Copyright (c) 1996 Robert Black 7 * Copyright (c) 1994-1995 Melvyn Tang-Richardson 8 * Copyright (c) 1994-1995 RiscBSD kernel team 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the RiscBSD kernel team 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE RISCBSD TEAM ``AS IS'' AND ANY EXPRESS 27 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE 30 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGE. 37 * 38 * NetBSD kernel project 39 * 40 * vidcvideo.c 41 * 42 * This file is the lower basis of the wscons driver for VIDC based ARM machines. 43 * It features the initialisation and all VIDC writing and keeps in internal state 44 * copy. 45 * Its currenly set up as a library file and not as a device; it could be named 46 * vidcvideo0 eventually. 47 */ 48 49#include <sys/cdefs.h> 50 51__KERNEL_RCSID(0, "$NetBSD: vidc20config.c,v 1.31 2009/03/14 15:36:02 dsl Exp $"); 52 53#include <sys/types.h> 54#include <sys/param.h> 55#include <arm/iomd/vidc.h> 56#include <arm/arm32/katelib.h> 57#include <machine/bootconfig.h> 58#include <machine/intr.h> 59 60#include <sys/systm.h> 61#include <sys/device.h> 62#include <uvm/uvm_extern.h> 63 64#include <arm/iomd/iomdreg.h> 65#include <arm/iomd/iomdvar.h> 66#include <arm/iomd/vidc20config.h> 67 68 69/* 70 * A structure containing ALL the information required to restore 71 * the VIDC20 to any given state. ALL vidc transactions should 72 * go through these procedures, which record the vidc's state. 73 * it may be an idea to set the permissions of the vidc base address 74 * so we get a fault, so the fault routine can record the state but 75 * I guess that's not really necessary for the time being, since we 76 * can make the kernel more secure later on. Also, it is possible 77 * to write a routine to allow 'reading' of the vidc registers. 78 */ 79 80static struct vidc_state vidc_lookup = { 81 { 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 82 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 83 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 84 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 85 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 86 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 87 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 88 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0 89 }, 90 91 VIDC_PALREG, 92 VIDC_BCOL, 93 VIDC_CP1 , 94 VIDC_CP2, 95 VIDC_CP3, 96 VIDC_HCR, 97 VIDC_HSWR, 98 VIDC_HBSR, 99 VIDC_HDSR, 100 VIDC_HDER, 101 VIDC_HBER, 102 VIDC_HCSR, 103 VIDC_HIR, 104 VIDC_VCR, 105 VIDC_VSWR, 106 VIDC_VBSR, 107 VIDC_VDSR, 108 VIDC_VDER, 109 VIDC_VBER, 110 VIDC_VCSR, 111 VIDC_VCER, 112 VIDC_EREG, 113 VIDC_FSYNREG, 114 VIDC_CONREG, 115 VIDC_DCTL 116}; 117 118struct vidc_state vidc_current[1]; 119 120 121/* 122 * XXX global display variables XXX ... should be a structure 123 */ 124static int cold_init = 0; /* flags initialisation */ 125extern videomemory_t videomemory; 126 127static struct vidc_mode vidc_currentmode; 128 129unsigned int dispstart; 130unsigned int dispsize; 131unsigned int dispbase; 132unsigned int dispend; 133unsigned int ptov; 134unsigned int vmem_base; 135unsigned int phys_base; 136unsigned int transfersize; 137 138 139/* cursor stuff */ 140char *cursor_normal; 141char *cursor_transparent; 142int p_cursor_normal; 143int p_cursor_transparent; 144int cursor_width; 145int cursor_height; 146 147 148/* 149 * VIDC mode definitions 150 * generated from RISC OS mode definition file by an `awk' script 151 */ 152extern const struct videomode vidc_videomode_list[]; 153extern const int vidc_videomode_count; 154 155 156/* 157 * configuration printing 158 * 159 */ 160 161void 162vidcvideo_printdetails(void) 163{ 164 printf(": refclk=%dMHz %dKB %s ", (vidc_fref / 1000000), 165 videomemory.vidm_size / 1024, 166 (videomemory.vidm_type == VIDEOMEM_TYPE_VRAM) ? "VRAM" : "DRAM"); 167} 168 169 170/* 171 * Common functions to directly access VIDC registers 172 */ 173int 174vidcvideo_write(u_int reg, int value) 175{ 176 int counter; 177 178 int *current; 179 int *tab; 180 181 tab = (int *)&vidc_lookup; 182 current = (int *)vidc_current; 183 184 185 /* 186 * OK, the VIDC_PALETTE register is handled differently 187 * to the others on the VIDC, so take that into account here 188 */ 189 if (reg == VIDC_PALREG) { 190 vidc_current->palreg = 0; 191 WriteWord(vidc_base, reg | value); 192 return 0; 193 } 194 195 if (reg == VIDC_PALETTE) { 196 WriteWord(vidc_base, reg | value); 197 vidc_current->palette[vidc_current->palreg] = value; 198 vidc_current->palreg++; 199 vidc_current->palreg = vidc_current->palreg & 0xff; 200 return 0; 201 } 202 203 /* 204 * Undefine SAFER if you wish to speed things up (a little) 205 * although this means the function will assume things abou 206 * the structure of vidc_state. i.e. the first 256 words are 207 * the palette array 208 */ 209 210#define SAFER 211 212#ifdef SAFER 213#define INITVALUE 0 214#else 215#define INITVALUE 256 216#endif 217 218 for (counter = INITVALUE; 219 counter <= sizeof(struct vidc_state); 220 counter++) { 221 if (reg == tab[counter]) { 222 WriteWord ( vidc_base, reg | value ); 223 current[counter] = value; 224 return 0; 225 } 226 } 227 return -1; 228} 229 230 231void 232vidcvideo_setpalette(struct vidc_state *vidc) 233{ 234 int counter = 0; 235 236 vidcvideo_write(VIDC_PALREG, 0x00000000); 237 for (counter = 0; counter <= 255; counter++) 238 vidcvideo_write(VIDC_PALETTE, vidc->palette[counter]); 239} 240 241 242void 243vidcvideo_setstate(struct vidc_state *vidc) 244{ 245 vidcvideo_write ( VIDC_PALREG, vidc->palreg ); 246 vidcvideo_write ( VIDC_BCOL, vidc->bcol ); 247 vidcvideo_write ( VIDC_CP1, vidc->cp1 ); 248 vidcvideo_write ( VIDC_CP2, vidc->cp2 ); 249 vidcvideo_write ( VIDC_CP3, vidc->cp3 ); 250 vidcvideo_write ( VIDC_HCR, vidc->hcr ); 251 vidcvideo_write ( VIDC_HSWR, vidc->hswr ); 252 vidcvideo_write ( VIDC_HBSR, vidc->hbsr ); 253 vidcvideo_write ( VIDC_HDSR, vidc->hdsr ); 254 vidcvideo_write ( VIDC_HDER, vidc->hder ); 255 vidcvideo_write ( VIDC_HBER, vidc->hber ); 256 vidcvideo_write ( VIDC_HCSR, vidc->hcsr ); 257 vidcvideo_write ( VIDC_HIR, vidc->hir ); 258 vidcvideo_write ( VIDC_VCR, vidc->vcr ); 259 vidcvideo_write ( VIDC_VSWR, vidc->vswr ); 260 vidcvideo_write ( VIDC_VBSR, vidc->vbsr ); 261 vidcvideo_write ( VIDC_VDSR, vidc->vdsr ); 262 vidcvideo_write ( VIDC_VDER, vidc->vder ); 263 vidcvideo_write ( VIDC_VBER, vidc->vber ); 264 vidcvideo_write ( VIDC_VCSR, vidc->vcsr ); 265 vidcvideo_write ( VIDC_VCER, vidc->vcer ); 266/* 267 * Right, dunno what to set these to yet, but let's keep RiscOS's 268 * ones for now, until the time is right to finish this code 269 */ 270 271/* vidcvideo_write ( VIDC_EREG, vidc->ereg ); */ 272/* vidcvideo_write ( VIDC_FSYNREG, vidc->fsynreg ); */ 273/* vidcvideo_write ( VIDC_CONREG, vidc->conreg ); */ 274/* vidcvideo_write ( VIDC_DCTL, vidc->dctl ); */ 275 276 vidcvideo_setpalette(vidc); 277} 278 279 280void 281vidcvideo_getstate(struct vidc_state *vidc) 282{ 283 284 *vidc = *vidc_current; 285} 286 287 288void 289vidcvideo_getmode(struct vidc_mode *mode) 290{ 291 292 *mode = vidc_currentmode; 293} 294 295 296static int 297vidcvideo_coldinit(void) 298{ 299 struct videomode const *modes; 300 unsigned besterror; 301 int count; 302 int i; 303 unsigned framerate; 304 305 /* Blank out the cursor */ 306 307 vidcvideo_write(VIDC_CP1, 0x0); 308 vidcvideo_write(VIDC_CP2, 0x0); 309 vidcvideo_write(VIDC_CP3, 0x0); 310 311 dispbase = vmem_base = dispstart = videomemory.vidm_vbase; 312 phys_base = videomemory.vidm_pbase; 313 314 /* Nut - should be using videomemory.vidm_size - mark */ 315 if (videomemory.vidm_type == VIDEOMEM_TYPE_DRAM) { 316 dispsize = videomemory.vidm_size; 317 transfersize = 16; 318 } else { 319 dispsize = bootconfig.vram[0].pages * PAGE_SIZE; 320 transfersize = dispsize >> 10; 321 } 322 323 ptov = dispbase - phys_base; 324 325 dispend = dispstart+dispsize; 326 327 if (vidc_videomode_count > 0) { 328 modes = vidc_videomode_list; 329 count = vidc_videomode_count; 330 } else { 331 modes = videomode_list; 332 count = videomode_count; 333 } 334 335 /* try to find the current mode from the bootloader in my table */ 336 vidc_currentmode.timings = modes[0]; 337 besterror = 1000000; 338 for (i = 0; i < count; i++) { 339 /* We don't support interlace or doublescan */ 340 if (modes[i].flags & (VID_INTERLACE | VID_DBLSCAN)) 341 continue; 342 /* 343 * We jump through a few hoops here to ensure that we 344 * round roughly to the nearest integer without too 345 * much danger of overflow. 346 */ 347 framerate = (modes[i].dot_clock * 1000 / 348 modes[i].htotal * 2 / modes[i].vtotal + 1) / 2; 349 if (modes[i].hdisplay == bootconfig.width + 1 350 && modes[i].vdisplay == bootconfig.height + 1 351 && abs(framerate - bootconfig.framerate) < besterror) { 352 vidc_currentmode.timings = modes[i]; 353 besterror = abs(framerate - bootconfig.framerate); 354 } 355 } 356 357 vidc_currentmode.log2_bpp = bootconfig.log2_bpp; 358 359 dispstart = dispbase; 360 dispend = dispstart+dispsize; 361 362 IOMD_WRITE_WORD(IOMD_VIDINIT, dispstart-ptov); 363 IOMD_WRITE_WORD(IOMD_VIDSTART, dispstart-ptov); 364 IOMD_WRITE_WORD(IOMD_VIDEND, (dispend-transfersize)-ptov); 365 return 0; 366} 367 368 369/* simple function to abstract vidc variables ; returns virt start address of screen */ 370/* XXX asumption that video memory is mapped in twice */ 371void *vidcvideo_hwscroll(int bytes) 372{ 373 374 dispstart += bytes; 375 if (dispstart >= dispbase + dispsize) dispstart -= dispsize; 376 if (dispstart < dispbase) dispstart += dispsize; 377 dispend = dispstart+dispsize; 378 379 /* return the start of the bit map of the screen (left top) */ 380 return (void *)dispstart; 381} 382 383 384/* reset the HW scroll to be at the start for the benefit of f.e. X */ 385void *vidcvideo_hwscroll_reset(void) 386{ 387 void *cookie = (void *)dispstart; 388 389 dispstart = dispbase; 390 dispend = dispstart + dispsize; 391 return cookie; 392} 393 394 395/* put HW scroll back to where it was */ 396void *vidcvideo_hwscroll_back(void *cookie) 397{ 398 399 dispstart = (int)cookie; 400 dispend = dispstart + dispsize; 401 return cookie; 402} 403 404 405/* this function is to be called perferably at vsync */ 406void vidcvideo_progr_scroll(void) 407{ 408 409 IOMD_WRITE_WORD(IOMD_VIDINIT, dispstart-ptov); 410 IOMD_WRITE_WORD(IOMD_VIDSTART, dispstart-ptov); 411 IOMD_WRITE_WORD(IOMD_VIDEND, (dispend-transfersize)-ptov); 412} 413 414 415/* 416 * Select a new mode by reprogramming the VIDC chip 417 * XXX this part is known not to work for 32bpp 418 */ 419 420struct vidc_mode newmode; 421 422static const int bpp_mask_table[] = { 423 0, /* 1bpp */ 424 1, /* 2bpp */ 425 2, /* 4bpp */ 426 3, /* 8bpp */ 427 4, /* 16bpp */ 428 6 /* 32bpp */ 429}; 430 431 432void 433vidcvideo_setmode(struct vidc_mode *mode) 434{ 435 struct videomode *vm; 436 int bpp_mask; 437 int ereg; 438 int best_r, best_v; 439 int least_error; 440 int r, v, f; 441 442 /* 443 * Find out what bit mask we need to or with the vidc20 444 * control register in order to generate the desired number of 445 * bits per pixel. log_bpp is log base 2 of the number of 446 * bits per pixel. 447 */ 448 449 bpp_mask = bpp_mask_table[mode->log2_bpp]; 450 451 vidc_currentmode = *mode; 452 vm = &vidc_currentmode.timings; 453 454 least_error = INT_MAX; 455 best_r = 0; best_v = 0; 456 457 for (v = 63; v > 0; v--) { 458 for (r = 63; r > 0; r--) { 459 f = ((v * vidc_fref) /1000) / r; 460 if (least_error >= abs(f - vm->dot_clock)) { 461 least_error = abs(f - vm->dot_clock); 462 best_r = r; 463 best_v = v; 464 } 465 } 466 } 467 468 if (best_r > 63) best_r=63; 469 if (best_v > 63) best_v=63; 470 if (best_r < 1) best_r= 1; 471 if (best_v < 1) best_v= 1; 472 473 vidcvideo_write(VIDC_FSYNREG, (best_v-1)<<8 | (best_r-1)<<0); 474 475 /* 476 * The translation from struct videomode to VIDC timings is made 477 * fun by the fact that the VIDC counts from the start of the sync 478 * pulse while struct videomode counts from the start of the display. 479 */ 480 vidcvideo_write(VIDC_HSWR, (vm->hsync_end - vm->hsync_start - 8) & ~1); 481 vidcvideo_write(VIDC_HBSR, (vm->htotal - vm->hsync_start - 12) & ~1); 482 vidcvideo_write(VIDC_HDSR, (vm->htotal - vm->hsync_start - 18) & ~1); 483 vidcvideo_write(VIDC_HDER, 484 (vm->htotal - vm->hsync_start + vm->hdisplay - 18) & ~1); 485 vidcvideo_write(VIDC_HBER, 486 (vm->htotal - vm->hsync_start + vm->hdisplay - 12) & ~1); 487 vidcvideo_write(VIDC_HCR, (vm->htotal - 8) & ~3); 488 489 vidcvideo_write(VIDC_VSWR, vm->vsync_end - vm->vsync_start - 1); 490 vidcvideo_write(VIDC_VBSR, vm->vtotal - vm->vsync_start - 1); 491 vidcvideo_write(VIDC_VDSR, vm->vtotal - vm->vsync_start - 1); 492 vidcvideo_write(VIDC_VDER, 493 vm->vtotal - vm->vsync_start + vm->vdisplay - 1); 494 vidcvideo_write(VIDC_VBER, 495 vm->vtotal - vm->vsync_start + vm->vdisplay - 1); 496 /* XXX VIDC20 data sheet say to subtract 2 */ 497 vidcvideo_write(VIDC_VCR, vm->vtotal - 1); 498 499 IOMD_WRITE_WORD(IOMD_FSIZE, vm->vtotal - vm->vdisplay - 1); 500 501 if (dispsize <= 1024*1024) 502 vidcvideo_write(VIDC_DCTL, vm->hdisplay>>2 | 1<<16 | 1<<12); 503 else 504 vidcvideo_write(VIDC_DCTL, vm->hdisplay>>2 | 3<<16 | 1<<12); 505 506 ereg = 1<<12; 507 if (vm->flags & VID_NHSYNC) 508 ereg |= 1<<16; 509 if (vm->flags & VID_NVSYNC) 510 ereg |= 1<<18; 511 vidcvideo_write(VIDC_EREG, ereg); 512 513 /* 514 * Set the video FIFO preload value and bit depth. Chapter 6 515 * of the VIDC20 Data Sheet has full details of the FIFO 516 * preload, but we don't do anything clever and just use the 517 * largest possible value, which is 7 when the VIDC20 is in 518 * 32-bit mode (0MB or 1MB VRAM) and 6 when it is in 64-bit 519 * mode (2MB VRAM). 520 */ 521 if (dispsize > 1024*1024) 522 vidcvideo_write(VIDC_CONREG, 6<<8 | bpp_mask<<5); 523 else 524 vidcvideo_write(VIDC_CONREG, 7<<8 | bpp_mask<<5); 525} 526 527 528#if 0 529/* not used for now */ 530void 531vidcvideo_set_display_base(u_int base) 532{ 533 dispstart = dispstart-dispbase + base; 534 dispbase = vmem_base = base; 535 dispend = base + dispsize; 536 ptov = dispbase - phys_base; 537} 538#endif 539 540 541/* 542 * Main initialisation routine for now 543 */ 544 545static int cursor_init = 0; 546 547int 548vidcvideo_init(void) 549{ 550 vidcvideo_coldinit(); 551 if (cold_init && (cursor_init == 0)) 552 /* vidcvideo_flash_go() */; 553 554 /* setting a mode goes wrong in 32 bpp ... 8 and 16 seem OK */ 555 vidcvideo_setmode(&vidc_currentmode); 556 vidcvideo_blank(0); /* display on */ 557 558 vidcvideo_stdpalette(); 559 560 if (cold_init == 0) { 561 vidcvideo_write(VIDC_CP1, 0x0); 562 vidcvideo_write(VIDC_CP2, 0x0); 563 vidcvideo_write(VIDC_CP3, 0x0); 564 } else 565 vidcvideo_cursor_init(CURSOR_MAX_WIDTH, CURSOR_MAX_HEIGHT); 566 567 cold_init = 1; 568 return 0; 569} 570 571 572/* reinitialise the vidcvideo */ 573void 574vidcvideo_reinit(void) 575{ 576 577 vidcvideo_coldinit(); 578 vidcvideo_setmode(&vidc_currentmode); 579} 580 581 582int 583vidcvideo_cursor_init(int width, int height) 584{ 585 static char *cursor_data = NULL; 586 int counter; 587 int line; 588 paddr_t pa; 589 590 cursor_width = width; 591 cursor_height = height; 592 593 if (!cursor_data) { 594 /* Allocate cursor memory first time round */ 595 cursor_data = (char *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 596 UVM_KMF_WIRED | UVM_KMF_ZERO); 597 if (!cursor_data) 598 panic("Cannot allocate memory for hardware cursor"); 599 (void) pmap_extract(pmap_kernel(), (vaddr_t)cursor_data, &pa); 600 IOMD_WRITE_WORD(IOMD_CURSINIT, pa); 601 } 602 603 /* Blank the cursor while initialising it's sprite */ 604 605 vidcvideo_write ( VIDC_CP1, 0x0 ); 606 vidcvideo_write ( VIDC_CP2, 0x0 ); 607 vidcvideo_write ( VIDC_CP3, 0x0 ); 608 609 cursor_normal = cursor_data; 610 cursor_transparent = cursor_data + (height * width); 611 612 cursor_transparent += 32; /* ALIGN */ 613 cursor_transparent = (char *)((int)cursor_transparent & (~31) ); 614 615 for ( line = 0; line<height; ++line ) { 616 for ( counter=0; counter<width/4;counter++ ) 617 cursor_normal[line * width + counter]=0x55; /* why 0x55 ? */ 618 for ( ; counter<8; counter++ ) 619 cursor_normal[line * width + counter]=0; 620 } 621 622 for ( line = 0; line<height; ++line ) { 623 for ( counter=0; counter<width/4;counter++ ) 624 cursor_transparent[line * width + counter]=0x00; 625 for ( ; counter<8; counter++ ) 626 cursor_transparent[line * width + counter]=0; 627 } 628 629 630 (void) pmap_extract(pmap_kernel(), (vaddr_t)cursor_normal, 631 (void *)&p_cursor_normal); 632 (void) pmap_extract(pmap_kernel(), (vaddr_t)cursor_transparent, 633 (void *)&p_cursor_transparent); 634 635 memset(cursor_normal, 0x55, width*height); /* white? */ 636 memset(cursor_transparent, 0x00, width*height);/* to see the diffence */ 637 638 /* Ok, now program the cursor; should be blank */ 639 vidcvideo_enablecursor(0); 640 641 return 0; 642} 643 644 645void 646vidcvideo_updatecursor(int xcur, int ycur) 647{ 648 int frontporch = vidc_currentmode.timings.htotal - 649 vidc_currentmode.timings.hsync_start; 650 int topporch = vidc_currentmode.timings.vtotal - 651 vidc_currentmode.timings.vsync_start; 652 653 vidcvideo_write(VIDC_HCSR, frontporch -17 + xcur); 654 vidcvideo_write(VIDC_VCSR, topporch -2 + (ycur+1)-2 + 3 - 655 cursor_height); 656 vidcvideo_write(VIDC_VCER, topporch -2 + (ycur+3)+2 + 3 ); 657} 658 659 660void 661vidcvideo_enablecursor(int on) 662{ 663 664 if (on) 665 IOMD_WRITE_WORD(IOMD_CURSINIT,p_cursor_normal); 666 else 667 IOMD_WRITE_WORD(IOMD_CURSINIT,p_cursor_transparent); 668 vidcvideo_write ( VIDC_CP1, 0xffffff ); /* enable */ 669} 670 671 672void 673vidcvideo_stdpalette(void) 674{ 675 int i; 676 677 switch (vidc_currentmode.log2_bpp) { 678 case 0: /* 1 bpp */ 679 case 1: /* 2 bpp */ 680 case 2: /* 4 bpp */ 681 case 3: /* 8 bpp */ 682 vidcvideo_write(VIDC_PALREG, 0x00000000); 683 vidcvideo_write(VIDC_PALETTE, VIDC_COL( 0, 0, 0)); 684 vidcvideo_write(VIDC_PALETTE, VIDC_COL(255, 0, 0)); 685 vidcvideo_write(VIDC_PALETTE, VIDC_COL( 0, 255, 0)); 686 vidcvideo_write(VIDC_PALETTE, VIDC_COL(255, 255, 0)); 687 vidcvideo_write(VIDC_PALETTE, VIDC_COL( 0, 0, 255)); 688 vidcvideo_write(VIDC_PALETTE, VIDC_COL(255, 0, 255)); 689 vidcvideo_write(VIDC_PALETTE, VIDC_COL( 0, 255, 255)); 690 vidcvideo_write(VIDC_PALETTE, VIDC_COL(255, 255, 255)); 691 vidcvideo_write(VIDC_PALETTE, VIDC_COL(128, 128, 128)); 692 vidcvideo_write(VIDC_PALETTE, VIDC_COL(255, 128, 128)); 693 vidcvideo_write(VIDC_PALETTE, VIDC_COL(128, 255, 128)); 694 vidcvideo_write(VIDC_PALETTE, VIDC_COL(255, 255, 128)); 695 vidcvideo_write(VIDC_PALETTE, VIDC_COL(128, 128, 255)); 696 vidcvideo_write(VIDC_PALETTE, VIDC_COL(255, 128, 255)); 697 vidcvideo_write(VIDC_PALETTE, VIDC_COL(255, 255, 255)); 698 break; 699 case 4: /* 16 bpp */ 700 /* 701 * The use of the palette in 16-bit modes is quite 702 * fun. Comments in linux/drivers/video/acornfb.c 703 * imply that it goes something like this: 704 * 705 * red = LUT[pixel[7:0]].red 706 * green = LUT[pixel[11:4]].green 707 * blue = LUT[pixel[15:8]].blue 708 * 709 * We use 6:5:5 R:G:B cos that's what Xarm32VIDC wants. 710 */ 711#define RBITS 6 712#define GBITS 5 713#define BBITS 5 714 vidcvideo_write(VIDC_PALREG, 0x00000000); 715 for (i = 0; i < 256; i++) { 716 int r, g, b; 717 718 r = i & ((1 << RBITS) - 1); 719 g = (i >> (RBITS - 4)) & ((1 << GBITS) - 1); 720 b = (i >> (RBITS + GBITS - 8)) & ((1 << BBITS) - 1); 721 vidcvideo_write(VIDC_PALETTE, 722 VIDC_COL(r << (8 - RBITS) | r >> (2 * RBITS - 8), 723 g << (8 - GBITS) | g >> (2 * GBITS - 8), 724 b << (8 - BBITS) | b >> (2 * BBITS - 8))); 725 } 726 break; 727 case 5: /* 32 bpp */ 728 vidcvideo_write(VIDC_PALREG, 0x00000000); 729 for (i = 0; i < 256; i++) 730 vidcvideo_write(VIDC_PALETTE, VIDC_COL(i, i, i)); 731 break; 732 } 733} 734 735int 736vidcvideo_blank(int video_off) 737{ 738 int ereg; 739 740 ereg = 1<<12; 741 if (vidc_currentmode.timings.flags & VID_NHSYNC) 742 ereg |= 1<<16; 743 if (vidc_currentmode.timings.flags & VID_NVSYNC) 744 ereg |= 1<<18; 745 746 if (!video_off) 747 vidcvideo_write(VIDC_EREG, ereg); 748 else 749 vidcvideo_write(VIDC_EREG, 0); 750 return 0; 751} 752 753/* end of vidc20config.c */ 754