1/* $NetBSD$ */ 2 3/* 4 * Copyright (c) 2009 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi and Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef _IMXSDMAREG_H 30#define _IMXSDMAREG_H 31 32#define SDMA_SIZE 0x100 33 34/* SDMA Controller */ 35#define SDMA_N_CHANNELS 32 36#define SDMA_PRIORITY_MIN 1 37#define SDMA_PRIORITY_MAX 7 38 39#define SDMA_N_EVENTS 32 /* DMA events from periperals */ 40 41#define SDMA_MC0PTR 0x0000 42#define SDMA_INTR 0x0004 43#define SDMA_STOP_STAT 0x0008 44#define SDMA_HSTART 0x000C 45#define SDMA_EVTOVR 0x0010 46#define SDMA_DSPOVR 0x0014 47#define SDMA_HOSTOVR 0x0018 48#define SDMA_EVTPEND 0x001C 49#define SDMA_RESET 0x0024 50#define SDMA_RESET_RESCHED __BIT(1) 51#define SDMA_RESET_RESET __BIT(0) 52#define SDMA_EVTERR 0x0028 53#define SDMA_INTRMASK 0x002C 54#define SDMA_PSW 0x0030 55#define SDMA_EVTERRDBG 0x0034 56#define SDMA_CONFIG 0x0038 57#define SDMA_ONCE_ENB 0x0040 58#define SDMA_ONCE_DATA 0x0044 59#define SDMA_ONCE_INSTR 0x0048 60#define SDMA_ONCE_STAT 0x004c 61#define ONCE_STAT_PST_SHIFT 12 62#define ONCE_STAT_PST_MASK (0xf<<ONCE_STAT_PST_SHIFT) 63#define ONCE_STAT_PST_PROGRAM (0<<ONCE_STAT_PST_SHIFT) 64#define ONCE_STAT_PST_DATA (1<<ONCE_STAT_PST_SHIFT) 65#define ONCE_STAT_PST_CHGFLOW (2<<ONCE_STAT_PST_SHIFT) 66#define ONCE_STAT_PST_CHGFLOW_IN_LOOP (3<<ONCE_STAT_PST_SHIFT) 67#define ONCE_STAT_PST_DEBUG (4<<ONCE_STAT_PST_SHIFT) 68#define ONCE_STAT_PST_FUNCUNIT (5<<ONCE_STAT_PST_SHIFT) 69#define ONCE_STAT_PST_SLEEP (6<<ONCE_STAT_PST_SHIFT) 70#define ONCE_STAT_PST_SAVE (7<<ONCE_STAT_PST_SHIFT) 71#define ONCE_STAT_PST_PROGRAM_IN_SLEEP (8<<ONCE_STAT_PST_SHIFT) 72#define ONCE_STAT_PST_DATA_IN_SLEEP (9<<ONCE_STAT_PST_SHIFT) 73#define ONCE_STAT_PST_CHGFLOW_IN_SLEEP (10<<ONCE_STAT_PST_SHIFT) 74#define ONCE_STAT_PST_CHGFLOW_IN_LOOP_IN_SLEEP (10<<ONCE_STAT_PST_SHIFT) 75#define ONCE_STAT_PST_DEBUG_IN_SLEEP (12<<ONCE_STAT_PST_SHIFT) 76#define ONCE_STAT_PST_FUNCUNIT_IN_SLEEP (13<<ONCE_STAT_PST_SHIFT) 77#define ONCE_STAT_PST_SLEEP_AFTER_RESET (14<<ONCE_STAT_PST_SHIFT) 78#define ONCE_STAT_PST_RESTORE (15<<ONCE_STAT_PST_SHIFT) 79 80#define ONCE_STAT_RCV __BIT(11) 81#define ONCE_STAT_EDR __BIT(10) 82#define ONCE_STAT_ODR __BIT(9) 83#define ONCE_STAT_SWB __BIT(8) 84#define ONCE_STAT_MST __BIT(7) 85#define ONCE_STAT_ECDR 0X07 86 87#define SDMA_ONCE_CMD 0x0050 88#define ONCE_RSTATUS 0 89#define ONCE_DMOV 1 90#define ONCE_EXEC_ONCE 2 91#define ONCE_RUN 3 92#define ONCE_EXEC_CORE 4 93#define ONCE_DEBUG_RQST 5 94#define ONCE_RBUFFER 6 95#define SDMA_EVT_MIRROR 0x0054 96#define SDMA_ILLINSTADDR 0x0058 /* Illegal Instruction Trap Address */ 97#define SDMA_CHN0ADDR 0x005c /* Channel 0 Boot address */ 98#define SDMA_XTRIG_CONF1 0x0070 /* Cross-Triger Evennts Config */ 99#define SDMA_XTRIG_CONF2 0x0074 100#define SDMA_CHNENBL(n) (0x80+(n)*4) /* Channel Enable RAM */ 101#define SDMA_CHNPRI(n) (0x100+(n)*4) /* Channel Priority */ 102 103 104/* 105 * Memory of SDMA Risc Core 106 */ 107 108#define SDMACORE_ROM_BASE 0x0000 109#define SDMACORE_ROM_SIZE 0x0400 /* in 32-bit word. 4K bytes */ 110#define SDMACORE_RAM_BASE 0x0800 111#define SDMACORE_RAM_SIZE 0x0800 /* in 32-bit word. 8K byte */ 112 113#define SDMACORE_CONTEXT_BASE 0x0800 114#define SDMACORE_CONTEXT_SIZE 32 /* XXX: or 24 */ 115#define SDMACORE_CONTEXT_ADDR(ch) (SDMACORE_CONTEXT_BASE+ \ 116 (SDMACORE_CONTEXT_SIZE * (ch))) 117#define SDMACORE_CONTEXT_END SDMACORE_CONTEXT_ADDR(SDMA_N_CHANNELS) 118 119 120#endif /* _IMXSDMAREG_H */ 121