1/* $NetBSD: db_interface.c,v 1.17 2009/03/18 10:22:21 cegger Exp $ */ 2 3/* 4 * Copyright (c) 1996 Scott K. Stevens 5 * 6 * Mach Operating System 7 * Copyright (c) 1991,1990 Carnegie Mellon University 8 * All Rights Reserved. 9 * 10 * Permission to use, copy, modify and distribute this software and its 11 * documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 * 30 * From: db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU) 31 */ 32 33/* 34 * Interface to new debugger. 35 */ 36 37#include <sys/cdefs.h> 38__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.17 2009/03/18 10:22:21 cegger Exp $"); 39 40#include "opt_ddb.h" 41 42#include <sys/param.h> 43#include <sys/proc.h> 44#include <sys/reboot.h> 45#include <sys/systm.h> /* just for boothowto */ 46#include <sys/exec.h> 47 48#include <uvm/uvm_extern.h> 49 50#include <machine/db_machdep.h> 51#include <arm/undefined.h> 52#include <ddb/db_access.h> 53#include <ddb/db_command.h> 54#include <ddb/db_output.h> 55#include <ddb/db_interface.h> 56#include <ddb/db_variables.h> 57#include <ddb/db_sym.h> 58#include <ddb/db_extern.h> 59#include <dev/cons.h> 60 61int db_access_und_sp(const struct db_variable *, db_expr_t *, int); 62int db_access_abt_sp(const struct db_variable *, db_expr_t *, int); 63int db_access_irq_sp(const struct db_variable *, db_expr_t *, int); 64u_int db_fetch_reg(int, db_regs_t *); 65int db_trapper(u_int addr, u_int inst, struct trapframe *frame, 66 int fault_code); 67 68static void db_write_text(unsigned char *, int ch); 69 70const struct db_variable db_regs[] = { 71 { "spsr", (long *)&DDB_REGS->tf_spsr, FCN_NULL, }, 72 { "r0", (long *)&DDB_REGS->tf_r0, FCN_NULL, }, 73 { "r1", (long *)&DDB_REGS->tf_r1, FCN_NULL, }, 74 { "r2", (long *)&DDB_REGS->tf_r2, FCN_NULL, }, 75 { "r3", (long *)&DDB_REGS->tf_r3, FCN_NULL, }, 76 { "r4", (long *)&DDB_REGS->tf_r4, FCN_NULL, }, 77 { "r5", (long *)&DDB_REGS->tf_r5, FCN_NULL, }, 78 { "r6", (long *)&DDB_REGS->tf_r6, FCN_NULL, }, 79 { "r7", (long *)&DDB_REGS->tf_r7, FCN_NULL, }, 80 { "r8", (long *)&DDB_REGS->tf_r8, FCN_NULL, }, 81 { "r9", (long *)&DDB_REGS->tf_r9, FCN_NULL, }, 82 { "r10", (long *)&DDB_REGS->tf_r10, FCN_NULL, }, 83 { "r11", (long *)&DDB_REGS->tf_r11, FCN_NULL, }, 84 { "r12", (long *)&DDB_REGS->tf_r12, FCN_NULL, }, 85 { "usr_sp", (long *)&DDB_REGS->tf_usr_sp, FCN_NULL, }, 86 { "usr_lr", (long *)&DDB_REGS->tf_usr_lr, FCN_NULL, }, 87 { "svc_sp", (long *)&DDB_REGS->tf_svc_sp, FCN_NULL, }, 88 { "svc_lr", (long *)&DDB_REGS->tf_svc_lr, FCN_NULL, }, 89 { "pc", (long *)&DDB_REGS->tf_pc, FCN_NULL, }, 90#ifdef __PROG32 91 { "und_sp", (long *)&nil, db_access_und_sp, }, 92 { "abt_sp", (long *)&nil, db_access_abt_sp, }, 93 { "irq_sp", (long *)&nil, db_access_irq_sp, }, 94#endif 95}; 96 97const struct db_variable * const db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]); 98 99int db_active = 0; 100db_regs_t ddb_regs; /* register state */ 101 102#ifdef __PROG32 103int 104db_access_und_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 105{ 106 107 if (rw == DB_VAR_GET) 108 *valp = get_stackptr(PSR_UND32_MODE); 109 return 0; 110} 111 112int 113db_access_abt_sp(const struct db_variable *vp, db_expr_t valp, int rw) 114{ 115 116 if (rw == DB_VAR_GET) 117 *valp = get_stackptr(PSR_ABT32_MODE); 118 return 0; 119} 120 121int 122db_access_irq_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 123{ 124 125 if (rw == DB_VAR_GET) 126 *valp = get_stackptr(PSR_IRQ32_MODE); 127 return 0; 128} 129#endif /* __PROG32 */ 130 131/* 132 * kdb_trap - field a TRACE or BPT trap 133 */ 134int 135kdb_trap(int type, db_regs_t *regs) 136{ 137 int s; 138 139 switch (type) { 140 case T_BREAKPOINT: /* breakpoint */ 141 case -1: /* keyboard interrupt */ 142 break; 143 default: 144 if (db_recover != 0) { 145 db_error("Faulted in DDB; continuing...\n"); 146 /*NOTREACHED*/ 147 } 148 } 149 150 /* Should switch to kdb`s own stack here. */ 151 152 ddb_regs = *regs; 153 154 s = splhigh(); 155 db_active++; 156 cnpollc(true); 157 db_trap(type, 0/*code*/); 158 cnpollc(false); 159 db_active--; 160 splx(s); 161 162 *regs = ddb_regs; 163 164 return 1; 165} 166 167volatile bool db_validating, db_faulted; 168 169int 170db_validate_address(vm_offset_t addr) 171{ 172 volatile uint8_t tmp; 173 174 db_faulted = false; 175 db_validating = true; 176 tmp = *(uint8_t *)addr; 177 db_validating = false; 178 return db_faulted; 179} 180 181/* 182 * Read bytes from kernel address space for debugger. 183 */ 184void 185db_read_bytes(vm_offset_t addr, size_t size, char *data) 186{ 187 char *src; 188 189 src = (char *)addr; 190 for (; size > 0; size--) { 191 if (db_validate_address((u_int)src)) { 192 db_printf("address %p is invalid\n", src); 193 return; 194 } 195 *data++ = *src++; 196 } 197} 198 199static void 200db_write_text(unsigned char *dst, int ch) 201{ 202 203 if (db_validate_address((u_int)dst)) { 204 db_printf(" address %p not a valid page\n", dst); 205 return; 206 } 207 208 *dst = (unsigned char)ch; 209} 210 211/* 212 * Write bytes to kernel address space for debugger. 213 */ 214void 215db_write_bytes(vm_offset_t addr, size_t size, const char *data) 216{ 217#if 0 218 extern char _stext_[], _etext[]; 219#endif 220 char *dst; 221 int loop; 222 223 dst = (char *)addr; 224 loop = size; 225 while (--loop >= 0) { 226#if 0 /* FIXME */ 227 if ((dst >= _stext_) && (dst < _etext)) 228#endif 229 db_write_text(dst, *data); 230#if 0 231 else { 232 if (db_validate_address((u_int)dst)) { 233 db_printf("address %p is invalid\n", dst); 234 return; 235 } 236 *dst = *data; 237 } 238#endif 239 dst++, data++; 240 } 241} 242 243const struct db_command db_machine_command_table[] = { 244 { DDB_ADD_CMD("bsw", db_bus_write_cmd, CS_MORE, 245 "Writes a one or two bytes to the IObus", 246 "[/bh] [addr]", 247 " addr:\tIO address to write\n" 248 " /b:\twrite a single byte\n" 249 " /h:\twrite two bytes") }, 250 { DDB_ADD_CMD("frame", db_show_frame_cmd, 0, 251 "Displays the contents of a trapframe", 252 "[address]", 253 " address:\taddress of trapfame to display")}, 254 { DDB_ADD_CMD("irqstat", db_irqstat_cmd, 0, 255 "Displays the IRQ statistics", 256 NULL,NULL) }, 257 { DDB_ADD_CMD("panic", db_show_panic_cmd, 0, 258 "Displays the last panic string", 259 NULL,NULL) }, 260 { DDB_ADD_CMD( NULL, NULL, 0, NULL, NULL,NULL) } 261}; 262 263int 264db_trapper(u_int addr, u_int inst, trapframe_t *frame, int fault_code) 265{ 266 267 if (fault_code == 0) { 268 if ((inst & ~INSN_COND_MASK) == (BKPT_INST & ~INSN_COND_MASK)) 269 kdb_trap(T_BREAKPOINT, frame); 270 else 271 kdb_trap(-1, frame); 272 } else 273 return 1; 274 return 0; 275} 276 277extern u_int esym; 278extern u_int end; 279 280static struct undefined_handler db_uh; 281 282void 283db_machine_init(void) 284{ 285 286 /* 287 * We get called before malloc() is available, so supply a static 288 * struct undefined_handler. 289 */ 290 db_uh.uh_handler = db_trapper; 291 install_coproc_handler_static(CORE_UNKNOWN_HANDLER, &db_uh); 292} 293 294u_int 295db_fetch_reg(int reg, db_regs_t *regs) 296{ 297 298 switch (reg) { 299 case 0: 300 return regs->tf_r0; 301 case 1: 302 return regs->tf_r1; 303 case 2: 304 return regs->tf_r2; 305 case 3: 306 return regs->tf_r3; 307 case 4: 308 return regs->tf_r4; 309 case 5: 310 return regs->tf_r5; 311 case 6: 312 return regs->tf_r6; 313 case 7: 314 return regs->tf_r7; 315 case 8: 316 return regs->tf_r8; 317 case 9: 318 return regs->tf_r9; 319 case 10: 320 return regs->tf_r10; 321 case 11: 322 return regs->tf_r11; 323 case 12: 324 return regs->tf_r12; 325 case 13: 326 return regs->tf_svc_sp; 327 case 14: 328 return regs->tf_svc_lr; 329 case 15: 330 return regs->tf_pc; 331 default: 332 panic("db_fetch_reg: botch"); 333 } 334} 335 336u_int 337branch_taken(u_int insn, u_int pc, db_regs_t *regs) 338{ 339 u_int addr, nregs; 340 341 switch ((insn >> 24) & 0xf) { 342 case 0xa: /* b ... */ 343 case 0xb: /* bl ... */ 344 addr = ((insn << 2) & 0x03ffffff); 345 if (addr & 0x02000000) 346 addr |= 0xfc000000; 347 return pc + 8 + addr; 348 case 0x7: /* ldr pc, [pc, reg, lsl #2] */ 349 addr = db_fetch_reg(insn & 0xf, regs); 350 addr = pc + 8 + (addr << 2); 351 db_read_bytes(addr, 4, (char *)&addr); 352 return addr; 353 case 0x1: /* mov pc, reg */ 354 addr = db_fetch_reg(insn & 0xf, regs); 355 return addr; 356 case 0x8: /* ldmxx reg, {..., pc} */ 357 case 0x9: 358 addr = db_fetch_reg((insn >> 16) & 0xf, regs); 359 nregs = (insn & 0x5555) + ((insn >> 1) & 0x5555); 360 nregs = (nregs & 0x3333) + ((nregs >> 2) & 0x3333); 361 nregs = (nregs + (nregs >> 4)) & 0x0f0f; 362 nregs = (nregs + (nregs >> 8)) & 0x001f; 363 switch ((insn >> 23) & 0x3) { 364 case 0x0: /* ldmda */ 365 addr = addr - 0; 366 break; 367 case 0x1: /* ldmia */ 368 addr = addr + 0 + ((nregs - 1) << 2); 369 break; 370 case 0x2: /* ldmdb */ 371 addr = addr - 4; 372 break; 373 case 0x3: /* ldmib */ 374 addr = addr + 4 + ((nregs - 1) << 2); 375 break; 376 } 377 db_read_bytes(addr, 4, (char *)&addr); 378 return addr; 379 default: 380 panic("branch_taken: botch"); 381 } 382} 383