1/* Based on execute/simd-1.c, modifed by joern.rennecke@st.com to
2   trigger a reload bug.  Verified for gcc mainline from 20050722 13:00 UTC
3   for sh-elf -m4 -O2.  */
4#ifndef STACK_SIZE
5#define STACK_SIZE (256*1024)
6#endif
7
8typedef struct { char c[STACK_SIZE/2]; } big_t;
9
10typedef int __attribute__((vector_size (8))) vecint;
11typedef int __attribute__((mode(SI))) siint;
12
13vecint i = { 150, 100 };
14vecint j = { 10, 13 };
15vecint k;
16
17union {
18  vecint v;
19  siint i[2];
20} res;
21
22void
23verify (siint a1, siint a2, siint b1, siint b2, big_t big)
24{
25  if (a1 != b1
26      || a2 != b2)
27    abort ();
28}
29
30int
31main ()
32{
33  big_t big;
34  vecint k0, k1, k2, k3, k4, k5, k6, k7;
35
36  k0 = i + j;
37  res.v = k0;
38
39  verify (res.i[0], res.i[1], 160, 113, big);
40
41  k1 = i * j;
42  res.v = k1;
43
44  verify (res.i[0], res.i[1], 1500, 1300, big);
45
46  k2 = i / j;
47/* This is the observed failure - reload 0 has the wrong type and thus the
48   conflict with reload 1 is missed:
49
50(insn:HI 94 92 96 1 pr23135.c:46 (parallel [
51            (set (subreg:SI (reg:DI 253) 0)
52                (div:SI (reg:SI 4 r4)
53                    (reg:SI 5 r5)))
54            (clobber (reg:SI 146 pr))
55            (clobber (reg:DF 64 fr0))
56            (clobber (reg:DF 66 fr2))
57            (use (reg:PSI 151 ))
58            (use (reg/f:SI 256))
59        ]) 60 {divsi3_i4} (insn_list:REG_DEP_TRUE 90 (insn_list:REG_DEP_TRUE 89
60(insn_list:REG_DEP_TRUE 42 (insn_list:REG_DEP_TRUE 83 (insn_list:REG_DEP_TRUE 92
61 (insn_list:REG_DEP_TRUE 91 (nil)))))))
62    (expr_list:REG_DEAD (reg:SI 4 r4)
63        (expr_list:REG_DEAD (reg:SI 5 r5)
64            (expr_list:REG_UNUSED (reg:DF 66 fr2)
65                (expr_list:REG_UNUSED (reg:DF 64 fr0)
66                    (expr_list:REG_UNUSED (reg:SI 146 pr)
67                        (insn_list:REG_RETVAL 91 (nil))))))))
68
69Reloads for insn # 94
70Reload 0: reload_in (SI) = (plus:SI (reg/f:SI 14 r14)
71                                                    (const_int 64 [0x40]))
72        GENERAL_REGS, RELOAD_FOR_OUTADDR_ADDRESS (opnum = 0)
73        reload_in_reg: (plus:SI (reg/f:SI 14 r14)
74                                                    (const_int 64 [0x40]))
75        reload_reg_rtx: (reg:SI 3 r3)
76Reload 1: GENERAL_REGS, RELOAD_FOR_OUTPUT_ADDRESS (opnum = 0), can't combine, se
77condary_reload_p
78        reload_reg_rtx: (reg:SI 3 r3)
79Reload 2: reload_out (SI) = (mem:SI (plus:SI (plus:SI (reg/f:SI 14 r14)
80                                                            (const_int 64 [0x40]))
81                                                        (const_int 28 [0x1c])) [ 16 S8 A32])
82        FPUL_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
83        reload_out_reg: (subreg:SI (reg:DI 253) 0)
84        reload_reg_rtx: (reg:SI 150 fpul)
85        secondary_out_reload = 1
86
87Reload 3: reload_in (SI) = (symbol_ref:SI ("__sdivsi3_i4") [flags 0x1])
88        GENERAL_REGS, RELOAD_FOR_INPUT (opnum = 1), can't combine
89        reload_in_reg: (reg/f:SI 256)
90        reload_reg_rtx: (reg:SI 3 r3)
91  */
92
93
94  res.v = k2;
95
96  verify (res.i[0], res.i[1], 15, 7, big);
97
98  k3 = i & j;
99  res.v = k3;
100
101  verify (res.i[0], res.i[1], 2, 4, big);
102
103  k4 = i | j;
104  res.v = k4;
105
106  verify (res.i[0], res.i[1], 158, 109, big);
107
108  k5 = i ^ j;
109  res.v = k5;
110
111  verify (res.i[0], res.i[1], 156, 105, big);
112
113  k6 = -i;
114  res.v = k6;
115  verify (res.i[0], res.i[1], -150, -100, big);
116
117  k7 = ~i;
118  res.v = k7;
119  verify (res.i[0], res.i[1], -151, -101, big);
120
121  k = k0 + k1 + k3 + k4 + k5 + k6 + k7;
122  res.v = k;
123  verify (res.i[0], res.i[1], 1675, 1430, big);
124
125  k = k0 * k1 * k3 * k4 * k5 * k6 * k7;
126  res.v = k;
127  verify (res.i[0], res.i[1], 1456467968, -1579586240, big);
128
129  k = k0 / k1 / k2 / k3 / k4 / k5 / k6 / k7;
130  res.v = k;
131  verify (res.i[0], res.i[1], 0, 0, big);
132
133  exit (0);
134}
135