1/* Definitions of Tensilica's Xtensa target machine for GNU compiler.
2   Copyright 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
3   Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify it under
8the terms of the GNU General Public License as published by the Free
9Software Foundation; either version 2, or (at your option) any later
10version.
11
12GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13WARRANTY; without even the implied warranty of MERCHANTABILITY or
14FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
15for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING.  If not, write to the Free
19Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
2002110-1301, USA.  */
21
22/* Get Xtensa configuration settings */
23#include "xtensa-config.h"
24
25/* Standard GCC variables that we reference.  */
26extern int current_function_calls_alloca;
27extern int optimize;
28
29/* External variables defined in xtensa.c.  */
30
31/* comparison type */
32enum cmp_type {
33  CMP_SI,				/* four byte integers */
34  CMP_DI,				/* eight byte integers */
35  CMP_SF,				/* single precision floats */
36  CMP_DF,				/* double precision floats */
37  CMP_MAX				/* max comparison type */
38};
39
40extern struct rtx_def * branch_cmp[2];	/* operands for compare */
41extern enum cmp_type branch_type;	/* what type of branch to use */
42extern unsigned xtensa_current_frame_size;
43
44/* Macros used in the machine description to select various Xtensa
45   configuration options.  */
46#define TARGET_BIG_ENDIAN	XCHAL_HAVE_BE
47#define TARGET_DENSITY		XCHAL_HAVE_DENSITY
48#define TARGET_MAC16		XCHAL_HAVE_MAC16
49#define TARGET_MUL16		XCHAL_HAVE_MUL16
50#define TARGET_MUL32		XCHAL_HAVE_MUL32
51#define TARGET_DIV32		XCHAL_HAVE_DIV32
52#define TARGET_NSA		XCHAL_HAVE_NSA
53#define TARGET_MINMAX		XCHAL_HAVE_MINMAX
54#define TARGET_SEXT		XCHAL_HAVE_SEXT
55#define TARGET_BOOLEANS		XCHAL_HAVE_BOOLEANS
56#define TARGET_HARD_FLOAT	XCHAL_HAVE_FP
57#define TARGET_HARD_FLOAT_DIV	XCHAL_HAVE_FP_DIV
58#define TARGET_HARD_FLOAT_RECIP	XCHAL_HAVE_FP_RECIP
59#define TARGET_HARD_FLOAT_SQRT	XCHAL_HAVE_FP_SQRT
60#define TARGET_HARD_FLOAT_RSQRT	XCHAL_HAVE_FP_RSQRT
61#define TARGET_ABS		XCHAL_HAVE_ABS
62#define TARGET_ADDX		XCHAL_HAVE_ADDX
63
64#define TARGET_DEFAULT (						\
65  (XCHAL_HAVE_L32R	? 0 : MASK_CONST16))
66
67#define OVERRIDE_OPTIONS override_options ()
68
69/* Reordering blocks for Xtensa is not a good idea unless the compiler
70   understands the range of conditional branches.  Currently all branch
71   relaxation for Xtensa is handled in the assembler, so GCC cannot do a
72   good job of reordering blocks.  Do not enable reordering unless it is
73   explicitly requested.  */
74#define OPTIMIZATION_OPTIONS(LEVEL, SIZE)				\
75  do									\
76    {									\
77      flag_reorder_blocks = 0;						\
78    }									\
79  while (0)
80
81
82/* Target CPU builtins.  */
83#define TARGET_CPU_CPP_BUILTINS()					\
84  do {									\
85    builtin_assert ("cpu=xtensa");					\
86    builtin_assert ("machine=xtensa");					\
87    builtin_define ("__xtensa__");					\
88    builtin_define ("__XTENSA__");					\
89    builtin_define ("__XTENSA_WINDOWED_ABI__");				\
90    builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \
91    if (!TARGET_HARD_FLOAT)						\
92      builtin_define ("__XTENSA_SOFT_FLOAT__");				\
93    if (flag_pic)							\
94      {									\
95        builtin_define ("__PIC__");					\
96        builtin_define ("__pic__");					\
97      }									\
98  } while (0)
99
100#define CPP_SPEC " %(subtarget_cpp_spec) "
101
102#ifndef SUBTARGET_CPP_SPEC
103#define SUBTARGET_CPP_SPEC ""
104#endif
105
106#define EXTRA_SPECS							\
107  { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },
108
109#ifdef __XTENSA_EB__
110#define LIBGCC2_WORDS_BIG_ENDIAN 1
111#else
112#define LIBGCC2_WORDS_BIG_ENDIAN 0
113#endif
114
115/* Show we can debug even without a frame pointer.  */
116#define CAN_DEBUG_WITHOUT_FP
117
118
119/* Target machine storage layout */
120
121/* Define this if most significant bit is lowest numbered
122   in instructions that operate on numbered bit-fields.  */
123#define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
124
125/* Define this if most significant byte of a word is the lowest numbered.  */
126#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
127
128/* Define this if most significant word of a multiword number is the lowest.  */
129#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
130
131#define MAX_BITS_PER_WORD 32
132
133/* Width of a word, in units (bytes).  */
134#define UNITS_PER_WORD 4
135#define MIN_UNITS_PER_WORD 4
136
137/* Width of a floating point register.  */
138#define UNITS_PER_FPREG 4
139
140/* Size in bits of various types on the target machine.  */
141#define INT_TYPE_SIZE 32
142#define SHORT_TYPE_SIZE 16
143#define LONG_TYPE_SIZE 32
144#define LONG_LONG_TYPE_SIZE 64
145#define FLOAT_TYPE_SIZE 32
146#define DOUBLE_TYPE_SIZE 64
147#define LONG_DOUBLE_TYPE_SIZE 64
148
149/* Allocation boundary (in *bits*) for storing pointers in memory.  */
150#define POINTER_BOUNDARY 32
151
152/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
153#define PARM_BOUNDARY 32
154
155/* Allocation boundary (in *bits*) for the code of a function.  */
156#define FUNCTION_BOUNDARY 32
157
158/* Alignment of field after 'int : 0' in a structure.  */
159#define EMPTY_FIELD_BOUNDARY 32
160
161/* Every structure's size must be a multiple of this.  */
162#define STRUCTURE_SIZE_BOUNDARY 8
163
164/* There is no point aligning anything to a rounder boundary than this.  */
165#define BIGGEST_ALIGNMENT 128
166
167/* Set this nonzero if move instructions will actually fail to work
168   when given unaligned data.  */
169#define STRICT_ALIGNMENT 1
170
171/* Promote integer modes smaller than a word to SImode.  Set UNSIGNEDP
172   for QImode, because there is no 8-bit load from memory with sign
173   extension.  Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit
174   loads both with and without sign extension.  */
175#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)				\
176  do {									\
177    if (GET_MODE_CLASS (MODE) == MODE_INT				\
178	&& GET_MODE_SIZE (MODE) < UNITS_PER_WORD)			\
179      {									\
180	if ((MODE) == QImode)						\
181	  (UNSIGNEDP) = 1;						\
182	(MODE) = SImode;						\
183      }									\
184  } while (0)
185
186/* Imitate the way many other C compilers handle alignment of
187   bitfields and the structures that contain them.  */
188#define PCC_BITFIELD_TYPE_MATTERS 1
189
190/* Disable the use of word-sized or smaller complex modes for structures,
191   and for function arguments in particular, where they cause problems with
192   register a7.  The xtensa_copy_incoming_a7 function assumes that there is
193   a single reference to an argument in a7, but with small complex modes the
194   real and imaginary components may be extracted separately, leading to two
195   uses of the register, only one of which would be replaced.  */
196#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
197  ((MODE) == CQImode || (MODE) == CHImode)
198
199/* Align string constants and constructors to at least a word boundary.
200   The typical use of this macro is to increase alignment for string
201   constants to be word aligned so that 'strcpy' calls that copy
202   constants can be done inline.  */
203#define CONSTANT_ALIGNMENT(EXP, ALIGN)					\
204  ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR)	\
205   && (ALIGN) < BITS_PER_WORD						\
206	? BITS_PER_WORD							\
207	: (ALIGN))
208
209/* Align arrays, unions and records to at least a word boundary.
210   One use of this macro is to increase alignment of medium-size
211   data to make it all fit in fewer cache lines.  Another is to
212   cause character arrays to be word-aligned so that 'strcpy' calls
213   that copy constants to character arrays can be done inline.  */
214#undef DATA_ALIGNMENT
215#define DATA_ALIGNMENT(TYPE, ALIGN)					\
216  ((((ALIGN) < BITS_PER_WORD)						\
217    && (TREE_CODE (TYPE) == ARRAY_TYPE					\
218	|| TREE_CODE (TYPE) == UNION_TYPE				\
219	|| TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
220
221/* Operations between registers always perform the operation
222   on the full register even if a narrower mode is specified.  */
223#define WORD_REGISTER_OPERATIONS
224
225/* Xtensa loads are zero-extended by default.  */
226#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
227
228/* Standard register usage.  */
229
230/* Number of actual hardware registers.
231   The hardware registers are assigned numbers for the compiler
232   from 0 to just below FIRST_PSEUDO_REGISTER.
233   All registers that the compiler knows about must be given numbers,
234   even those that are not normally considered general registers.
235
236   The fake frame pointer and argument pointer will never appear in
237   the generated code, since they will always be eliminated and replaced
238   by either the stack pointer or the hard frame pointer.
239
240   0 - 15	AR[0] - AR[15]
241   16		FRAME_POINTER (fake = initial sp)
242   17		ARG_POINTER (fake = initial sp + framesize)
243   18		BR[0] for floating-point CC
244   19 - 34	FR[0] - FR[15]
245   35		MAC16 accumulator */
246
247#define FIRST_PSEUDO_REGISTER 36
248
249/* Return the stabs register number to use for REGNO.  */
250#define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO)
251
252/* 1 for registers that have pervasive standard uses
253   and are not available for the register allocator.  */
254#define FIXED_REGISTERS							\
255{									\
256  1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
257  1, 1, 0,								\
258  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
259  0,									\
260}
261
262/* 1 for registers not available across function calls.
263   These must include the FIXED_REGISTERS and also any
264   registers that can be used without being saved.
265   The latter must include the registers where values are returned
266   and the register where structure-value addresses are passed.
267   Aside from that, you can include as many other registers as you like.  */
268#define CALL_USED_REGISTERS						\
269{									\
270  1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,			\
271  1, 1, 1,								\
272  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
273  1,									\
274}
275
276/* For non-leaf procedures on Xtensa processors, the allocation order
277   is as specified below by REG_ALLOC_ORDER.  For leaf procedures, we
278   want to use the lowest numbered registers first to minimize
279   register window overflows.  However, local-alloc is not smart
280   enough to consider conflicts with incoming arguments.  If an
281   incoming argument in a2 is live throughout the function and
282   local-alloc decides to use a2, then the incoming argument must
283   either be spilled or copied to another register.  To get around
284   this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine
285   reg_alloc_order for leaf functions such that lowest numbered
286   registers are used first with the exception that the incoming
287   argument registers are not used until after other register choices
288   have been exhausted.  */
289
290#define REG_ALLOC_ORDER \
291{  8,  9, 10, 11, 12, 13, 14, 15,  7,  6,  5,  4,  3,  2, \
292  18, \
293  19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \
294   0,  1, 16, 17, \
295  35, \
296}
297
298#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
299
300/* For Xtensa, the only point of this is to prevent GCC from otherwise
301   giving preference to call-used registers.  To minimize window
302   overflows for the AR registers, we want to give preference to the
303   lower-numbered AR registers.  For other register files, which are
304   not windowed, we still prefer call-used registers, if there are any.  */
305extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER];
306#define LEAF_REGISTERS xtensa_leaf_regs
307
308/* For Xtensa, no remapping is necessary, but this macro must be
309   defined if LEAF_REGISTERS is defined.  */
310#define LEAF_REG_REMAP(REGNO) (REGNO)
311
312/* This must be declared if LEAF_REGISTERS is set.  */
313extern int leaf_function;
314
315/* Internal macros to classify a register number.  */
316
317/* 16 address registers + fake registers */
318#define GP_REG_FIRST 0
319#define GP_REG_LAST  17
320#define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
321
322/* Coprocessor registers */
323#define BR_REG_FIRST 18
324#define BR_REG_LAST  18
325#define BR_REG_NUM   (BR_REG_LAST - BR_REG_FIRST + 1)
326
327/* 16 floating-point registers */
328#define FP_REG_FIRST 19
329#define FP_REG_LAST  34
330#define FP_REG_NUM   (FP_REG_LAST - FP_REG_FIRST + 1)
331
332/* MAC16 accumulator */
333#define ACC_REG_FIRST 35
334#define ACC_REG_LAST 35
335#define ACC_REG_NUM  (ACC_REG_LAST - ACC_REG_FIRST + 1)
336
337#define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
338#define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM)
339#define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
340#define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM)
341
342/* Return number of consecutive hard regs needed starting at reg REGNO
343   to hold something of mode MODE.  */
344#define HARD_REGNO_NREGS(REGNO, MODE)					\
345  (FP_REG_P (REGNO) ?							\
346	((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \
347	((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
348
349/* Value is 1 if hard register REGNO can hold a value of machine-mode
350   MODE.  */
351extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
352
353#define HARD_REGNO_MODE_OK(REGNO, MODE)					\
354  xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)]
355
356/* Value is 1 if it is a good idea to tie two pseudo registers
357   when one has mode MODE1 and one has mode MODE2.
358   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
359   for any hard reg, then this must be 0 for correct output.  */
360#define MODES_TIEABLE_P(MODE1, MODE2)					\
361  ((GET_MODE_CLASS (MODE1) == MODE_FLOAT ||				\
362    GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)			\
363   == (GET_MODE_CLASS (MODE2) == MODE_FLOAT ||				\
364       GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
365
366/* Register to use for pushing function arguments.  */
367#define STACK_POINTER_REGNUM (GP_REG_FIRST + 1)
368
369/* Base register for access to local variables of the function.  */
370#define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7)
371
372/* The register number of the frame pointer register, which is used to
373   access automatic variables in the stack frame.  For Xtensa, this
374   register never appears in the output.  It is always eliminated to
375   either the stack pointer or the hard frame pointer.  */
376#define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16)
377
378/* Value should be nonzero if functions must have frame pointers.
379   Zero means the frame pointer need not be set up (and parms
380   may be accessed via the stack pointer) in functions that seem suitable.
381   This is computed in 'reload', in reload1.c.  */
382#define FRAME_POINTER_REQUIRED xtensa_frame_pointer_required ()
383
384/* Base register for access to arguments of the function.  */
385#define ARG_POINTER_REGNUM (GP_REG_FIRST + 17)
386
387/* If the static chain is passed in memory, these macros provide rtx
388   giving 'mem' expressions that denote where they are stored.
389   'STATIC_CHAIN' and 'STATIC_CHAIN_INCOMING' give the locations as
390   seen by the calling and called functions, respectively.  */
391
392#define STATIC_CHAIN							\
393  gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -5 * UNITS_PER_WORD))
394
395#define STATIC_CHAIN_INCOMING						\
396  gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -5 * UNITS_PER_WORD))
397
398/* For now we don't try to use the full set of boolean registers.  Without
399   software pipelining of FP operations, there's not much to gain and it's
400   a real pain to get them reloaded.  */
401#define FPCC_REGNUM (BR_REG_FIRST + 0)
402
403/* It is as good or better to call a constant function address than to
404   call an address kept in a register.  */
405#define NO_FUNCTION_CSE 1
406
407/* Xtensa processors have "register windows".  GCC does not currently
408   take advantage of the possibility for variable-sized windows; instead,
409   we use a fixed window size of 8.  */
410
411#define INCOMING_REGNO(OUT)						\
412  ((GP_REG_P (OUT) &&							\
413    ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ?		\
414   (OUT) - WINDOW_SIZE : (OUT))
415
416#define OUTGOING_REGNO(IN)						\
417  ((GP_REG_P (IN) &&							\
418    ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ?			\
419   (IN) + WINDOW_SIZE : (IN))
420
421
422/* Define the classes of registers for register constraints in the
423   machine description.  */
424enum reg_class
425{
426  NO_REGS,			/* no registers in set */
427  BR_REGS,			/* coprocessor boolean registers */
428  FP_REGS,			/* floating point registers */
429  ACC_REG,			/* MAC16 accumulator */
430  SP_REG,			/* sp register (aka a1) */
431  RL_REGS,			/* preferred reload regs (not sp or fp) */
432  GR_REGS,			/* integer registers except sp */
433  AR_REGS,			/* all integer registers */
434  ALL_REGS,			/* all registers */
435  LIM_REG_CLASSES		/* max value + 1 */
436};
437
438#define N_REG_CLASSES (int) LIM_REG_CLASSES
439
440#define GENERAL_REGS AR_REGS
441
442/* An initializer containing the names of the register classes as C
443   string constants.  These names are used in writing some of the
444   debugging dumps.  */
445#define REG_CLASS_NAMES							\
446{									\
447  "NO_REGS",								\
448  "BR_REGS",								\
449  "FP_REGS",								\
450  "ACC_REG",								\
451  "SP_REG",								\
452  "RL_REGS",								\
453  "GR_REGS",								\
454  "AR_REGS",								\
455  "ALL_REGS"								\
456}
457
458/* Contents of the register classes.  The Nth integer specifies the
459   contents of class N.  The way the integer MASK is interpreted is
460   that register R is in the class if 'MASK & (1 << R)' is 1.  */
461#define REG_CLASS_CONTENTS \
462{ \
463  { 0x00000000, 0x00000000 }, /* no registers */ \
464  { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \
465  { 0xfff80000, 0x00000007 }, /* floating-point registers */ \
466  { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \
467  { 0x00000002, 0x00000000 }, /* stack pointer register */ \
468  { 0x0000ff7d, 0x00000000 }, /* preferred reload registers */ \
469  { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \
470  { 0x0003ffff, 0x00000000 }, /* integer registers */ \
471  { 0xffffffff, 0x0000000f }  /* all registers */ \
472}
473
474/* A C expression whose value is a register class containing hard
475   register REGNO.  In general there is more that one such class;
476   choose a class which is "minimal", meaning that no smaller class
477   also contains the register.  */
478extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER];
479
480#define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ]
481
482/* Use the Xtensa AR register file for base registers.
483   No index registers.  */
484#define BASE_REG_CLASS AR_REGS
485#define INDEX_REG_CLASS NO_REGS
486
487/* SMALL_REGISTER_CLASSES is required for Xtensa, because all of the
488   16 AR registers may be explicitly used in the RTL, as either
489   incoming or outgoing arguments.  */
490#define SMALL_REGISTER_CLASSES 1
491
492
493/* REGISTER AND CONSTANT CLASSES */
494
495/* Get reg_class from a letter such as appears in the machine
496   description.
497
498   Available letters: a-f,h,j-l,q,t-z,A-D,W,Y-Z
499
500   DEFINED REGISTER CLASSES:
501
502   'a'  general-purpose registers except sp
503   'q'  sp (aka a1)
504   'D'	general-purpose registers (only if density option enabled)
505   'd'  general-purpose registers, including sp (only if density enabled)
506   'A'	MAC16 accumulator (only if MAC16 option enabled)
507   'B'	general-purpose registers (only if sext instruction enabled)
508   'C'  general-purpose registers (only if mul16 option enabled)
509   'W'  general-purpose registers (only if const16 option enabled)
510   'b'	coprocessor boolean registers
511   'f'	floating-point registers
512*/
513
514extern enum reg_class xtensa_char_to_class[256];
515
516#define REG_CLASS_FROM_LETTER(C) xtensa_char_to_class[ (int) (C) ]
517
518/* The letters I, J, K, L, M, N, O, and P in a register constraint
519   string can be used to stand for particular ranges of immediate
520   operands.  This macro defines what the ranges are.  C is the
521   letter, and VALUE is a constant value.  Return 1 if VALUE is
522   in the range specified by C.
523
524   For Xtensa:
525
526   I = 12-bit signed immediate for MOVI
527   J = 8-bit signed immediate for ADDI
528   K = 4-bit value in (b4const U {0})
529   L = 4-bit value in b4constu
530   M = 7-bit immediate value for MOVI.N
531   N = 8-bit unsigned immediate shifted left by 8 bits for ADDMI
532   O = 4-bit immediate for ADDI.N
533   P = valid immediate mask value for EXTUI */
534
535#define CONST_OK_FOR_LETTER_P  xtensa_const_ok_for_letter_p
536#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) (0)
537
538
539/* Other letters can be defined in a machine-dependent fashion to
540   stand for particular classes of registers or other arbitrary
541   operand types.
542
543   R = memory that can be accessed with a 4-bit unsigned offset
544   T = memory in a constant pool (addressable with a pc-relative load)
545   U = memory *NOT* in a constant pool
546
547   The offset range should not be checked here (except to distinguish
548   denser versions of the instructions for which more general versions
549   are available).  Doing so leads to problems in reloading: an
550   argptr-relative address may become invalid when the phony argptr is
551   eliminated in favor of the stack pointer (the offset becomes too
552   large to fit in the instruction's immediate field); a reload is
553   generated to fix this but the RTL is not immediately updated; in
554   the meantime, the constraints are checked and none match.  The
555   solution seems to be to simply skip the offset check here.  The
556   address will be checked anyway because of the code in
557   GO_IF_LEGITIMATE_ADDRESS.  */
558
559#define EXTRA_CONSTRAINT  xtensa_extra_constraint
560
561#define PREFERRED_RELOAD_CLASS(X, CLASS)				\
562  xtensa_preferred_reload_class (X, CLASS, 0)
563
564#define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS)				\
565  xtensa_preferred_reload_class (X, CLASS, 1)
566
567#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X)			\
568  xtensa_secondary_reload_class (CLASS, MODE, X, 0)
569
570#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X)			\
571  xtensa_secondary_reload_class (CLASS, MODE, X, 1)
572
573/* Return the maximum number of consecutive registers
574   needed to represent mode MODE in a register of class CLASS.  */
575#define CLASS_UNITS(mode, size)						\
576  ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
577
578#define CLASS_MAX_NREGS(CLASS, MODE)					\
579  (CLASS_UNITS (MODE, UNITS_PER_WORD))
580
581
582/* Stack layout; function entry, exit and calling.  */
583
584#define STACK_GROWS_DOWNWARD
585
586/* Offset within stack frame to start allocating local variables at.  */
587#define STARTING_FRAME_OFFSET						\
588  current_function_outgoing_args_size
589
590/* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so
591   they are eliminated to either the stack pointer or hard frame pointer.  */
592#define ELIMINABLE_REGS							\
593{{ ARG_POINTER_REGNUM,		STACK_POINTER_REGNUM},			\
594 { ARG_POINTER_REGNUM,		HARD_FRAME_POINTER_REGNUM},		\
595 { FRAME_POINTER_REGNUM,	STACK_POINTER_REGNUM},			\
596 { FRAME_POINTER_REGNUM,	HARD_FRAME_POINTER_REGNUM}}
597
598#define CAN_ELIMINATE(FROM, TO) 1
599
600/* Specify the initial difference between the specified pair of registers.  */
601#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)			\
602  do {									\
603    compute_frame_size (get_frame_size ());				\
604    switch (FROM)							\
605      {									\
606      case FRAME_POINTER_REGNUM:					\
607        (OFFSET) = 0;							\
608	break;								\
609      case ARG_POINTER_REGNUM:						\
610        (OFFSET) = xtensa_current_frame_size;				\
611	break;								\
612      default:								\
613	gcc_unreachable ();						\
614      }									\
615  } while (0)
616
617/* If defined, the maximum amount of space required for outgoing
618   arguments will be computed and placed into the variable
619   'current_function_outgoing_args_size'.  No space will be pushed
620   onto the stack for each call; instead, the function prologue
621   should increase the stack frame size by this amount.  */
622#define ACCUMULATE_OUTGOING_ARGS 1
623
624/* Offset from the argument pointer register to the first argument's
625   address.  On some machines it may depend on the data type of the
626   function.  If 'ARGS_GROW_DOWNWARD', this is the offset to the
627   location above the first argument's address.  */
628#define FIRST_PARM_OFFSET(FNDECL) 0
629
630/* Align stack frames on 128 bits for Xtensa.  This is necessary for
631   128-bit datatypes defined in TIE (e.g., for Vectra).  */
632#define STACK_BOUNDARY 128
633
634/* Functions do not pop arguments off the stack.  */
635#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
636
637/* Use a fixed register window size of 8.  */
638#define WINDOW_SIZE 8
639
640/* Symbolic macros for the registers used to return integer, floating
641   point, and values of coprocessor and user-defined modes.  */
642#define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE)
643#define GP_OUTGOING_RETURN (GP_REG_FIRST + 2)
644
645/* Symbolic macros for the first/last argument registers.  */
646#define GP_ARG_FIRST (GP_REG_FIRST + 2)
647#define GP_ARG_LAST  (GP_REG_FIRST + 7)
648#define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE)
649#define GP_OUTGOING_ARG_LAST  (GP_REG_FIRST + 7 + WINDOW_SIZE)
650
651#define MAX_ARGS_IN_REGISTERS 6
652
653/* Don't worry about compatibility with PCC.  */
654#define DEFAULT_PCC_STRUCT_RETURN 0
655
656/* Define how to find the value returned by a library function
657   assuming the value has mode MODE.  Because we have defined
658   TARGET_PROMOTE_FUNCTION_RETURN that returns true, we have to
659   perform the same promotions as PROMOTE_MODE.  */
660#define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP)				\
661  gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT			\
662		&& GET_MODE_SIZE (MODE) < UNITS_PER_WORD)		\
663	       ? SImode : (MODE),					\
664	       OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
665
666#define LIBCALL_VALUE(MODE)						\
667  XTENSA_LIBCALL_VALUE ((MODE), 0)
668
669#define LIBCALL_OUTGOING_VALUE(MODE)			 		\
670  XTENSA_LIBCALL_VALUE ((MODE), 1)
671
672/* Define how to find the value returned by a function.
673   VALTYPE is the data type of the value (as a tree).
674   If the precise function being called is known, FUNC is its FUNCTION_DECL;
675   otherwise, FUNC is 0.  */
676#define XTENSA_FUNCTION_VALUE(VALTYPE, FUNC, OUTGOINGP)			\
677  gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE)				\
678	        && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD)		\
679	       ? SImode: TYPE_MODE (VALTYPE),				\
680	       OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
681
682#define FUNCTION_VALUE(VALTYPE, FUNC)					\
683  XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 0)
684
685#define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC)				\
686  XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 1)
687
688/* A C expression that is nonzero if REGNO is the number of a hard
689   register in which the values of called function may come back.  A
690   register whose use for returning values is limited to serving as
691   the second of a pair (for a value of type 'double', say) need not
692   be recognized by this macro.  If the machine has register windows,
693   so that the caller and the called function use different registers
694   for the return value, this macro should recognize only the caller's
695   register numbers.  */
696#define FUNCTION_VALUE_REGNO_P(N)					\
697  ((N) == GP_RETURN)
698
699/* A C expression that is nonzero if REGNO is the number of a hard
700   register in which function arguments are sometimes passed.  This
701   does *not* include implicit arguments such as the static chain and
702   the structure-value address.  On many machines, no registers can be
703   used for this purpose since all function arguments are pushed on
704   the stack.  */
705#define FUNCTION_ARG_REGNO_P(N)						\
706  ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST)
707
708/* Record the number of argument words seen so far, along with a flag to
709   indicate whether these are incoming arguments.  (FUNCTION_INCOMING_ARG
710   is used for both incoming and outgoing args, so a separate flag is
711   needed.  */
712typedef struct xtensa_args
713{
714  int arg_words;
715  int incoming;
716} CUMULATIVE_ARGS;
717
718#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
719  init_cumulative_args (&CUM, 0)
720
721#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME)		\
722  init_cumulative_args (&CUM, 1)
723
724/* Update the data in CUM to advance over an argument
725   of mode MODE and data type TYPE.
726   (TYPE is null for libcalls where that information may not be available.)  */
727#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)			\
728  function_arg_advance (&CUM, MODE, TYPE)
729
730#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
731  function_arg (&CUM, MODE, TYPE, FALSE)
732
733#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
734  function_arg (&CUM, MODE, TYPE, TRUE)
735
736/* Specify function argument alignment.  */
737#define FUNCTION_ARG_BOUNDARY(MODE, TYPE)				\
738  ((TYPE) != 0								\
739   ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY				\
740      ? PARM_BOUNDARY							\
741      : TYPE_ALIGN (TYPE))						\
742   : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY			\
743      ? PARM_BOUNDARY							\
744      : GET_MODE_ALIGNMENT (MODE)))
745
746/* Profiling Xtensa code is typically done with the built-in profiling
747   feature of Tensilica's instruction set simulator, which does not
748   require any compiler support.  Profiling code on a real (i.e.,
749   non-simulated) Xtensa processor is currently only supported by
750   GNU/Linux with glibc.  The glibc version of _mcount doesn't require
751   counter variables.  The _mcount function needs the current PC and
752   the current return address to identify an arc in the call graph.
753   Pass the current return address as the first argument; the current
754   PC is available as a0 in _mcount's register window.  Both of these
755   values contain window size information in the two most significant
756   bits; we assume that _mcount will mask off those bits.  The call to
757   _mcount uses a window size of 8 to make sure that it doesn't clobber
758   any incoming argument values.  */
759
760#define NO_PROFILE_COUNTERS	1
761
762#define FUNCTION_PROFILER(FILE, LABELNO) \
763  do {									\
764    fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \
765    if (flag_pic)							\
766      {									\
767	fprintf (FILE, "\tmovi\ta8, _mcount@PLT\n");			\
768	fprintf (FILE, "\tcallx8\ta8\n");				\
769      }									\
770    else								\
771      fprintf (FILE, "\tcall8\t_mcount\n");				\
772  } while (0)
773
774/* Stack pointer value doesn't matter at exit.  */
775#define EXIT_IGNORE_STACK 1
776
777/* A C statement to output, on the stream FILE, assembler code for a
778   block of data that contains the constant parts of a trampoline.
779   This code should not include a label--the label is taken care of
780   automatically.
781
782   For Xtensa, the trampoline must perform an entry instruction with a
783   minimal stack frame in order to get some free registers.  Once the
784   actual call target is known, the proper stack frame size is extracted
785   from the entry instruction at the target and the current frame is
786   adjusted to match.  The trampoline then transfers control to the
787   instruction following the entry at the target.  Note: this assumes
788   that the target begins with an entry instruction.  */
789
790/* minimum frame = reg save area (4 words) plus static chain (1 word)
791   and the total number of words must be a multiple of 128 bits */
792#define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
793
794#define TRAMPOLINE_TEMPLATE(STREAM)					\
795  do {									\
796    fprintf (STREAM, "\t.begin no-transform\n");			\
797    fprintf (STREAM, "\tentry\tsp, %d\n", MIN_FRAME_SIZE);		\
798									\
799    /* save the return address */					\
800    fprintf (STREAM, "\tmov\ta10, a0\n");				\
801									\
802    /* Use a CALL0 instruction to skip past the constants and in the	\
803       process get the PC into A0.  This allows PC-relative access to	\
804       the constants without relying on L32R, which may not always be	\
805       available.  */							\
806									\
807    fprintf (STREAM, "\tcall0\t.Lskipconsts\n");			\
808    fprintf (STREAM, "\t.align\t4\n");					\
809    fprintf (STREAM, ".Lchainval:%s0\n", integer_asm_op (4, TRUE));	\
810    fprintf (STREAM, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE));	\
811    fprintf (STREAM, ".Lskipconsts:\n");				\
812									\
813    /* store the static chain */					\
814    fprintf (STREAM, "\taddi\ta0, a0, 3\n");				\
815    fprintf (STREAM, "\tl32i\ta8, a0, 0\n");				\
816    fprintf (STREAM, "\ts32i\ta8, sp, %d\n", MIN_FRAME_SIZE - 20);	\
817									\
818    /* set the proper stack pointer value */				\
819    fprintf (STREAM, "\tl32i\ta8, a0, 4\n");				\
820    fprintf (STREAM, "\tl32i\ta9, a8, 0\n");				\
821    fprintf (STREAM, "\textui\ta9, a9, %d, 12\n",			\
822	     TARGET_BIG_ENDIAN ? 8 : 12);				\
823    fprintf (STREAM, "\tslli\ta9, a9, 3\n");				\
824    fprintf (STREAM, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE);		\
825    fprintf (STREAM, "\tsub\ta9, sp, a9\n");				\
826    fprintf (STREAM, "\tmovsp\tsp, a9\n");				\
827									\
828    /* restore the return address */					\
829    fprintf (STREAM, "\tmov\ta0, a10\n");				\
830									\
831    /* jump to the instruction following the entry */			\
832    fprintf (STREAM, "\taddi\ta8, a8, 3\n");				\
833    fprintf (STREAM, "\tjx\ta8\n");					\
834    fprintf (STREAM, "\t.byte\t0\n");					\
835    fprintf (STREAM, "\t.end no-transform\n");				\
836  } while (0)
837
838/* Size in bytes of the trampoline, as an integer.  Make sure this is
839   a multiple of TRAMPOLINE_ALIGNMENT to avoid -Wpadded warnings.  */
840#define TRAMPOLINE_SIZE 60
841
842/* Alignment required for trampolines, in bits.  */
843#define TRAMPOLINE_ALIGNMENT (32)
844
845/* A C statement to initialize the variable parts of a trampoline.  */
846#define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN)			\
847  do {									\
848    rtx addr = ADDR;							\
849    emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 12)), CHAIN); \
850    emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 16)), FUNC); \
851    emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_sync_caches"), \
852		       0, VOIDmode, 1, addr, Pmode);			\
853  } while (0)
854
855/* Implement `va_start' for varargs and stdarg.  */
856#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
857  xtensa_va_start (valist, nextarg)
858
859/* If defined, a C expression that produces the machine-specific code
860   to setup the stack so that arbitrary frames can be accessed.
861
862   On Xtensa, a stack back-trace must always begin from the stack pointer,
863   so that the register overflow save area can be located.  However, the
864   stack-walking code in GCC always begins from the hard_frame_pointer
865   register, not the stack pointer.  The frame pointer is usually equal
866   to the stack pointer, but the __builtin_return_address and
867   __builtin_frame_address functions will not work if count > 0 and
868   they are called from a routine that uses alloca.  These functions
869   are not guaranteed to work at all if count > 0 so maybe that is OK.
870
871   A nicer solution would be to allow the architecture-specific files to
872   specify whether to start from the stack pointer or frame pointer.  That
873   would also allow us to skip the machine->accesses_prev_frame stuff that
874   we currently need to ensure that there is a frame pointer when these
875   builtin functions are used.  */
876
877#define SETUP_FRAME_ADDRESSES  xtensa_setup_frame_addresses
878
879/* A C expression whose value is RTL representing the address in a
880   stack frame where the pointer to the caller's frame is stored.
881   Assume that FRAMEADDR is an RTL expression for the address of the
882   stack frame itself.
883
884   For Xtensa, there is no easy way to get the frame pointer if it is
885   not equivalent to the stack pointer.  Moreover, the result of this
886   macro is used for continuing to walk back up the stack, so it must
887   return the stack pointer address.  Thus, there is some inconsistency
888   here in that __builtin_frame_address will return the frame pointer
889   when count == 0 and the stack pointer when count > 0.  */
890
891#define DYNAMIC_CHAIN_ADDRESS(frame)					\
892  gen_rtx_PLUS (Pmode, frame, GEN_INT (-3 * UNITS_PER_WORD))
893
894/* Define this if the return address of a particular stack frame is
895   accessed from the frame pointer of the previous stack frame.  */
896#define RETURN_ADDR_IN_PREVIOUS_FRAME
897
898/* A C expression whose value is RTL representing the value of the
899   return address for the frame COUNT steps up from the current
900   frame, after the prologue.  */
901#define RETURN_ADDR_RTX  xtensa_return_addr
902
903/* Addressing modes, and classification of registers for them.  */
904
905/* C expressions which are nonzero if register number NUM is suitable
906   for use as a base or index register in operand addresses.  It may
907   be either a suitable hard register or a pseudo register that has
908   been allocated such a hard register. The difference between an
909   index register and a base register is that the index register may
910   be scaled.  */
911
912#define REGNO_OK_FOR_BASE_P(NUM) \
913  (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM]))
914
915#define REGNO_OK_FOR_INDEX_P(NUM) 0
916
917/* C expressions that are nonzero if X (assumed to be a `reg' RTX) is
918   valid for use as a base or index register.  For hard registers, it
919   should always accept those which the hardware permits and reject
920   the others.  Whether the macro accepts or rejects pseudo registers
921   must be controlled by `REG_OK_STRICT'.  This usually requires two
922   variant definitions, of which `REG_OK_STRICT' controls the one
923   actually used. The difference between an index register and a base
924   register is that the index register may be scaled.  */
925
926#ifdef REG_OK_STRICT
927
928#define REG_OK_FOR_INDEX_P(X) 0
929#define REG_OK_FOR_BASE_P(X) \
930  REGNO_OK_FOR_BASE_P (REGNO (X))
931
932#else /* !REG_OK_STRICT */
933
934#define REG_OK_FOR_INDEX_P(X) 0
935#define REG_OK_FOR_BASE_P(X) \
936  ((REGNO (X) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (REGNO (X))))
937
938#endif /* !REG_OK_STRICT */
939
940/* Maximum number of registers that can appear in a valid memory address.  */
941#define MAX_REGS_PER_ADDRESS 1
942
943/* Identify valid Xtensa addresses.  */
944#define GO_IF_LEGITIMATE_ADDRESS(MODE, ADDR, LABEL)			\
945  do {									\
946    rtx xinsn = (ADDR);							\
947									\
948    /* allow constant pool addresses */					\
949    if ((MODE) != BLKmode && GET_MODE_SIZE (MODE) >= UNITS_PER_WORD	\
950	&& !TARGET_CONST16 && constantpool_address_p (xinsn))		\
951      goto LABEL;							\
952									\
953    while (GET_CODE (xinsn) == SUBREG)					\
954      xinsn = SUBREG_REG (xinsn);					\
955									\
956    /* allow base registers */						\
957    if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn))		\
958      goto LABEL;							\
959									\
960    /* check for "register + offset" addressing */			\
961    if (GET_CODE (xinsn) == PLUS)					\
962      {									\
963	rtx xplus0 = XEXP (xinsn, 0);					\
964	rtx xplus1 = XEXP (xinsn, 1);					\
965	enum rtx_code code0;						\
966	enum rtx_code code1;						\
967									\
968	while (GET_CODE (xplus0) == SUBREG)				\
969	  xplus0 = SUBREG_REG (xplus0);					\
970	code0 = GET_CODE (xplus0);					\
971									\
972	while (GET_CODE (xplus1) == SUBREG)				\
973	  xplus1 = SUBREG_REG (xplus1);					\
974	code1 = GET_CODE (xplus1);					\
975									\
976	/* swap operands if necessary so the register is first */	\
977	if (code0 != REG && code1 == REG)				\
978	  {								\
979	    xplus0 = XEXP (xinsn, 1);					\
980	    xplus1 = XEXP (xinsn, 0);					\
981	    code0 = GET_CODE (xplus0);					\
982	    code1 = GET_CODE (xplus1);					\
983	  }								\
984									\
985	if (code0 == REG && REG_OK_FOR_BASE_P (xplus0)			\
986	    && code1 == CONST_INT					\
987	    && xtensa_mem_offset (INTVAL (xplus1), (MODE)))		\
988	  {								\
989	    goto LABEL;							\
990	  }								\
991      }									\
992  } while (0)
993
994/* A C expression that is 1 if the RTX X is a constant which is a
995   valid address.  This is defined to be the same as 'CONSTANT_P (X)',
996   but rejecting CONST_DOUBLE.  */
997#define CONSTANT_ADDRESS_P(X)						\
998  ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
999    || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH		\
1000    || (GET_CODE (X) == CONST)))
1001
1002/* Nonzero if the constant value X is a legitimate general operand.
1003   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
1004#define LEGITIMATE_CONSTANT_P(X) 1
1005
1006/* A C expression that is nonzero if X is a legitimate immediate
1007   operand on the target machine when generating position independent
1008   code.  */
1009#define LEGITIMATE_PIC_OPERAND_P(X)					\
1010  ((GET_CODE (X) != SYMBOL_REF						\
1011    || (SYMBOL_REF_LOCAL_P (X) && !SYMBOL_REF_EXTERNAL_P (X)))		\
1012   && GET_CODE (X) != LABEL_REF						\
1013   && GET_CODE (X) != CONST)
1014
1015/* Tell GCC how to use ADDMI to generate addresses.  */
1016#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)				\
1017  do {									\
1018    rtx xinsn = (X);							\
1019    if (GET_CODE (xinsn) == PLUS)					\
1020      { 								\
1021	rtx plus0 = XEXP (xinsn, 0);					\
1022	rtx plus1 = XEXP (xinsn, 1);					\
1023									\
1024	if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)		\
1025	  {								\
1026	    plus0 = XEXP (xinsn, 1);					\
1027	    plus1 = XEXP (xinsn, 0);					\
1028	  }								\
1029									\
1030	if (GET_CODE (plus0) == REG					\
1031	    && GET_CODE (plus1) == CONST_INT				\
1032	    && !xtensa_mem_offset (INTVAL (plus1), MODE)		\
1033	    && !xtensa_simm8 (INTVAL (plus1))				\
1034	    && xtensa_mem_offset (INTVAL (plus1) & 0xff, MODE)		\
1035	    && xtensa_simm8x256 (INTVAL (plus1) & ~0xff))		\
1036	  {								\
1037	    rtx temp = gen_reg_rtx (Pmode);				\
1038	    emit_insn (gen_rtx_SET (Pmode, temp,			\
1039				gen_rtx_PLUS (Pmode, plus0,		\
1040					 GEN_INT (INTVAL (plus1) & ~0xff)))); \
1041	    (X) = gen_rtx_PLUS (Pmode, temp,				\
1042			   GEN_INT (INTVAL (plus1) & 0xff));		\
1043	    goto WIN;							\
1044	  }								\
1045      }									\
1046  } while (0)
1047
1048
1049/* Treat constant-pool references as "mode dependent" since they can
1050   only be accessed with SImode loads.  This works around a bug in the
1051   combiner where a constant pool reference is temporarily converted
1052   to an HImode load, which is then assumed to zero-extend based on
1053   our definition of LOAD_EXTEND_OP.  This is wrong because the high
1054   bits of a 16-bit value in the constant pool are now sign-extended
1055   by default.  */
1056
1057#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)			\
1058  do {									\
1059    if (constantpool_address_p (ADDR))					\
1060      goto LABEL;							\
1061  } while (0)
1062
1063/* Specify the machine mode that this machine uses
1064   for the index in the tablejump instruction.  */
1065#define CASE_VECTOR_MODE (SImode)
1066
1067/* Define this as 1 if 'char' should by default be signed; else as 0.  */
1068#define DEFAULT_SIGNED_CHAR 0
1069
1070/* Max number of bytes we can move from memory to memory
1071   in one reasonably fast instruction.  */
1072#define MOVE_MAX 4
1073#define MAX_MOVE_MAX 4
1074
1075/* Prefer word-sized loads.  */
1076#define SLOW_BYTE_ACCESS 1
1077
1078/* Shift instructions ignore all but the low-order few bits.  */
1079#define SHIFT_COUNT_TRUNCATED 1
1080
1081/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1082   is done just by pretending it is already truncated.  */
1083#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1084
1085/* Specify the machine mode that pointers have.
1086   After generation of rtl, the compiler makes no further distinction
1087   between pointers and any other objects of this machine mode.  */
1088#define Pmode SImode
1089
1090/* A function address in a call instruction is a word address (for
1091   indexing purposes) so give the MEM rtx a words's mode.  */
1092#define FUNCTION_MODE SImode
1093
1094/* A C expression for the cost of moving data from a register in
1095   class FROM to one in class TO.  The classes are expressed using
1096   the enumeration values such as 'GENERAL_REGS'.  A value of 2 is
1097   the default; other values are interpreted relative to that.  */
1098#define REGISTER_MOVE_COST(MODE, FROM, TO)				\
1099  (((FROM) == (TO) && (FROM) != BR_REGS && (TO) != BR_REGS)		\
1100   ? 2									\
1101   : (reg_class_subset_p ((FROM), AR_REGS)				\
1102      && reg_class_subset_p ((TO), AR_REGS)				\
1103      ? 2								\
1104      : (reg_class_subset_p ((FROM), AR_REGS)				\
1105	 && (TO) == ACC_REG						\
1106	 ? 3								\
1107	 : ((FROM) == ACC_REG						\
1108	    && reg_class_subset_p ((TO), AR_REGS)			\
1109	    ? 3								\
1110	    : 10))))
1111
1112#define MEMORY_MOVE_COST(MODE, CLASS, IN) 4
1113
1114#define BRANCH_COST 3
1115
1116/* How to refer to registers in assembler output.
1117   This sequence is indexed by compiler's hard-register-number (see above).  */
1118#define REGISTER_NAMES							\
1119{									\
1120  "a0",   "sp",   "a2",   "a3",   "a4",   "a5",   "a6",   "a7",		\
1121  "a8",   "a9",   "a10",  "a11",  "a12",  "a13",  "a14",  "a15",	\
1122  "fp",   "argp", "b0",							\
1123  "f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7",		\
1124  "f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15",	\
1125  "acc"									\
1126}
1127
1128/* If defined, a C initializer for an array of structures containing a
1129   name and a register number.  This macro defines additional names
1130   for hard registers, thus allowing the 'asm' option in declarations
1131   to refer to registers using alternate names.  */
1132#define ADDITIONAL_REGISTER_NAMES					\
1133{									\
1134  { "a1",	 1 + GP_REG_FIRST }					\
1135}
1136
1137#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1138#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1139
1140/* Recognize machine-specific patterns that may appear within
1141   constants.  Used for PIC-specific UNSPECs.  */
1142#define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL)			\
1143  do {									\
1144    if (flag_pic && GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1)	\
1145      {									\
1146	switch (XINT ((X), 1))						\
1147	  {								\
1148	  case UNSPEC_PLT:						\
1149	    output_addr_const ((STREAM), XVECEXP ((X), 0, 0));		\
1150	    fputs ("@PLT", (STREAM));					\
1151	    break;							\
1152	  default:							\
1153	    goto FAIL;							\
1154	  }								\
1155	break;								\
1156      }									\
1157    else								\
1158      goto FAIL;							\
1159  } while (0)
1160
1161/* Globalizing directive for a label.  */
1162#define GLOBAL_ASM_OP "\t.global\t"
1163
1164/* Declare an uninitialized external linkage data object.  */
1165#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1166  asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1167
1168/* This is how to output an element of a case-vector that is absolute.  */
1169#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)				\
1170  fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE),		\
1171	   LOCAL_LABEL_PREFIX, VALUE)
1172
1173/* This is how to output an element of a case-vector that is relative.
1174   This is used for pc-relative code.  */
1175#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)		\
1176  do {									\
1177    fprintf (STREAM, "%s%sL%u-%sL%u\n",	integer_asm_op (4, TRUE),	\
1178	     LOCAL_LABEL_PREFIX, (VALUE),				\
1179	     LOCAL_LABEL_PREFIX, (REL));				\
1180  } while (0)
1181
1182/* This is how to output an assembler line that says to advance the
1183   location counter to a multiple of 2**LOG bytes.  */
1184#define ASM_OUTPUT_ALIGN(STREAM, LOG)					\
1185  do {									\
1186    if ((LOG) != 0)							\
1187      fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG));			\
1188  } while (0)
1189
1190/* Indicate that jump tables go in the text section.  This is
1191   necessary when compiling PIC code.  */
1192#define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1193
1194
1195/* Define the strings to put out for each section in the object file.  */
1196#define TEXT_SECTION_ASM_OP	"\t.text"
1197#define DATA_SECTION_ASM_OP	"\t.data"
1198#define BSS_SECTION_ASM_OP	"\t.section\t.bss"
1199
1200
1201/* Define output to appear before the constant pool.  If the function
1202   has been assigned to a specific ELF section, or if it goes into a
1203   unique section, set the name of that section to be the literal
1204   prefix.  */
1205#define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE)          \
1206  do {									\
1207    tree fnsection;							\
1208    resolve_unique_section ((FUNDECL), 0, flag_function_sections);	\
1209    fnsection = DECL_SECTION_NAME (FUNDECL);				\
1210    if (fnsection != NULL_TREE)						\
1211      {									\
1212	const char *fnsectname = TREE_STRING_POINTER (fnsection);	\
1213	fprintf (FILE, "\t.begin\tliteral_prefix %s\n",			\
1214		 strcmp (fnsectname, ".text") ? fnsectname : "");	\
1215      }									\
1216    if ((SIZE) > 0)							\
1217      {									\
1218	function_section (FUNDECL);  					\
1219	fprintf (FILE, "\t.literal_position\n");			\
1220      }									\
1221  } while (0)
1222
1223
1224/* Define code to write out the ".end literal_prefix" directive for a
1225   function in a special section.  This is appended to the standard ELF
1226   code for ASM_DECLARE_FUNCTION_SIZE.  */
1227#define XTENSA_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL)			\
1228  if (DECL_SECTION_NAME (DECL) != NULL_TREE)				\
1229    fprintf (FILE, "\t.end\tliteral_prefix\n")
1230
1231/* A C statement (with or without semicolon) to output a constant in
1232   the constant pool, if it needs special treatment.  */
1233#define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \
1234  do {									\
1235    xtensa_output_literal (FILE, X, MODE, LABELNO);			\
1236    goto JUMPTO;							\
1237  } while (0)
1238
1239/* How to start an assembler comment.  */
1240#define ASM_COMMENT_START "#"
1241
1242/* Exception handling TODO!! */
1243#define DWARF_UNWIND_INFO 0
1244
1245/* Xtensa constant pool breaks the devices in crtstuff.c to control
1246   section in where code resides.  We have to write it as asm code.  Use
1247   a MOVI and let the assembler relax it -- for the .init and .fini
1248   sections, the assembler knows to put the literal in the right
1249   place.  */
1250#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
1251    asm (SECTION_OP "\n\
1252	movi\ta8, " USER_LABEL_PREFIX #FUNC "\n\
1253	callx8\ta8\n" \
1254	TEXT_SECTION_ASM_OP);
1255