1/* Subroutines used for code generation on IBM RS/6000. 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2004, 2005, 2006 4 Free Software Foundation, Inc. 5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 6 7 This file is part of GCC. 8 9 GCC is free software; you can redistribute it and/or modify it 10 under the terms of the GNU General Public License as published 11 by the Free Software Foundation; either version 2, or (at your 12 option) any later version. 13 14 GCC is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GCC; see the file COPYING. If not, write to the 21 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 22 MA 02110-1301, USA. */ 23 24#include "config.h" 25#include "system.h" 26#include "coretypes.h" 27#include "tm.h" 28#include "rtl.h" 29#include "regs.h" 30#include "hard-reg-set.h" 31#include "real.h" 32#include "insn-config.h" 33#include "conditions.h" 34#include "insn-attr.h" 35#include "flags.h" 36#include "recog.h" 37#include "obstack.h" 38#include "tree.h" 39#include "expr.h" 40#include "optabs.h" 41#include "except.h" 42#include "function.h" 43#include "output.h" 44#include "basic-block.h" 45#include "integrate.h" 46#include "toplev.h" 47#include "ggc.h" 48#include "hashtab.h" 49#include "tm_p.h" 50#include "target.h" 51#include "target-def.h" 52#include "langhooks.h" 53#include "reload.h" 54#include "cfglayout.h" 55#include "sched-int.h" 56#include "tree-gimple.h" 57#include "intl.h" 58#include "params.h" 59#if TARGET_XCOFF 60#include "xcoffout.h" /* get declarations of xcoff_*_section_name */ 61#endif 62#if TARGET_MACHO 63#include "gstab.h" /* for N_SLINE */ 64#endif 65 66#ifndef TARGET_NO_PROTOTYPE 67#define TARGET_NO_PROTOTYPE 0 68#endif 69 70#define min(A,B) ((A) < (B) ? (A) : (B)) 71#define max(A,B) ((A) > (B) ? (A) : (B)) 72 73/* Structure used to define the rs6000 stack */ 74typedef struct rs6000_stack { 75 int first_gp_reg_save; /* first callee saved GP register used */ 76 int first_fp_reg_save; /* first callee saved FP register used */ 77 int first_altivec_reg_save; /* first callee saved AltiVec register used */ 78 int lr_save_p; /* true if the link reg needs to be saved */ 79 int cr_save_p; /* true if the CR reg needs to be saved */ 80 unsigned int vrsave_mask; /* mask of vec registers to save */ 81 int toc_save_p; /* true if the TOC needs to be saved */ 82 int push_p; /* true if we need to allocate stack space */ 83 int calls_p; /* true if the function makes any calls */ 84 int world_save_p; /* true if we're saving *everything*: 85 r13-r31, cr, f14-f31, vrsave, v20-v31 */ 86 enum rs6000_abi abi; /* which ABI to use */ 87 int gp_save_offset; /* offset to save GP regs from initial SP */ 88 int fp_save_offset; /* offset to save FP regs from initial SP */ 89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */ 90 int lr_save_offset; /* offset to save LR from initial SP */ 91 int cr_save_offset; /* offset to save CR from initial SP */ 92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */ 93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */ 94 int toc_save_offset; /* offset to save the TOC pointer */ 95 int varargs_save_offset; /* offset to save the varargs registers */ 96 int ehrd_offset; /* offset to EH return data */ 97 int reg_size; /* register size (4 or 8) */ 98 HOST_WIDE_INT vars_size; /* variable save area size */ 99 int parm_size; /* outgoing parameter size */ 100 int save_size; /* save area size */ 101 int fixed_size; /* fixed size of stack frame */ 102 int gp_size; /* size of saved GP registers */ 103 int fp_size; /* size of saved FP registers */ 104 int altivec_size; /* size of saved AltiVec registers */ 105 int cr_size; /* size to hold CR if not in save_size */ 106 int lr_size; /* size to hold LR if not in save_size */ 107 int vrsave_size; /* size to hold VRSAVE if not in save_size */ 108 int altivec_padding_size; /* size of altivec alignment padding if 109 not in save_size */ 110 int spe_gp_size; /* size of 64-bit GPR save size for SPE */ 111 int spe_padding_size; 112 int toc_size; /* size to hold TOC if not in save_size */ 113 HOST_WIDE_INT total_size; /* total bytes allocated for stack */ 114 int spe_64bit_regs_used; 115} rs6000_stack_t; 116 117/* A C structure for machine-specific, per-function data. 118 This is added to the cfun structure. */ 119typedef struct machine_function GTY(()) 120{ 121 /* Flags if __builtin_return_address (n) with n >= 1 was used. */ 122 int ra_needs_full_frame; 123 /* Some local-dynamic symbol. */ 124 const char *some_ld_name; 125 /* Whether the instruction chain has been scanned already. */ 126 int insn_chain_scanned_p; 127 /* Flags if __builtin_return_address (0) was used. */ 128 int ra_need_lr; 129 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4 130 varargs save area. */ 131 HOST_WIDE_INT varargs_save_offset; 132} machine_function; 133 134/* Target cpu type */ 135 136enum processor_type rs6000_cpu; 137struct rs6000_cpu_select rs6000_select[3] = 138{ 139 /* switch name, tune arch */ 140 { (const char *)0, "--with-cpu=", 1, 1 }, 141 { (const char *)0, "-mcpu=", 1, 1 }, 142 { (const char *)0, "-mtune=", 1, 0 }, 143}; 144 145/* Always emit branch hint bits. */ 146static GTY(()) bool rs6000_always_hint; 147 148/* Schedule instructions for group formation. */ 149static GTY(()) bool rs6000_sched_groups; 150 151/* Support for -msched-costly-dep option. */ 152const char *rs6000_sched_costly_dep_str; 153enum rs6000_dependence_cost rs6000_sched_costly_dep; 154 155/* Support for -minsert-sched-nops option. */ 156const char *rs6000_sched_insert_nops_str; 157enum rs6000_nop_insertion rs6000_sched_insert_nops; 158 159/* Support targetm.vectorize.builtin_mask_for_load. */ 160static GTY(()) tree altivec_builtin_mask_for_load; 161 162/* Size of long double. */ 163int rs6000_long_double_type_size; 164 165/* IEEE quad extended precision long double. */ 166int rs6000_ieeequad; 167 168/* Whether -mabi=altivec has appeared. */ 169int rs6000_altivec_abi; 170 171/* Nonzero if we want SPE ABI extensions. */ 172int rs6000_spe_abi; 173 174/* Nonzero if floating point operations are done in the GPRs. */ 175int rs6000_float_gprs = 0; 176 177/* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */ 178int rs6000_darwin64_abi; 179 180/* Set to nonzero once AIX common-mode calls have been defined. */ 181static GTY(()) int common_mode_defined; 182 183/* Save information from a "cmpxx" operation until the branch or scc is 184 emitted. */ 185rtx rs6000_compare_op0, rs6000_compare_op1; 186int rs6000_compare_fp_p; 187 188/* Label number of label created for -mrelocatable, to call to so we can 189 get the address of the GOT section */ 190int rs6000_pic_labelno; 191 192#ifdef USING_ELFOS_H 193/* Which abi to adhere to */ 194const char *rs6000_abi_name; 195 196/* Semantics of the small data area */ 197enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; 198 199/* Which small data model to use */ 200const char *rs6000_sdata_name = (char *)0; 201 202/* Counter for labels which are to be placed in .fixup. */ 203int fixuplabelno = 0; 204#endif 205 206/* Bit size of immediate TLS offsets and string from which it is decoded. */ 207int rs6000_tls_size = 32; 208const char *rs6000_tls_size_string; 209 210/* ABI enumeration available for subtarget to use. */ 211enum rs6000_abi rs6000_current_abi; 212 213/* Whether to use variant of AIX ABI for PowerPC64 Linux. */ 214int dot_symbols; 215 216/* Debug flags */ 217const char *rs6000_debug_name; 218int rs6000_debug_stack; /* debug stack applications */ 219int rs6000_debug_arg; /* debug argument handling */ 220 221/* Value is TRUE if register/mode pair is acceptable. */ 222bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; 223 224/* Built in types. */ 225 226tree rs6000_builtin_types[RS6000_BTI_MAX]; 227tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; 228 229const char *rs6000_traceback_name; 230static enum { 231 traceback_default = 0, 232 traceback_none, 233 traceback_part, 234 traceback_full 235} rs6000_traceback; 236 237/* Flag to say the TOC is initialized */ 238int toc_initialized; 239char toc_label_name[10]; 240 241/* Alias set for saves and restores from the rs6000 stack. */ 242static GTY(()) int rs6000_sr_alias_set; 243 244/* Control alignment for fields within structures. */ 245/* String from -malign-XXXXX. */ 246int rs6000_alignment_flags; 247 248/* True for any options that were explicitly set. */ 249struct { 250 bool aix_struct_ret; /* True if -maix-struct-ret was used. */ 251 bool alignment; /* True if -malign- was used. */ 252 bool abi; /* True if -mabi=spe/nospe was used. */ 253 bool spe; /* True if -mspe= was used. */ 254 bool float_gprs; /* True if -mfloat-gprs= was used. */ 255 bool isel; /* True if -misel was used. */ 256 bool long_double; /* True if -mlong-double- was used. */ 257 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */ 258} rs6000_explicit_options; 259 260struct builtin_description 261{ 262 /* mask is not const because we're going to alter it below. This 263 nonsense will go away when we rewrite the -march infrastructure 264 to give us more target flag bits. */ 265 unsigned int mask; 266 const enum insn_code icode; 267 const char *const name; 268 const enum rs6000_builtins code; 269}; 270 271/* Target cpu costs. */ 272 273struct processor_costs { 274 const int mulsi; /* cost of SImode multiplication. */ 275 const int mulsi_const; /* cost of SImode multiplication by constant. */ 276 const int mulsi_const9; /* cost of SImode mult by short constant. */ 277 const int muldi; /* cost of DImode multiplication. */ 278 const int divsi; /* cost of SImode division. */ 279 const int divdi; /* cost of DImode division. */ 280 const int fp; /* cost of simple SFmode and DFmode insns. */ 281 const int dmul; /* cost of DFmode multiplication (and fmadd). */ 282 const int sdiv; /* cost of SFmode division (fdivs). */ 283 const int ddiv; /* cost of DFmode division (fdiv). */ 284}; 285 286const struct processor_costs *rs6000_cost; 287 288/* Processor costs (relative to an add) */ 289 290/* Instruction size costs on 32bit processors. */ 291static const 292struct processor_costs size32_cost = { 293 COSTS_N_INSNS (1), /* mulsi */ 294 COSTS_N_INSNS (1), /* mulsi_const */ 295 COSTS_N_INSNS (1), /* mulsi_const9 */ 296 COSTS_N_INSNS (1), /* muldi */ 297 COSTS_N_INSNS (1), /* divsi */ 298 COSTS_N_INSNS (1), /* divdi */ 299 COSTS_N_INSNS (1), /* fp */ 300 COSTS_N_INSNS (1), /* dmul */ 301 COSTS_N_INSNS (1), /* sdiv */ 302 COSTS_N_INSNS (1), /* ddiv */ 303}; 304 305/* Instruction size costs on 64bit processors. */ 306static const 307struct processor_costs size64_cost = { 308 COSTS_N_INSNS (1), /* mulsi */ 309 COSTS_N_INSNS (1), /* mulsi_const */ 310 COSTS_N_INSNS (1), /* mulsi_const9 */ 311 COSTS_N_INSNS (1), /* muldi */ 312 COSTS_N_INSNS (1), /* divsi */ 313 COSTS_N_INSNS (1), /* divdi */ 314 COSTS_N_INSNS (1), /* fp */ 315 COSTS_N_INSNS (1), /* dmul */ 316 COSTS_N_INSNS (1), /* sdiv */ 317 COSTS_N_INSNS (1), /* ddiv */ 318}; 319 320/* Instruction costs on RIOS1 processors. */ 321static const 322struct processor_costs rios1_cost = { 323 COSTS_N_INSNS (5), /* mulsi */ 324 COSTS_N_INSNS (4), /* mulsi_const */ 325 COSTS_N_INSNS (3), /* mulsi_const9 */ 326 COSTS_N_INSNS (5), /* muldi */ 327 COSTS_N_INSNS (19), /* divsi */ 328 COSTS_N_INSNS (19), /* divdi */ 329 COSTS_N_INSNS (2), /* fp */ 330 COSTS_N_INSNS (2), /* dmul */ 331 COSTS_N_INSNS (19), /* sdiv */ 332 COSTS_N_INSNS (19), /* ddiv */ 333}; 334 335/* Instruction costs on RIOS2 processors. */ 336static const 337struct processor_costs rios2_cost = { 338 COSTS_N_INSNS (2), /* mulsi */ 339 COSTS_N_INSNS (2), /* mulsi_const */ 340 COSTS_N_INSNS (2), /* mulsi_const9 */ 341 COSTS_N_INSNS (2), /* muldi */ 342 COSTS_N_INSNS (13), /* divsi */ 343 COSTS_N_INSNS (13), /* divdi */ 344 COSTS_N_INSNS (2), /* fp */ 345 COSTS_N_INSNS (2), /* dmul */ 346 COSTS_N_INSNS (17), /* sdiv */ 347 COSTS_N_INSNS (17), /* ddiv */ 348}; 349 350/* Instruction costs on RS64A processors. */ 351static const 352struct processor_costs rs64a_cost = { 353 COSTS_N_INSNS (20), /* mulsi */ 354 COSTS_N_INSNS (12), /* mulsi_const */ 355 COSTS_N_INSNS (8), /* mulsi_const9 */ 356 COSTS_N_INSNS (34), /* muldi */ 357 COSTS_N_INSNS (65), /* divsi */ 358 COSTS_N_INSNS (67), /* divdi */ 359 COSTS_N_INSNS (4), /* fp */ 360 COSTS_N_INSNS (4), /* dmul */ 361 COSTS_N_INSNS (31), /* sdiv */ 362 COSTS_N_INSNS (31), /* ddiv */ 363}; 364 365/* Instruction costs on MPCCORE processors. */ 366static const 367struct processor_costs mpccore_cost = { 368 COSTS_N_INSNS (2), /* mulsi */ 369 COSTS_N_INSNS (2), /* mulsi_const */ 370 COSTS_N_INSNS (2), /* mulsi_const9 */ 371 COSTS_N_INSNS (2), /* muldi */ 372 COSTS_N_INSNS (6), /* divsi */ 373 COSTS_N_INSNS (6), /* divdi */ 374 COSTS_N_INSNS (4), /* fp */ 375 COSTS_N_INSNS (5), /* dmul */ 376 COSTS_N_INSNS (10), /* sdiv */ 377 COSTS_N_INSNS (17), /* ddiv */ 378}; 379 380/* Instruction costs on PPC403 processors. */ 381static const 382struct processor_costs ppc403_cost = { 383 COSTS_N_INSNS (4), /* mulsi */ 384 COSTS_N_INSNS (4), /* mulsi_const */ 385 COSTS_N_INSNS (4), /* mulsi_const9 */ 386 COSTS_N_INSNS (4), /* muldi */ 387 COSTS_N_INSNS (33), /* divsi */ 388 COSTS_N_INSNS (33), /* divdi */ 389 COSTS_N_INSNS (11), /* fp */ 390 COSTS_N_INSNS (11), /* dmul */ 391 COSTS_N_INSNS (11), /* sdiv */ 392 COSTS_N_INSNS (11), /* ddiv */ 393}; 394 395/* Instruction costs on PPC405 processors. */ 396static const 397struct processor_costs ppc405_cost = { 398 COSTS_N_INSNS (5), /* mulsi */ 399 COSTS_N_INSNS (4), /* mulsi_const */ 400 COSTS_N_INSNS (3), /* mulsi_const9 */ 401 COSTS_N_INSNS (5), /* muldi */ 402 COSTS_N_INSNS (35), /* divsi */ 403 COSTS_N_INSNS (35), /* divdi */ 404 COSTS_N_INSNS (11), /* fp */ 405 COSTS_N_INSNS (11), /* dmul */ 406 COSTS_N_INSNS (11), /* sdiv */ 407 COSTS_N_INSNS (11), /* ddiv */ 408}; 409 410/* Instruction costs on PPC440 processors. */ 411static const 412struct processor_costs ppc440_cost = { 413 COSTS_N_INSNS (3), /* mulsi */ 414 COSTS_N_INSNS (2), /* mulsi_const */ 415 COSTS_N_INSNS (2), /* mulsi_const9 */ 416 COSTS_N_INSNS (3), /* muldi */ 417 COSTS_N_INSNS (34), /* divsi */ 418 COSTS_N_INSNS (34), /* divdi */ 419 COSTS_N_INSNS (5), /* fp */ 420 COSTS_N_INSNS (5), /* dmul */ 421 COSTS_N_INSNS (19), /* sdiv */ 422 COSTS_N_INSNS (33), /* ddiv */ 423}; 424 425/* Instruction costs on PPC601 processors. */ 426static const 427struct processor_costs ppc601_cost = { 428 COSTS_N_INSNS (5), /* mulsi */ 429 COSTS_N_INSNS (5), /* mulsi_const */ 430 COSTS_N_INSNS (5), /* mulsi_const9 */ 431 COSTS_N_INSNS (5), /* muldi */ 432 COSTS_N_INSNS (36), /* divsi */ 433 COSTS_N_INSNS (36), /* divdi */ 434 COSTS_N_INSNS (4), /* fp */ 435 COSTS_N_INSNS (5), /* dmul */ 436 COSTS_N_INSNS (17), /* sdiv */ 437 COSTS_N_INSNS (31), /* ddiv */ 438}; 439 440/* Instruction costs on PPC603 processors. */ 441static const 442struct processor_costs ppc603_cost = { 443 COSTS_N_INSNS (5), /* mulsi */ 444 COSTS_N_INSNS (3), /* mulsi_const */ 445 COSTS_N_INSNS (2), /* mulsi_const9 */ 446 COSTS_N_INSNS (5), /* muldi */ 447 COSTS_N_INSNS (37), /* divsi */ 448 COSTS_N_INSNS (37), /* divdi */ 449 COSTS_N_INSNS (3), /* fp */ 450 COSTS_N_INSNS (4), /* dmul */ 451 COSTS_N_INSNS (18), /* sdiv */ 452 COSTS_N_INSNS (33), /* ddiv */ 453}; 454 455/* Instruction costs on PPC604 processors. */ 456static const 457struct processor_costs ppc604_cost = { 458 COSTS_N_INSNS (4), /* mulsi */ 459 COSTS_N_INSNS (4), /* mulsi_const */ 460 COSTS_N_INSNS (4), /* mulsi_const9 */ 461 COSTS_N_INSNS (4), /* muldi */ 462 COSTS_N_INSNS (20), /* divsi */ 463 COSTS_N_INSNS (20), /* divdi */ 464 COSTS_N_INSNS (3), /* fp */ 465 COSTS_N_INSNS (3), /* dmul */ 466 COSTS_N_INSNS (18), /* sdiv */ 467 COSTS_N_INSNS (32), /* ddiv */ 468}; 469 470/* Instruction costs on PPC604e processors. */ 471static const 472struct processor_costs ppc604e_cost = { 473 COSTS_N_INSNS (2), /* mulsi */ 474 COSTS_N_INSNS (2), /* mulsi_const */ 475 COSTS_N_INSNS (2), /* mulsi_const9 */ 476 COSTS_N_INSNS (2), /* muldi */ 477 COSTS_N_INSNS (20), /* divsi */ 478 COSTS_N_INSNS (20), /* divdi */ 479 COSTS_N_INSNS (3), /* fp */ 480 COSTS_N_INSNS (3), /* dmul */ 481 COSTS_N_INSNS (18), /* sdiv */ 482 COSTS_N_INSNS (32), /* ddiv */ 483}; 484 485/* Instruction costs on PPC620 processors. */ 486static const 487struct processor_costs ppc620_cost = { 488 COSTS_N_INSNS (5), /* mulsi */ 489 COSTS_N_INSNS (4), /* mulsi_const */ 490 COSTS_N_INSNS (3), /* mulsi_const9 */ 491 COSTS_N_INSNS (7), /* muldi */ 492 COSTS_N_INSNS (21), /* divsi */ 493 COSTS_N_INSNS (37), /* divdi */ 494 COSTS_N_INSNS (3), /* fp */ 495 COSTS_N_INSNS (3), /* dmul */ 496 COSTS_N_INSNS (18), /* sdiv */ 497 COSTS_N_INSNS (32), /* ddiv */ 498}; 499 500/* Instruction costs on PPC630 processors. */ 501static const 502struct processor_costs ppc630_cost = { 503 COSTS_N_INSNS (5), /* mulsi */ 504 COSTS_N_INSNS (4), /* mulsi_const */ 505 COSTS_N_INSNS (3), /* mulsi_const9 */ 506 COSTS_N_INSNS (7), /* muldi */ 507 COSTS_N_INSNS (21), /* divsi */ 508 COSTS_N_INSNS (37), /* divdi */ 509 COSTS_N_INSNS (3), /* fp */ 510 COSTS_N_INSNS (3), /* dmul */ 511 COSTS_N_INSNS (17), /* sdiv */ 512 COSTS_N_INSNS (21), /* ddiv */ 513}; 514 515/* Instruction costs on PPC750 and PPC7400 processors. */ 516static const 517struct processor_costs ppc750_cost = { 518 COSTS_N_INSNS (5), /* mulsi */ 519 COSTS_N_INSNS (3), /* mulsi_const */ 520 COSTS_N_INSNS (2), /* mulsi_const9 */ 521 COSTS_N_INSNS (5), /* muldi */ 522 COSTS_N_INSNS (17), /* divsi */ 523 COSTS_N_INSNS (17), /* divdi */ 524 COSTS_N_INSNS (3), /* fp */ 525 COSTS_N_INSNS (3), /* dmul */ 526 COSTS_N_INSNS (17), /* sdiv */ 527 COSTS_N_INSNS (31), /* ddiv */ 528}; 529 530/* Instruction costs on PPC7450 processors. */ 531static const 532struct processor_costs ppc7450_cost = { 533 COSTS_N_INSNS (4), /* mulsi */ 534 COSTS_N_INSNS (3), /* mulsi_const */ 535 COSTS_N_INSNS (3), /* mulsi_const9 */ 536 COSTS_N_INSNS (4), /* muldi */ 537 COSTS_N_INSNS (23), /* divsi */ 538 COSTS_N_INSNS (23), /* divdi */ 539 COSTS_N_INSNS (5), /* fp */ 540 COSTS_N_INSNS (5), /* dmul */ 541 COSTS_N_INSNS (21), /* sdiv */ 542 COSTS_N_INSNS (35), /* ddiv */ 543}; 544 545/* Instruction costs on PPC8540 processors. */ 546static const 547struct processor_costs ppc8540_cost = { 548 COSTS_N_INSNS (4), /* mulsi */ 549 COSTS_N_INSNS (4), /* mulsi_const */ 550 COSTS_N_INSNS (4), /* mulsi_const9 */ 551 COSTS_N_INSNS (4), /* muldi */ 552 COSTS_N_INSNS (19), /* divsi */ 553 COSTS_N_INSNS (19), /* divdi */ 554 COSTS_N_INSNS (4), /* fp */ 555 COSTS_N_INSNS (4), /* dmul */ 556 COSTS_N_INSNS (29), /* sdiv */ 557 COSTS_N_INSNS (29), /* ddiv */ 558}; 559 560/* Instruction costs on POWER4 and POWER5 processors. */ 561static const 562struct processor_costs power4_cost = { 563 COSTS_N_INSNS (3), /* mulsi */ 564 COSTS_N_INSNS (2), /* mulsi_const */ 565 COSTS_N_INSNS (2), /* mulsi_const9 */ 566 COSTS_N_INSNS (4), /* muldi */ 567 COSTS_N_INSNS (18), /* divsi */ 568 COSTS_N_INSNS (34), /* divdi */ 569 COSTS_N_INSNS (3), /* fp */ 570 COSTS_N_INSNS (3), /* dmul */ 571 COSTS_N_INSNS (17), /* sdiv */ 572 COSTS_N_INSNS (17), /* ddiv */ 573}; 574 575 576static bool rs6000_function_ok_for_sibcall (tree, tree); 577static const char *rs6000_invalid_within_doloop (rtx); 578static rtx rs6000_generate_compare (enum rtx_code); 579static void rs6000_maybe_dead (rtx); 580static void rs6000_emit_stack_tie (void); 581static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx); 582static rtx spe_synthesize_frame_save (rtx); 583static bool spe_func_has_64bit_regs_p (void); 584static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int, 585 int, HOST_WIDE_INT); 586static rtx gen_frame_mem_offset (enum machine_mode, rtx, int); 587static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int); 588static unsigned rs6000_hash_constant (rtx); 589static unsigned toc_hash_function (const void *); 590static int toc_hash_eq (const void *, const void *); 591static int constant_pool_expr_1 (rtx, int *, int *); 592static bool constant_pool_expr_p (rtx); 593static bool legitimate_indexed_address_p (rtx, int); 594static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int); 595static struct machine_function * rs6000_init_machine_status (void); 596static bool rs6000_assemble_integer (rtx, unsigned int, int); 597static bool no_global_regs_above (int); 598#ifdef HAVE_GAS_HIDDEN 599static void rs6000_assemble_visibility (tree, int); 600#endif 601static int rs6000_ra_ever_killed (void); 602static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *); 603static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *); 604static void rs6000_eliminate_indexed_memrefs (rtx operands[2]); 605static const char *rs6000_mangle_fundamental_type (tree); 606extern const struct attribute_spec rs6000_attribute_table[]; 607static void rs6000_set_default_type_attributes (tree); 608static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT); 609static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT); 610static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, 611 tree); 612static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT); 613static bool rs6000_return_in_memory (tree, tree); 614static void rs6000_file_start (void); 615#if TARGET_ELF 616static unsigned int rs6000_elf_section_type_flags (tree, const char *, int); 617static void rs6000_elf_asm_out_constructor (rtx, int); 618static void rs6000_elf_asm_out_destructor (rtx, int); 619static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED; 620static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT); 621static void rs6000_elf_unique_section (tree, int); 622static void rs6000_elf_select_rtx_section (enum machine_mode, rtx, 623 unsigned HOST_WIDE_INT); 624static void rs6000_elf_encode_section_info (tree, rtx, int) 625 ATTRIBUTE_UNUSED; 626static bool rs6000_elf_in_small_data_p (tree); 627#endif 628#if TARGET_XCOFF 629static void rs6000_xcoff_asm_globalize_label (FILE *, const char *); 630static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree); 631static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT); 632static void rs6000_xcoff_unique_section (tree, int); 633static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx, 634 unsigned HOST_WIDE_INT); 635static const char * rs6000_xcoff_strip_name_encoding (const char *); 636static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int); 637static void rs6000_xcoff_file_start (void); 638static void rs6000_xcoff_file_end (void); 639#endif 640static int rs6000_variable_issue (FILE *, int, rtx, int); 641static bool rs6000_rtx_costs (rtx, int, int, int *); 642static int rs6000_adjust_cost (rtx, rtx, rtx, int); 643static bool is_microcoded_insn (rtx); 644static int is_dispatch_slot_restricted (rtx); 645static bool is_cracked_insn (rtx); 646static bool is_branch_slot_insn (rtx); 647static int rs6000_adjust_priority (rtx, int); 648static int rs6000_issue_rate (void); 649static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int); 650static rtx get_next_active_insn (rtx, rtx); 651static bool insn_terminates_group_p (rtx , enum group_termination); 652static bool is_costly_group (rtx *, rtx); 653static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *); 654static int redefine_groups (FILE *, int, rtx, rtx); 655static int pad_groups (FILE *, int, rtx, rtx); 656static void rs6000_sched_finish (FILE *, int); 657static int rs6000_use_sched_lookahead (void); 658static tree rs6000_builtin_mask_for_load (void); 659 660static void def_builtin (int, const char *, tree, int); 661static void rs6000_init_builtins (void); 662static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx); 663static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx); 664static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx); 665static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int); 666static void altivec_init_builtins (void); 667static void rs6000_common_init_builtins (void); 668static void rs6000_init_libfuncs (void); 669 670static void enable_mask_for_builtins (struct builtin_description *, int, 671 enum rs6000_builtins, 672 enum rs6000_builtins); 673static tree build_opaque_vector_type (tree, int); 674static void spe_init_builtins (void); 675static rtx spe_expand_builtin (tree, rtx, bool *); 676static rtx spe_expand_stv_builtin (enum insn_code, tree); 677static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx); 678static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx); 679static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx); 680static rs6000_stack_t *rs6000_stack_info (void); 681static void debug_stack_info (rs6000_stack_t *); 682 683static rtx altivec_expand_builtin (tree, rtx, bool *); 684static rtx altivec_expand_ld_builtin (tree, rtx, bool *); 685static rtx altivec_expand_st_builtin (tree, rtx, bool *); 686static rtx altivec_expand_dst_builtin (tree, rtx, bool *); 687static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx); 688static rtx altivec_expand_predicate_builtin (enum insn_code, 689 const char *, tree, rtx); 690static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx); 691static rtx altivec_expand_stv_builtin (enum insn_code, tree); 692static rtx altivec_expand_vec_init_builtin (tree, tree, rtx); 693static rtx altivec_expand_vec_set_builtin (tree); 694static rtx altivec_expand_vec_ext_builtin (tree, rtx); 695static int get_element_number (tree, tree); 696static bool rs6000_handle_option (size_t, const char *, int); 697static void rs6000_parse_tls_size_option (void); 698static void rs6000_parse_yes_no_option (const char *, const char *, int *); 699static int first_altivec_reg_to_save (void); 700static unsigned int compute_vrsave_mask (void); 701static void compute_save_world_info (rs6000_stack_t *info_ptr); 702static void is_altivec_return_reg (rtx, void *); 703static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int); 704int easy_vector_constant (rtx, enum machine_mode); 705static bool rs6000_is_opaque_type (tree); 706static rtx rs6000_dwarf_register_span (rtx); 707static rtx rs6000_legitimize_tls_address (rtx, enum tls_model); 708static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; 709static rtx rs6000_tls_get_addr (void); 710static rtx rs6000_got_sym (void); 711static int rs6000_tls_symbol_ref_1 (rtx *, void *); 712static const char *rs6000_get_some_local_dynamic_name (void); 713static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *); 714static rtx rs6000_complex_function_value (enum machine_mode); 715static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *, 716 enum machine_mode, tree); 717static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *, 718 HOST_WIDE_INT); 719static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *, 720 tree, HOST_WIDE_INT); 721static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *, 722 HOST_WIDE_INT, 723 rtx[], int *); 724static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *, 725 tree, HOST_WIDE_INT, 726 rtx[], int *); 727static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool); 728static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int); 729static void rs6000_move_block_from_reg (int regno, rtx x, int nregs); 730static void setup_incoming_varargs (CUMULATIVE_ARGS *, 731 enum machine_mode, tree, 732 int *, int); 733static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, 734 tree, bool); 735static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, 736 tree, bool); 737static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree); 738#if TARGET_MACHO 739static void macho_branch_islands (void); 740static void add_compiler_branch_island (tree, tree, int); 741static int no_previous_def (tree function_name); 742static tree get_prev_label (tree function_name); 743static void rs6000_darwin_file_start (void); 744#endif 745 746static tree rs6000_build_builtin_va_list (void); 747static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *); 748static bool rs6000_must_pass_in_stack (enum machine_mode, tree); 749static bool rs6000_vector_mode_supported_p (enum machine_mode); 750static int get_vec_cmp_insn (enum rtx_code, enum machine_mode, 751 enum machine_mode); 752static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx, 753 enum machine_mode); 754static int get_vsel_insn (enum machine_mode); 755static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx); 756static tree rs6000_stack_protect_fail (void); 757 758const int INSN_NOT_AVAILABLE = -1; 759static enum machine_mode rs6000_eh_return_filter_mode (void); 760 761/* Hash table stuff for keeping track of TOC entries. */ 762 763struct toc_hash_struct GTY(()) 764{ 765 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy 766 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ 767 rtx key; 768 enum machine_mode key_mode; 769 int labelno; 770}; 771 772static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table; 773 774/* Default register names. */ 775char rs6000_reg_names[][8] = 776{ 777 "0", "1", "2", "3", "4", "5", "6", "7", 778 "8", "9", "10", "11", "12", "13", "14", "15", 779 "16", "17", "18", "19", "20", "21", "22", "23", 780 "24", "25", "26", "27", "28", "29", "30", "31", 781 "0", "1", "2", "3", "4", "5", "6", "7", 782 "8", "9", "10", "11", "12", "13", "14", "15", 783 "16", "17", "18", "19", "20", "21", "22", "23", 784 "24", "25", "26", "27", "28", "29", "30", "31", 785 "mq", "lr", "ctr","ap", 786 "0", "1", "2", "3", "4", "5", "6", "7", 787 "xer", 788 /* AltiVec registers. */ 789 "0", "1", "2", "3", "4", "5", "6", "7", 790 "8", "9", "10", "11", "12", "13", "14", "15", 791 "16", "17", "18", "19", "20", "21", "22", "23", 792 "24", "25", "26", "27", "28", "29", "30", "31", 793 "vrsave", "vscr", 794 /* SPE registers. */ 795 "spe_acc", "spefscr", 796 /* Soft frame pointer. */ 797 "sfp" 798}; 799 800#ifdef TARGET_REGNAMES 801static const char alt_reg_names[][8] = 802{ 803 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 804 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", 805 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", 806 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", 807 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", 808 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", 809 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", 810 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", 811 "mq", "lr", "ctr", "ap", 812 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", 813 "xer", 814 /* AltiVec registers. */ 815 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", 816 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", 817 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", 818 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", 819 "vrsave", "vscr", 820 /* SPE registers. */ 821 "spe_acc", "spefscr", 822 /* Soft frame pointer. */ 823 "sfp" 824}; 825#endif 826 827#ifndef MASK_STRICT_ALIGN 828#define MASK_STRICT_ALIGN 0 829#endif 830#ifndef TARGET_PROFILE_KERNEL 831#define TARGET_PROFILE_KERNEL 0 832#endif 833 834/* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ 835#define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) 836 837/* Initialize the GCC target structure. */ 838#undef TARGET_ATTRIBUTE_TABLE 839#define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table 840#undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES 841#define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes 842 843#undef TARGET_ASM_ALIGNED_DI_OP 844#define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP 845 846/* Default unaligned ops are only provided for ELF. Find the ops needed 847 for non-ELF systems. */ 848#ifndef OBJECT_FORMAT_ELF 849#if TARGET_XCOFF 850/* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on 851 64-bit targets. */ 852#undef TARGET_ASM_UNALIGNED_HI_OP 853#define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2," 854#undef TARGET_ASM_UNALIGNED_SI_OP 855#define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4," 856#undef TARGET_ASM_UNALIGNED_DI_OP 857#define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8," 858#else 859/* For Darwin. */ 860#undef TARGET_ASM_UNALIGNED_HI_OP 861#define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" 862#undef TARGET_ASM_UNALIGNED_SI_OP 863#define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t" 864#undef TARGET_ASM_UNALIGNED_DI_OP 865#define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t" 866#undef TARGET_ASM_ALIGNED_DI_OP 867#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" 868#endif 869#endif 870 871/* This hook deals with fixups for relocatable code and DI-mode objects 872 in 64-bit code. */ 873#undef TARGET_ASM_INTEGER 874#define TARGET_ASM_INTEGER rs6000_assemble_integer 875 876#ifdef HAVE_GAS_HIDDEN 877#undef TARGET_ASM_ASSEMBLE_VISIBILITY 878#define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility 879#endif 880 881#undef TARGET_HAVE_TLS 882#define TARGET_HAVE_TLS HAVE_AS_TLS 883 884#undef TARGET_CANNOT_FORCE_CONST_MEM 885#define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p 886 887#undef TARGET_ASM_FUNCTION_PROLOGUE 888#define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue 889#undef TARGET_ASM_FUNCTION_EPILOGUE 890#define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue 891 892#undef TARGET_SCHED_VARIABLE_ISSUE 893#define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue 894 895#undef TARGET_SCHED_ISSUE_RATE 896#define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate 897#undef TARGET_SCHED_ADJUST_COST 898#define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost 899#undef TARGET_SCHED_ADJUST_PRIORITY 900#define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority 901#undef TARGET_SCHED_IS_COSTLY_DEPENDENCE 902#define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence 903#undef TARGET_SCHED_FINISH 904#define TARGET_SCHED_FINISH rs6000_sched_finish 905 906#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD 907#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead 908 909#undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD 910#define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load 911 912#undef TARGET_INIT_BUILTINS 913#define TARGET_INIT_BUILTINS rs6000_init_builtins 914 915#undef TARGET_EXPAND_BUILTIN 916#define TARGET_EXPAND_BUILTIN rs6000_expand_builtin 917 918#undef TARGET_MANGLE_FUNDAMENTAL_TYPE 919#define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type 920 921#undef TARGET_INIT_LIBFUNCS 922#define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs 923 924#if TARGET_MACHO 925#undef TARGET_BINDS_LOCAL_P 926#define TARGET_BINDS_LOCAL_P darwin_binds_local_p 927#endif 928 929#undef TARGET_ASM_OUTPUT_MI_THUNK 930#define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk 931 932#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 933#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true 934 935#undef TARGET_FUNCTION_OK_FOR_SIBCALL 936#define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall 937 938#undef TARGET_INVALID_WITHIN_DOLOOP 939#define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop 940 941#undef TARGET_RTX_COSTS 942#define TARGET_RTX_COSTS rs6000_rtx_costs 943#undef TARGET_ADDRESS_COST 944#define TARGET_ADDRESS_COST hook_int_rtx_0 945 946#undef TARGET_VECTOR_OPAQUE_P 947#define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type 948 949#undef TARGET_DWARF_REGISTER_SPAN 950#define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span 951 952/* On rs6000, function arguments are promoted, as are function return 953 values. */ 954#undef TARGET_PROMOTE_FUNCTION_ARGS 955#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true 956#undef TARGET_PROMOTE_FUNCTION_RETURN 957#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true 958 959#undef TARGET_RETURN_IN_MEMORY 960#define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory 961 962#undef TARGET_SETUP_INCOMING_VARARGS 963#define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs 964 965/* Always strict argument naming on rs6000. */ 966#undef TARGET_STRICT_ARGUMENT_NAMING 967#define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true 968#undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED 969#define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true 970#undef TARGET_SPLIT_COMPLEX_ARG 971#define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true 972#undef TARGET_MUST_PASS_IN_STACK 973#define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack 974#undef TARGET_PASS_BY_REFERENCE 975#define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference 976#undef TARGET_ARG_PARTIAL_BYTES 977#define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes 978 979#undef TARGET_BUILD_BUILTIN_VA_LIST 980#define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list 981 982#undef TARGET_GIMPLIFY_VA_ARG_EXPR 983#define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg 984 985#undef TARGET_EH_RETURN_FILTER_MODE 986#define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode 987 988#undef TARGET_VECTOR_MODE_SUPPORTED_P 989#define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p 990 991#undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN 992#define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn 993 994#undef TARGET_HANDLE_OPTION 995#define TARGET_HANDLE_OPTION rs6000_handle_option 996 997#undef TARGET_DEFAULT_TARGET_FLAGS 998#define TARGET_DEFAULT_TARGET_FLAGS \ 999 (TARGET_DEFAULT | MASK_SCHED_PROLOG) 1000 1001#undef TARGET_STACK_PROTECT_FAIL 1002#define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail 1003 1004/* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors 1005 The PowerPC architecture requires only weak consistency among 1006 processors--that is, memory accesses between processors need not be 1007 sequentially consistent and memory accesses among processors can occur 1008 in any order. The ability to order memory accesses weakly provides 1009 opportunities for more efficient use of the system bus. Unless a 1010 dependency exists, the 604e allows read operations to precede store 1011 operations. */ 1012#undef TARGET_RELAXED_ORDERING 1013#define TARGET_RELAXED_ORDERING true 1014 1015#ifdef HAVE_AS_TLS 1016#undef TARGET_ASM_OUTPUT_DWARF_DTPREL 1017#define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel 1018#endif 1019 1020struct gcc_target targetm = TARGET_INITIALIZER; 1021 1022 1023/* Value is 1 if hard register REGNO can hold a value of machine-mode 1024 MODE. */ 1025static int 1026rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) 1027{ 1028 /* The GPRs can hold any mode, but values bigger than one register 1029 cannot go past R31. */ 1030 if (INT_REGNO_P (regno)) 1031 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1); 1032 1033 /* The float registers can only hold floating modes and DImode. */ 1034 if (FP_REGNO_P (regno)) 1035 return 1036 (GET_MODE_CLASS (mode) == MODE_FLOAT 1037 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1)) 1038 || (GET_MODE_CLASS (mode) == MODE_INT 1039 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD); 1040 1041 /* The CR register can only hold CC modes. */ 1042 if (CR_REGNO_P (regno)) 1043 return GET_MODE_CLASS (mode) == MODE_CC; 1044 1045 if (XER_REGNO_P (regno)) 1046 return mode == PSImode; 1047 1048 /* AltiVec only in AldyVec registers. */ 1049 if (ALTIVEC_REGNO_P (regno)) 1050 return ALTIVEC_VECTOR_MODE (mode); 1051 1052 /* ...but GPRs can hold SIMD data on the SPE in one register. */ 1053 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) 1054 return 1; 1055 1056 /* We cannot put TImode anywhere except general register and it must be 1057 able to fit within the register set. */ 1058 1059 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD; 1060} 1061 1062/* Initialize rs6000_hard_regno_mode_ok_p table. */ 1063static void 1064rs6000_init_hard_regno_mode_ok (void) 1065{ 1066 int r, m; 1067 1068 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r) 1069 for (m = 0; m < NUM_MACHINE_MODES; ++m) 1070 if (rs6000_hard_regno_mode_ok (r, m)) 1071 rs6000_hard_regno_mode_ok_p[m][r] = true; 1072} 1073 1074/* If not otherwise specified by a target, make 'long double' equivalent to 1075 'double'. */ 1076 1077#ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE 1078#define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64 1079#endif 1080 1081/* Override command line options. Mostly we process the processor 1082 type and sometimes adjust other TARGET_ options. */ 1083 1084void 1085rs6000_override_options (const char *default_cpu) 1086{ 1087 size_t i, j; 1088 struct rs6000_cpu_select *ptr; 1089 int set_masks; 1090 1091 /* Simplifications for entries below. */ 1092 1093 enum { 1094 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS, 1095 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC 1096 }; 1097 1098 /* This table occasionally claims that a processor does not support 1099 a particular feature even though it does, but the feature is slower 1100 than the alternative. Thus, it shouldn't be relied on as a 1101 complete description of the processor's support. 1102 1103 Please keep this list in order, and don't forget to update the 1104 documentation in invoke.texi when adding a new processor or 1105 flag. */ 1106 static struct ptt 1107 { 1108 const char *const name; /* Canonical processor name. */ 1109 const enum processor_type processor; /* Processor type enum value. */ 1110 const int target_enable; /* Target flags to enable. */ 1111 } const processor_target_table[] 1112 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, 1113 {"403", PROCESSOR_PPC403, 1114 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN}, 1115 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, 1116 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK}, 1117 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, 1118 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK}, 1119 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK}, 1120 {"601", PROCESSOR_PPC601, 1121 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING}, 1122 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, 1123 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, 1124 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, 1125 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, 1126 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, 1127 {"620", PROCESSOR_PPC620, 1128 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, 1129 {"630", PROCESSOR_PPC630, 1130 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, 1131 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, 1132 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK}, 1133 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK}, 1134 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, 1135 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, 1136 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, 1137 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, 1138 {"8540", PROCESSOR_PPC8540, 1139 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_STRICT_ALIGN}, 1140 /* 8548 has a dummy entry for now. */ 1141 {"8548", PROCESSOR_PPC8540, 1142 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_STRICT_ALIGN}, 1143 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, 1144 {"970", PROCESSOR_POWER4, 1145 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, 1146 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS}, 1147 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, 1148 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, 1149 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK}, 1150 {"G5", PROCESSOR_POWER4, 1151 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, 1152 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, 1153 {"power2", PROCESSOR_POWER, 1154 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, 1155 {"power3", PROCESSOR_PPC630, 1156 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, 1157 {"power4", PROCESSOR_POWER4, 1158 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64}, 1159 {"power5", PROCESSOR_POWER5, 1160 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT 1161 | MASK_MFCRF | MASK_POPCNTB}, 1162 {"power5+", PROCESSOR_POWER5, 1163 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT 1164 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND}, 1165 {"power6", PROCESSOR_POWER5, 1166 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB 1167 | MASK_FPRND}, 1168 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK}, 1169 {"powerpc64", PROCESSOR_POWERPC64, 1170 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, 1171 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, 1172 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, 1173 {"rios2", PROCESSOR_RIOS2, 1174 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, 1175 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, 1176 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, 1177 {"rs64", PROCESSOR_RS64A, 1178 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64} 1179 }; 1180 1181 const size_t ptt_size = ARRAY_SIZE (processor_target_table); 1182 1183 /* Some OSs don't support saving the high part of 64-bit registers on 1184 context switch. Other OSs don't support saving Altivec registers. 1185 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC 1186 settings; if the user wants either, the user must explicitly specify 1187 them and we won't interfere with the user's specification. */ 1188 1189 enum { 1190 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, 1191 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN 1192 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC 1193 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND) 1194 }; 1195 1196 rs6000_init_hard_regno_mode_ok (); 1197 1198 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT; 1199#ifdef OS_MISSING_POWERPC64 1200 if (OS_MISSING_POWERPC64) 1201 set_masks &= ~MASK_POWERPC64; 1202#endif 1203#ifdef OS_MISSING_ALTIVEC 1204 if (OS_MISSING_ALTIVEC) 1205 set_masks &= ~MASK_ALTIVEC; 1206#endif 1207 1208 /* Don't override by the processor default if given explicitly. */ 1209 set_masks &= ~target_flags_explicit; 1210 1211 /* Identify the processor type. */ 1212 rs6000_select[0].string = default_cpu; 1213 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; 1214 1215 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) 1216 { 1217 ptr = &rs6000_select[i]; 1218 if (ptr->string != (char *)0 && ptr->string[0] != '\0') 1219 { 1220 for (j = 0; j < ptt_size; j++) 1221 if (! strcmp (ptr->string, processor_target_table[j].name)) 1222 { 1223 if (ptr->set_tune_p) 1224 rs6000_cpu = processor_target_table[j].processor; 1225 1226 if (ptr->set_arch_p) 1227 { 1228 target_flags &= ~set_masks; 1229 target_flags |= (processor_target_table[j].target_enable 1230 & set_masks); 1231 } 1232 break; 1233 } 1234 1235 if (j == ptt_size) 1236 error ("bad value (%s) for %s switch", ptr->string, ptr->name); 1237 } 1238 } 1239 1240 if (TARGET_E500) 1241 rs6000_isel = 1; 1242 1243 /* If we are optimizing big endian systems for space, use the load/store 1244 multiple and string instructions. */ 1245 if (BYTES_BIG_ENDIAN && optimize_size) 1246 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); 1247 1248 /* Don't allow -mmultiple or -mstring on little endian systems 1249 unless the cpu is a 750, because the hardware doesn't support the 1250 instructions used in little endian mode, and causes an alignment 1251 trap. The 750 does not cause an alignment trap (except when the 1252 target is unaligned). */ 1253 1254 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) 1255 { 1256 if (TARGET_MULTIPLE) 1257 { 1258 target_flags &= ~MASK_MULTIPLE; 1259 if ((target_flags_explicit & MASK_MULTIPLE) != 0) 1260 warning (0, "-mmultiple is not supported on little endian systems"); 1261 } 1262 1263 if (TARGET_STRING) 1264 { 1265 target_flags &= ~MASK_STRING; 1266 if ((target_flags_explicit & MASK_STRING) != 0) 1267 warning (0, "-mstring is not supported on little endian systems"); 1268 } 1269 } 1270 1271 /* Set debug flags */ 1272 if (rs6000_debug_name) 1273 { 1274 if (! strcmp (rs6000_debug_name, "all")) 1275 rs6000_debug_stack = rs6000_debug_arg = 1; 1276 else if (! strcmp (rs6000_debug_name, "stack")) 1277 rs6000_debug_stack = 1; 1278 else if (! strcmp (rs6000_debug_name, "arg")) 1279 rs6000_debug_arg = 1; 1280 else 1281 error ("unknown -mdebug-%s switch", rs6000_debug_name); 1282 } 1283 1284 if (rs6000_traceback_name) 1285 { 1286 if (! strncmp (rs6000_traceback_name, "full", 4)) 1287 rs6000_traceback = traceback_full; 1288 else if (! strncmp (rs6000_traceback_name, "part", 4)) 1289 rs6000_traceback = traceback_part; 1290 else if (! strncmp (rs6000_traceback_name, "no", 2)) 1291 rs6000_traceback = traceback_none; 1292 else 1293 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>", 1294 rs6000_traceback_name); 1295 } 1296 1297 if (!rs6000_explicit_options.long_double) 1298 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; 1299 1300#if !defined(POWERPC_LINUX) && !defined(POWERPC_NETBSD) 1301 if (!rs6000_explicit_options.ieee) 1302 rs6000_ieeequad = 1; 1303#endif 1304 1305 /* Set Altivec ABI as default for powerpc64 linux. */ 1306 if (TARGET_ELF && TARGET_64BIT) 1307 { 1308 rs6000_altivec_abi = 1; 1309 TARGET_ALTIVEC_VRSAVE = 1; 1310 } 1311 1312 /* Set the Darwin64 ABI as default for 64-bit Darwin. */ 1313 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT) 1314 { 1315 rs6000_darwin64_abi = 1; 1316#if TARGET_MACHO 1317 darwin_one_byte_bool = 1; 1318#endif 1319 /* Default to natural alignment, for better performance. */ 1320 rs6000_alignment_flags = MASK_ALIGN_NATURAL; 1321 } 1322 1323 /* Handle -mtls-size option. */ 1324 rs6000_parse_tls_size_option (); 1325 1326#ifdef SUBTARGET_OVERRIDE_OPTIONS 1327 SUBTARGET_OVERRIDE_OPTIONS; 1328#endif 1329#ifdef SUBSUBTARGET_OVERRIDE_OPTIONS 1330 SUBSUBTARGET_OVERRIDE_OPTIONS; 1331#endif 1332#ifdef SUB3TARGET_OVERRIDE_OPTIONS 1333 SUB3TARGET_OVERRIDE_OPTIONS; 1334#endif 1335 1336 if (TARGET_E500) 1337 { 1338 if (TARGET_ALTIVEC) 1339 error ("AltiVec and E500 instructions cannot coexist"); 1340 1341 /* The e500 does not have string instructions, and we set 1342 MASK_STRING above when optimizing for size. */ 1343 if ((target_flags & MASK_STRING) != 0) 1344 target_flags = target_flags & ~MASK_STRING; 1345 } 1346 else if (rs6000_select[1].string != NULL) 1347 { 1348 /* For the powerpc-eabispe configuration, we set all these by 1349 default, so let's unset them if we manually set another 1350 CPU that is not the E500. */ 1351 if (!rs6000_explicit_options.abi) 1352 rs6000_spe_abi = 0; 1353 if (!rs6000_explicit_options.spe) 1354 rs6000_spe = 0; 1355 if (!rs6000_explicit_options.float_gprs) 1356 rs6000_float_gprs = 0; 1357 if (!rs6000_explicit_options.isel) 1358 rs6000_isel = 0; 1359 if (!rs6000_explicit_options.long_double) 1360 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; 1361 } 1362 1363 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4 1364 && rs6000_cpu != PROCESSOR_POWER5); 1365 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4 1366 || rs6000_cpu == PROCESSOR_POWER5); 1367 1368 rs6000_sched_restricted_insns_priority 1369 = (rs6000_sched_groups ? 1 : 0); 1370 1371 /* Handle -msched-costly-dep option. */ 1372 rs6000_sched_costly_dep 1373 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly); 1374 1375 if (rs6000_sched_costly_dep_str) 1376 { 1377 if (! strcmp (rs6000_sched_costly_dep_str, "no")) 1378 rs6000_sched_costly_dep = no_dep_costly; 1379 else if (! strcmp (rs6000_sched_costly_dep_str, "all")) 1380 rs6000_sched_costly_dep = all_deps_costly; 1381 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load")) 1382 rs6000_sched_costly_dep = true_store_to_load_dep_costly; 1383 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load")) 1384 rs6000_sched_costly_dep = store_to_load_dep_costly; 1385 else 1386 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str); 1387 } 1388 1389 /* Handle -minsert-sched-nops option. */ 1390 rs6000_sched_insert_nops 1391 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none); 1392 1393 if (rs6000_sched_insert_nops_str) 1394 { 1395 if (! strcmp (rs6000_sched_insert_nops_str, "no")) 1396 rs6000_sched_insert_nops = sched_finish_none; 1397 else if (! strcmp (rs6000_sched_insert_nops_str, "pad")) 1398 rs6000_sched_insert_nops = sched_finish_pad_groups; 1399 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact")) 1400 rs6000_sched_insert_nops = sched_finish_regroup_exact; 1401 else 1402 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str); 1403 } 1404 1405#ifdef TARGET_REGNAMES 1406 /* If the user desires alternate register names, copy in the 1407 alternate names now. */ 1408 if (TARGET_REGNAMES) 1409 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); 1410#endif 1411 1412 /* Set aix_struct_return last, after the ABI is determined. 1413 If -maix-struct-return or -msvr4-struct-return was explicitly 1414 used, don't override with the ABI default. */ 1415 if (!rs6000_explicit_options.aix_struct_ret) 1416 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET); 1417 1418 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD) 1419 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format; 1420 1421 /* Allocate an alias set for register saves & restores from stack. */ 1422 rs6000_sr_alias_set = new_alias_set (); 1423 1424 if (TARGET_TOC) 1425 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); 1426 1427 /* We can only guarantee the availability of DI pseudo-ops when 1428 assembling for 64-bit targets. */ 1429 if (!TARGET_64BIT) 1430 { 1431 targetm.asm_out.aligned_op.di = NULL; 1432 targetm.asm_out.unaligned_op.di = NULL; 1433 } 1434 1435 /* Set branch target alignment, if not optimizing for size. */ 1436 if (!optimize_size) 1437 { 1438 if (rs6000_sched_groups) 1439 { 1440 if (align_functions <= 0) 1441 align_functions = 16; 1442 if (align_jumps <= 0) 1443 align_jumps = 16; 1444 if (align_loops <= 0) 1445 align_loops = 16; 1446 } 1447 if (align_jumps_max_skip <= 0) 1448 align_jumps_max_skip = 15; 1449 if (align_loops_max_skip <= 0) 1450 align_loops_max_skip = 15; 1451 } 1452 1453 /* Arrange to save and restore machine status around nested functions. */ 1454 init_machine_status = rs6000_init_machine_status; 1455 1456 /* We should always be splitting complex arguments, but we can't break 1457 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */ 1458 if (DEFAULT_ABI != ABI_AIX) 1459 targetm.calls.split_complex_arg = NULL; 1460 1461 /* Initialize rs6000_cost with the appropriate target costs. */ 1462 if (optimize_size) 1463 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost; 1464 else 1465 switch (rs6000_cpu) 1466 { 1467 case PROCESSOR_RIOS1: 1468 rs6000_cost = &rios1_cost; 1469 break; 1470 1471 case PROCESSOR_RIOS2: 1472 rs6000_cost = &rios2_cost; 1473 break; 1474 1475 case PROCESSOR_RS64A: 1476 rs6000_cost = &rs64a_cost; 1477 break; 1478 1479 case PROCESSOR_MPCCORE: 1480 rs6000_cost = &mpccore_cost; 1481 break; 1482 1483 case PROCESSOR_PPC403: 1484 rs6000_cost = &ppc403_cost; 1485 break; 1486 1487 case PROCESSOR_PPC405: 1488 rs6000_cost = &ppc405_cost; 1489 break; 1490 1491 case PROCESSOR_PPC440: 1492 rs6000_cost = &ppc440_cost; 1493 break; 1494 1495 case PROCESSOR_PPC601: 1496 rs6000_cost = &ppc601_cost; 1497 break; 1498 1499 case PROCESSOR_PPC603: 1500 rs6000_cost = &ppc603_cost; 1501 break; 1502 1503 case PROCESSOR_PPC604: 1504 rs6000_cost = &ppc604_cost; 1505 break; 1506 1507 case PROCESSOR_PPC604e: 1508 rs6000_cost = &ppc604e_cost; 1509 break; 1510 1511 case PROCESSOR_PPC620: 1512 rs6000_cost = &ppc620_cost; 1513 break; 1514 1515 case PROCESSOR_PPC630: 1516 rs6000_cost = &ppc630_cost; 1517 break; 1518 1519 case PROCESSOR_PPC750: 1520 case PROCESSOR_PPC7400: 1521 rs6000_cost = &ppc750_cost; 1522 break; 1523 1524 case PROCESSOR_PPC7450: 1525 rs6000_cost = &ppc7450_cost; 1526 break; 1527 1528 case PROCESSOR_PPC8540: 1529 rs6000_cost = &ppc8540_cost; 1530 break; 1531 1532 case PROCESSOR_POWER4: 1533 case PROCESSOR_POWER5: 1534 rs6000_cost = &power4_cost; 1535 break; 1536 1537 default: 1538 gcc_unreachable (); 1539 } 1540} 1541 1542/* Implement targetm.vectorize.builtin_mask_for_load. */ 1543static tree 1544rs6000_builtin_mask_for_load (void) 1545{ 1546 if (TARGET_ALTIVEC) 1547 return altivec_builtin_mask_for_load; 1548 else 1549 return 0; 1550} 1551 1552/* Handle generic options of the form -mfoo=yes/no. 1553 NAME is the option name. 1554 VALUE is the option value. 1555 FLAG is the pointer to the flag where to store a 1 or 0, depending on 1556 whether the option value is 'yes' or 'no' respectively. */ 1557static void 1558rs6000_parse_yes_no_option (const char *name, const char *value, int *flag) 1559{ 1560 if (value == 0) 1561 return; 1562 else if (!strcmp (value, "yes")) 1563 *flag = 1; 1564 else if (!strcmp (value, "no")) 1565 *flag = 0; 1566 else 1567 error ("unknown -m%s= option specified: '%s'", name, value); 1568} 1569 1570/* Validate and record the size specified with the -mtls-size option. */ 1571 1572static void 1573rs6000_parse_tls_size_option (void) 1574{ 1575 if (rs6000_tls_size_string == 0) 1576 return; 1577 else if (strcmp (rs6000_tls_size_string, "16") == 0) 1578 rs6000_tls_size = 16; 1579 else if (strcmp (rs6000_tls_size_string, "32") == 0) 1580 rs6000_tls_size = 32; 1581 else if (strcmp (rs6000_tls_size_string, "64") == 0) 1582 rs6000_tls_size = 64; 1583 else 1584 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string); 1585} 1586 1587void 1588optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED) 1589{ 1590 if (DEFAULT_ABI == ABI_DARWIN) 1591 /* The Darwin libraries never set errno, so we might as well 1592 avoid calling them when that's the only reason we would. */ 1593 flag_errno_math = 0; 1594 1595 /* Double growth factor to counter reduced min jump length. */ 1596 set_param_value ("max-grow-copy-bb-insns", 16); 1597} 1598 1599/* Implement TARGET_HANDLE_OPTION. */ 1600 1601static bool 1602rs6000_handle_option (size_t code, const char *arg, int value) 1603{ 1604 switch (code) 1605 { 1606 case OPT_mno_power: 1607 target_flags &= ~(MASK_POWER | MASK_POWER2 1608 | MASK_MULTIPLE | MASK_STRING); 1609 target_flags_explicit |= (MASK_POWER | MASK_POWER2 1610 | MASK_MULTIPLE | MASK_STRING); 1611 break; 1612 case OPT_mno_powerpc: 1613 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT 1614 | MASK_PPC_GFXOPT | MASK_POWERPC64); 1615 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT 1616 | MASK_PPC_GFXOPT | MASK_POWERPC64); 1617 break; 1618 case OPT_mfull_toc: 1619 target_flags &= ~(MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC 1620 | MASK_NO_SUM_IN_TOC); 1621 target_flags_explicit |= (MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC 1622 | MASK_NO_SUM_IN_TOC); 1623#ifdef TARGET_USES_SYSV4_OPT 1624 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be 1625 just the same as -mminimal-toc. */ 1626 target_flags |= MASK_MINIMAL_TOC; 1627 target_flags_explicit |= MASK_MINIMAL_TOC; 1628#endif 1629 break; 1630 1631#ifdef TARGET_USES_SYSV4_OPT 1632 case OPT_mtoc: 1633 /* Make -mtoc behave like -mminimal-toc. */ 1634 target_flags |= MASK_MINIMAL_TOC; 1635 target_flags_explicit |= MASK_MINIMAL_TOC; 1636 break; 1637#endif 1638 1639#ifdef TARGET_USES_AIX64_OPT 1640 case OPT_maix64: 1641#else 1642 case OPT_m64: 1643#endif 1644 target_flags |= MASK_POWERPC64 | MASK_POWERPC; 1645 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT; 1646 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC; 1647 break; 1648 1649#ifdef TARGET_USES_AIX64_OPT 1650 case OPT_maix32: 1651#else 1652 case OPT_m32: 1653#endif 1654 target_flags &= ~MASK_POWERPC64; 1655 target_flags_explicit |= MASK_POWERPC64; 1656 break; 1657 1658 case OPT_minsert_sched_nops_: 1659 rs6000_sched_insert_nops_str = arg; 1660 break; 1661 1662 case OPT_mminimal_toc: 1663 if (value == 1) 1664 { 1665 target_flags &= ~(MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC); 1666 target_flags_explicit |= (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC); 1667 } 1668 break; 1669 1670 case OPT_mpower: 1671 if (value == 1) 1672 { 1673 target_flags |= (MASK_MULTIPLE | MASK_STRING); 1674 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING); 1675 } 1676 break; 1677 1678 case OPT_mpower2: 1679 if (value == 1) 1680 { 1681 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING); 1682 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING); 1683 } 1684 break; 1685 1686 case OPT_mpowerpc_gpopt: 1687 case OPT_mpowerpc_gfxopt: 1688 if (value == 1) 1689 { 1690 target_flags |= MASK_POWERPC; 1691 target_flags_explicit |= MASK_POWERPC; 1692 } 1693 break; 1694 1695 case OPT_maix_struct_return: 1696 case OPT_msvr4_struct_return: 1697 rs6000_explicit_options.aix_struct_ret = true; 1698 break; 1699 1700 case OPT_mvrsave_: 1701 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE)); 1702 break; 1703 1704 case OPT_misel_: 1705 rs6000_explicit_options.isel = true; 1706 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel)); 1707 break; 1708 1709 case OPT_mspe_: 1710 rs6000_explicit_options.spe = true; 1711 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe)); 1712 /* No SPE means 64-bit long doubles, even if an E500. */ 1713 if (!rs6000_spe) 1714 rs6000_long_double_type_size = 64; 1715 break; 1716 1717 case OPT_mdebug_: 1718 rs6000_debug_name = arg; 1719 break; 1720 1721#ifdef TARGET_USES_SYSV4_OPT 1722 case OPT_mcall_: 1723 rs6000_abi_name = arg; 1724 break; 1725 1726 case OPT_msdata_: 1727 rs6000_sdata_name = arg; 1728 break; 1729 1730 case OPT_mtls_size_: 1731 rs6000_tls_size_string = arg; 1732 break; 1733 1734 case OPT_mrelocatable: 1735 if (value == 1) 1736 { 1737 target_flags |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC; 1738 target_flags_explicit |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC; 1739 } 1740 break; 1741 1742 case OPT_mrelocatable_lib: 1743 if (value == 1) 1744 { 1745 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC 1746 | MASK_NO_FP_IN_TOC; 1747 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC 1748 | MASK_NO_FP_IN_TOC; 1749 } 1750 else 1751 { 1752 target_flags &= ~MASK_RELOCATABLE; 1753 target_flags_explicit |= MASK_RELOCATABLE; 1754 } 1755 break; 1756#endif 1757 1758 case OPT_mabi_: 1759 if (!strcmp (arg, "altivec")) 1760 { 1761 rs6000_explicit_options.abi = true; 1762 rs6000_altivec_abi = 1; 1763 rs6000_spe_abi = 0; 1764 } 1765 else if (! strcmp (arg, "no-altivec")) 1766 { 1767 /* ??? Don't set rs6000_explicit_options.abi here, to allow 1768 the default for rs6000_spe_abi to be chosen later. */ 1769 rs6000_altivec_abi = 0; 1770 } 1771 else if (! strcmp (arg, "spe")) 1772 { 1773 rs6000_explicit_options.abi = true; 1774 rs6000_spe_abi = 1; 1775 rs6000_altivec_abi = 0; 1776 if (!TARGET_SPE_ABI) 1777 error ("not configured for ABI: '%s'", arg); 1778 } 1779 else if (! strcmp (arg, "no-spe")) 1780 { 1781 rs6000_explicit_options.abi = true; 1782 rs6000_spe_abi = 0; 1783 } 1784 1785 /* These are here for testing during development only, do not 1786 document in the manual please. */ 1787 else if (! strcmp (arg, "d64")) 1788 { 1789 rs6000_darwin64_abi = 1; 1790 warning (0, "Using darwin64 ABI"); 1791 } 1792 else if (! strcmp (arg, "d32")) 1793 { 1794 rs6000_darwin64_abi = 0; 1795 warning (0, "Using old darwin ABI"); 1796 } 1797 1798 else if (! strcmp (arg, "ibmlongdouble")) 1799 { 1800 rs6000_explicit_options.ieee = true; 1801 rs6000_ieeequad = 0; 1802 warning (0, "Using IBM extended precision long double"); 1803 } 1804 else if (! strcmp (arg, "ieeelongdouble")) 1805 { 1806 rs6000_explicit_options.ieee = true; 1807 rs6000_ieeequad = 1; 1808 warning (0, "Using IEEE extended precision long double"); 1809 } 1810 1811 else 1812 { 1813 error ("unknown ABI specified: '%s'", arg); 1814 return false; 1815 } 1816 break; 1817 1818 case OPT_mcpu_: 1819 rs6000_select[1].string = arg; 1820 break; 1821 1822 case OPT_mtune_: 1823 rs6000_select[2].string = arg; 1824 break; 1825 1826 case OPT_mtraceback_: 1827 rs6000_traceback_name = arg; 1828 break; 1829 1830 case OPT_mfloat_gprs_: 1831 rs6000_explicit_options.float_gprs = true; 1832 if (! strcmp (arg, "yes") || ! strcmp (arg, "single")) 1833 rs6000_float_gprs = 1; 1834 else if (! strcmp (arg, "double")) 1835 rs6000_float_gprs = 2; 1836 else if (! strcmp (arg, "no")) 1837 rs6000_float_gprs = 0; 1838 else 1839 { 1840 error ("invalid option for -mfloat-gprs: '%s'", arg); 1841 return false; 1842 } 1843 break; 1844 1845 case OPT_mlong_double_: 1846 rs6000_explicit_options.long_double = true; 1847 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; 1848 if (value != 64 && value != 128) 1849 { 1850 error ("Unknown switch -mlong-double-%s", arg); 1851 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; 1852 return false; 1853 } 1854 else 1855 rs6000_long_double_type_size = value; 1856 break; 1857 1858 case OPT_msched_costly_dep_: 1859 rs6000_sched_costly_dep_str = arg; 1860 break; 1861 1862 case OPT_malign_: 1863 rs6000_explicit_options.alignment = true; 1864 if (! strcmp (arg, "power")) 1865 { 1866 /* On 64-bit Darwin, power alignment is ABI-incompatible with 1867 some C library functions, so warn about it. The flag may be 1868 useful for performance studies from time to time though, so 1869 don't disable it entirely. */ 1870 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT) 1871 warning (0, "-malign-power is not supported for 64-bit Darwin;" 1872 " it is incompatible with the installed C and C++ libraries"); 1873 rs6000_alignment_flags = MASK_ALIGN_POWER; 1874 } 1875 else if (! strcmp (arg, "natural")) 1876 rs6000_alignment_flags = MASK_ALIGN_NATURAL; 1877 else 1878 { 1879 error ("unknown -malign-XXXXX option specified: '%s'", arg); 1880 return false; 1881 } 1882 break; 1883 } 1884 return true; 1885} 1886 1887/* Do anything needed at the start of the asm file. */ 1888 1889static void 1890rs6000_file_start (void) 1891{ 1892 size_t i; 1893 char buffer[80]; 1894 const char *start = buffer; 1895 struct rs6000_cpu_select *ptr; 1896 const char *default_cpu = TARGET_CPU_DEFAULT; 1897 FILE *file = asm_out_file; 1898 1899 default_file_start (); 1900 1901#ifdef TARGET_BI_ARCH 1902 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT) 1903 default_cpu = 0; 1904#endif 1905 1906 if (flag_verbose_asm) 1907 { 1908 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); 1909 rs6000_select[0].string = default_cpu; 1910 1911 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) 1912 { 1913 ptr = &rs6000_select[i]; 1914 if (ptr->string != (char *)0 && ptr->string[0] != '\0') 1915 { 1916 fprintf (file, "%s %s%s", start, ptr->name, ptr->string); 1917 start = ""; 1918 } 1919 } 1920 1921 if (PPC405_ERRATUM77) 1922 { 1923 fprintf (file, "%s PPC405CR_ERRATUM77", start); 1924 start = ""; 1925 } 1926 1927#ifdef USING_ELFOS_H 1928 switch (rs6000_sdata) 1929 { 1930 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; 1931 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; 1932 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; 1933 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; 1934 } 1935 1936 if (rs6000_sdata && g_switch_value) 1937 { 1938 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start, 1939 g_switch_value); 1940 start = ""; 1941 } 1942#endif 1943 1944 if (*start == '\0') 1945 putc ('\n', file); 1946 } 1947 1948 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2)) 1949 { 1950 toc_section (); 1951 text_section (); 1952 } 1953} 1954 1955 1956/* Return nonzero if this function is known to have a null epilogue. */ 1957 1958int 1959direct_return (void) 1960{ 1961 if (reload_completed) 1962 { 1963 rs6000_stack_t *info = rs6000_stack_info (); 1964 1965 if (info->first_gp_reg_save == 32 1966 && info->first_fp_reg_save == 64 1967 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 1968 && ! info->lr_save_p 1969 && ! info->cr_save_p 1970 && info->vrsave_mask == 0 1971 && ! info->push_p) 1972 return 1; 1973 } 1974 1975 return 0; 1976} 1977 1978/* Return the number of instructions it takes to form a constant in an 1979 integer register. */ 1980 1981int 1982num_insns_constant_wide (HOST_WIDE_INT value) 1983{ 1984 /* signed constant loadable with {cal|addi} */ 1985 if (CONST_OK_FOR_LETTER_P (value, 'I')) 1986 return 1; 1987 1988 /* constant loadable with {cau|addis} */ 1989 else if (CONST_OK_FOR_LETTER_P (value, 'L')) 1990 return 1; 1991 1992#if HOST_BITS_PER_WIDE_INT == 64 1993 else if (TARGET_POWERPC64) 1994 { 1995 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; 1996 HOST_WIDE_INT high = value >> 31; 1997 1998 if (high == 0 || high == -1) 1999 return 2; 2000 2001 high >>= 1; 2002 2003 if (low == 0) 2004 return num_insns_constant_wide (high) + 1; 2005 else 2006 return (num_insns_constant_wide (high) 2007 + num_insns_constant_wide (low) + 1); 2008 } 2009#endif 2010 2011 else 2012 return 2; 2013} 2014 2015int 2016num_insns_constant (rtx op, enum machine_mode mode) 2017{ 2018 HOST_WIDE_INT low, high; 2019 2020 switch (GET_CODE (op)) 2021 { 2022 case CONST_INT: 2023#if HOST_BITS_PER_WIDE_INT == 64 2024 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 2025 && mask64_operand (op, mode)) 2026 return 2; 2027 else 2028#endif 2029 return num_insns_constant_wide (INTVAL (op)); 2030 2031 case CONST_DOUBLE: 2032 if (mode == SFmode) 2033 { 2034 long l; 2035 REAL_VALUE_TYPE rv; 2036 2037 REAL_VALUE_FROM_CONST_DOUBLE (rv, op); 2038 REAL_VALUE_TO_TARGET_SINGLE (rv, l); 2039 return num_insns_constant_wide ((HOST_WIDE_INT) l); 2040 } 2041 2042 if (mode == VOIDmode || mode == DImode) 2043 { 2044 high = CONST_DOUBLE_HIGH (op); 2045 low = CONST_DOUBLE_LOW (op); 2046 } 2047 else 2048 { 2049 long l[2]; 2050 REAL_VALUE_TYPE rv; 2051 2052 REAL_VALUE_FROM_CONST_DOUBLE (rv, op); 2053 REAL_VALUE_TO_TARGET_DOUBLE (rv, l); 2054 high = l[WORDS_BIG_ENDIAN == 0]; 2055 low = l[WORDS_BIG_ENDIAN != 0]; 2056 } 2057 2058 if (TARGET_32BIT) 2059 return (num_insns_constant_wide (low) 2060 + num_insns_constant_wide (high)); 2061 else 2062 { 2063 if ((high == 0 && low >= 0) 2064 || (high == -1 && low < 0)) 2065 return num_insns_constant_wide (low); 2066 2067 else if (mask64_operand (op, mode)) 2068 return 2; 2069 2070 else if (low == 0) 2071 return num_insns_constant_wide (high) + 1; 2072 2073 else 2074 return (num_insns_constant_wide (high) 2075 + num_insns_constant_wide (low) + 1); 2076 } 2077 2078 default: 2079 gcc_unreachable (); 2080 } 2081} 2082 2083 2084/* Interpret element ELT of the CONST_VECTOR OP as an integer value. 2085 If the mode of OP is MODE_VECTOR_INT, this simply returns the 2086 corresponding element of the vector, but for V4SFmode and V2SFmode, 2087 the corresponding "float" is interpreted as an SImode integer. */ 2088 2089static HOST_WIDE_INT 2090const_vector_elt_as_int (rtx op, unsigned int elt) 2091{ 2092 rtx tmp = CONST_VECTOR_ELT (op, elt); 2093 if (GET_MODE (op) == V4SFmode 2094 || GET_MODE (op) == V2SFmode) 2095 tmp = gen_lowpart (SImode, tmp); 2096 return INTVAL (tmp); 2097} 2098 2099 2100/* Return true if OP can be synthesized with a particular vspltisb, vspltish 2101 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used 2102 depends on STEP and COPIES, one of which will be 1. If COPIES > 1, 2103 all items are set to the same value and contain COPIES replicas of the 2104 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's 2105 operand and the others are set to the value of the operand's msb. */ 2106 2107static bool 2108vspltis_constant (rtx op, unsigned step, unsigned copies) 2109{ 2110 enum machine_mode mode = GET_MODE (op); 2111 enum machine_mode inner = GET_MODE_INNER (mode); 2112 2113 unsigned i; 2114 unsigned nunits = GET_MODE_NUNITS (mode); 2115 unsigned bitsize = GET_MODE_BITSIZE (inner); 2116 unsigned mask = GET_MODE_MASK (inner); 2117 2118 HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1); 2119 HOST_WIDE_INT splat_val = val; 2120 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1; 2121 2122 /* Construct the value to be splatted, if possible. If not, return 0. */ 2123 for (i = 2; i <= copies; i *= 2) 2124 { 2125 HOST_WIDE_INT small_val; 2126 bitsize /= 2; 2127 small_val = splat_val >> bitsize; 2128 mask >>= bitsize; 2129 if (splat_val != ((small_val << bitsize) | (small_val & mask))) 2130 return false; 2131 splat_val = small_val; 2132 } 2133 2134 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */ 2135 if (EASY_VECTOR_15 (splat_val)) 2136 ; 2137 2138 /* Also check if we can splat, and then add the result to itself. Do so if 2139 the value is positive, of if the splat instruction is using OP's mode; 2140 for splat_val < 0, the splat and the add should use the same mode. */ 2141 else if (EASY_VECTOR_15_ADD_SELF (splat_val) 2142 && (splat_val >= 0 || (step == 1 && copies == 1))) 2143 ; 2144 2145 else 2146 return false; 2147 2148 /* Check if VAL is present in every STEP-th element, and the 2149 other elements are filled with its most significant bit. */ 2150 for (i = 0; i < nunits - 1; ++i) 2151 { 2152 HOST_WIDE_INT desired_val; 2153 if (((i + 1) & (step - 1)) == 0) 2154 desired_val = val; 2155 else 2156 desired_val = msb_val; 2157 2158 if (desired_val != const_vector_elt_as_int (op, i)) 2159 return false; 2160 } 2161 2162 return true; 2163} 2164 2165 2166/* Return true if OP is of the given MODE and can be synthesized 2167 with a vspltisb, vspltish or vspltisw. */ 2168 2169bool 2170easy_altivec_constant (rtx op, enum machine_mode mode) 2171{ 2172 unsigned step, copies; 2173 2174 if (mode == VOIDmode) 2175 mode = GET_MODE (op); 2176 else if (mode != GET_MODE (op)) 2177 return false; 2178 2179 /* Start with a vspltisw. */ 2180 step = GET_MODE_NUNITS (mode) / 4; 2181 copies = 1; 2182 2183 if (vspltis_constant (op, step, copies)) 2184 return true; 2185 2186 /* Then try with a vspltish. */ 2187 if (step == 1) 2188 copies <<= 1; 2189 else 2190 step >>= 1; 2191 2192 if (vspltis_constant (op, step, copies)) 2193 return true; 2194 2195 /* And finally a vspltisb. */ 2196 if (step == 1) 2197 copies <<= 1; 2198 else 2199 step >>= 1; 2200 2201 if (vspltis_constant (op, step, copies)) 2202 return true; 2203 2204 return false; 2205} 2206 2207/* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose 2208 result is OP. Abort if it is not possible. */ 2209 2210rtx 2211gen_easy_altivec_constant (rtx op) 2212{ 2213 enum machine_mode mode = GET_MODE (op); 2214 int nunits = GET_MODE_NUNITS (mode); 2215 rtx last = CONST_VECTOR_ELT (op, nunits - 1); 2216 unsigned step = nunits / 4; 2217 unsigned copies = 1; 2218 2219 /* Start with a vspltisw. */ 2220 if (vspltis_constant (op, step, copies)) 2221 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last)); 2222 2223 /* Then try with a vspltish. */ 2224 if (step == 1) 2225 copies <<= 1; 2226 else 2227 step >>= 1; 2228 2229 if (vspltis_constant (op, step, copies)) 2230 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last)); 2231 2232 /* And finally a vspltisb. */ 2233 if (step == 1) 2234 copies <<= 1; 2235 else 2236 step >>= 1; 2237 2238 if (vspltis_constant (op, step, copies)) 2239 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last)); 2240 2241 gcc_unreachable (); 2242} 2243 2244const char * 2245output_vec_const_move (rtx *operands) 2246{ 2247 int cst, cst2; 2248 enum machine_mode mode; 2249 rtx dest, vec; 2250 2251 dest = operands[0]; 2252 vec = operands[1]; 2253 mode = GET_MODE (dest); 2254 2255 if (TARGET_ALTIVEC) 2256 { 2257 rtx splat_vec; 2258 if (zero_constant (vec, mode)) 2259 return "vxor %0,%0,%0"; 2260 2261 splat_vec = gen_easy_altivec_constant (vec); 2262 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE); 2263 operands[1] = XEXP (splat_vec, 0); 2264 if (!EASY_VECTOR_15 (INTVAL (operands[1]))) 2265 return "#"; 2266 2267 switch (GET_MODE (splat_vec)) 2268 { 2269 case V4SImode: 2270 return "vspltisw %0,%1"; 2271 2272 case V8HImode: 2273 return "vspltish %0,%1"; 2274 2275 case V16QImode: 2276 return "vspltisb %0,%1"; 2277 2278 default: 2279 gcc_unreachable (); 2280 } 2281 } 2282 2283 gcc_assert (TARGET_SPE); 2284 2285 /* Vector constant 0 is handled as a splitter of V2SI, and in the 2286 pattern of V1DI, V4HI, and V2SF. 2287 2288 FIXME: We should probably return # and add post reload 2289 splitters for these, but this way is so easy ;-). */ 2290 cst = INTVAL (CONST_VECTOR_ELT (vec, 0)); 2291 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1)); 2292 operands[1] = CONST_VECTOR_ELT (vec, 0); 2293 operands[2] = CONST_VECTOR_ELT (vec, 1); 2294 if (cst == cst2) 2295 return "li %0,%1\n\tevmergelo %0,%0,%0"; 2296 else 2297 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2"; 2298} 2299 2300/* Initialize vector TARGET to VALS. */ 2301 2302void 2303rs6000_expand_vector_init (rtx target, rtx vals) 2304{ 2305 enum machine_mode mode = GET_MODE (target); 2306 enum machine_mode inner_mode = GET_MODE_INNER (mode); 2307 int n_elts = GET_MODE_NUNITS (mode); 2308 int n_var = 0, one_var = -1; 2309 bool all_same = true, all_const_zero = true; 2310 rtx x, mem; 2311 int i; 2312 2313 for (i = 0; i < n_elts; ++i) 2314 { 2315 x = XVECEXP (vals, 0, i); 2316 if (!CONSTANT_P (x)) 2317 ++n_var, one_var = i; 2318 else if (x != CONST0_RTX (inner_mode)) 2319 all_const_zero = false; 2320 2321 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0))) 2322 all_same = false; 2323 } 2324 2325 if (n_var == 0) 2326 { 2327 if (mode != V4SFmode && all_const_zero) 2328 { 2329 /* Zero register. */ 2330 emit_insn (gen_rtx_SET (VOIDmode, target, 2331 gen_rtx_XOR (mode, target, target))); 2332 return; 2333 } 2334 else if (mode != V4SFmode && easy_vector_constant (vals, mode)) 2335 { 2336 /* Splat immediate. */ 2337 emit_insn (gen_rtx_SET (VOIDmode, target, vals)); 2338 return; 2339 } 2340 else if (all_same) 2341 ; /* Splat vector element. */ 2342 else 2343 { 2344 /* Load from constant pool. */ 2345 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0))); 2346 return; 2347 } 2348 } 2349 2350 /* Store value to stack temp. Load vector element. Splat. */ 2351 if (all_same) 2352 { 2353 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0); 2354 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), 2355 XVECEXP (vals, 0, 0)); 2356 x = gen_rtx_UNSPEC (VOIDmode, 2357 gen_rtvec (1, const0_rtx), UNSPEC_LVE); 2358 emit_insn (gen_rtx_PARALLEL (VOIDmode, 2359 gen_rtvec (2, 2360 gen_rtx_SET (VOIDmode, 2361 target, mem), 2362 x))); 2363 x = gen_rtx_VEC_SELECT (inner_mode, target, 2364 gen_rtx_PARALLEL (VOIDmode, 2365 gen_rtvec (1, const0_rtx))); 2366 emit_insn (gen_rtx_SET (VOIDmode, target, 2367 gen_rtx_VEC_DUPLICATE (mode, x))); 2368 return; 2369 } 2370 2371 /* One field is non-constant. Load constant then overwrite 2372 varying field. */ 2373 if (n_var == 1) 2374 { 2375 rtx copy = copy_rtx (vals); 2376 2377 /* Load constant part of vector, substitute neighboring value for 2378 varying element. */ 2379 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts); 2380 rs6000_expand_vector_init (target, copy); 2381 2382 /* Insert variable. */ 2383 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var); 2384 return; 2385 } 2386 2387 /* Construct the vector in memory one field at a time 2388 and load the whole vector. */ 2389 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0); 2390 for (i = 0; i < n_elts; i++) 2391 emit_move_insn (adjust_address_nv (mem, inner_mode, 2392 i * GET_MODE_SIZE (inner_mode)), 2393 XVECEXP (vals, 0, i)); 2394 emit_move_insn (target, mem); 2395} 2396 2397/* Set field ELT of TARGET to VAL. */ 2398 2399void 2400rs6000_expand_vector_set (rtx target, rtx val, int elt) 2401{ 2402 enum machine_mode mode = GET_MODE (target); 2403 enum machine_mode inner_mode = GET_MODE_INNER (mode); 2404 rtx reg = gen_reg_rtx (mode); 2405 rtx mask, mem, x; 2406 int width = GET_MODE_SIZE (inner_mode); 2407 int i; 2408 2409 /* Load single variable value. */ 2410 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0); 2411 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val); 2412 x = gen_rtx_UNSPEC (VOIDmode, 2413 gen_rtvec (1, const0_rtx), UNSPEC_LVE); 2414 emit_insn (gen_rtx_PARALLEL (VOIDmode, 2415 gen_rtvec (2, 2416 gen_rtx_SET (VOIDmode, 2417 reg, mem), 2418 x))); 2419 2420 /* Linear sequence. */ 2421 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16)); 2422 for (i = 0; i < 16; ++i) 2423 XVECEXP (mask, 0, i) = GEN_INT (i); 2424 2425 /* Set permute mask to insert element into target. */ 2426 for (i = 0; i < width; ++i) 2427 XVECEXP (mask, 0, elt*width + i) 2428 = GEN_INT (i + 0x10); 2429 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0)); 2430 x = gen_rtx_UNSPEC (mode, 2431 gen_rtvec (3, target, reg, 2432 force_reg (V16QImode, x)), 2433 UNSPEC_VPERM); 2434 emit_insn (gen_rtx_SET (VOIDmode, target, x)); 2435} 2436 2437/* Extract field ELT from VEC into TARGET. */ 2438 2439void 2440rs6000_expand_vector_extract (rtx target, rtx vec, int elt) 2441{ 2442 enum machine_mode mode = GET_MODE (vec); 2443 enum machine_mode inner_mode = GET_MODE_INNER (mode); 2444 rtx mem, x; 2445 2446 /* Allocate mode-sized buffer. */ 2447 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0); 2448 2449 /* Add offset to field within buffer matching vector element. */ 2450 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode)); 2451 2452 /* Store single field into mode-sized buffer. */ 2453 x = gen_rtx_UNSPEC (VOIDmode, 2454 gen_rtvec (1, const0_rtx), UNSPEC_STVE); 2455 emit_insn (gen_rtx_PARALLEL (VOIDmode, 2456 gen_rtvec (2, 2457 gen_rtx_SET (VOIDmode, 2458 mem, vec), 2459 x))); 2460 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0)); 2461} 2462 2463/* Generates shifts and masks for a pair of rldicl or rldicr insns to 2464 implement ANDing by the mask IN. */ 2465void 2466build_mask64_2_operands (rtx in, rtx *out) 2467{ 2468#if HOST_BITS_PER_WIDE_INT >= 64 2469 unsigned HOST_WIDE_INT c, lsb, m1, m2; 2470 int shift; 2471 2472 gcc_assert (GET_CODE (in) == CONST_INT); 2473 2474 c = INTVAL (in); 2475 if (c & 1) 2476 { 2477 /* Assume c initially something like 0x00fff000000fffff. The idea 2478 is to rotate the word so that the middle ^^^^^^ group of zeros 2479 is at the MS end and can be cleared with an rldicl mask. We then 2480 rotate back and clear off the MS ^^ group of zeros with a 2481 second rldicl. */ 2482 c = ~c; /* c == 0xff000ffffff00000 */ 2483 lsb = c & -c; /* lsb == 0x0000000000100000 */ 2484 m1 = -lsb; /* m1 == 0xfffffffffff00000 */ 2485 c = ~c; /* c == 0x00fff000000fffff */ 2486 c &= -lsb; /* c == 0x00fff00000000000 */ 2487 lsb = c & -c; /* lsb == 0x0000100000000000 */ 2488 c = ~c; /* c == 0xff000fffffffffff */ 2489 c &= -lsb; /* c == 0xff00000000000000 */ 2490 shift = 0; 2491 while ((lsb >>= 1) != 0) 2492 shift++; /* shift == 44 on exit from loop */ 2493 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */ 2494 m1 = ~m1; /* m1 == 0x000000ffffffffff */ 2495 m2 = ~c; /* m2 == 0x00ffffffffffffff */ 2496 } 2497 else 2498 { 2499 /* Assume c initially something like 0xff000f0000000000. The idea 2500 is to rotate the word so that the ^^^ middle group of zeros 2501 is at the LS end and can be cleared with an rldicr mask. We then 2502 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with 2503 a second rldicr. */ 2504 lsb = c & -c; /* lsb == 0x0000010000000000 */ 2505 m2 = -lsb; /* m2 == 0xffffff0000000000 */ 2506 c = ~c; /* c == 0x00fff0ffffffffff */ 2507 c &= -lsb; /* c == 0x00fff00000000000 */ 2508 lsb = c & -c; /* lsb == 0x0000100000000000 */ 2509 c = ~c; /* c == 0xff000fffffffffff */ 2510 c &= -lsb; /* c == 0xff00000000000000 */ 2511 shift = 0; 2512 while ((lsb >>= 1) != 0) 2513 shift++; /* shift == 44 on exit from loop */ 2514 m1 = ~c; /* m1 == 0x00ffffffffffffff */ 2515 m1 >>= shift; /* m1 == 0x0000000000000fff */ 2516 m1 = ~m1; /* m1 == 0xfffffffffffff000 */ 2517 } 2518 2519 /* Note that when we only have two 0->1 and 1->0 transitions, one of the 2520 masks will be all 1's. We are guaranteed more than one transition. */ 2521 out[0] = GEN_INT (64 - shift); 2522 out[1] = GEN_INT (m1); 2523 out[2] = GEN_INT (shift); 2524 out[3] = GEN_INT (m2); 2525#else 2526 (void)in; 2527 (void)out; 2528 gcc_unreachable (); 2529#endif 2530} 2531 2532/* Return TRUE if OP is an invalid SUBREG operation on the e500. */ 2533 2534bool 2535invalid_e500_subreg (rtx op, enum machine_mode mode) 2536{ 2537 if (TARGET_E500_DOUBLE) 2538 { 2539 /* Reject (subreg:SI (reg:DF)). */ 2540 if (GET_CODE (op) == SUBREG 2541 && mode == SImode 2542 && REG_P (SUBREG_REG (op)) 2543 && GET_MODE (SUBREG_REG (op)) == DFmode) 2544 return true; 2545 2546 /* Reject (subreg:DF (reg:DI)). */ 2547 if (GET_CODE (op) == SUBREG 2548 && mode == DFmode 2549 && REG_P (SUBREG_REG (op)) 2550 && GET_MODE (SUBREG_REG (op)) == DImode) 2551 return true; 2552 } 2553 2554 if (TARGET_SPE 2555 && GET_CODE (op) == SUBREG 2556 && mode == SImode 2557 && REG_P (SUBREG_REG (op)) 2558 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op)))) 2559 return true; 2560 2561 return false; 2562} 2563 2564/* Darwin, AIX increases natural record alignment to doubleword if the first 2565 field is an FP double while the FP fields remain word aligned. */ 2566 2567unsigned int 2568rs6000_special_round_type_align (tree type, int computed, int specified) 2569{ 2570 tree field = TYPE_FIELDS (type); 2571 2572 /* Skip all non field decls */ 2573 while (field != NULL && TREE_CODE (field) != FIELD_DECL) 2574 field = TREE_CHAIN (field); 2575 2576 if (field == NULL || field == type || DECL_MODE (field) != DFmode) 2577 return MAX (computed, specified); 2578 2579 return MAX (MAX (computed, specified), 64); 2580} 2581 2582/* Return 1 for an operand in small memory on V.4/eabi. */ 2583 2584int 2585small_data_operand (rtx op ATTRIBUTE_UNUSED, 2586 enum machine_mode mode ATTRIBUTE_UNUSED) 2587{ 2588#if TARGET_ELF 2589 rtx sym_ref; 2590 2591 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) 2592 return 0; 2593 2594 if (DEFAULT_ABI != ABI_V4) 2595 return 0; 2596 2597 if (GET_CODE (op) == SYMBOL_REF) 2598 sym_ref = op; 2599 2600 else if (GET_CODE (op) != CONST 2601 || GET_CODE (XEXP (op, 0)) != PLUS 2602 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF 2603 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) 2604 return 0; 2605 2606 else 2607 { 2608 rtx sum = XEXP (op, 0); 2609 HOST_WIDE_INT summand; 2610 2611 /* We have to be careful here, because it is the referenced address 2612 that must be 32k from _SDA_BASE_, not just the symbol. */ 2613 summand = INTVAL (XEXP (sum, 1)); 2614 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value) 2615 return 0; 2616 2617 sym_ref = XEXP (sum, 0); 2618 } 2619 2620 return SYMBOL_REF_SMALL_P (sym_ref); 2621#else 2622 return 0; 2623#endif 2624} 2625 2626/* Return true if either operand is a general purpose register. */ 2627 2628bool 2629gpr_or_gpr_p (rtx op0, rtx op1) 2630{ 2631 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0))) 2632 || (REG_P (op1) && INT_REGNO_P (REGNO (op1)))); 2633} 2634 2635 2636/* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */ 2637 2638static int 2639constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc) 2640{ 2641 switch (GET_CODE (op)) 2642 { 2643 case SYMBOL_REF: 2644 if (RS6000_SYMBOL_REF_TLS_P (op)) 2645 return 0; 2646 else if (CONSTANT_POOL_ADDRESS_P (op)) 2647 { 2648 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) 2649 { 2650 *have_sym = 1; 2651 return 1; 2652 } 2653 else 2654 return 0; 2655 } 2656 else if (! strcmp (XSTR (op, 0), toc_label_name)) 2657 { 2658 *have_toc = 1; 2659 return 1; 2660 } 2661 else 2662 return 0; 2663 case PLUS: 2664 case MINUS: 2665 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) 2666 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc)); 2667 case CONST: 2668 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); 2669 case CONST_INT: 2670 return 1; 2671 default: 2672 return 0; 2673 } 2674} 2675 2676static bool 2677constant_pool_expr_p (rtx op) 2678{ 2679 int have_sym = 0; 2680 int have_toc = 0; 2681 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; 2682} 2683 2684bool 2685toc_relative_expr_p (rtx op) 2686{ 2687 int have_sym = 0; 2688 int have_toc = 0; 2689 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; 2690} 2691 2692bool 2693legitimate_constant_pool_address_p (rtx x) 2694{ 2695 return (TARGET_TOC 2696 && GET_CODE (x) == PLUS 2697 && GET_CODE (XEXP (x, 0)) == REG 2698 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER) 2699 && constant_pool_expr_p (XEXP (x, 1))); 2700} 2701 2702bool 2703rs6000_legitimate_small_data_p (enum machine_mode mode, rtx x) 2704{ 2705 return (DEFAULT_ABI == ABI_V4 2706 && !flag_pic && !TARGET_TOC 2707 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST) 2708 && small_data_operand (x, mode)); 2709} 2710 2711/* SPE offset addressing is limited to 5-bits worth of double words. */ 2712#define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0) 2713 2714bool 2715rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict) 2716{ 2717 unsigned HOST_WIDE_INT offset, extra; 2718 2719 if (GET_CODE (x) != PLUS) 2720 return false; 2721 if (GET_CODE (XEXP (x, 0)) != REG) 2722 return false; 2723 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) 2724 return false; 2725 if (legitimate_constant_pool_address_p (x)) 2726 return true; 2727 if (GET_CODE (XEXP (x, 1)) != CONST_INT) 2728 return false; 2729 2730 offset = INTVAL (XEXP (x, 1)); 2731 extra = 0; 2732 switch (mode) 2733 { 2734 case V16QImode: 2735 case V8HImode: 2736 case V4SFmode: 2737 case V4SImode: 2738 /* AltiVec vector modes. Only reg+reg addressing is valid and 2739 constant offset zero should not occur due to canonicalization. 2740 Allow any offset when not strict before reload. */ 2741 return !strict; 2742 2743 case V4HImode: 2744 case V2SImode: 2745 case V1DImode: 2746 case V2SFmode: 2747 /* SPE vector modes. */ 2748 return SPE_CONST_OFFSET_OK (offset); 2749 2750 case DFmode: 2751 if (TARGET_E500_DOUBLE) 2752 return SPE_CONST_OFFSET_OK (offset); 2753 2754 case DImode: 2755 /* On e500v2, we may have: 2756 2757 (subreg:DF (mem:DI (plus (reg) (const_int))) 0). 2758 2759 Which gets addressed with evldd instructions. */ 2760 if (TARGET_E500_DOUBLE) 2761 return SPE_CONST_OFFSET_OK (offset); 2762 2763 if (mode == DFmode || !TARGET_POWERPC64) 2764 extra = 4; 2765 else if (offset & 3) 2766 return false; 2767 break; 2768 2769 case TFmode: 2770 case TImode: 2771 if (mode == TFmode || !TARGET_POWERPC64) 2772 extra = 12; 2773 else if (offset & 3) 2774 return false; 2775 else 2776 extra = 8; 2777 break; 2778 2779 default: 2780 break; 2781 } 2782 2783 offset += 0x8000; 2784 return (offset < 0x10000) && (offset + extra < 0x10000); 2785} 2786 2787static bool 2788legitimate_indexed_address_p (rtx x, int strict) 2789{ 2790 rtx op0, op1; 2791 2792 if (GET_CODE (x) != PLUS) 2793 return false; 2794 2795 op0 = XEXP (x, 0); 2796 op1 = XEXP (x, 1); 2797 2798 /* Recognize the rtl generated by reload which we know will later be 2799 replaced with proper base and index regs. */ 2800 if (!strict 2801 && reload_in_progress 2802 && (REG_P (op0) || GET_CODE (op0) == PLUS) 2803 && REG_P (op1)) 2804 return true; 2805 2806 return (REG_P (op0) && REG_P (op1) 2807 && ((INT_REG_OK_FOR_BASE_P (op0, strict) 2808 && INT_REG_OK_FOR_INDEX_P (op1, strict)) 2809 || (INT_REG_OK_FOR_BASE_P (op1, strict) 2810 && INT_REG_OK_FOR_INDEX_P (op0, strict)))); 2811} 2812 2813inline bool 2814legitimate_indirect_address_p (rtx x, int strict) 2815{ 2816 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict); 2817} 2818 2819bool 2820macho_lo_sum_memory_operand (rtx x, enum machine_mode mode) 2821{ 2822 if (!TARGET_MACHO || !flag_pic 2823 || mode != SImode || GET_CODE (x) != MEM) 2824 return false; 2825 x = XEXP (x, 0); 2826 2827 if (GET_CODE (x) != LO_SUM) 2828 return false; 2829 if (GET_CODE (XEXP (x, 0)) != REG) 2830 return false; 2831 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0)) 2832 return false; 2833 x = XEXP (x, 1); 2834 2835 return CONSTANT_P (x); 2836} 2837 2838static bool 2839legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict) 2840{ 2841 if (GET_CODE (x) != LO_SUM) 2842 return false; 2843 if (GET_CODE (XEXP (x, 0)) != REG) 2844 return false; 2845 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) 2846 return false; 2847 /* Restrict addressing for DI because of our SUBREG hackery. */ 2848 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode)) 2849 return false; 2850 x = XEXP (x, 1); 2851 2852 if (TARGET_ELF || TARGET_MACHO) 2853 { 2854 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic) 2855 return false; 2856 if (TARGET_TOC) 2857 return false; 2858 if (GET_MODE_NUNITS (mode) != 1) 2859 return false; 2860 if (GET_MODE_BITSIZE (mode) > 64 2861 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64 2862 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode))) 2863 return false; 2864 2865 return CONSTANT_P (x); 2866 } 2867 2868 return false; 2869} 2870 2871 2872/* Try machine-dependent ways of modifying an illegitimate address 2873 to be legitimate. If we find one, return the new, valid address. 2874 This is used from only one place: `memory_address' in explow.c. 2875 2876 OLDX is the address as it was before break_out_memory_refs was 2877 called. In some cases it is useful to look at this to decide what 2878 needs to be done. 2879 2880 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS. 2881 2882 It is always safe for this function to do nothing. It exists to 2883 recognize opportunities to optimize the output. 2884 2885 On RS/6000, first check for the sum of a register with a constant 2886 integer that is out of range. If so, generate code to add the 2887 constant with the low-order 16 bits masked to the register and force 2888 this result into another register (this can be done with `cau'). 2889 Then generate an address of REG+(CONST&0xffff), allowing for the 2890 possibility of bit 16 being a one. 2891 2892 Then check for the sum of a register and something not constant, try to 2893 load the other things into a register and return the sum. */ 2894 2895rtx 2896rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, 2897 enum machine_mode mode) 2898{ 2899 if (GET_CODE (x) == SYMBOL_REF) 2900 { 2901 enum tls_model model = SYMBOL_REF_TLS_MODEL (x); 2902 if (model != 0) 2903 return rs6000_legitimize_tls_address (x, model); 2904 } 2905 2906 if (GET_CODE (x) == PLUS 2907 && GET_CODE (XEXP (x, 0)) == REG 2908 && GET_CODE (XEXP (x, 1)) == CONST_INT 2909 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) 2910 { 2911 HOST_WIDE_INT high_int, low_int; 2912 rtx sum; 2913 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000; 2914 high_int = INTVAL (XEXP (x, 1)) - low_int; 2915 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), 2916 GEN_INT (high_int)), 0); 2917 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); 2918 } 2919 else if (GET_CODE (x) == PLUS 2920 && GET_CODE (XEXP (x, 0)) == REG 2921 && GET_CODE (XEXP (x, 1)) != CONST_INT 2922 && GET_MODE_NUNITS (mode) == 1 2923 && ((TARGET_HARD_FLOAT && TARGET_FPRS) 2924 || TARGET_POWERPC64 2925 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE) 2926 && mode != TFmode)) 2927 && (TARGET_POWERPC64 || mode != DImode) 2928 && mode != TImode) 2929 { 2930 return gen_rtx_PLUS (Pmode, XEXP (x, 0), 2931 force_reg (Pmode, force_operand (XEXP (x, 1), 0))); 2932 } 2933 else if (ALTIVEC_VECTOR_MODE (mode)) 2934 { 2935 rtx reg; 2936 2937 /* Make sure both operands are registers. */ 2938 if (GET_CODE (x) == PLUS) 2939 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), 2940 force_reg (Pmode, XEXP (x, 1))); 2941 2942 reg = force_reg (Pmode, x); 2943 return reg; 2944 } 2945 else if (SPE_VECTOR_MODE (mode) 2946 || (TARGET_E500_DOUBLE && (mode == DFmode 2947 || mode == DImode))) 2948 { 2949 if (mode == DImode) 2950 return NULL_RTX; 2951 /* We accept [reg + reg] and [reg + OFFSET]. */ 2952 2953 if (GET_CODE (x) == PLUS) 2954 { 2955 rtx op1 = XEXP (x, 0); 2956 rtx op2 = XEXP (x, 1); 2957 2958 op1 = force_reg (Pmode, op1); 2959 2960 if (GET_CODE (op2) != REG 2961 && (GET_CODE (op2) != CONST_INT 2962 || !SPE_CONST_OFFSET_OK (INTVAL (op2)))) 2963 op2 = force_reg (Pmode, op2); 2964 2965 return gen_rtx_PLUS (Pmode, op1, op2); 2966 } 2967 2968 return force_reg (Pmode, x); 2969 } 2970 else if (TARGET_ELF 2971 && TARGET_32BIT 2972 && TARGET_NO_TOC 2973 && ! flag_pic 2974 && GET_CODE (x) != CONST_INT 2975 && GET_CODE (x) != CONST_DOUBLE 2976 && CONSTANT_P (x) 2977 && GET_MODE_NUNITS (mode) == 1 2978 && (GET_MODE_BITSIZE (mode) <= 32 2979 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode))) 2980 { 2981 rtx reg = gen_reg_rtx (Pmode); 2982 emit_insn (gen_elf_high (reg, x)); 2983 return gen_rtx_LO_SUM (Pmode, reg, x); 2984 } 2985 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC 2986 && ! flag_pic 2987#if TARGET_MACHO 2988 && ! MACHO_DYNAMIC_NO_PIC_P 2989#endif 2990 && GET_CODE (x) != CONST_INT 2991 && GET_CODE (x) != CONST_DOUBLE 2992 && CONSTANT_P (x) 2993 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode) 2994 && mode != DImode 2995 && mode != TImode) 2996 { 2997 rtx reg = gen_reg_rtx (Pmode); 2998 emit_insn (gen_macho_high (reg, x)); 2999 return gen_rtx_LO_SUM (Pmode, reg, x); 3000 } 3001 else if (TARGET_TOC 3002 && constant_pool_expr_p (x) 3003 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) 3004 { 3005 return create_TOC_reference (x); 3006 } 3007 else 3008 return NULL_RTX; 3009} 3010 3011/* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. 3012 We need to emit DTP-relative relocations. */ 3013 3014static void 3015rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x) 3016{ 3017 switch (size) 3018 { 3019 case 4: 3020 fputs ("\t.long\t", file); 3021 break; 3022 case 8: 3023 fputs (DOUBLE_INT_ASM_OP, file); 3024 break; 3025 default: 3026 gcc_unreachable (); 3027 } 3028 output_addr_const (file, x); 3029 fputs ("@dtprel+0x8000", file); 3030} 3031 3032/* Construct the SYMBOL_REF for the tls_get_addr function. */ 3033 3034static GTY(()) rtx rs6000_tls_symbol; 3035static rtx 3036rs6000_tls_get_addr (void) 3037{ 3038 if (!rs6000_tls_symbol) 3039 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr"); 3040 3041 return rs6000_tls_symbol; 3042} 3043 3044/* Construct the SYMBOL_REF for TLS GOT references. */ 3045 3046static GTY(()) rtx rs6000_got_symbol; 3047static rtx 3048rs6000_got_sym (void) 3049{ 3050 if (!rs6000_got_symbol) 3051 { 3052 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); 3053 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL; 3054 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL; 3055 } 3056 3057 return rs6000_got_symbol; 3058} 3059 3060/* ADDR contains a thread-local SYMBOL_REF. Generate code to compute 3061 this (thread-local) address. */ 3062 3063static rtx 3064rs6000_legitimize_tls_address (rtx addr, enum tls_model model) 3065{ 3066 rtx dest, insn; 3067 3068 dest = gen_reg_rtx (Pmode); 3069 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16) 3070 { 3071 rtx tlsreg; 3072 3073 if (TARGET_64BIT) 3074 { 3075 tlsreg = gen_rtx_REG (Pmode, 13); 3076 insn = gen_tls_tprel_64 (dest, tlsreg, addr); 3077 } 3078 else 3079 { 3080 tlsreg = gen_rtx_REG (Pmode, 2); 3081 insn = gen_tls_tprel_32 (dest, tlsreg, addr); 3082 } 3083 emit_insn (insn); 3084 } 3085 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32) 3086 { 3087 rtx tlsreg, tmp; 3088 3089 tmp = gen_reg_rtx (Pmode); 3090 if (TARGET_64BIT) 3091 { 3092 tlsreg = gen_rtx_REG (Pmode, 13); 3093 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr); 3094 } 3095 else 3096 { 3097 tlsreg = gen_rtx_REG (Pmode, 2); 3098 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr); 3099 } 3100 emit_insn (insn); 3101 if (TARGET_64BIT) 3102 insn = gen_tls_tprel_lo_64 (dest, tmp, addr); 3103 else 3104 insn = gen_tls_tprel_lo_32 (dest, tmp, addr); 3105 emit_insn (insn); 3106 } 3107 else 3108 { 3109 rtx r3, got, tga, tmp1, tmp2, eqv; 3110 3111 /* We currently use relocations like @got@tlsgd for tls, which 3112 means the linker will handle allocation of tls entries, placing 3113 them in the .got section. So use a pointer to the .got section, 3114 not one to secondary TOC sections used by 64-bit -mminimal-toc, 3115 or to secondary GOT sections used by 32-bit -fPIC. */ 3116 if (TARGET_64BIT) 3117 got = gen_rtx_REG (Pmode, 2); 3118 else 3119 { 3120 if (flag_pic == 1) 3121 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); 3122 else 3123 { 3124 rtx gsym = rs6000_got_sym (); 3125 got = gen_reg_rtx (Pmode); 3126 if (flag_pic == 0) 3127 rs6000_emit_move (got, gsym, Pmode); 3128 else 3129 { 3130 rtx tempLR, tmp3, mem; 3131 rtx first, last; 3132 3133 tempLR = gen_reg_rtx (Pmode); 3134 tmp1 = gen_reg_rtx (Pmode); 3135 tmp2 = gen_reg_rtx (Pmode); 3136 tmp3 = gen_reg_rtx (Pmode); 3137 mem = gen_const_mem (Pmode, tmp1); 3138 3139 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym)); 3140 emit_move_insn (tmp1, tempLR); 3141 emit_move_insn (tmp2, mem); 3142 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2)); 3143 last = emit_move_insn (got, tmp3); 3144 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym, 3145 REG_NOTES (last)); 3146 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, 3147 REG_NOTES (first)); 3148 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, 3149 REG_NOTES (last)); 3150 } 3151 } 3152 } 3153 3154 if (model == TLS_MODEL_GLOBAL_DYNAMIC) 3155 { 3156 r3 = gen_rtx_REG (Pmode, 3); 3157 if (TARGET_64BIT) 3158 insn = gen_tls_gd_64 (r3, got, addr); 3159 else 3160 insn = gen_tls_gd_32 (r3, got, addr); 3161 start_sequence (); 3162 emit_insn (insn); 3163 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); 3164 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); 3165 insn = emit_call_insn (insn); 3166 CONST_OR_PURE_CALL_P (insn) = 1; 3167 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); 3168 insn = get_insns (); 3169 end_sequence (); 3170 emit_libcall_block (insn, dest, r3, addr); 3171 } 3172 else if (model == TLS_MODEL_LOCAL_DYNAMIC) 3173 { 3174 r3 = gen_rtx_REG (Pmode, 3); 3175 if (TARGET_64BIT) 3176 insn = gen_tls_ld_64 (r3, got); 3177 else 3178 insn = gen_tls_ld_32 (r3, got); 3179 start_sequence (); 3180 emit_insn (insn); 3181 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); 3182 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); 3183 insn = emit_call_insn (insn); 3184 CONST_OR_PURE_CALL_P (insn) = 1; 3185 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); 3186 insn = get_insns (); 3187 end_sequence (); 3188 tmp1 = gen_reg_rtx (Pmode); 3189 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), 3190 UNSPEC_TLSLD); 3191 emit_libcall_block (insn, tmp1, r3, eqv); 3192 if (rs6000_tls_size == 16) 3193 { 3194 if (TARGET_64BIT) 3195 insn = gen_tls_dtprel_64 (dest, tmp1, addr); 3196 else 3197 insn = gen_tls_dtprel_32 (dest, tmp1, addr); 3198 } 3199 else if (rs6000_tls_size == 32) 3200 { 3201 tmp2 = gen_reg_rtx (Pmode); 3202 if (TARGET_64BIT) 3203 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr); 3204 else 3205 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr); 3206 emit_insn (insn); 3207 if (TARGET_64BIT) 3208 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr); 3209 else 3210 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr); 3211 } 3212 else 3213 { 3214 tmp2 = gen_reg_rtx (Pmode); 3215 if (TARGET_64BIT) 3216 insn = gen_tls_got_dtprel_64 (tmp2, got, addr); 3217 else 3218 insn = gen_tls_got_dtprel_32 (tmp2, got, addr); 3219 emit_insn (insn); 3220 insn = gen_rtx_SET (Pmode, dest, 3221 gen_rtx_PLUS (Pmode, tmp2, tmp1)); 3222 } 3223 emit_insn (insn); 3224 } 3225 else 3226 { 3227 /* IE, or 64 bit offset LE. */ 3228 tmp2 = gen_reg_rtx (Pmode); 3229 if (TARGET_64BIT) 3230 insn = gen_tls_got_tprel_64 (tmp2, got, addr); 3231 else 3232 insn = gen_tls_got_tprel_32 (tmp2, got, addr); 3233 emit_insn (insn); 3234 if (TARGET_64BIT) 3235 insn = gen_tls_tls_64 (dest, tmp2, addr); 3236 else 3237 insn = gen_tls_tls_32 (dest, tmp2, addr); 3238 emit_insn (insn); 3239 } 3240 } 3241 3242 return dest; 3243} 3244 3245/* Return 1 if X contains a thread-local symbol. */ 3246 3247bool 3248rs6000_tls_referenced_p (rtx x) 3249{ 3250 if (! TARGET_HAVE_TLS) 3251 return false; 3252 3253 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0); 3254} 3255 3256/* Return 1 if *X is a thread-local symbol. This is the same as 3257 rs6000_tls_symbol_ref except for the type of the unused argument. */ 3258 3259static int 3260rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) 3261{ 3262 return RS6000_SYMBOL_REF_TLS_P (*x); 3263} 3264 3265/* The convention appears to be to define this wherever it is used. 3266 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P 3267 is now used here. */ 3268#ifndef REG_MODE_OK_FOR_BASE_P 3269#define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO) 3270#endif 3271 3272/* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to 3273 replace the input X, or the original X if no replacement is called for. 3274 The output parameter *WIN is 1 if the calling macro should goto WIN, 3275 0 if it should not. 3276 3277 For RS/6000, we wish to handle large displacements off a base 3278 register by splitting the addend across an addiu/addis and the mem insn. 3279 This cuts number of extra insns needed from 3 to 1. 3280 3281 On Darwin, we use this to generate code for floating point constants. 3282 A movsf_low is generated so we wind up with 2 instructions rather than 3. 3283 The Darwin code is inside #if TARGET_MACHO because only then is 3284 machopic_function_base_name() defined. */ 3285rtx 3286rs6000_legitimize_reload_address (rtx x, enum machine_mode mode, 3287 int opnum, int type, 3288 int ind_levels ATTRIBUTE_UNUSED, int *win) 3289{ 3290 /* We must recognize output that we have already generated ourselves. */ 3291 if (GET_CODE (x) == PLUS 3292 && GET_CODE (XEXP (x, 0)) == PLUS 3293 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG 3294 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3295 && GET_CODE (XEXP (x, 1)) == CONST_INT) 3296 { 3297 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, 3298 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, 3299 opnum, (enum reload_type)type); 3300 *win = 1; 3301 return x; 3302 } 3303 3304#if TARGET_MACHO 3305 if (DEFAULT_ABI == ABI_DARWIN && flag_pic 3306 && GET_CODE (x) == LO_SUM 3307 && GET_CODE (XEXP (x, 0)) == PLUS 3308 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx 3309 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH 3310 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST 3311 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1) 3312 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS 3313 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF 3314 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF) 3315 { 3316 /* Result of previous invocation of this function on Darwin 3317 floating point constant. */ 3318 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, 3319 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, 3320 opnum, (enum reload_type)type); 3321 *win = 1; 3322 return x; 3323 } 3324#endif 3325 3326 /* Force ld/std non-word aligned offset into base register by wrapping 3327 in offset 0. */ 3328 if (GET_CODE (x) == PLUS 3329 && GET_CODE (XEXP (x, 0)) == REG 3330 && REGNO (XEXP (x, 0)) < 32 3331 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) 3332 && GET_CODE (XEXP (x, 1)) == CONST_INT 3333 && (INTVAL (XEXP (x, 1)) & 3) != 0 3334 && !ALTIVEC_VECTOR_MODE (mode) 3335 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD 3336 && TARGET_POWERPC64) 3337 { 3338 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0)); 3339 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, 3340 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, 3341 opnum, (enum reload_type) type); 3342 *win = 1; 3343 return x; 3344 } 3345 3346 if (GET_CODE (x) == PLUS 3347 && GET_CODE (XEXP (x, 0)) == REG 3348 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER 3349 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) 3350 && GET_CODE (XEXP (x, 1)) == CONST_INT 3351 && !SPE_VECTOR_MODE (mode) 3352 && !(TARGET_E500_DOUBLE && (mode == DFmode 3353 || mode == DImode)) 3354 && !ALTIVEC_VECTOR_MODE (mode)) 3355 { 3356 HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); 3357 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; 3358 HOST_WIDE_INT high 3359 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; 3360 3361 /* Check for 32-bit overflow. */ 3362 if (high + low != val) 3363 { 3364 *win = 0; 3365 return x; 3366 } 3367 3368 /* Reload the high part into a base reg; leave the low part 3369 in the mem directly. */ 3370 3371 x = gen_rtx_PLUS (GET_MODE (x), 3372 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), 3373 GEN_INT (high)), 3374 GEN_INT (low)); 3375 3376 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, 3377 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, 3378 opnum, (enum reload_type)type); 3379 *win = 1; 3380 return x; 3381 } 3382 3383 if (GET_CODE (x) == SYMBOL_REF 3384 && !ALTIVEC_VECTOR_MODE (mode) 3385 && !SPE_VECTOR_MODE (mode) 3386#if TARGET_MACHO 3387 && DEFAULT_ABI == ABI_DARWIN 3388 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P) 3389#else 3390 && DEFAULT_ABI == ABI_V4 3391 && !flag_pic 3392#endif 3393 /* Don't do this for TFmode, since the result isn't offsettable. 3394 The same goes for DImode without 64-bit gprs and DFmode 3395 without fprs. */ 3396 && mode != TFmode 3397 && (mode != DImode || TARGET_POWERPC64) 3398 && (mode != DFmode || TARGET_POWERPC64 3399 || (TARGET_FPRS && TARGET_HARD_FLOAT))) 3400 { 3401#if TARGET_MACHO 3402 if (flag_pic) 3403 { 3404 rtx offset = gen_rtx_CONST (Pmode, 3405 gen_rtx_MINUS (Pmode, x, 3406 machopic_function_base_sym ())); 3407 x = gen_rtx_LO_SUM (GET_MODE (x), 3408 gen_rtx_PLUS (Pmode, pic_offset_table_rtx, 3409 gen_rtx_HIGH (Pmode, offset)), offset); 3410 } 3411 else 3412#endif 3413 x = gen_rtx_LO_SUM (GET_MODE (x), 3414 gen_rtx_HIGH (Pmode, x), x); 3415 3416 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, 3417 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, 3418 opnum, (enum reload_type)type); 3419 *win = 1; 3420 return x; 3421 } 3422 3423 /* Reload an offset address wrapped by an AND that represents the 3424 masking of the lower bits. Strip the outer AND and let reload 3425 convert the offset address into an indirect address. */ 3426 if (TARGET_ALTIVEC 3427 && ALTIVEC_VECTOR_MODE (mode) 3428 && GET_CODE (x) == AND 3429 && GET_CODE (XEXP (x, 0)) == PLUS 3430 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG 3431 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3432 && GET_CODE (XEXP (x, 1)) == CONST_INT 3433 && INTVAL (XEXP (x, 1)) == -16) 3434 { 3435 x = XEXP (x, 0); 3436 *win = 1; 3437 return x; 3438 } 3439 3440 if (TARGET_TOC 3441 && constant_pool_expr_p (x) 3442 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode)) 3443 { 3444 (x) = create_TOC_reference (x); 3445 *win = 1; 3446 return x; 3447 } 3448 *win = 0; 3449 return x; 3450} 3451 3452/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 3453 that is a valid memory address for an instruction. 3454 The MODE argument is the machine mode for the MEM expression 3455 that wants to use this address. 3456 3457 On the RS/6000, there are four valid address: a SYMBOL_REF that 3458 refers to a constant pool entry of an address (or the sum of it 3459 plus a constant), a short (16-bit signed) constant plus a register, 3460 the sum of two registers, or a register indirect, possibly with an 3461 auto-increment. For DFmode and DImode with a constant plus register, 3462 we must ensure that both words are addressable or PowerPC64 with offset 3463 word aligned. 3464 3465 For modes spanning multiple registers (DFmode in 32-bit GPRs, 3466 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because 3467 adjacent memory cells are accessed by adding word-sized offsets 3468 during assembly output. */ 3469int 3470rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict) 3471{ 3472 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */ 3473 if (TARGET_ALTIVEC 3474 && ALTIVEC_VECTOR_MODE (mode) 3475 && GET_CODE (x) == AND 3476 && GET_CODE (XEXP (x, 1)) == CONST_INT 3477 && INTVAL (XEXP (x, 1)) == -16) 3478 x = XEXP (x, 0); 3479 3480 if (RS6000_SYMBOL_REF_TLS_P (x)) 3481 return 0; 3482 if (legitimate_indirect_address_p (x, reg_ok_strict)) 3483 return 1; 3484 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) 3485 && !ALTIVEC_VECTOR_MODE (mode) 3486 && !SPE_VECTOR_MODE (mode) 3487 && mode != TFmode 3488 /* Restrict addressing for DI because of our SUBREG hackery. */ 3489 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode)) 3490 && TARGET_UPDATE 3491 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)) 3492 return 1; 3493 if (rs6000_legitimate_small_data_p (mode, x)) 3494 return 1; 3495 if (legitimate_constant_pool_address_p (x)) 3496 return 1; 3497 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ 3498 if (! reg_ok_strict 3499 && GET_CODE (x) == PLUS 3500 && GET_CODE (XEXP (x, 0)) == REG 3501 && (XEXP (x, 0) == virtual_stack_vars_rtx 3502 || XEXP (x, 0) == arg_pointer_rtx) 3503 && GET_CODE (XEXP (x, 1)) == CONST_INT) 3504 return 1; 3505 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict)) 3506 return 1; 3507 if (mode != TImode 3508 && mode != TFmode 3509 && ((TARGET_HARD_FLOAT && TARGET_FPRS) 3510 || TARGET_POWERPC64 3511 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode)) 3512 && (TARGET_POWERPC64 || mode != DImode) 3513 && legitimate_indexed_address_p (x, reg_ok_strict)) 3514 return 1; 3515 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict)) 3516 return 1; 3517 return 0; 3518} 3519 3520/* Go to LABEL if ADDR (a legitimate address expression) 3521 has an effect that depends on the machine mode it is used for. 3522 3523 On the RS/6000 this is true of all integral offsets (since AltiVec 3524 modes don't allow them) or is a pre-increment or decrement. 3525 3526 ??? Except that due to conceptual problems in offsettable_address_p 3527 we can't really report the problems of integral offsets. So leave 3528 this assuming that the adjustable offset must be valid for the 3529 sub-words of a TFmode operand, which is what we had before. */ 3530 3531bool 3532rs6000_mode_dependent_address (rtx addr) 3533{ 3534 switch (GET_CODE (addr)) 3535 { 3536 case PLUS: 3537 if (GET_CODE (XEXP (addr, 1)) == CONST_INT) 3538 { 3539 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1)); 3540 return val + 12 + 0x8000 >= 0x10000; 3541 } 3542 break; 3543 3544 case LO_SUM: 3545 return true; 3546 3547 case PRE_INC: 3548 case PRE_DEC: 3549 return TARGET_UPDATE; 3550 3551 default: 3552 break; 3553 } 3554 3555 return false; 3556} 3557 3558/* Return number of consecutive hard regs needed starting at reg REGNO 3559 to hold something of mode MODE. 3560 This is ordinarily the length in words of a value of mode MODE 3561 but can be less for certain modes in special long registers. 3562 3563 For the SPE, GPRs are 64 bits but only 32 bits are visible in 3564 scalar instructions. The upper 32 bits are only available to the 3565 SIMD instructions. 3566 3567 POWER and PowerPC GPRs hold 32 bits worth; 3568 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */ 3569 3570int 3571rs6000_hard_regno_nregs (int regno, enum machine_mode mode) 3572{ 3573 if (FP_REGNO_P (regno)) 3574 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD; 3575 3576 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) 3577 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD; 3578 3579 if (ALTIVEC_REGNO_P (regno)) 3580 return 3581 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD; 3582 3583 /* The value returned for SCmode in the E500 double case is 2 for 3584 ABI compatibility; storing an SCmode value in a single register 3585 would require function_arg and rs6000_spe_function_arg to handle 3586 SCmode so as to pass the value correctly in a pair of 3587 registers. */ 3588 if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode) 3589 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD; 3590 3591 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 3592} 3593 3594/* Change register usage conditional on target flags. */ 3595void 3596rs6000_conditional_register_usage (void) 3597{ 3598 int i; 3599 3600 /* Set MQ register fixed (already call_used) if not POWER 3601 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not 3602 be allocated. */ 3603 if (! TARGET_POWER) 3604 fixed_regs[64] = 1; 3605 3606 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */ 3607 if (TARGET_64BIT) 3608 fixed_regs[13] = call_used_regs[13] 3609 = call_really_used_regs[13] = 1; 3610 3611 /* Conditionally disable FPRs. */ 3612 if (TARGET_SOFT_FLOAT || !TARGET_FPRS) 3613 for (i = 32; i < 64; i++) 3614 fixed_regs[i] = call_used_regs[i] 3615 = call_really_used_regs[i] = 1; 3616 3617 /* The TOC register is not killed across calls in a way that is 3618 visible to the compiler. */ 3619 if (DEFAULT_ABI == ABI_AIX) 3620 call_really_used_regs[2] = 0; 3621 3622 if (DEFAULT_ABI == ABI_V4 3623 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM 3624 && flag_pic == 2) 3625 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; 3626 3627 if (DEFAULT_ABI == ABI_V4 3628 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM 3629 && flag_pic == 1) 3630 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] 3631 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] 3632 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; 3633 3634 if (DEFAULT_ABI == ABI_DARWIN 3635 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) 3636 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] 3637 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] 3638 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; 3639 3640 if (TARGET_TOC && TARGET_MINIMAL_TOC) 3641 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] 3642 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; 3643 3644 if (TARGET_ALTIVEC) 3645 global_regs[VSCR_REGNO] = 1; 3646 3647 if (TARGET_SPE) 3648 { 3649 global_regs[SPEFSCR_REGNO] = 1; 3650 fixed_regs[FIXED_SCRATCH] 3651 = call_used_regs[FIXED_SCRATCH] 3652 = call_really_used_regs[FIXED_SCRATCH] = 1; 3653 } 3654 3655 if (! TARGET_ALTIVEC) 3656 { 3657 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) 3658 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; 3659 call_really_used_regs[VRSAVE_REGNO] = 1; 3660 } 3661 3662 if (TARGET_ALTIVEC_ABI) 3663 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) 3664 call_used_regs[i] = call_really_used_regs[i] = 1; 3665} 3666 3667/* Try to output insns to set TARGET equal to the constant C if it can 3668 be done in less than N insns. Do all computations in MODE. 3669 Returns the place where the output has been placed if it can be 3670 done and the insns have been emitted. If it would take more than N 3671 insns, zero is returned and no insns and emitted. */ 3672 3673rtx 3674rs6000_emit_set_const (rtx dest, enum machine_mode mode, 3675 rtx source, int n ATTRIBUTE_UNUSED) 3676{ 3677 rtx result, insn, set; 3678 HOST_WIDE_INT c0, c1; 3679 3680 switch (mode) 3681 { 3682 case QImode: 3683 case HImode: 3684 if (dest == NULL) 3685 dest = gen_reg_rtx (mode); 3686 emit_insn (gen_rtx_SET (VOIDmode, dest, source)); 3687 return dest; 3688 3689 case SImode: 3690 result = no_new_pseudos ? dest : gen_reg_rtx (SImode); 3691 3692 emit_insn (gen_rtx_SET (VOIDmode, result, 3693 GEN_INT (INTVAL (source) 3694 & (~ (HOST_WIDE_INT) 0xffff)))); 3695 emit_insn (gen_rtx_SET (VOIDmode, dest, 3696 gen_rtx_IOR (SImode, result, 3697 GEN_INT (INTVAL (source) & 0xffff)))); 3698 result = dest; 3699 break; 3700 3701 case DImode: 3702 switch (GET_CODE (source)) 3703 { 3704 case CONST_INT: 3705 c0 = INTVAL (source); 3706 c1 = -(c0 < 0); 3707 break; 3708 3709 case CONST_DOUBLE: 3710#if HOST_BITS_PER_WIDE_INT >= 64 3711 c0 = CONST_DOUBLE_LOW (source); 3712 c1 = -(c0 < 0); 3713#else 3714 c0 = CONST_DOUBLE_LOW (source); 3715 c1 = CONST_DOUBLE_HIGH (source); 3716#endif 3717 break; 3718 3719 default: 3720 gcc_unreachable (); 3721 } 3722 3723 result = rs6000_emit_set_long_const (dest, c0, c1); 3724 break; 3725 3726 default: 3727 gcc_unreachable (); 3728 } 3729 3730 insn = get_last_insn (); 3731 set = single_set (insn); 3732 if (! CONSTANT_P (SET_SRC (set))) 3733 set_unique_reg_note (insn, REG_EQUAL, source); 3734 3735 return result; 3736} 3737 3738/* Having failed to find a 3 insn sequence in rs6000_emit_set_const, 3739 fall back to a straight forward decomposition. We do this to avoid 3740 exponential run times encountered when looking for longer sequences 3741 with rs6000_emit_set_const. */ 3742static rtx 3743rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2) 3744{ 3745 if (!TARGET_POWERPC64) 3746 { 3747 rtx operand1, operand2; 3748 3749 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, 3750 DImode); 3751 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, 3752 DImode); 3753 emit_move_insn (operand1, GEN_INT (c1)); 3754 emit_move_insn (operand2, GEN_INT (c2)); 3755 } 3756 else 3757 { 3758 HOST_WIDE_INT ud1, ud2, ud3, ud4; 3759 3760 ud1 = c1 & 0xffff; 3761 ud2 = (c1 & 0xffff0000) >> 16; 3762#if HOST_BITS_PER_WIDE_INT >= 64 3763 c2 = c1 >> 32; 3764#endif 3765 ud3 = c2 & 0xffff; 3766 ud4 = (c2 & 0xffff0000) >> 16; 3767 3768 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000)) 3769 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000))) 3770 { 3771 if (ud1 & 0x8000) 3772 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000))); 3773 else 3774 emit_move_insn (dest, GEN_INT (ud1)); 3775 } 3776 3777 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000)) 3778 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000))) 3779 { 3780 if (ud2 & 0x8000) 3781 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000) 3782 - 0x80000000)); 3783 else 3784 emit_move_insn (dest, GEN_INT (ud2 << 16)); 3785 if (ud1 != 0) 3786 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); 3787 } 3788 else if ((ud4 == 0xffff && (ud3 & 0x8000)) 3789 || (ud4 == 0 && ! (ud3 & 0x8000))) 3790 { 3791 if (ud3 & 0x8000) 3792 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000) 3793 - 0x80000000)); 3794 else 3795 emit_move_insn (dest, GEN_INT (ud3 << 16)); 3796 3797 if (ud2 != 0) 3798 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2))); 3799 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16))); 3800 if (ud1 != 0) 3801 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); 3802 } 3803 else 3804 { 3805 if (ud4 & 0x8000) 3806 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000) 3807 - 0x80000000)); 3808 else 3809 emit_move_insn (dest, GEN_INT (ud4 << 16)); 3810 3811 if (ud3 != 0) 3812 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3))); 3813 3814 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); 3815 if (ud2 != 0) 3816 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, 3817 GEN_INT (ud2 << 16))); 3818 if (ud1 != 0) 3819 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); 3820 } 3821 } 3822 return dest; 3823} 3824 3825/* Helper for the following. Get rid of [r+r] memory refs 3826 in cases where it won't work (TImode, TFmode). */ 3827 3828static void 3829rs6000_eliminate_indexed_memrefs (rtx operands[2]) 3830{ 3831 if (GET_CODE (operands[0]) == MEM 3832 && GET_CODE (XEXP (operands[0], 0)) != REG 3833 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0)) 3834 && ! reload_in_progress) 3835 operands[0] 3836 = replace_equiv_address (operands[0], 3837 copy_addr_to_reg (XEXP (operands[0], 0))); 3838 3839 if (GET_CODE (operands[1]) == MEM 3840 && GET_CODE (XEXP (operands[1], 0)) != REG 3841 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0)) 3842 && ! reload_in_progress) 3843 operands[1] 3844 = replace_equiv_address (operands[1], 3845 copy_addr_to_reg (XEXP (operands[1], 0))); 3846} 3847 3848/* Emit a move from SOURCE to DEST in mode MODE. */ 3849void 3850rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) 3851{ 3852 rtx operands[2]; 3853 operands[0] = dest; 3854 operands[1] = source; 3855 3856 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ 3857 if (GET_CODE (operands[1]) == CONST_DOUBLE 3858 && ! FLOAT_MODE_P (mode) 3859 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 3860 { 3861 /* FIXME. This should never happen. */ 3862 /* Since it seems that it does, do the safe thing and convert 3863 to a CONST_INT. */ 3864 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode); 3865 } 3866 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE 3867 || FLOAT_MODE_P (mode) 3868 || ((CONST_DOUBLE_HIGH (operands[1]) != 0 3869 || CONST_DOUBLE_LOW (operands[1]) < 0) 3870 && (CONST_DOUBLE_HIGH (operands[1]) != -1 3871 || CONST_DOUBLE_LOW (operands[1]) >= 0))); 3872 3873 /* Check if GCC is setting up a block move that will end up using FP 3874 registers as temporaries. We must make sure this is acceptable. */ 3875 if (GET_CODE (operands[0]) == MEM 3876 && GET_CODE (operands[1]) == MEM 3877 && mode == DImode 3878 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0])) 3879 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1]))) 3880 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32 3881 ? 32 : MEM_ALIGN (operands[0]))) 3882 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32 3883 ? 32 3884 : MEM_ALIGN (operands[1])))) 3885 && ! MEM_VOLATILE_P (operands [0]) 3886 && ! MEM_VOLATILE_P (operands [1])) 3887 { 3888 emit_move_insn (adjust_address (operands[0], SImode, 0), 3889 adjust_address (operands[1], SImode, 0)); 3890 emit_move_insn (adjust_address (operands[0], SImode, 4), 3891 adjust_address (operands[1], SImode, 4)); 3892 return; 3893 } 3894 3895 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM 3896 && !gpc_reg_operand (operands[1], mode)) 3897 operands[1] = force_reg (mode, operands[1]); 3898 3899 if (mode == SFmode && ! TARGET_POWERPC 3900 && TARGET_HARD_FLOAT && TARGET_FPRS 3901 && GET_CODE (operands[0]) == MEM) 3902 { 3903 int regnum; 3904 3905 if (reload_in_progress || reload_completed) 3906 regnum = true_regnum (operands[1]); 3907 else if (GET_CODE (operands[1]) == REG) 3908 regnum = REGNO (operands[1]); 3909 else 3910 regnum = -1; 3911 3912 /* If operands[1] is a register, on POWER it may have 3913 double-precision data in it, so truncate it to single 3914 precision. */ 3915 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) 3916 { 3917 rtx newreg; 3918 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); 3919 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); 3920 operands[1] = newreg; 3921 } 3922 } 3923 3924 /* Recognize the case where operand[1] is a reference to thread-local 3925 data and load its address to a register. */ 3926 if (rs6000_tls_referenced_p (operands[1])) 3927 { 3928 enum tls_model model; 3929 rtx tmp = operands[1]; 3930 rtx addend = NULL; 3931 3932 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS) 3933 { 3934 addend = XEXP (XEXP (tmp, 0), 1); 3935 tmp = XEXP (XEXP (tmp, 0), 0); 3936 } 3937 3938 gcc_assert (GET_CODE (tmp) == SYMBOL_REF); 3939 model = SYMBOL_REF_TLS_MODEL (tmp); 3940 gcc_assert (model != 0); 3941 3942 tmp = rs6000_legitimize_tls_address (tmp, model); 3943 if (addend) 3944 { 3945 tmp = gen_rtx_PLUS (mode, tmp, addend); 3946 tmp = force_operand (tmp, operands[0]); 3947 } 3948 operands[1] = tmp; 3949 } 3950 3951 /* Handle the case where reload calls us with an invalid address. */ 3952 if (reload_in_progress && mode == Pmode 3953 && (! general_operand (operands[1], mode) 3954 || ! nonimmediate_operand (operands[0], mode))) 3955 goto emit_set; 3956 3957 /* 128-bit constant floating-point values on Darwin should really be 3958 loaded as two parts. */ 3959 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 3960 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE) 3961 { 3962 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't 3963 know how to get a DFmode SUBREG of a TFmode. */ 3964 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0), 3965 simplify_gen_subreg (DImode, operands[1], mode, 0), 3966 DImode); 3967 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 3968 GET_MODE_SIZE (DImode)), 3969 simplify_gen_subreg (DImode, operands[1], mode, 3970 GET_MODE_SIZE (DImode)), 3971 DImode); 3972 return; 3973 } 3974 3975 /* FIXME: In the long term, this switch statement should go away 3976 and be replaced by a sequence of tests based on things like 3977 mode == Pmode. */ 3978 switch (mode) 3979 { 3980 case HImode: 3981 case QImode: 3982 if (CONSTANT_P (operands[1]) 3983 && GET_CODE (operands[1]) != CONST_INT) 3984 operands[1] = force_const_mem (mode, operands[1]); 3985 break; 3986 3987 case TFmode: 3988 rs6000_eliminate_indexed_memrefs (operands); 3989 /* fall through */ 3990 3991 case DFmode: 3992 case SFmode: 3993 if (CONSTANT_P (operands[1]) 3994 && ! easy_fp_constant (operands[1], mode)) 3995 operands[1] = force_const_mem (mode, operands[1]); 3996 break; 3997 3998 case V16QImode: 3999 case V8HImode: 4000 case V4SFmode: 4001 case V4SImode: 4002 case V4HImode: 4003 case V2SFmode: 4004 case V2SImode: 4005 case V1DImode: 4006 if (CONSTANT_P (operands[1]) 4007 && !easy_vector_constant (operands[1], mode)) 4008 operands[1] = force_const_mem (mode, operands[1]); 4009 break; 4010 4011 case SImode: 4012 case DImode: 4013 /* Use default pattern for address of ELF small data */ 4014 if (TARGET_ELF 4015 && mode == Pmode 4016 && DEFAULT_ABI == ABI_V4 4017 && (GET_CODE (operands[1]) == SYMBOL_REF 4018 || GET_CODE (operands[1]) == CONST) 4019 && small_data_operand (operands[1], mode)) 4020 { 4021 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); 4022 return; 4023 } 4024 4025 if (DEFAULT_ABI == ABI_V4 4026 && mode == Pmode && mode == SImode 4027 && flag_pic == 1 && got_operand (operands[1], mode)) 4028 { 4029 emit_insn (gen_movsi_got (operands[0], operands[1])); 4030 return; 4031 } 4032 4033 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) 4034 && TARGET_NO_TOC 4035 && ! flag_pic 4036 && mode == Pmode 4037 && CONSTANT_P (operands[1]) 4038 && GET_CODE (operands[1]) != HIGH 4039 && GET_CODE (operands[1]) != CONST_INT) 4040 { 4041 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); 4042 4043 /* If this is a function address on -mcall-aixdesc, 4044 convert it to the address of the descriptor. */ 4045 if (DEFAULT_ABI == ABI_AIX 4046 && GET_CODE (operands[1]) == SYMBOL_REF 4047 && XSTR (operands[1], 0)[0] == '.') 4048 { 4049 const char *name = XSTR (operands[1], 0); 4050 rtx new_ref; 4051 while (*name == '.') 4052 name++; 4053 new_ref = gen_rtx_SYMBOL_REF (Pmode, name); 4054 CONSTANT_POOL_ADDRESS_P (new_ref) 4055 = CONSTANT_POOL_ADDRESS_P (operands[1]); 4056 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]); 4057 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); 4058 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]); 4059 operands[1] = new_ref; 4060 } 4061 4062 if (DEFAULT_ABI == ABI_DARWIN) 4063 { 4064#if TARGET_MACHO 4065 if (MACHO_DYNAMIC_NO_PIC_P) 4066 { 4067 /* Take care of any required data indirection. */ 4068 operands[1] = rs6000_machopic_legitimize_pic_address ( 4069 operands[1], mode, operands[0]); 4070 if (operands[0] != operands[1]) 4071 emit_insn (gen_rtx_SET (VOIDmode, 4072 operands[0], operands[1])); 4073 return; 4074 } 4075#endif 4076 emit_insn (gen_macho_high (target, operands[1])); 4077 emit_insn (gen_macho_low (operands[0], target, operands[1])); 4078 return; 4079 } 4080 4081 emit_insn (gen_elf_high (target, operands[1])); 4082 emit_insn (gen_elf_low (operands[0], target, operands[1])); 4083 return; 4084 } 4085 4086 /* If this is a SYMBOL_REF that refers to a constant pool entry, 4087 and we have put it in the TOC, we just need to make a TOC-relative 4088 reference to it. */ 4089 if (TARGET_TOC 4090 && GET_CODE (operands[1]) == SYMBOL_REF 4091 && constant_pool_expr_p (operands[1]) 4092 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), 4093 get_pool_mode (operands[1]))) 4094 { 4095 operands[1] = create_TOC_reference (operands[1]); 4096 } 4097 else if (mode == Pmode 4098 && CONSTANT_P (operands[1]) 4099 && ((GET_CODE (operands[1]) != CONST_INT 4100 && ! easy_fp_constant (operands[1], mode)) 4101 || (GET_CODE (operands[1]) == CONST_INT 4102 && num_insns_constant (operands[1], mode) > 2) 4103 || (GET_CODE (operands[0]) == REG 4104 && FP_REGNO_P (REGNO (operands[0])))) 4105 && GET_CODE (operands[1]) != HIGH 4106 && ! legitimate_constant_pool_address_p (operands[1]) 4107 && ! toc_relative_expr_p (operands[1])) 4108 { 4109 /* Emit a USE operation so that the constant isn't deleted if 4110 expensive optimizations are turned on because nobody 4111 references it. This should only be done for operands that 4112 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. 4113 This should not be done for operands that contain LABEL_REFs. 4114 For now, we just handle the obvious case. */ 4115 if (GET_CODE (operands[1]) != LABEL_REF) 4116 emit_insn (gen_rtx_USE (VOIDmode, operands[1])); 4117 4118#if TARGET_MACHO 4119 /* Darwin uses a special PIC legitimizer. */ 4120 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT) 4121 { 4122 operands[1] = 4123 rs6000_machopic_legitimize_pic_address (operands[1], mode, 4124 operands[0]); 4125 if (operands[0] != operands[1]) 4126 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); 4127 return; 4128 } 4129#endif 4130 4131 /* If we are to limit the number of things we put in the TOC and 4132 this is a symbol plus a constant we can add in one insn, 4133 just put the symbol in the TOC and add the constant. Don't do 4134 this if reload is in progress. */ 4135 if (GET_CODE (operands[1]) == CONST 4136 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress 4137 && GET_CODE (XEXP (operands[1], 0)) == PLUS 4138 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) 4139 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF 4140 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) 4141 && ! side_effects_p (operands[0])) 4142 { 4143 rtx sym = 4144 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); 4145 rtx other = XEXP (XEXP (operands[1], 0), 1); 4146 4147 sym = force_reg (mode, sym); 4148 if (mode == SImode) 4149 emit_insn (gen_addsi3 (operands[0], sym, other)); 4150 else 4151 emit_insn (gen_adddi3 (operands[0], sym, other)); 4152 return; 4153 } 4154 4155 operands[1] = force_const_mem (mode, operands[1]); 4156 4157 if (TARGET_TOC 4158 && constant_pool_expr_p (XEXP (operands[1], 0)) 4159 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( 4160 get_pool_constant (XEXP (operands[1], 0)), 4161 get_pool_mode (XEXP (operands[1], 0)))) 4162 { 4163 operands[1] 4164 = gen_const_mem (mode, 4165 create_TOC_reference (XEXP (operands[1], 0))); 4166 set_mem_alias_set (operands[1], get_TOC_alias_set ()); 4167 } 4168 } 4169 break; 4170 4171 case TImode: 4172 rs6000_eliminate_indexed_memrefs (operands); 4173 4174 if (TARGET_POWER) 4175 { 4176 emit_insn (gen_rtx_PARALLEL (VOIDmode, 4177 gen_rtvec (2, 4178 gen_rtx_SET (VOIDmode, 4179 operands[0], operands[1]), 4180 gen_rtx_CLOBBER (VOIDmode, 4181 gen_rtx_SCRATCH (SImode))))); 4182 return; 4183 } 4184 break; 4185 4186 default: 4187 gcc_unreachable (); 4188 } 4189 4190 /* Above, we may have called force_const_mem which may have returned 4191 an invalid address. If we can, fix this up; otherwise, reload will 4192 have to deal with it. */ 4193 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress) 4194 operands[1] = validize_mem (operands[1]); 4195 4196 emit_set: 4197 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); 4198} 4199 4200/* Nonzero if we can use a floating-point register to pass this arg. */ 4201#define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \ 4202 (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 4203 && (CUM)->fregno <= FP_ARG_MAX_REG \ 4204 && TARGET_HARD_FLOAT && TARGET_FPRS) 4205 4206/* Nonzero if we can use an AltiVec register to pass this arg. */ 4207#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \ 4208 (ALTIVEC_VECTOR_MODE (MODE) \ 4209 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \ 4210 && TARGET_ALTIVEC_ABI \ 4211 && (NAMED)) 4212 4213/* Return a nonzero value to say to return the function value in 4214 memory, just as large structures are always returned. TYPE will be 4215 the data type of the value, and FNTYPE will be the type of the 4216 function doing the returning, or @code{NULL} for libcalls. 4217 4218 The AIX ABI for the RS/6000 specifies that all structures are 4219 returned in memory. The Darwin ABI does the same. The SVR4 ABI 4220 specifies that structures <= 8 bytes are returned in r3/r4, but a 4221 draft put them in memory, and GCC used to implement the draft 4222 instead of the final standard. Therefore, aix_struct_return 4223 controls this instead of DEFAULT_ABI; V.4 targets needing backward 4224 compatibility can change DRAFT_V4_STRUCT_RET to override the 4225 default, and -m switches get the final word. See 4226 rs6000_override_options for more details. 4227 4228 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit 4229 long double support is enabled. These values are returned in memory. 4230 4231 int_size_in_bytes returns -1 for variable size objects, which go in 4232 memory always. The cast to unsigned makes -1 > 8. */ 4233 4234static bool 4235rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) 4236{ 4237 /* In the darwin64 abi, try to use registers for larger structs 4238 if possible. */ 4239 if (rs6000_darwin64_abi 4240 && TREE_CODE (type) == RECORD_TYPE 4241 && int_size_in_bytes (type) > 0) 4242 { 4243 CUMULATIVE_ARGS valcum; 4244 rtx valret; 4245 4246 valcum.words = 0; 4247 valcum.fregno = FP_ARG_MIN_REG; 4248 valcum.vregno = ALTIVEC_ARG_MIN_REG; 4249 /* Do a trial code generation as if this were going to be passed 4250 as an argument; if any part goes in memory, we return NULL. */ 4251 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true); 4252 if (valret) 4253 return false; 4254 /* Otherwise fall through to more conventional ABI rules. */ 4255 } 4256 4257 if (AGGREGATE_TYPE_P (type) 4258 && (aix_struct_return 4259 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)) 4260 return true; 4261 4262 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector 4263 modes only exist for GCC vector types if -maltivec. */ 4264 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI 4265 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type))) 4266 return false; 4267 4268 /* Return synthetic vectors in memory. */ 4269 if (TREE_CODE (type) == VECTOR_TYPE 4270 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8)) 4271 { 4272 static bool warned_for_return_big_vectors = false; 4273 if (!warned_for_return_big_vectors) 4274 { 4275 warning (0, "GCC vector returned by reference: " 4276 "non-standard ABI extension with no compatibility guarantee"); 4277 warned_for_return_big_vectors = true; 4278 } 4279 return true; 4280 } 4281 4282 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode) 4283 return true; 4284 4285 return false; 4286} 4287 4288/* Initialize a variable CUM of type CUMULATIVE_ARGS 4289 for a call to a function whose data type is FNTYPE. 4290 For a library call, FNTYPE is 0. 4291 4292 For incoming args we set the number of arguments in the prototype large 4293 so we never return a PARALLEL. */ 4294 4295void 4296init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, 4297 rtx libname ATTRIBUTE_UNUSED, int incoming, 4298 int libcall, int n_named_args) 4299{ 4300 static CUMULATIVE_ARGS zero_cumulative; 4301 4302 *cum = zero_cumulative; 4303 cum->words = 0; 4304 cum->fregno = FP_ARG_MIN_REG; 4305 cum->vregno = ALTIVEC_ARG_MIN_REG; 4306 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); 4307 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall) 4308 ? CALL_LIBCALL : CALL_NORMAL); 4309 cum->sysv_gregno = GP_ARG_MIN_REG; 4310 cum->stdarg = fntype 4311 && (TYPE_ARG_TYPES (fntype) != 0 4312 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) 4313 != void_type_node)); 4314 4315 cum->nargs_prototype = 0; 4316 if (incoming || cum->prototype) 4317 cum->nargs_prototype = n_named_args; 4318 4319 /* Check for a longcall attribute. */ 4320 if ((!fntype && rs6000_default_long_calls) 4321 || (fntype 4322 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)) 4323 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))) 4324 cum->call_cookie |= CALL_LONG; 4325 4326 if (TARGET_DEBUG_ARG) 4327 { 4328 fprintf (stderr, "\ninit_cumulative_args:"); 4329 if (fntype) 4330 { 4331 tree ret_type = TREE_TYPE (fntype); 4332 fprintf (stderr, " ret code = %s,", 4333 tree_code_name[ (int)TREE_CODE (ret_type) ]); 4334 } 4335 4336 if (cum->call_cookie & CALL_LONG) 4337 fprintf (stderr, " longcall,"); 4338 4339 fprintf (stderr, " proto = %d, nargs = %d\n", 4340 cum->prototype, cum->nargs_prototype); 4341 } 4342 4343 if (fntype 4344 && !TARGET_ALTIVEC 4345 && TARGET_ALTIVEC_ABI 4346 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype)))) 4347 { 4348 error ("cannot return value in vector register because" 4349 " altivec instructions are disabled, use -maltivec" 4350 " to enable them"); 4351 } 4352} 4353 4354/* Return true if TYPE must be passed on the stack and not in registers. */ 4355 4356static bool 4357rs6000_must_pass_in_stack (enum machine_mode mode, tree type) 4358{ 4359 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT) 4360 return must_pass_in_stack_var_size (mode, type); 4361 else 4362 return must_pass_in_stack_var_size_or_pad (mode, type); 4363} 4364 4365/* If defined, a C expression which determines whether, and in which 4366 direction, to pad out an argument with extra space. The value 4367 should be of type `enum direction': either `upward' to pad above 4368 the argument, `downward' to pad below, or `none' to inhibit 4369 padding. 4370 4371 For the AIX ABI structs are always stored left shifted in their 4372 argument slot. */ 4373 4374enum direction 4375function_arg_padding (enum machine_mode mode, tree type) 4376{ 4377#ifndef AGGREGATE_PADDING_FIXED 4378#define AGGREGATE_PADDING_FIXED 0 4379#endif 4380#ifndef AGGREGATES_PAD_UPWARD_ALWAYS 4381#define AGGREGATES_PAD_UPWARD_ALWAYS 0 4382#endif 4383 4384 if (!AGGREGATE_PADDING_FIXED) 4385 { 4386 /* GCC used to pass structures of the same size as integer types as 4387 if they were in fact integers, ignoring FUNCTION_ARG_PADDING. 4388 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were 4389 passed padded downward, except that -mstrict-align further 4390 muddied the water in that multi-component structures of 2 and 4 4391 bytes in size were passed padded upward. 4392 4393 The following arranges for best compatibility with previous 4394 versions of gcc, but removes the -mstrict-align dependency. */ 4395 if (BYTES_BIG_ENDIAN) 4396 { 4397 HOST_WIDE_INT size = 0; 4398 4399 if (mode == BLKmode) 4400 { 4401 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST) 4402 size = int_size_in_bytes (type); 4403 } 4404 else 4405 size = GET_MODE_SIZE (mode); 4406 4407 if (size == 1 || size == 2 || size == 4) 4408 return downward; 4409 } 4410 return upward; 4411 } 4412 4413 if (AGGREGATES_PAD_UPWARD_ALWAYS) 4414 { 4415 if (type != 0 && AGGREGATE_TYPE_P (type)) 4416 return upward; 4417 } 4418 4419 /* Fall back to the default. */ 4420 return DEFAULT_FUNCTION_ARG_PADDING (mode, type); 4421} 4422 4423/* If defined, a C expression that gives the alignment boundary, in bits, 4424 of an argument with the specified mode and type. If it is not defined, 4425 PARM_BOUNDARY is used for all arguments. 4426 4427 V.4 wants long longs and doubles to be double word aligned. Just 4428 testing the mode size is a boneheaded way to do this as it means 4429 that other types such as complex int are also double word aligned. 4430 However, we're stuck with this because changing the ABI might break 4431 existing library interfaces. 4432 4433 Doubleword align SPE vectors. 4434 Quadword align Altivec vectors. 4435 Quadword align large synthetic vector types. */ 4436 4437int 4438function_arg_boundary (enum machine_mode mode, tree type) 4439{ 4440 if (DEFAULT_ABI == ABI_V4 4441 && (GET_MODE_SIZE (mode) == 8 4442 || (TARGET_HARD_FLOAT 4443 && TARGET_FPRS 4444 && mode == TFmode))) 4445 return 64; 4446 else if (SPE_VECTOR_MODE (mode) 4447 || (type && TREE_CODE (type) == VECTOR_TYPE 4448 && int_size_in_bytes (type) >= 8 4449 && int_size_in_bytes (type) < 16)) 4450 return 64; 4451 else if (ALTIVEC_VECTOR_MODE (mode) 4452 || (type && TREE_CODE (type) == VECTOR_TYPE 4453 && int_size_in_bytes (type) >= 16)) 4454 return 128; 4455 else if (rs6000_darwin64_abi && mode == BLKmode 4456 && type && TYPE_ALIGN (type) > 64) 4457 return 128; 4458 else 4459 return PARM_BOUNDARY; 4460} 4461 4462/* For a function parm of MODE and TYPE, return the starting word in 4463 the parameter area. NWORDS of the parameter area are already used. */ 4464 4465static unsigned int 4466rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords) 4467{ 4468 unsigned int align; 4469 unsigned int parm_offset; 4470 4471 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; 4472 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6; 4473 return nwords + (-(parm_offset + nwords) & align); 4474} 4475 4476/* Compute the size (in words) of a function argument. */ 4477 4478static unsigned long 4479rs6000_arg_size (enum machine_mode mode, tree type) 4480{ 4481 unsigned long size; 4482 4483 if (mode != BLKmode) 4484 size = GET_MODE_SIZE (mode); 4485 else 4486 size = int_size_in_bytes (type); 4487 4488 if (TARGET_32BIT) 4489 return (size + 3) >> 2; 4490 else 4491 return (size + 7) >> 3; 4492} 4493 4494/* Use this to flush pending int fields. */ 4495 4496static void 4497rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum, 4498 HOST_WIDE_INT bitpos) 4499{ 4500 unsigned int startbit, endbit; 4501 int intregs, intoffset; 4502 enum machine_mode mode; 4503 4504 if (cum->intoffset == -1) 4505 return; 4506 4507 intoffset = cum->intoffset; 4508 cum->intoffset = -1; 4509 4510 if (intoffset % BITS_PER_WORD != 0) 4511 { 4512 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, 4513 MODE_INT, 0); 4514 if (mode == BLKmode) 4515 { 4516 /* We couldn't find an appropriate mode, which happens, 4517 e.g., in packed structs when there are 3 bytes to load. 4518 Back intoffset back to the beginning of the word in this 4519 case. */ 4520 intoffset = intoffset & -BITS_PER_WORD; 4521 } 4522 } 4523 4524 startbit = intoffset & -BITS_PER_WORD; 4525 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; 4526 intregs = (endbit - startbit) / BITS_PER_WORD; 4527 cum->words += intregs; 4528} 4529 4530/* The darwin64 ABI calls for us to recurse down through structs, 4531 looking for elements passed in registers. Unfortunately, we have 4532 to track int register count here also because of misalignments 4533 in powerpc alignment mode. */ 4534 4535static void 4536rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum, 4537 tree type, 4538 HOST_WIDE_INT startbitpos) 4539{ 4540 tree f; 4541 4542 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f)) 4543 if (TREE_CODE (f) == FIELD_DECL) 4544 { 4545 HOST_WIDE_INT bitpos = startbitpos; 4546 tree ftype = TREE_TYPE (f); 4547 enum machine_mode mode = TYPE_MODE (ftype); 4548 4549 if (DECL_SIZE (f) != 0 4550 && host_integerp (bit_position (f), 1)) 4551 bitpos += int_bit_position (f); 4552 4553 /* ??? FIXME: else assume zero offset. */ 4554 4555 if (TREE_CODE (ftype) == RECORD_TYPE) 4556 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos); 4557 else if (USE_FP_FOR_ARG_P (cum, mode, ftype)) 4558 { 4559 rs6000_darwin64_record_arg_advance_flush (cum, bitpos); 4560 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3; 4561 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3; 4562 } 4563 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1)) 4564 { 4565 rs6000_darwin64_record_arg_advance_flush (cum, bitpos); 4566 cum->vregno++; 4567 cum->words += 2; 4568 } 4569 else if (cum->intoffset == -1) 4570 cum->intoffset = bitpos; 4571 } 4572} 4573 4574/* Update the data in CUM to advance over an argument 4575 of mode MODE and data type TYPE. 4576 (TYPE is null for libcalls where that information may not be available.) 4577 4578 Note that for args passed by reference, function_arg will be called 4579 with MODE and TYPE set to that of the pointer to the arg, not the arg 4580 itself. */ 4581 4582void 4583function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, 4584 tree type, int named, int depth) 4585{ 4586 int size; 4587 4588 /* Only tick off an argument if we're not recursing. */ 4589 if (depth == 0) 4590 cum->nargs_prototype--; 4591 4592 if (TARGET_ALTIVEC_ABI 4593 && (ALTIVEC_VECTOR_MODE (mode) 4594 || (type && TREE_CODE (type) == VECTOR_TYPE 4595 && int_size_in_bytes (type) == 16))) 4596 { 4597 bool stack = false; 4598 4599 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) 4600 { 4601 cum->vregno++; 4602 if (!TARGET_ALTIVEC) 4603 error ("cannot pass argument in vector register because" 4604 " altivec instructions are disabled, use -maltivec" 4605 " to enable them"); 4606 4607 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument 4608 even if it is going to be passed in a vector register. 4609 Darwin does the same for variable-argument functions. */ 4610 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT) 4611 || (cum->stdarg && DEFAULT_ABI != ABI_V4)) 4612 stack = true; 4613 } 4614 else 4615 stack = true; 4616 4617 if (stack) 4618 { 4619 int align; 4620 4621 /* Vector parameters must be 16-byte aligned. This places 4622 them at 2 mod 4 in terms of words in 32-bit mode, since 4623 the parameter save area starts at offset 24 from the 4624 stack. In 64-bit mode, they just have to start on an 4625 even word, since the parameter save area is 16-byte 4626 aligned. Space for GPRs is reserved even if the argument 4627 will be passed in memory. */ 4628 if (TARGET_32BIT) 4629 align = (2 - cum->words) & 3; 4630 else 4631 align = cum->words & 1; 4632 cum->words += align + rs6000_arg_size (mode, type); 4633 4634 if (TARGET_DEBUG_ARG) 4635 { 4636 fprintf (stderr, "function_adv: words = %2d, align=%d, ", 4637 cum->words, align); 4638 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n", 4639 cum->nargs_prototype, cum->prototype, 4640 GET_MODE_NAME (mode)); 4641 } 4642 } 4643 } 4644 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) 4645 && !cum->stdarg 4646 && cum->sysv_gregno <= GP_ARG_MAX_REG) 4647 cum->sysv_gregno++; 4648 4649 else if (rs6000_darwin64_abi 4650 && mode == BLKmode 4651 && TREE_CODE (type) == RECORD_TYPE 4652 && (size = int_size_in_bytes (type)) > 0) 4653 { 4654 /* Variable sized types have size == -1 and are 4655 treated as if consisting entirely of ints. 4656 Pad to 16 byte boundary if needed. */ 4657 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD 4658 && (cum->words % 2) != 0) 4659 cum->words++; 4660 /* For varargs, we can just go up by the size of the struct. */ 4661 if (!named) 4662 cum->words += (size + 7) / 8; 4663 else 4664 { 4665 /* It is tempting to say int register count just goes up by 4666 sizeof(type)/8, but this is wrong in a case such as 4667 { int; double; int; } [powerpc alignment]. We have to 4668 grovel through the fields for these too. */ 4669 cum->intoffset = 0; 4670 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0); 4671 rs6000_darwin64_record_arg_advance_flush (cum, 4672 size * BITS_PER_UNIT); 4673 } 4674 } 4675 else if (DEFAULT_ABI == ABI_V4) 4676 { 4677 if (TARGET_HARD_FLOAT && TARGET_FPRS 4678 && (mode == SFmode || mode == DFmode 4679 || (mode == TFmode && !TARGET_IEEEQUAD))) 4680 { 4681 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG) 4682 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3; 4683 else 4684 { 4685 cum->fregno = FP_ARG_V4_MAX_REG + 1; 4686 if (mode == DFmode || mode == TFmode) 4687 cum->words += cum->words & 1; 4688 cum->words += rs6000_arg_size (mode, type); 4689 } 4690 } 4691 else 4692 { 4693 int n_words = rs6000_arg_size (mode, type); 4694 int gregno = cum->sysv_gregno; 4695 4696 /* Long long and SPE vectors are put in (r3,r4), (r5,r6), 4697 (r7,r8) or (r9,r10). As does any other 2 word item such 4698 as complex int due to a historical mistake. */ 4699 if (n_words == 2) 4700 gregno += (1 - gregno) & 1; 4701 4702 /* Multi-reg args are not split between registers and stack. */ 4703 if (gregno + n_words - 1 > GP_ARG_MAX_REG) 4704 { 4705 /* Long long and SPE vectors are aligned on the stack. 4706 So are other 2 word items such as complex int due to 4707 a historical mistake. */ 4708 if (n_words == 2) 4709 cum->words += cum->words & 1; 4710 cum->words += n_words; 4711 } 4712 4713 /* Note: continuing to accumulate gregno past when we've started 4714 spilling to the stack indicates the fact that we've started 4715 spilling to the stack to expand_builtin_saveregs. */ 4716 cum->sysv_gregno = gregno + n_words; 4717 } 4718 4719 if (TARGET_DEBUG_ARG) 4720 { 4721 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", 4722 cum->words, cum->fregno); 4723 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", 4724 cum->sysv_gregno, cum->nargs_prototype, cum->prototype); 4725 fprintf (stderr, "mode = %4s, named = %d\n", 4726 GET_MODE_NAME (mode), named); 4727 } 4728 } 4729 else 4730 { 4731 int n_words = rs6000_arg_size (mode, type); 4732 int start_words = cum->words; 4733 int align_words = rs6000_parm_start (mode, type, start_words); 4734 4735 cum->words = align_words + n_words; 4736 4737 if (GET_MODE_CLASS (mode) == MODE_FLOAT 4738 && TARGET_HARD_FLOAT && TARGET_FPRS) 4739 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3; 4740 4741 if (TARGET_DEBUG_ARG) 4742 { 4743 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", 4744 cum->words, cum->fregno); 4745 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", 4746 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); 4747 fprintf (stderr, "named = %d, align = %d, depth = %d\n", 4748 named, align_words - start_words, depth); 4749 } 4750 } 4751} 4752 4753static rtx 4754spe_build_register_parallel (enum machine_mode mode, int gregno) 4755{ 4756 rtx r1, r3; 4757 4758 switch (mode) 4759 { 4760 case DFmode: 4761 r1 = gen_rtx_REG (DImode, gregno); 4762 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx); 4763 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1)); 4764 4765 case DCmode: 4766 r1 = gen_rtx_REG (DImode, gregno); 4767 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx); 4768 r3 = gen_rtx_REG (DImode, gregno + 2); 4769 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8)); 4770 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3)); 4771 4772 default: 4773 gcc_unreachable (); 4774 } 4775} 4776 4777/* Determine where to put a SIMD argument on the SPE. */ 4778static rtx 4779rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, 4780 tree type) 4781{ 4782 int gregno = cum->sysv_gregno; 4783 4784 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but 4785 are passed and returned in a pair of GPRs for ABI compatibility. */ 4786 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode)) 4787 { 4788 int n_words = rs6000_arg_size (mode, type); 4789 4790 /* Doubles go in an odd/even register pair (r5/r6, etc). */ 4791 if (mode == DFmode) 4792 gregno += (1 - gregno) & 1; 4793 4794 /* Multi-reg args are not split between registers and stack. */ 4795 if (gregno + n_words - 1 > GP_ARG_MAX_REG) 4796 return NULL_RTX; 4797 4798 return spe_build_register_parallel (mode, gregno); 4799 } 4800 if (cum->stdarg) 4801 { 4802 int n_words = rs6000_arg_size (mode, type); 4803 4804 /* SPE vectors are put in odd registers. */ 4805 if (n_words == 2 && (gregno & 1) == 0) 4806 gregno += 1; 4807 4808 if (gregno + n_words - 1 <= GP_ARG_MAX_REG) 4809 { 4810 rtx r1, r2; 4811 enum machine_mode m = SImode; 4812 4813 r1 = gen_rtx_REG (m, gregno); 4814 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx); 4815 r2 = gen_rtx_REG (m, gregno + 1); 4816 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4)); 4817 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); 4818 } 4819 else 4820 return NULL_RTX; 4821 } 4822 else 4823 { 4824 if (gregno <= GP_ARG_MAX_REG) 4825 return gen_rtx_REG (mode, gregno); 4826 else 4827 return NULL_RTX; 4828 } 4829} 4830 4831/* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the 4832 structure between cum->intoffset and bitpos to integer registers. */ 4833 4834static void 4835rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum, 4836 HOST_WIDE_INT bitpos, rtx rvec[], int *k) 4837{ 4838 enum machine_mode mode; 4839 unsigned int regno; 4840 unsigned int startbit, endbit; 4841 int this_regno, intregs, intoffset; 4842 rtx reg; 4843 4844 if (cum->intoffset == -1) 4845 return; 4846 4847 intoffset = cum->intoffset; 4848 cum->intoffset = -1; 4849 4850 /* If this is the trailing part of a word, try to only load that 4851 much into the register. Otherwise load the whole register. Note 4852 that in the latter case we may pick up unwanted bits. It's not a 4853 problem at the moment but may wish to revisit. */ 4854 4855 if (intoffset % BITS_PER_WORD != 0) 4856 { 4857 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, 4858 MODE_INT, 0); 4859 if (mode == BLKmode) 4860 { 4861 /* We couldn't find an appropriate mode, which happens, 4862 e.g., in packed structs when there are 3 bytes to load. 4863 Back intoffset back to the beginning of the word in this 4864 case. */ 4865 intoffset = intoffset & -BITS_PER_WORD; 4866 mode = word_mode; 4867 } 4868 } 4869 else 4870 mode = word_mode; 4871 4872 startbit = intoffset & -BITS_PER_WORD; 4873 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; 4874 intregs = (endbit - startbit) / BITS_PER_WORD; 4875 this_regno = cum->words + intoffset / BITS_PER_WORD; 4876 4877 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno) 4878 cum->use_stack = 1; 4879 4880 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno); 4881 if (intregs <= 0) 4882 return; 4883 4884 intoffset /= BITS_PER_UNIT; 4885 do 4886 { 4887 regno = GP_ARG_MIN_REG + this_regno; 4888 reg = gen_rtx_REG (mode, regno); 4889 rvec[(*k)++] = 4890 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); 4891 4892 this_regno += 1; 4893 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; 4894 mode = word_mode; 4895 intregs -= 1; 4896 } 4897 while (intregs > 0); 4898} 4899 4900/* Recursive workhorse for the following. */ 4901 4902static void 4903rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type, 4904 HOST_WIDE_INT startbitpos, rtx rvec[], 4905 int *k) 4906{ 4907 tree f; 4908 4909 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f)) 4910 if (TREE_CODE (f) == FIELD_DECL) 4911 { 4912 HOST_WIDE_INT bitpos = startbitpos; 4913 tree ftype = TREE_TYPE (f); 4914 enum machine_mode mode = TYPE_MODE (ftype); 4915 4916 if (DECL_SIZE (f) != 0 4917 && host_integerp (bit_position (f), 1)) 4918 bitpos += int_bit_position (f); 4919 4920 /* ??? FIXME: else assume zero offset. */ 4921 4922 if (TREE_CODE (ftype) == RECORD_TYPE) 4923 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k); 4924 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype)) 4925 { 4926#if 0 4927 switch (mode) 4928 { 4929 case SCmode: mode = SFmode; break; 4930 case DCmode: mode = DFmode; break; 4931 case TCmode: mode = TFmode; break; 4932 default: break; 4933 } 4934#endif 4935 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k); 4936 rvec[(*k)++] 4937 = gen_rtx_EXPR_LIST (VOIDmode, 4938 gen_rtx_REG (mode, cum->fregno++), 4939 GEN_INT (bitpos / BITS_PER_UNIT)); 4940 if (mode == TFmode) 4941 cum->fregno++; 4942 } 4943 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1)) 4944 { 4945 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k); 4946 rvec[(*k)++] 4947 = gen_rtx_EXPR_LIST (VOIDmode, 4948 gen_rtx_REG (mode, cum->vregno++), 4949 GEN_INT (bitpos / BITS_PER_UNIT)); 4950 } 4951 else if (cum->intoffset == -1) 4952 cum->intoffset = bitpos; 4953 } 4954} 4955 4956/* For the darwin64 ABI, we want to construct a PARALLEL consisting of 4957 the register(s) to be used for each field and subfield of a struct 4958 being passed by value, along with the offset of where the 4959 register's value may be found in the block. FP fields go in FP 4960 register, vector fields go in vector registers, and everything 4961 else goes in int registers, packed as in memory. 4962 4963 This code is also used for function return values. RETVAL indicates 4964 whether this is the case. 4965 4966 Much of this is taken from the SPARC V9 port, which has a similar 4967 calling convention. */ 4968 4969static rtx 4970rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type, 4971 int named, bool retval) 4972{ 4973 rtx rvec[FIRST_PSEUDO_REGISTER]; 4974 int k = 1, kbase = 1; 4975 HOST_WIDE_INT typesize = int_size_in_bytes (type); 4976 /* This is a copy; modifications are not visible to our caller. */ 4977 CUMULATIVE_ARGS copy_cum = *orig_cum; 4978 CUMULATIVE_ARGS *cum = ©_cum; 4979 4980 /* Pad to 16 byte boundary if needed. */ 4981 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD 4982 && (cum->words % 2) != 0) 4983 cum->words++; 4984 4985 cum->intoffset = 0; 4986 cum->use_stack = 0; 4987 cum->named = named; 4988 4989 /* Put entries into rvec[] for individual FP and vector fields, and 4990 for the chunks of memory that go in int regs. Note we start at 4991 element 1; 0 is reserved for an indication of using memory, and 4992 may or may not be filled in below. */ 4993 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k); 4994 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k); 4995 4996 /* If any part of the struct went on the stack put all of it there. 4997 This hack is because the generic code for 4998 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register 4999 parts of the struct are not at the beginning. */ 5000 if (cum->use_stack) 5001 { 5002 if (retval) 5003 return NULL_RTX; /* doesn't go in registers at all */ 5004 kbase = 0; 5005 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 5006 } 5007 if (k > 1 || cum->use_stack) 5008 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase])); 5009 else 5010 return NULL_RTX; 5011} 5012 5013/* Determine where to place an argument in 64-bit mode with 32-bit ABI. */ 5014 5015static rtx 5016rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words) 5017{ 5018 int n_units; 5019 int i, k; 5020 rtx rvec[GP_ARG_NUM_REG + 1]; 5021 5022 if (align_words >= GP_ARG_NUM_REG) 5023 return NULL_RTX; 5024 5025 n_units = rs6000_arg_size (mode, type); 5026 5027 /* Optimize the simple case where the arg fits in one gpr, except in 5028 the case of BLKmode due to assign_parms assuming that registers are 5029 BITS_PER_WORD wide. */ 5030 if (n_units == 0 5031 || (n_units == 1 && mode != BLKmode)) 5032 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); 5033 5034 k = 0; 5035 if (align_words + n_units > GP_ARG_NUM_REG) 5036 /* Not all of the arg fits in gprs. Say that it goes in memory too, 5037 using a magic NULL_RTX component. 5038 FIXME: This is not strictly correct. Only some of the arg 5039 belongs in memory, not all of it. However, there isn't any way 5040 to do this currently, apart from building rtx descriptions for 5041 the pieces of memory we want stored. Due to bugs in the generic 5042 code we can't use the normal function_arg_partial_nregs scheme 5043 with the PARALLEL arg description we emit here. 5044 In any case, the code to store the whole arg to memory is often 5045 more efficient than code to store pieces, and we know that space 5046 is available in the right place for the whole arg. */ 5047 /* FIXME: This should be fixed since the conversion to 5048 TARGET_ARG_PARTIAL_BYTES. */ 5049 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 5050 5051 i = 0; 5052 do 5053 { 5054 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words); 5055 rtx off = GEN_INT (i++ * 4); 5056 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); 5057 } 5058 while (++align_words < GP_ARG_NUM_REG && --n_units != 0); 5059 5060 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); 5061} 5062 5063/* Determine where to put an argument to a function. 5064 Value is zero to push the argument on the stack, 5065 or a hard register in which to store the argument. 5066 5067 MODE is the argument's machine mode. 5068 TYPE is the data type of the argument (as a tree). 5069 This is null for libcalls where that information may 5070 not be available. 5071 CUM is a variable of type CUMULATIVE_ARGS which gives info about 5072 the preceding args and about the function being called. It is 5073 not modified in this routine. 5074 NAMED is nonzero if this argument is a named parameter 5075 (otherwise it is an extra parameter matching an ellipsis). 5076 5077 On RS/6000 the first eight words of non-FP are normally in registers 5078 and the rest are pushed. Under AIX, the first 13 FP args are in registers. 5079 Under V.4, the first 8 FP args are in registers. 5080 5081 If this is floating-point and no prototype is specified, we use 5082 both an FP and integer register (or possibly FP reg and stack). Library 5083 functions (when CALL_LIBCALL is set) always have the proper types for args, 5084 so we can pass the FP value just in one register. emit_library_function 5085 doesn't support PARALLEL anyway. 5086 5087 Note that for args passed by reference, function_arg will be called 5088 with MODE and TYPE set to that of the pointer to the arg, not the arg 5089 itself. */ 5090 5091rtx 5092function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, 5093 tree type, int named) 5094{ 5095 enum rs6000_abi abi = DEFAULT_ABI; 5096 5097 /* Return a marker to indicate whether CR1 needs to set or clear the 5098 bit that V.4 uses to say fp args were passed in registers. 5099 Assume that we don't need the marker for software floating point, 5100 or compiler generated library calls. */ 5101 if (mode == VOIDmode) 5102 { 5103 if (abi == ABI_V4 5104 && (cum->call_cookie & CALL_LIBCALL) == 0 5105 && (cum->stdarg 5106 || (cum->nargs_prototype < 0 5107 && (cum->prototype || TARGET_NO_PROTOTYPE)))) 5108 { 5109 /* For the SPE, we need to crxor CR6 always. */ 5110 if (TARGET_SPE_ABI) 5111 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS); 5112 else if (TARGET_HARD_FLOAT && TARGET_FPRS) 5113 return GEN_INT (cum->call_cookie 5114 | ((cum->fregno == FP_ARG_MIN_REG) 5115 ? CALL_V4_SET_FP_ARGS 5116 : CALL_V4_CLEAR_FP_ARGS)); 5117 } 5118 5119 return GEN_INT (cum->call_cookie); 5120 } 5121 5122 if (rs6000_darwin64_abi && mode == BLKmode 5123 && TREE_CODE (type) == RECORD_TYPE) 5124 { 5125 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false); 5126 if (rslt != NULL_RTX) 5127 return rslt; 5128 /* Else fall through to usual handling. */ 5129 } 5130 5131 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) 5132 if (TARGET_64BIT && ! cum->prototype) 5133 { 5134 /* Vector parameters get passed in vector register 5135 and also in GPRs or memory, in absence of prototype. */ 5136 int align_words; 5137 rtx slot; 5138 align_words = (cum->words + 1) & ~1; 5139 5140 if (align_words >= GP_ARG_NUM_REG) 5141 { 5142 slot = NULL_RTX; 5143 } 5144 else 5145 { 5146 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); 5147 } 5148 return gen_rtx_PARALLEL (mode, 5149 gen_rtvec (2, 5150 gen_rtx_EXPR_LIST (VOIDmode, 5151 slot, const0_rtx), 5152 gen_rtx_EXPR_LIST (VOIDmode, 5153 gen_rtx_REG (mode, cum->vregno), 5154 const0_rtx))); 5155 } 5156 else 5157 return gen_rtx_REG (mode, cum->vregno); 5158 else if (TARGET_ALTIVEC_ABI 5159 && (ALTIVEC_VECTOR_MODE (mode) 5160 || (type && TREE_CODE (type) == VECTOR_TYPE 5161 && int_size_in_bytes (type) == 16))) 5162 { 5163 if (named || abi == ABI_V4) 5164 return NULL_RTX; 5165 else 5166 { 5167 /* Vector parameters to varargs functions under AIX or Darwin 5168 get passed in memory and possibly also in GPRs. */ 5169 int align, align_words, n_words; 5170 enum machine_mode part_mode; 5171 5172 /* Vector parameters must be 16-byte aligned. This places them at 5173 2 mod 4 in terms of words in 32-bit mode, since the parameter 5174 save area starts at offset 24 from the stack. In 64-bit mode, 5175 they just have to start on an even word, since the parameter 5176 save area is 16-byte aligned. */ 5177 if (TARGET_32BIT) 5178 align = (2 - cum->words) & 3; 5179 else 5180 align = cum->words & 1; 5181 align_words = cum->words + align; 5182 5183 /* Out of registers? Memory, then. */ 5184 if (align_words >= GP_ARG_NUM_REG) 5185 return NULL_RTX; 5186 5187 if (TARGET_32BIT && TARGET_POWERPC64) 5188 return rs6000_mixed_function_arg (mode, type, align_words); 5189 5190 /* The vector value goes in GPRs. Only the part of the 5191 value in GPRs is reported here. */ 5192 part_mode = mode; 5193 n_words = rs6000_arg_size (mode, type); 5194 if (align_words + n_words > GP_ARG_NUM_REG) 5195 /* Fortunately, there are only two possibilities, the value 5196 is either wholly in GPRs or half in GPRs and half not. */ 5197 part_mode = DImode; 5198 5199 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words); 5200 } 5201 } 5202 else if (TARGET_SPE_ABI && TARGET_SPE 5203 && (SPE_VECTOR_MODE (mode) 5204 || (TARGET_E500_DOUBLE && (mode == DFmode 5205 || mode == DCmode)))) 5206 return rs6000_spe_function_arg (cum, mode, type); 5207 5208 else if (abi == ABI_V4) 5209 { 5210 if (TARGET_HARD_FLOAT && TARGET_FPRS 5211 && (mode == SFmode || mode == DFmode 5212 || (mode == TFmode && !TARGET_IEEEQUAD))) 5213 { 5214 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG) 5215 return gen_rtx_REG (mode, cum->fregno); 5216 else 5217 return NULL_RTX; 5218 } 5219 else 5220 { 5221 int n_words = rs6000_arg_size (mode, type); 5222 int gregno = cum->sysv_gregno; 5223 5224 /* Long long and SPE vectors are put in (r3,r4), (r5,r6), 5225 (r7,r8) or (r9,r10). As does any other 2 word item such 5226 as complex int due to a historical mistake. */ 5227 if (n_words == 2) 5228 gregno += (1 - gregno) & 1; 5229 5230 /* Multi-reg args are not split between registers and stack. */ 5231 if (gregno + n_words - 1 > GP_ARG_MAX_REG) 5232 return NULL_RTX; 5233 5234 if (TARGET_32BIT && TARGET_POWERPC64) 5235 return rs6000_mixed_function_arg (mode, type, 5236 gregno - GP_ARG_MIN_REG); 5237 return gen_rtx_REG (mode, gregno); 5238 } 5239 } 5240 else 5241 { 5242 int align_words = rs6000_parm_start (mode, type, cum->words); 5243 5244 if (USE_FP_FOR_ARG_P (cum, mode, type)) 5245 { 5246 rtx rvec[GP_ARG_NUM_REG + 1]; 5247 rtx r; 5248 int k; 5249 bool needs_psave; 5250 enum machine_mode fmode = mode; 5251 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3; 5252 5253 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1) 5254 { 5255 /* Currently, we only ever need one reg here because complex 5256 doubles are split. */ 5257 gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode); 5258 5259 /* Long double split over regs and memory. */ 5260 fmode = DFmode; 5261 } 5262 5263 /* Do we also need to pass this arg in the parameter save 5264 area? */ 5265 needs_psave = (type 5266 && (cum->nargs_prototype <= 0 5267 || (DEFAULT_ABI == ABI_AIX 5268 && TARGET_XL_COMPAT 5269 && align_words >= GP_ARG_NUM_REG))); 5270 5271 if (!needs_psave && mode == fmode) 5272 return gen_rtx_REG (fmode, cum->fregno); 5273 5274 k = 0; 5275 if (needs_psave) 5276 { 5277 /* Describe the part that goes in gprs or the stack. 5278 This piece must come first, before the fprs. */ 5279 if (align_words < GP_ARG_NUM_REG) 5280 { 5281 unsigned long n_words = rs6000_arg_size (mode, type); 5282 5283 if (align_words + n_words > GP_ARG_NUM_REG 5284 || (TARGET_32BIT && TARGET_POWERPC64)) 5285 { 5286 /* If this is partially on the stack, then we only 5287 include the portion actually in registers here. */ 5288 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode; 5289 rtx off; 5290 int i=0; 5291 if (align_words + n_words > GP_ARG_NUM_REG 5292 && (TARGET_32BIT && TARGET_POWERPC64)) 5293 /* Not all of the arg fits in gprs. Say that it 5294 goes in memory too, using a magic NULL_RTX 5295 component. Also see comment in 5296 rs6000_mixed_function_arg for why the normal 5297 function_arg_partial_nregs scheme doesn't work 5298 in this case. */ 5299 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, 5300 const0_rtx); 5301 do 5302 { 5303 r = gen_rtx_REG (rmode, 5304 GP_ARG_MIN_REG + align_words); 5305 off = GEN_INT (i++ * GET_MODE_SIZE (rmode)); 5306 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); 5307 } 5308 while (++align_words < GP_ARG_NUM_REG && --n_words != 0); 5309 } 5310 else 5311 { 5312 /* The whole arg fits in gprs. */ 5313 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); 5314 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); 5315 } 5316 } 5317 else 5318 /* It's entirely in memory. */ 5319 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 5320 } 5321 5322 /* Describe where this piece goes in the fprs. */ 5323 r = gen_rtx_REG (fmode, cum->fregno); 5324 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); 5325 5326 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); 5327 } 5328 else if (align_words < GP_ARG_NUM_REG) 5329 { 5330 if (TARGET_32BIT && TARGET_POWERPC64) 5331 return rs6000_mixed_function_arg (mode, type, align_words); 5332 5333 if (mode == BLKmode) 5334 mode = Pmode; 5335 5336 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); 5337 } 5338 else 5339 return NULL_RTX; 5340 } 5341} 5342 5343/* For an arg passed partly in registers and partly in memory, this is 5344 the number of bytes passed in registers. For args passed entirely in 5345 registers or entirely in memory, zero. When an arg is described by a 5346 PARALLEL, perhaps using more than one register type, this function 5347 returns the number of bytes used by the first element of the PARALLEL. */ 5348 5349static int 5350rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, 5351 tree type, bool named) 5352{ 5353 int ret = 0; 5354 int align_words; 5355 5356 if (DEFAULT_ABI == ABI_V4) 5357 return 0; 5358 5359 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named) 5360 && cum->nargs_prototype >= 0) 5361 return 0; 5362 5363 /* In this complicated case we just disable the partial_nregs code. */ 5364 if (rs6000_darwin64_abi && mode == BLKmode 5365 && TREE_CODE (type) == RECORD_TYPE 5366 && int_size_in_bytes (type) > 0) 5367 return 0; 5368 5369 align_words = rs6000_parm_start (mode, type, cum->words); 5370 5371 if (USE_FP_FOR_ARG_P (cum, mode, type) 5372 /* If we are passing this arg in the fixed parameter save area 5373 (gprs or memory) as well as fprs, then this function should 5374 return the number of bytes passed in the parameter save area 5375 rather than bytes passed in fprs. */ 5376 && !(type 5377 && (cum->nargs_prototype <= 0 5378 || (DEFAULT_ABI == ABI_AIX 5379 && TARGET_XL_COMPAT 5380 && align_words >= GP_ARG_NUM_REG)))) 5381 { 5382 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1) 5383 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8; 5384 else if (cum->nargs_prototype >= 0) 5385 return 0; 5386 } 5387 5388 if (align_words < GP_ARG_NUM_REG 5389 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type)) 5390 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8); 5391 5392 if (ret != 0 && TARGET_DEBUG_ARG) 5393 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret); 5394 5395 return ret; 5396} 5397 5398/* A C expression that indicates when an argument must be passed by 5399 reference. If nonzero for an argument, a copy of that argument is 5400 made in memory and a pointer to the argument is passed instead of 5401 the argument itself. The pointer is passed in whatever way is 5402 appropriate for passing a pointer to that type. 5403 5404 Under V.4, aggregates and long double are passed by reference. 5405 5406 As an extension to all 32-bit ABIs, AltiVec vectors are passed by 5407 reference unless the AltiVec vector extension ABI is in force. 5408 5409 As an extension to all ABIs, variable sized types are passed by 5410 reference. */ 5411 5412static bool 5413rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, 5414 enum machine_mode mode, tree type, 5415 bool named ATTRIBUTE_UNUSED) 5416{ 5417 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode) 5418 { 5419 if (TARGET_DEBUG_ARG) 5420 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n"); 5421 return 1; 5422 } 5423 5424 if (!type) 5425 return 0; 5426 5427 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type)) 5428 { 5429 if (TARGET_DEBUG_ARG) 5430 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n"); 5431 return 1; 5432 } 5433 5434 if (int_size_in_bytes (type) < 0) 5435 { 5436 if (TARGET_DEBUG_ARG) 5437 fprintf (stderr, "function_arg_pass_by_reference: variable size\n"); 5438 return 1; 5439 } 5440 5441 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector 5442 modes only exist for GCC vector types if -maltivec. */ 5443 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) 5444 { 5445 if (TARGET_DEBUG_ARG) 5446 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n"); 5447 return 1; 5448 } 5449 5450 /* Pass synthetic vectors in memory. */ 5451 if (TREE_CODE (type) == VECTOR_TYPE 5452 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8)) 5453 { 5454 static bool warned_for_pass_big_vectors = false; 5455 if (TARGET_DEBUG_ARG) 5456 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n"); 5457 if (!warned_for_pass_big_vectors) 5458 { 5459 warning (0, "GCC vector passed by reference: " 5460 "non-standard ABI extension with no compatibility guarantee"); 5461 warned_for_pass_big_vectors = true; 5462 } 5463 return 1; 5464 } 5465 5466 return 0; 5467} 5468 5469static void 5470rs6000_move_block_from_reg (int regno, rtx x, int nregs) 5471{ 5472 int i; 5473 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode; 5474 5475 if (nregs == 0) 5476 return; 5477 5478 for (i = 0; i < nregs; i++) 5479 { 5480 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode)); 5481 if (reload_completed) 5482 { 5483 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0))) 5484 tem = NULL_RTX; 5485 else 5486 tem = simplify_gen_subreg (reg_mode, x, BLKmode, 5487 i * GET_MODE_SIZE (reg_mode)); 5488 } 5489 else 5490 tem = replace_equiv_address (tem, XEXP (tem, 0)); 5491 5492 gcc_assert (tem); 5493 5494 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i)); 5495 } 5496} 5497 5498/* Perform any needed actions needed for a function that is receiving a 5499 variable number of arguments. 5500 5501 CUM is as above. 5502 5503 MODE and TYPE are the mode and type of the current parameter. 5504 5505 PRETEND_SIZE is a variable that should be set to the amount of stack 5506 that must be pushed by the prolog to pretend that our caller pushed 5507 it. 5508 5509 Normally, this macro will push all remaining incoming registers on the 5510 stack and set PRETEND_SIZE to the length of the registers pushed. */ 5511 5512static void 5513setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, 5514 tree type, int *pretend_size ATTRIBUTE_UNUSED, 5515 int no_rtl) 5516{ 5517 CUMULATIVE_ARGS next_cum; 5518 int reg_size = TARGET_32BIT ? 4 : 8; 5519 rtx save_area = NULL_RTX, mem; 5520 int first_reg_offset, set; 5521 5522 /* Skip the last named argument. */ 5523 next_cum = *cum; 5524 function_arg_advance (&next_cum, mode, type, 1, 0); 5525 5526 if (DEFAULT_ABI == ABI_V4) 5527 { 5528 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; 5529 5530 if (! no_rtl) 5531 { 5532 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0; 5533 HOST_WIDE_INT offset = 0; 5534 5535 /* Try to optimize the size of the varargs save area. 5536 The ABI requires that ap.reg_save_area is doubleword 5537 aligned, but we don't need to allocate space for all 5538 the bytes, only those to which we actually will save 5539 anything. */ 5540 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG) 5541 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset; 5542 if (TARGET_HARD_FLOAT && TARGET_FPRS 5543 && next_cum.fregno <= FP_ARG_V4_MAX_REG 5544 && cfun->va_list_fpr_size) 5545 { 5546 if (gpr_reg_num) 5547 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG) 5548 * UNITS_PER_FP_WORD; 5549 if (cfun->va_list_fpr_size 5550 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno) 5551 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD; 5552 else 5553 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno) 5554 * UNITS_PER_FP_WORD; 5555 } 5556 if (gpr_reg_num) 5557 { 5558 offset = -((first_reg_offset * reg_size) & ~7); 5559 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size) 5560 { 5561 gpr_reg_num = cfun->va_list_gpr_size; 5562 if (reg_size == 4 && (first_reg_offset & 1)) 5563 gpr_reg_num++; 5564 } 5565 gpr_size = (gpr_reg_num * reg_size + 7) & ~7; 5566 } 5567 else if (fpr_size) 5568 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG) 5569 * UNITS_PER_FP_WORD 5570 - (int) (GP_ARG_NUM_REG * reg_size); 5571 5572 if (gpr_size + fpr_size) 5573 { 5574 rtx reg_save_area 5575 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64); 5576 gcc_assert (GET_CODE (reg_save_area) == MEM); 5577 reg_save_area = XEXP (reg_save_area, 0); 5578 if (GET_CODE (reg_save_area) == PLUS) 5579 { 5580 gcc_assert (XEXP (reg_save_area, 0) 5581 == virtual_stack_vars_rtx); 5582 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT); 5583 offset += INTVAL (XEXP (reg_save_area, 1)); 5584 } 5585 else 5586 gcc_assert (reg_save_area == virtual_stack_vars_rtx); 5587 } 5588 5589 cfun->machine->varargs_save_offset = offset; 5590 save_area = plus_constant (virtual_stack_vars_rtx, offset); 5591 } 5592 } 5593 else 5594 { 5595 first_reg_offset = next_cum.words; 5596 save_area = virtual_incoming_args_rtx; 5597 5598 if (targetm.calls.must_pass_in_stack (mode, type)) 5599 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type); 5600 } 5601 5602 set = get_varargs_alias_set (); 5603 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG 5604 && cfun->va_list_gpr_size) 5605 { 5606 int nregs = GP_ARG_NUM_REG - first_reg_offset; 5607 5608 if (va_list_gpr_counter_field) 5609 { 5610 /* V4 va_list_gpr_size counts number of registers needed. */ 5611 if (nregs > cfun->va_list_gpr_size) 5612 nregs = cfun->va_list_gpr_size; 5613 } 5614 else 5615 { 5616 /* char * va_list instead counts number of bytes needed. */ 5617 if (nregs > cfun->va_list_gpr_size / reg_size) 5618 nregs = cfun->va_list_gpr_size / reg_size; 5619 } 5620 5621 mem = gen_rtx_MEM (BLKmode, 5622 plus_constant (save_area, 5623 first_reg_offset * reg_size)); 5624 MEM_NOTRAP_P (mem) = 1; 5625 set_mem_alias_set (mem, set); 5626 set_mem_align (mem, BITS_PER_WORD); 5627 5628 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem, 5629 nregs); 5630 } 5631 5632 /* Save FP registers if needed. */ 5633 if (DEFAULT_ABI == ABI_V4 5634 && TARGET_HARD_FLOAT && TARGET_FPRS 5635 && ! no_rtl 5636 && next_cum.fregno <= FP_ARG_V4_MAX_REG 5637 && cfun->va_list_fpr_size) 5638 { 5639 int fregno = next_cum.fregno, nregs; 5640 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); 5641 rtx lab = gen_label_rtx (); 5642 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) 5643 * UNITS_PER_FP_WORD); 5644 5645 emit_jump_insn 5646 (gen_rtx_SET (VOIDmode, 5647 pc_rtx, 5648 gen_rtx_IF_THEN_ELSE (VOIDmode, 5649 gen_rtx_NE (VOIDmode, cr1, 5650 const0_rtx), 5651 gen_rtx_LABEL_REF (VOIDmode, lab), 5652 pc_rtx))); 5653 5654 for (nregs = 0; 5655 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size; 5656 fregno++, off += UNITS_PER_FP_WORD, nregs++) 5657 { 5658 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); 5659 MEM_NOTRAP_P (mem) = 1; 5660 set_mem_alias_set (mem, set); 5661 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode)); 5662 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); 5663 } 5664 5665 emit_label (lab); 5666 } 5667} 5668 5669/* Create the va_list data type. */ 5670 5671static tree 5672rs6000_build_builtin_va_list (void) 5673{ 5674 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl; 5675 5676 /* For AIX, prefer 'char *' because that's what the system 5677 header files like. */ 5678 if (DEFAULT_ABI != ABI_V4) 5679 return build_pointer_type (char_type_node); 5680 5681 record = (*lang_hooks.types.make_type) (RECORD_TYPE); 5682 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); 5683 5684 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), 5685 unsigned_char_type_node); 5686 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), 5687 unsigned_char_type_node); 5688 /* Give the two bytes of padding a name, so that -Wpadded won't warn on 5689 every user file. */ 5690 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"), 5691 short_unsigned_type_node); 5692 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), 5693 ptr_type_node); 5694 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), 5695 ptr_type_node); 5696 5697 va_list_gpr_counter_field = f_gpr; 5698 va_list_fpr_counter_field = f_fpr; 5699 5700 DECL_FIELD_CONTEXT (f_gpr) = record; 5701 DECL_FIELD_CONTEXT (f_fpr) = record; 5702 DECL_FIELD_CONTEXT (f_res) = record; 5703 DECL_FIELD_CONTEXT (f_ovf) = record; 5704 DECL_FIELD_CONTEXT (f_sav) = record; 5705 5706 TREE_CHAIN (record) = type_decl; 5707 TYPE_NAME (record) = type_decl; 5708 TYPE_FIELDS (record) = f_gpr; 5709 TREE_CHAIN (f_gpr) = f_fpr; 5710 TREE_CHAIN (f_fpr) = f_res; 5711 TREE_CHAIN (f_res) = f_ovf; 5712 TREE_CHAIN (f_ovf) = f_sav; 5713 5714 layout_type (record); 5715 5716 /* The correct type is an array type of one element. */ 5717 return build_array_type (record, build_index_type (size_zero_node)); 5718} 5719 5720/* Implement va_start. */ 5721 5722void 5723rs6000_va_start (tree valist, rtx nextarg) 5724{ 5725 HOST_WIDE_INT words, n_gpr, n_fpr; 5726 tree f_gpr, f_fpr, f_res, f_ovf, f_sav; 5727 tree gpr, fpr, ovf, sav, t; 5728 5729 /* Only SVR4 needs something special. */ 5730 if (DEFAULT_ABI != ABI_V4) 5731 { 5732 std_expand_builtin_va_start (valist, nextarg); 5733 return; 5734 } 5735 5736 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); 5737 f_fpr = TREE_CHAIN (f_gpr); 5738 f_res = TREE_CHAIN (f_fpr); 5739 f_ovf = TREE_CHAIN (f_res); 5740 f_sav = TREE_CHAIN (f_ovf); 5741 5742 valist = build_va_arg_indirect_ref (valist); 5743 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); 5744 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); 5745 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); 5746 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); 5747 5748 /* Count number of gp and fp argument registers used. */ 5749 words = current_function_args_info.words; 5750 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG, 5751 GP_ARG_NUM_REG); 5752 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG, 5753 FP_ARG_NUM_REG); 5754 5755 if (TARGET_DEBUG_ARG) 5756 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = " 5757 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n", 5758 words, n_gpr, n_fpr); 5759 5760 if (cfun->va_list_gpr_size) 5761 { 5762 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, 5763 build_int_cst (NULL_TREE, n_gpr)); 5764 TREE_SIDE_EFFECTS (t) = 1; 5765 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 5766 } 5767 5768 if (cfun->va_list_fpr_size) 5769 { 5770 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, 5771 build_int_cst (NULL_TREE, n_fpr)); 5772 TREE_SIDE_EFFECTS (t) = 1; 5773 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 5774 } 5775 5776 /* Find the overflow area. */ 5777 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); 5778 if (words != 0) 5779 t = build (PLUS_EXPR, TREE_TYPE (ovf), t, 5780 build_int_cst (NULL_TREE, words * UNITS_PER_WORD)); 5781 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); 5782 TREE_SIDE_EFFECTS (t) = 1; 5783 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 5784 5785 /* If there were no va_arg invocations, don't set up the register 5786 save area. */ 5787 if (!cfun->va_list_gpr_size 5788 && !cfun->va_list_fpr_size 5789 && n_gpr < GP_ARG_NUM_REG 5790 && n_fpr < FP_ARG_V4_MAX_REG) 5791 return; 5792 5793 /* Find the register save area. */ 5794 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); 5795 if (cfun->machine->varargs_save_offset) 5796 t = build (PLUS_EXPR, TREE_TYPE (sav), t, 5797 build_int_cst (NULL_TREE, cfun->machine->varargs_save_offset)); 5798 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); 5799 TREE_SIDE_EFFECTS (t) = 1; 5800 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 5801} 5802 5803/* Implement va_arg. */ 5804 5805tree 5806rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p) 5807{ 5808 tree f_gpr, f_fpr, f_res, f_ovf, f_sav; 5809 tree gpr, fpr, ovf, sav, reg, t, u; 5810 int size, rsize, n_reg, sav_ofs, sav_scale; 5811 tree lab_false, lab_over, addr; 5812 int align; 5813 tree ptrtype = build_pointer_type (type); 5814 5815 if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) 5816 { 5817 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p); 5818 return build_va_arg_indirect_ref (t); 5819 } 5820 5821 if (DEFAULT_ABI != ABI_V4) 5822 { 5823 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE) 5824 { 5825 tree elem_type = TREE_TYPE (type); 5826 enum machine_mode elem_mode = TYPE_MODE (elem_type); 5827 int elem_size = GET_MODE_SIZE (elem_mode); 5828 5829 if (elem_size < UNITS_PER_WORD) 5830 { 5831 tree real_part, imag_part; 5832 tree post = NULL_TREE; 5833 5834 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, 5835 &post); 5836 /* Copy the value into a temporary, lest the formal temporary 5837 be reused out from under us. */ 5838 real_part = get_initialized_tmp_var (real_part, pre_p, &post); 5839 append_to_statement_list (post, pre_p); 5840 5841 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, 5842 post_p); 5843 5844 return build (COMPLEX_EXPR, type, real_part, imag_part); 5845 } 5846 } 5847 5848 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); 5849 } 5850 5851 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); 5852 f_fpr = TREE_CHAIN (f_gpr); 5853 f_res = TREE_CHAIN (f_fpr); 5854 f_ovf = TREE_CHAIN (f_res); 5855 f_sav = TREE_CHAIN (f_ovf); 5856 5857 valist = build_va_arg_indirect_ref (valist); 5858 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); 5859 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); 5860 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); 5861 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); 5862 5863 size = int_size_in_bytes (type); 5864 rsize = (size + 3) / 4; 5865 align = 1; 5866 5867 if (TARGET_HARD_FLOAT && TARGET_FPRS 5868 && (TYPE_MODE (type) == SFmode 5869 || TYPE_MODE (type) == DFmode 5870 || TYPE_MODE (type) == TFmode)) 5871 { 5872 /* FP args go in FP registers, if present. */ 5873 reg = fpr; 5874 n_reg = (size + 7) / 8; 5875 sav_ofs = 8*4; 5876 sav_scale = 8; 5877 if (TYPE_MODE (type) != SFmode) 5878 align = 8; 5879 } 5880 else 5881 { 5882 /* Otherwise into GP registers. */ 5883 reg = gpr; 5884 n_reg = rsize; 5885 sav_ofs = 0; 5886 sav_scale = 4; 5887 if (n_reg == 2) 5888 align = 8; 5889 } 5890 5891 /* Pull the value out of the saved registers.... */ 5892 5893 lab_over = NULL; 5894 addr = create_tmp_var (ptr_type_node, "addr"); 5895 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set (); 5896 5897 /* AltiVec vectors never go in registers when -mabi=altivec. */ 5898 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type))) 5899 align = 16; 5900 else 5901 { 5902 lab_false = create_artificial_label (); 5903 lab_over = create_artificial_label (); 5904 5905 /* Long long and SPE vectors are aligned in the registers. 5906 As are any other 2 gpr item such as complex int due to a 5907 historical mistake. */ 5908 u = reg; 5909 if (n_reg == 2 && reg == gpr) 5910 { 5911 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg, 5912 size_int (n_reg - 1)); 5913 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u); 5914 } 5915 5916 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1)); 5917 t = build2 (GE_EXPR, boolean_type_node, u, t); 5918 u = build1 (GOTO_EXPR, void_type_node, lab_false); 5919 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE); 5920 gimplify_and_add (t, pre_p); 5921 5922 t = sav; 5923 if (sav_ofs) 5924 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs)); 5925 5926 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg)); 5927 u = build1 (CONVERT_EXPR, integer_type_node, u); 5928 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale)); 5929 t = build2 (PLUS_EXPR, ptr_type_node, t, u); 5930 5931 t = build2 (MODIFY_EXPR, void_type_node, addr, t); 5932 gimplify_and_add (t, pre_p); 5933 5934 t = build1 (GOTO_EXPR, void_type_node, lab_over); 5935 gimplify_and_add (t, pre_p); 5936 5937 t = build1 (LABEL_EXPR, void_type_node, lab_false); 5938 append_to_statement_list (t, pre_p); 5939 5940 if ((n_reg == 2 && reg != gpr) || n_reg > 2) 5941 { 5942 /* Ensure that we don't find any more args in regs. 5943 Alignment has taken care of the n_reg == 2 gpr case. */ 5944 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8)); 5945 gimplify_and_add (t, pre_p); 5946 } 5947 } 5948 5949 /* ... otherwise out of the overflow area. */ 5950 5951 /* Care for on-stack alignment if needed. */ 5952 t = ovf; 5953 if (align != 1) 5954 { 5955 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1)); 5956 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, 5957 build_int_cst (NULL_TREE, -align)); 5958 } 5959 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue); 5960 5961 u = build2 (MODIFY_EXPR, void_type_node, addr, t); 5962 gimplify_and_add (u, pre_p); 5963 5964 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size)); 5965 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); 5966 gimplify_and_add (t, pre_p); 5967 5968 if (lab_over) 5969 { 5970 t = build1 (LABEL_EXPR, void_type_node, lab_over); 5971 append_to_statement_list (t, pre_p); 5972 } 5973 5974 if (STRICT_ALIGNMENT 5975 && (TYPE_ALIGN (type) 5976 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align))) 5977 { 5978 /* The value (of type complex double, for example) may not be 5979 aligned in memory in the saved registers, so copy via a 5980 temporary. (This is the same code as used for SPARC.) */ 5981 tree tmp = create_tmp_var (type, "va_arg_tmp"); 5982 tree dest_addr = build_fold_addr_expr (tmp); 5983 5984 tree copy = build_function_call_expr 5985 (implicit_built_in_decls[BUILT_IN_MEMCPY], 5986 tree_cons (NULL_TREE, dest_addr, 5987 tree_cons (NULL_TREE, addr, 5988 tree_cons (NULL_TREE, size_int (rsize * 4), 5989 NULL_TREE)))); 5990 5991 gimplify_and_add (copy, pre_p); 5992 addr = dest_addr; 5993 } 5994 5995 addr = fold_convert (ptrtype, addr); 5996 return build_va_arg_indirect_ref (addr); 5997} 5998 5999/* Builtins. */ 6000 6001static void 6002def_builtin (int mask, const char *name, tree type, int code) 6003{ 6004 if (mask & target_flags) 6005 { 6006 if (rs6000_builtin_decls[code]) 6007 abort (); 6008 6009 rs6000_builtin_decls[code] = 6010 lang_hooks.builtin_function (name, type, code, BUILT_IN_MD, 6011 NULL, NULL_TREE); 6012 } 6013} 6014 6015/* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ 6016 6017static const struct builtin_description bdesc_3arg[] = 6018{ 6019 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP }, 6020 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS }, 6021 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS }, 6022 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM}, 6023 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM }, 6024 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM }, 6025 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM }, 6026 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM }, 6027 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS }, 6028 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS }, 6029 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, 6030 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF }, 6031 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI }, 6032 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI }, 6033 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI }, 6034 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF }, 6035 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI }, 6036 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI }, 6037 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI }, 6038 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI }, 6039 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI }, 6040 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI }, 6041 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF }, 6042 6043 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD }, 6044 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS }, 6045 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD }, 6046 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS }, 6047 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM }, 6048 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM }, 6049 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM }, 6050 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM }, 6051 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM }, 6052 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS }, 6053 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS }, 6054 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS }, 6055 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB }, 6056 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM }, 6057 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL }, 6058}; 6059 6060/* DST operations: void foo (void *, const int, const char). */ 6061 6062static const struct builtin_description bdesc_dst[] = 6063{ 6064 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST }, 6065 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT }, 6066 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST }, 6067 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }, 6068 6069 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST }, 6070 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT }, 6071 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST }, 6072 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT } 6073}; 6074 6075/* Simple binary operations: VECc = foo (VECa, VECb). */ 6076 6077static struct builtin_description bdesc_2arg[] = 6078{ 6079 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM }, 6080 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, 6081 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, 6082 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, 6083 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, 6084 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, 6085 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, 6086 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS }, 6087 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS }, 6088 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS }, 6089 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS }, 6090 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND }, 6091 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC }, 6092 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB }, 6093 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB }, 6094 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH }, 6095 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH }, 6096 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW }, 6097 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW }, 6098 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX }, 6099 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX }, 6100 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP }, 6101 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB }, 6102 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH }, 6103 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW }, 6104 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP }, 6105 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP }, 6106 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB }, 6107 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB }, 6108 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH }, 6109 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH }, 6110 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW }, 6111 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW }, 6112 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP }, 6113 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS }, 6114 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS }, 6115 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, 6116 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, 6117 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, 6118 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, 6119 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, 6120 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, 6121 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, 6122 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB }, 6123 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH }, 6124 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW }, 6125 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB }, 6126 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH }, 6127 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW }, 6128 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB }, 6129 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB }, 6130 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH }, 6131 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH }, 6132 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW }, 6133 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW }, 6134 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP }, 6135 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB }, 6136 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB }, 6137 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH }, 6138 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH }, 6139 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB }, 6140 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB }, 6141 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH }, 6142 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH }, 6143 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR }, 6144 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR }, 6145 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM }, 6146 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM }, 6147 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX }, 6148 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS }, 6149 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS }, 6150 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS }, 6151 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS }, 6152 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS }, 6153 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS }, 6154 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB }, 6155 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH }, 6156 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW }, 6157 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB }, 6158 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH }, 6159 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW }, 6160 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL }, 6161 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO }, 6162 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB }, 6163 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH }, 6164 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW }, 6165 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, 6166 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH }, 6167 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW }, 6168 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, 6169 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, 6170 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, 6171 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR }, 6172 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO }, 6173 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM }, 6174 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM }, 6175 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM }, 6176 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP }, 6177 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW }, 6178 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS }, 6179 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS }, 6180 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS }, 6181 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS }, 6182 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS }, 6183 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS }, 6184 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS }, 6185 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS }, 6186 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS }, 6187 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, 6188 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, 6189 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, 6190 6191 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD }, 6192 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP }, 6193 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM }, 6194 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM }, 6195 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM }, 6196 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC }, 6197 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS }, 6198 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS }, 6199 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS }, 6200 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS }, 6201 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS }, 6202 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS }, 6203 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS }, 6204 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND }, 6205 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC }, 6206 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG }, 6207 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW }, 6208 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW }, 6209 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH }, 6210 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH }, 6211 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB }, 6212 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB }, 6213 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB }, 6214 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ }, 6215 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP }, 6216 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW }, 6217 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH }, 6218 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB }, 6219 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE }, 6220 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT }, 6221 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP }, 6222 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW }, 6223 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW }, 6224 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH }, 6225 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH }, 6226 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB }, 6227 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB }, 6228 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE }, 6229 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT }, 6230 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX }, 6231 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP }, 6232 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW }, 6233 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW }, 6234 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH }, 6235 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH }, 6236 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB }, 6237 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB }, 6238 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH }, 6239 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW }, 6240 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH }, 6241 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB }, 6242 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL }, 6243 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW }, 6244 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH }, 6245 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB }, 6246 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN }, 6247 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP }, 6248 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW }, 6249 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW }, 6250 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH }, 6251 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH }, 6252 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB }, 6253 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB }, 6254 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE }, 6255 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB }, 6256 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB }, 6257 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH }, 6258 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH }, 6259 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO }, 6260 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH }, 6261 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH }, 6262 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB }, 6263 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB }, 6264 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR }, 6265 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR }, 6266 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK }, 6267 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM }, 6268 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM }, 6269 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX }, 6270 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS }, 6271 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS }, 6272 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS }, 6273 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS }, 6274 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS }, 6275 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU }, 6276 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS }, 6277 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS }, 6278 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL }, 6279 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW }, 6280 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH }, 6281 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB }, 6282 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL }, 6283 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW }, 6284 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH }, 6285 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB }, 6286 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL }, 6287 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO }, 6288 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR }, 6289 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW }, 6290 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH }, 6291 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB }, 6292 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA }, 6293 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW }, 6294 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH }, 6295 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB }, 6296 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL }, 6297 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO }, 6298 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB }, 6299 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP }, 6300 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM }, 6301 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM }, 6302 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM }, 6303 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC }, 6304 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS }, 6305 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS }, 6306 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS }, 6307 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS }, 6308 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS }, 6309 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS }, 6310 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS }, 6311 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S }, 6312 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS }, 6313 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS }, 6314 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS }, 6315 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S }, 6316 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS }, 6317 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR }, 6318 6319 /* Place holder, leave as first spe builtin. */ 6320 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW }, 6321 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND }, 6322 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC }, 6323 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS }, 6324 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU }, 6325 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV }, 6326 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD }, 6327 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV }, 6328 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL }, 6329 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB }, 6330 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI }, 6331 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO }, 6332 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO }, 6333 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI }, 6334 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA }, 6335 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN }, 6336 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA }, 6337 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN }, 6338 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA }, 6339 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN }, 6340 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF }, 6341 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA }, 6342 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW }, 6343 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW }, 6344 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI }, 6345 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA }, 6346 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW }, 6347 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW }, 6348 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF }, 6349 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA }, 6350 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW }, 6351 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW }, 6352 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW }, 6353 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW }, 6354 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI }, 6355 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA }, 6356 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW }, 6357 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW }, 6358 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW }, 6359 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW }, 6360 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA }, 6361 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN }, 6362 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA }, 6363 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN }, 6364 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA }, 6365 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN }, 6366 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF }, 6367 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA }, 6368 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW }, 6369 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW }, 6370 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI }, 6371 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA }, 6372 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW }, 6373 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW }, 6374 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF }, 6375 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA }, 6376 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW }, 6377 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW }, 6378 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW }, 6379 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW }, 6380 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI }, 6381 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA }, 6382 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW }, 6383 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW }, 6384 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW }, 6385 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW }, 6386 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF }, 6387 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA }, 6388 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI }, 6389 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA }, 6390 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF }, 6391 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA }, 6392 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI }, 6393 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA }, 6394 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW }, 6395 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW }, 6396 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW }, 6397 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW }, 6398 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI }, 6399 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA }, 6400 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW }, 6401 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW }, 6402 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW }, 6403 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW }, 6404 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF }, 6405 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA }, 6406 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA }, 6407 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN }, 6408 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI }, 6409 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA }, 6410 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA }, 6411 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN }, 6412 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF }, 6413 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA }, 6414 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA }, 6415 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN }, 6416 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI }, 6417 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA }, 6418 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA }, 6419 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN }, 6420 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND }, 6421 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR }, 6422 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR }, 6423 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC }, 6424 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW }, 6425 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW }, 6426 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS }, 6427 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU }, 6428 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW }, 6429 6430 /* SPE binary operations expecting a 5-bit unsigned literal. */ 6431 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW }, 6432 6433 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI }, 6434 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI }, 6435 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS }, 6436 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU }, 6437 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW }, 6438 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA }, 6439 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA }, 6440 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA }, 6441 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA }, 6442 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA }, 6443 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA }, 6444 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN }, 6445 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN }, 6446 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN }, 6447 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN }, 6448 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN }, 6449 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN }, 6450 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA }, 6451 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA }, 6452 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA }, 6453 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA }, 6454 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN }, 6455 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN }, 6456 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN }, 6457 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN }, 6458 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC }, 6459 6460 /* Place-holder. Leave as last binary SPE builtin. */ 6461 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR } 6462}; 6463 6464/* AltiVec predicates. */ 6465 6466struct builtin_description_predicates 6467{ 6468 const unsigned int mask; 6469 const enum insn_code icode; 6470 const char *opcode; 6471 const char *const name; 6472 const enum rs6000_builtins code; 6473}; 6474 6475static const struct builtin_description_predicates bdesc_altivec_preds[] = 6476{ 6477 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P }, 6478 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P }, 6479 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P }, 6480 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P }, 6481 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P }, 6482 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P }, 6483 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P }, 6484 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P }, 6485 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P }, 6486 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P }, 6487 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P }, 6488 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P }, 6489 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }, 6490 6491 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P }, 6492 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P }, 6493 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P } 6494}; 6495 6496/* SPE predicates. */ 6497static struct builtin_description bdesc_spe_predicates[] = 6498{ 6499 /* Place-holder. Leave as first. */ 6500 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ }, 6501 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS }, 6502 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU }, 6503 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS }, 6504 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU }, 6505 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ }, 6506 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT }, 6507 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT }, 6508 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ }, 6509 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT }, 6510 /* Place-holder. Leave as last. */ 6511 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT }, 6512}; 6513 6514/* SPE evsel predicates. */ 6515static struct builtin_description bdesc_spe_evsel[] = 6516{ 6517 /* Place-holder. Leave as first. */ 6518 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS }, 6519 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU }, 6520 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS }, 6521 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU }, 6522 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ }, 6523 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT }, 6524 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT }, 6525 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ }, 6526 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT }, 6527 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT }, 6528 /* Place-holder. Leave as last. */ 6529 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ }, 6530}; 6531 6532/* ABS* operations. */ 6533 6534static const struct builtin_description bdesc_abs[] = 6535{ 6536 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI }, 6537 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI }, 6538 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF }, 6539 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI }, 6540 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI }, 6541 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI }, 6542 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI } 6543}; 6544 6545/* Simple unary operations: VECb = foo (unsigned literal) or VECb = 6546 foo (VECa). */ 6547 6548static struct builtin_description bdesc_1arg[] = 6549{ 6550 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP }, 6551 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP }, 6552 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP }, 6553 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM }, 6554 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN }, 6555 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP }, 6556 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ }, 6557 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP }, 6558 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB }, 6559 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH }, 6560 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW }, 6561 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB }, 6562 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX }, 6563 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH }, 6564 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB }, 6565 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX }, 6566 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH }, 6567 6568 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS }, 6569 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS }, 6570 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL }, 6571 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE }, 6572 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR }, 6573 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE }, 6574 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR }, 6575 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE }, 6576 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND }, 6577 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE }, 6578 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC }, 6579 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH }, 6580 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH }, 6581 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX }, 6582 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB }, 6583 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL }, 6584 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX }, 6585 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH }, 6586 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB }, 6587 6588 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and 6589 end with SPE_BUILTIN_EVSUBFUSIAAW. */ 6590 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS }, 6591 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW }, 6592 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW }, 6593 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW }, 6594 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW }, 6595 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW }, 6596 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW }, 6597 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB }, 6598 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH }, 6599 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS }, 6600 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF }, 6601 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI }, 6602 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF }, 6603 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI }, 6604 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF }, 6605 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI }, 6606 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ }, 6607 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF }, 6608 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI }, 6609 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ }, 6610 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS }, 6611 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG }, 6612 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA }, 6613 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG }, 6614 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW }, 6615 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW }, 6616 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW }, 6617 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW }, 6618 6619 /* Place-holder. Leave as last unary SPE builtin. */ 6620 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW } 6621}; 6622 6623static rtx 6624rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target) 6625{ 6626 rtx pat; 6627 tree arg0 = TREE_VALUE (arglist); 6628 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); 6629 enum machine_mode tmode = insn_data[icode].operand[0].mode; 6630 enum machine_mode mode0 = insn_data[icode].operand[1].mode; 6631 6632 if (icode == CODE_FOR_nothing) 6633 /* Builtin not supported on this processor. */ 6634 return 0; 6635 6636 /* If we got invalid arguments bail out before generating bad rtl. */ 6637 if (arg0 == error_mark_node) 6638 return const0_rtx; 6639 6640 if (icode == CODE_FOR_altivec_vspltisb 6641 || icode == CODE_FOR_altivec_vspltish 6642 || icode == CODE_FOR_altivec_vspltisw 6643 || icode == CODE_FOR_spe_evsplatfi 6644 || icode == CODE_FOR_spe_evsplati) 6645 { 6646 /* Only allow 5-bit *signed* literals. */ 6647 if (GET_CODE (op0) != CONST_INT 6648 || INTVAL (op0) > 15 6649 || INTVAL (op0) < -16) 6650 { 6651 error ("argument 1 must be a 5-bit signed literal"); 6652 return const0_rtx; 6653 } 6654 } 6655 6656 if (target == 0 6657 || GET_MODE (target) != tmode 6658 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 6659 target = gen_reg_rtx (tmode); 6660 6661 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 6662 op0 = copy_to_mode_reg (mode0, op0); 6663 6664 pat = GEN_FCN (icode) (target, op0); 6665 if (! pat) 6666 return 0; 6667 emit_insn (pat); 6668 6669 return target; 6670} 6671 6672static rtx 6673altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target) 6674{ 6675 rtx pat, scratch1, scratch2; 6676 tree arg0 = TREE_VALUE (arglist); 6677 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); 6678 enum machine_mode tmode = insn_data[icode].operand[0].mode; 6679 enum machine_mode mode0 = insn_data[icode].operand[1].mode; 6680 6681 /* If we have invalid arguments, bail out before generating bad rtl. */ 6682 if (arg0 == error_mark_node) 6683 return const0_rtx; 6684 6685 if (target == 0 6686 || GET_MODE (target) != tmode 6687 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 6688 target = gen_reg_rtx (tmode); 6689 6690 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 6691 op0 = copy_to_mode_reg (mode0, op0); 6692 6693 scratch1 = gen_reg_rtx (mode0); 6694 scratch2 = gen_reg_rtx (mode0); 6695 6696 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2); 6697 if (! pat) 6698 return 0; 6699 emit_insn (pat); 6700 6701 return target; 6702} 6703 6704static rtx 6705rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target) 6706{ 6707 rtx pat; 6708 tree arg0 = TREE_VALUE (arglist); 6709 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); 6710 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); 6711 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); 6712 enum machine_mode tmode = insn_data[icode].operand[0].mode; 6713 enum machine_mode mode0 = insn_data[icode].operand[1].mode; 6714 enum machine_mode mode1 = insn_data[icode].operand[2].mode; 6715 6716 if (icode == CODE_FOR_nothing) 6717 /* Builtin not supported on this processor. */ 6718 return 0; 6719 6720 /* If we got invalid arguments bail out before generating bad rtl. */ 6721 if (arg0 == error_mark_node || arg1 == error_mark_node) 6722 return const0_rtx; 6723 6724 if (icode == CODE_FOR_altivec_vcfux 6725 || icode == CODE_FOR_altivec_vcfsx 6726 || icode == CODE_FOR_altivec_vctsxs 6727 || icode == CODE_FOR_altivec_vctuxs 6728 || icode == CODE_FOR_altivec_vspltb 6729 || icode == CODE_FOR_altivec_vsplth 6730 || icode == CODE_FOR_altivec_vspltw 6731 || icode == CODE_FOR_spe_evaddiw 6732 || icode == CODE_FOR_spe_evldd 6733 || icode == CODE_FOR_spe_evldh 6734 || icode == CODE_FOR_spe_evldw 6735 || icode == CODE_FOR_spe_evlhhesplat 6736 || icode == CODE_FOR_spe_evlhhossplat 6737 || icode == CODE_FOR_spe_evlhhousplat 6738 || icode == CODE_FOR_spe_evlwhe 6739 || icode == CODE_FOR_spe_evlwhos 6740 || icode == CODE_FOR_spe_evlwhou 6741 || icode == CODE_FOR_spe_evlwhsplat 6742 || icode == CODE_FOR_spe_evlwwsplat 6743 || icode == CODE_FOR_spe_evrlwi 6744 || icode == CODE_FOR_spe_evslwi 6745 || icode == CODE_FOR_spe_evsrwis 6746 || icode == CODE_FOR_spe_evsubifw 6747 || icode == CODE_FOR_spe_evsrwiu) 6748 { 6749 /* Only allow 5-bit unsigned literals. */ 6750 STRIP_NOPS (arg1); 6751 if (TREE_CODE (arg1) != INTEGER_CST 6752 || TREE_INT_CST_LOW (arg1) & ~0x1f) 6753 { 6754 error ("argument 2 must be a 5-bit unsigned literal"); 6755 return const0_rtx; 6756 } 6757 } 6758 6759 if (target == 0 6760 || GET_MODE (target) != tmode 6761 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 6762 target = gen_reg_rtx (tmode); 6763 6764 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 6765 op0 = copy_to_mode_reg (mode0, op0); 6766 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) 6767 op1 = copy_to_mode_reg (mode1, op1); 6768 6769 pat = GEN_FCN (icode) (target, op0, op1); 6770 if (! pat) 6771 return 0; 6772 emit_insn (pat); 6773 6774 return target; 6775} 6776 6777static rtx 6778altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode, 6779 tree arglist, rtx target) 6780{ 6781 rtx pat, scratch; 6782 tree cr6_form = TREE_VALUE (arglist); 6783 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); 6784 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); 6785 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); 6786 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); 6787 enum machine_mode tmode = SImode; 6788 enum machine_mode mode0 = insn_data[icode].operand[1].mode; 6789 enum machine_mode mode1 = insn_data[icode].operand[2].mode; 6790 int cr6_form_int; 6791 6792 if (TREE_CODE (cr6_form) != INTEGER_CST) 6793 { 6794 error ("argument 1 of __builtin_altivec_predicate must be a constant"); 6795 return const0_rtx; 6796 } 6797 else 6798 cr6_form_int = TREE_INT_CST_LOW (cr6_form); 6799 6800 gcc_assert (mode0 == mode1); 6801 6802 /* If we have invalid arguments, bail out before generating bad rtl. */ 6803 if (arg0 == error_mark_node || arg1 == error_mark_node) 6804 return const0_rtx; 6805 6806 if (target == 0 6807 || GET_MODE (target) != tmode 6808 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 6809 target = gen_reg_rtx (tmode); 6810 6811 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 6812 op0 = copy_to_mode_reg (mode0, op0); 6813 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) 6814 op1 = copy_to_mode_reg (mode1, op1); 6815 6816 scratch = gen_reg_rtx (mode0); 6817 6818 pat = GEN_FCN (icode) (scratch, op0, op1, 6819 gen_rtx_SYMBOL_REF (Pmode, opcode)); 6820 if (! pat) 6821 return 0; 6822 emit_insn (pat); 6823 6824 /* The vec_any* and vec_all* predicates use the same opcodes for two 6825 different operations, but the bits in CR6 will be different 6826 depending on what information we want. So we have to play tricks 6827 with CR6 to get the right bits out. 6828 6829 If you think this is disgusting, look at the specs for the 6830 AltiVec predicates. */ 6831 6832 switch (cr6_form_int) 6833 { 6834 case 0: 6835 emit_insn (gen_cr6_test_for_zero (target)); 6836 break; 6837 case 1: 6838 emit_insn (gen_cr6_test_for_zero_reverse (target)); 6839 break; 6840 case 2: 6841 emit_insn (gen_cr6_test_for_lt (target)); 6842 break; 6843 case 3: 6844 emit_insn (gen_cr6_test_for_lt_reverse (target)); 6845 break; 6846 default: 6847 error ("argument 1 of __builtin_altivec_predicate is out of range"); 6848 break; 6849 } 6850 6851 return target; 6852} 6853 6854static rtx 6855altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target) 6856{ 6857 rtx pat, addr; 6858 tree arg0 = TREE_VALUE (arglist); 6859 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); 6860 enum machine_mode tmode = insn_data[icode].operand[0].mode; 6861 enum machine_mode mode0 = Pmode; 6862 enum machine_mode mode1 = Pmode; 6863 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); 6864 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); 6865 6866 if (icode == CODE_FOR_nothing) 6867 /* Builtin not supported on this processor. */ 6868 return 0; 6869 6870 /* If we got invalid arguments bail out before generating bad rtl. */ 6871 if (arg0 == error_mark_node || arg1 == error_mark_node) 6872 return const0_rtx; 6873 6874 if (target == 0 6875 || GET_MODE (target) != tmode 6876 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 6877 target = gen_reg_rtx (tmode); 6878 6879 op1 = copy_to_mode_reg (mode1, op1); 6880 6881 if (op0 == const0_rtx) 6882 { 6883 addr = gen_rtx_MEM (tmode, op1); 6884 } 6885 else 6886 { 6887 op0 = copy_to_mode_reg (mode0, op0); 6888 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1)); 6889 } 6890 6891 pat = GEN_FCN (icode) (target, addr); 6892 6893 if (! pat) 6894 return 0; 6895 emit_insn (pat); 6896 6897 return target; 6898} 6899 6900static rtx 6901spe_expand_stv_builtin (enum insn_code icode, tree arglist) 6902{ 6903 tree arg0 = TREE_VALUE (arglist); 6904 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); 6905 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); 6906 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); 6907 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); 6908 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); 6909 rtx pat; 6910 enum machine_mode mode0 = insn_data[icode].operand[0].mode; 6911 enum machine_mode mode1 = insn_data[icode].operand[1].mode; 6912 enum machine_mode mode2 = insn_data[icode].operand[2].mode; 6913 6914 /* Invalid arguments. Bail before doing anything stoopid! */ 6915 if (arg0 == error_mark_node 6916 || arg1 == error_mark_node 6917 || arg2 == error_mark_node) 6918 return const0_rtx; 6919 6920 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2)) 6921 op0 = copy_to_mode_reg (mode2, op0); 6922 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0)) 6923 op1 = copy_to_mode_reg (mode0, op1); 6924 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) 6925 op2 = copy_to_mode_reg (mode1, op2); 6926 6927 pat = GEN_FCN (icode) (op1, op2, op0); 6928 if (pat) 6929 emit_insn (pat); 6930 return NULL_RTX; 6931} 6932 6933static rtx 6934altivec_expand_stv_builtin (enum insn_code icode, tree arglist) 6935{ 6936 tree arg0 = TREE_VALUE (arglist); 6937 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); 6938 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); 6939 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); 6940 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); 6941 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); 6942 rtx pat, addr; 6943 enum machine_mode tmode = insn_data[icode].operand[0].mode; 6944 enum machine_mode mode1 = Pmode; 6945 enum machine_mode mode2 = Pmode; 6946 6947 /* Invalid arguments. Bail before doing anything stoopid! */ 6948 if (arg0 == error_mark_node 6949 || arg1 == error_mark_node 6950 || arg2 == error_mark_node) 6951 return const0_rtx; 6952 6953 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode)) 6954 op0 = copy_to_mode_reg (tmode, op0); 6955 6956 op2 = copy_to_mode_reg (mode2, op2); 6957 6958 if (op1 == const0_rtx) 6959 { 6960 addr = gen_rtx_MEM (tmode, op2); 6961 } 6962 else 6963 { 6964 op1 = copy_to_mode_reg (mode1, op1); 6965 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2)); 6966 } 6967 6968 pat = GEN_FCN (icode) (addr, op0); 6969 if (pat) 6970 emit_insn (pat); 6971 return NULL_RTX; 6972} 6973 6974static rtx 6975rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target) 6976{ 6977 rtx pat; 6978 tree arg0 = TREE_VALUE (arglist); 6979 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); 6980 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); 6981 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); 6982 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); 6983 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); 6984 enum machine_mode tmode = insn_data[icode].operand[0].mode; 6985 enum machine_mode mode0 = insn_data[icode].operand[1].mode; 6986 enum machine_mode mode1 = insn_data[icode].operand[2].mode; 6987 enum machine_mode mode2 = insn_data[icode].operand[3].mode; 6988 6989 if (icode == CODE_FOR_nothing) 6990 /* Builtin not supported on this processor. */ 6991 return 0; 6992 6993 /* If we got invalid arguments bail out before generating bad rtl. */ 6994 if (arg0 == error_mark_node 6995 || arg1 == error_mark_node 6996 || arg2 == error_mark_node) 6997 return const0_rtx; 6998 6999 if (icode == CODE_FOR_altivec_vsldoi_v4sf 7000 || icode == CODE_FOR_altivec_vsldoi_v4si 7001 || icode == CODE_FOR_altivec_vsldoi_v8hi 7002 || icode == CODE_FOR_altivec_vsldoi_v16qi) 7003 { 7004 /* Only allow 4-bit unsigned literals. */ 7005 STRIP_NOPS (arg2); 7006 if (TREE_CODE (arg2) != INTEGER_CST 7007 || TREE_INT_CST_LOW (arg2) & ~0xf) 7008 { 7009 error ("argument 3 must be a 4-bit unsigned literal"); 7010 return const0_rtx; 7011 } 7012 } 7013 7014 if (target == 0 7015 || GET_MODE (target) != tmode 7016 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 7017 target = gen_reg_rtx (tmode); 7018 7019 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 7020 op0 = copy_to_mode_reg (mode0, op0); 7021 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) 7022 op1 = copy_to_mode_reg (mode1, op1); 7023 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) 7024 op2 = copy_to_mode_reg (mode2, op2); 7025 7026 pat = GEN_FCN (icode) (target, op0, op1, op2); 7027 if (! pat) 7028 return 0; 7029 emit_insn (pat); 7030 7031 return target; 7032} 7033 7034/* Expand the lvx builtins. */ 7035static rtx 7036altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp) 7037{ 7038 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); 7039 tree arglist = TREE_OPERAND (exp, 1); 7040 unsigned int fcode = DECL_FUNCTION_CODE (fndecl); 7041 tree arg0; 7042 enum machine_mode tmode, mode0; 7043 rtx pat, op0; 7044 enum insn_code icode; 7045 7046 switch (fcode) 7047 { 7048 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi: 7049 icode = CODE_FOR_altivec_lvx_v16qi; 7050 break; 7051 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi: 7052 icode = CODE_FOR_altivec_lvx_v8hi; 7053 break; 7054 case ALTIVEC_BUILTIN_LD_INTERNAL_4si: 7055 icode = CODE_FOR_altivec_lvx_v4si; 7056 break; 7057 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: 7058 icode = CODE_FOR_altivec_lvx_v4sf; 7059 break; 7060 default: 7061 *expandedp = false; 7062 return NULL_RTX; 7063 } 7064 7065 *expandedp = true; 7066 7067 arg0 = TREE_VALUE (arglist); 7068 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); 7069 tmode = insn_data[icode].operand[0].mode; 7070 mode0 = insn_data[icode].operand[1].mode; 7071 7072 if (target == 0 7073 || GET_MODE (target) != tmode 7074 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 7075 target = gen_reg_rtx (tmode); 7076 7077 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 7078 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); 7079 7080 pat = GEN_FCN (icode) (target, op0); 7081 if (! pat) 7082 return 0; 7083 emit_insn (pat); 7084 return target; 7085} 7086 7087/* Expand the stvx builtins. */ 7088static rtx 7089altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, 7090 bool *expandedp) 7091{ 7092 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); 7093 tree arglist = TREE_OPERAND (exp, 1); 7094 unsigned int fcode = DECL_FUNCTION_CODE (fndecl); 7095 tree arg0, arg1; 7096 enum machine_mode mode0, mode1; 7097 rtx pat, op0, op1; 7098 enum insn_code icode; 7099 7100 switch (fcode) 7101 { 7102 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: 7103 icode = CODE_FOR_altivec_stvx_v16qi; 7104 break; 7105 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: 7106 icode = CODE_FOR_altivec_stvx_v8hi; 7107 break; 7108 case ALTIVEC_BUILTIN_ST_INTERNAL_4si: 7109 icode = CODE_FOR_altivec_stvx_v4si; 7110 break; 7111 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: 7112 icode = CODE_FOR_altivec_stvx_v4sf; 7113 break; 7114 default: 7115 *expandedp = false; 7116 return NULL_RTX; 7117 } 7118 7119 arg0 = TREE_VALUE (arglist); 7120 arg1 = TREE_VALUE (TREE_CHAIN (arglist)); 7121 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); 7122 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); 7123 mode0 = insn_data[icode].operand[0].mode; 7124 mode1 = insn_data[icode].operand[1].mode; 7125 7126 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) 7127 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); 7128 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) 7129 op1 = copy_to_mode_reg (mode1, op1); 7130 7131 pat = GEN_FCN (icode) (op0, op1); 7132 if (pat) 7133 emit_insn (pat); 7134 7135 *expandedp = true; 7136 return NULL_RTX; 7137} 7138 7139/* Expand the dst builtins. */ 7140static rtx 7141altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, 7142 bool *expandedp) 7143{ 7144 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); 7145 tree arglist = TREE_OPERAND (exp, 1); 7146 unsigned int fcode = DECL_FUNCTION_CODE (fndecl); 7147 tree arg0, arg1, arg2; 7148 enum machine_mode mode0, mode1, mode2; 7149 rtx pat, op0, op1, op2; 7150 struct builtin_description *d; 7151 size_t i; 7152 7153 *expandedp = false; 7154 7155 /* Handle DST variants. */ 7156 d = (struct builtin_description *) bdesc_dst; 7157 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) 7158 if (d->code == fcode) 7159 { 7160 arg0 = TREE_VALUE (arglist); 7161 arg1 = TREE_VALUE (TREE_CHAIN (arglist)); 7162 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); 7163 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); 7164 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); 7165 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); 7166 mode0 = insn_data[d->icode].operand[0].mode; 7167 mode1 = insn_data[d->icode].operand[1].mode; 7168 mode2 = insn_data[d->icode].operand[2].mode; 7169 7170 /* Invalid arguments, bail out before generating bad rtl. */ 7171 if (arg0 == error_mark_node 7172 || arg1 == error_mark_node 7173 || arg2 == error_mark_node) 7174 return const0_rtx; 7175 7176 *expandedp = true; 7177 STRIP_NOPS (arg2); 7178 if (TREE_CODE (arg2) != INTEGER_CST 7179 || TREE_INT_CST_LOW (arg2) & ~0x3) 7180 { 7181 error ("argument to %qs must be a 2-bit unsigned literal", d->name); 7182 return const0_rtx; 7183 } 7184 7185 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) 7186 op0 = copy_to_mode_reg (Pmode, op0); 7187 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) 7188 op1 = copy_to_mode_reg (mode1, op1); 7189 7190 pat = GEN_FCN (d->icode) (op0, op1, op2); 7191 if (pat != 0) 7192 emit_insn (pat); 7193 7194 return NULL_RTX; 7195 } 7196 7197 return NULL_RTX; 7198} 7199 7200/* Expand vec_init builtin. */ 7201static rtx 7202altivec_expand_vec_init_builtin (tree type, tree arglist, rtx target) 7203{ 7204 enum machine_mode tmode = TYPE_MODE (type); 7205 enum machine_mode inner_mode = GET_MODE_INNER (tmode); 7206 int i, n_elt = GET_MODE_NUNITS (tmode); 7207 rtvec v = rtvec_alloc (n_elt); 7208 7209 gcc_assert (VECTOR_MODE_P (tmode)); 7210 7211 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist)) 7212 { 7213 rtx x = expand_expr (TREE_VALUE (arglist), NULL_RTX, VOIDmode, 0); 7214 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x); 7215 } 7216 7217 gcc_assert (arglist == NULL); 7218 7219 if (!target || !register_operand (target, tmode)) 7220 target = gen_reg_rtx (tmode); 7221 7222 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v)); 7223 return target; 7224} 7225 7226/* Return the integer constant in ARG. Constrain it to be in the range 7227 of the subparts of VEC_TYPE; issue an error if not. */ 7228 7229static int 7230get_element_number (tree vec_type, tree arg) 7231{ 7232 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1; 7233 7234 if (!host_integerp (arg, 1) 7235 || (elt = tree_low_cst (arg, 1), elt > max)) 7236 { 7237 error ("selector must be an integer constant in the range 0..%wi", max); 7238 return 0; 7239 } 7240 7241 return elt; 7242} 7243 7244/* Expand vec_set builtin. */ 7245static rtx 7246altivec_expand_vec_set_builtin (tree arglist) 7247{ 7248 enum machine_mode tmode, mode1; 7249 tree arg0, arg1, arg2; 7250 int elt; 7251 rtx op0, op1; 7252 7253 arg0 = TREE_VALUE (arglist); 7254 arg1 = TREE_VALUE (TREE_CHAIN (arglist)); 7255 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); 7256 7257 tmode = TYPE_MODE (TREE_TYPE (arg0)); 7258 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0))); 7259 gcc_assert (VECTOR_MODE_P (tmode)); 7260 7261 op0 = expand_expr (arg0, NULL_RTX, tmode, 0); 7262 op1 = expand_expr (arg1, NULL_RTX, mode1, 0); 7263 elt = get_element_number (TREE_TYPE (arg0), arg2); 7264 7265 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode) 7266 op1 = convert_modes (mode1, GET_MODE (op1), op1, true); 7267 7268 op0 = force_reg (tmode, op0); 7269 op1 = force_reg (mode1, op1); 7270 7271 rs6000_expand_vector_set (op0, op1, elt); 7272 7273 return op0; 7274} 7275 7276/* Expand vec_ext builtin. */ 7277static rtx 7278altivec_expand_vec_ext_builtin (tree arglist, rtx target) 7279{ 7280 enum machine_mode tmode, mode0; 7281 tree arg0, arg1; 7282 int elt; 7283 rtx op0; 7284 7285 arg0 = TREE_VALUE (arglist); 7286 arg1 = TREE_VALUE (TREE_CHAIN (arglist)); 7287 7288 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); 7289 elt = get_element_number (TREE_TYPE (arg0), arg1); 7290 7291 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0))); 7292 mode0 = TYPE_MODE (TREE_TYPE (arg0)); 7293 gcc_assert (VECTOR_MODE_P (mode0)); 7294 7295 op0 = force_reg (mode0, op0); 7296 7297 if (optimize || !target || !register_operand (target, tmode)) 7298 target = gen_reg_rtx (tmode); 7299 7300 rs6000_expand_vector_extract (target, op0, elt); 7301 7302 return target; 7303} 7304 7305/* Expand the builtin in EXP and store the result in TARGET. Store 7306 true in *EXPANDEDP if we found a builtin to expand. */ 7307static rtx 7308altivec_expand_builtin (tree exp, rtx target, bool *expandedp) 7309{ 7310 struct builtin_description *d; 7311 struct builtin_description_predicates *dp; 7312 size_t i; 7313 enum insn_code icode; 7314 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); 7315 tree arglist = TREE_OPERAND (exp, 1); 7316 tree arg0; 7317 rtx op0, pat; 7318 enum machine_mode tmode, mode0; 7319 unsigned int fcode = DECL_FUNCTION_CODE (fndecl); 7320 7321 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST 7322 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST) 7323 { 7324 *expandedp = true; 7325 error ("unresolved overload for Altivec builtin %qF", fndecl); 7326 return const0_rtx; 7327 } 7328 7329 target = altivec_expand_ld_builtin (exp, target, expandedp); 7330 if (*expandedp) 7331 return target; 7332 7333 target = altivec_expand_st_builtin (exp, target, expandedp); 7334 if (*expandedp) 7335 return target; 7336 7337 target = altivec_expand_dst_builtin (exp, target, expandedp); 7338 if (*expandedp) 7339 return target; 7340 7341 *expandedp = true; 7342 7343 switch (fcode) 7344 { 7345 case ALTIVEC_BUILTIN_STVX: 7346 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist); 7347 case ALTIVEC_BUILTIN_STVEBX: 7348 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist); 7349 case ALTIVEC_BUILTIN_STVEHX: 7350 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist); 7351 case ALTIVEC_BUILTIN_STVEWX: 7352 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist); 7353 case ALTIVEC_BUILTIN_STVXL: 7354 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist); 7355 7356 case ALTIVEC_BUILTIN_MFVSCR: 7357 icode = CODE_FOR_altivec_mfvscr; 7358 tmode = insn_data[icode].operand[0].mode; 7359 7360 if (target == 0 7361 || GET_MODE (target) != tmode 7362 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 7363 target = gen_reg_rtx (tmode); 7364 7365 pat = GEN_FCN (icode) (target); 7366 if (! pat) 7367 return 0; 7368 emit_insn (pat); 7369 return target; 7370 7371 case ALTIVEC_BUILTIN_MTVSCR: 7372 icode = CODE_FOR_altivec_mtvscr; 7373 arg0 = TREE_VALUE (arglist); 7374 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); 7375 mode0 = insn_data[icode].operand[0].mode; 7376 7377 /* If we got invalid arguments bail out before generating bad rtl. */ 7378 if (arg0 == error_mark_node) 7379 return const0_rtx; 7380 7381 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) 7382 op0 = copy_to_mode_reg (mode0, op0); 7383 7384 pat = GEN_FCN (icode) (op0); 7385 if (pat) 7386 emit_insn (pat); 7387 return NULL_RTX; 7388 7389 case ALTIVEC_BUILTIN_DSSALL: 7390 emit_insn (gen_altivec_dssall ()); 7391 return NULL_RTX; 7392 7393 case ALTIVEC_BUILTIN_DSS: 7394 icode = CODE_FOR_altivec_dss; 7395 arg0 = TREE_VALUE (arglist); 7396 STRIP_NOPS (arg0); 7397 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); 7398 mode0 = insn_data[icode].operand[0].mode; 7399 7400 /* If we got invalid arguments bail out before generating bad rtl. */ 7401 if (arg0 == error_mark_node) 7402 return const0_rtx; 7403 7404 if (TREE_CODE (arg0) != INTEGER_CST 7405 || TREE_INT_CST_LOW (arg0) & ~0x3) 7406 { 7407 error ("argument to dss must be a 2-bit unsigned literal"); 7408 return const0_rtx; 7409 } 7410 7411 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) 7412 op0 = copy_to_mode_reg (mode0, op0); 7413 7414 emit_insn (gen_altivec_dss (op0)); 7415 return NULL_RTX; 7416 7417 case ALTIVEC_BUILTIN_VEC_INIT_V4SI: 7418 case ALTIVEC_BUILTIN_VEC_INIT_V8HI: 7419 case ALTIVEC_BUILTIN_VEC_INIT_V16QI: 7420 case ALTIVEC_BUILTIN_VEC_INIT_V4SF: 7421 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target); 7422 7423 case ALTIVEC_BUILTIN_VEC_SET_V4SI: 7424 case ALTIVEC_BUILTIN_VEC_SET_V8HI: 7425 case ALTIVEC_BUILTIN_VEC_SET_V16QI: 7426 case ALTIVEC_BUILTIN_VEC_SET_V4SF: 7427 return altivec_expand_vec_set_builtin (arglist); 7428 7429 case ALTIVEC_BUILTIN_VEC_EXT_V4SI: 7430 case ALTIVEC_BUILTIN_VEC_EXT_V8HI: 7431 case ALTIVEC_BUILTIN_VEC_EXT_V16QI: 7432 case ALTIVEC_BUILTIN_VEC_EXT_V4SF: 7433 return altivec_expand_vec_ext_builtin (arglist, target); 7434 7435 default: 7436 break; 7437 /* Fall through. */ 7438 } 7439 7440 /* Expand abs* operations. */ 7441 d = (struct builtin_description *) bdesc_abs; 7442 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) 7443 if (d->code == fcode) 7444 return altivec_expand_abs_builtin (d->icode, arglist, target); 7445 7446 /* Expand the AltiVec predicates. */ 7447 dp = (struct builtin_description_predicates *) bdesc_altivec_preds; 7448 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) 7449 if (dp->code == fcode) 7450 return altivec_expand_predicate_builtin (dp->icode, dp->opcode, 7451 arglist, target); 7452 7453 /* LV* are funky. We initialized them differently. */ 7454 switch (fcode) 7455 { 7456 case ALTIVEC_BUILTIN_LVSL: 7457 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl, 7458 arglist, target); 7459 case ALTIVEC_BUILTIN_LVSR: 7460 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr, 7461 arglist, target); 7462 case ALTIVEC_BUILTIN_LVEBX: 7463 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx, 7464 arglist, target); 7465 case ALTIVEC_BUILTIN_LVEHX: 7466 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx, 7467 arglist, target); 7468 case ALTIVEC_BUILTIN_LVEWX: 7469 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx, 7470 arglist, target); 7471 case ALTIVEC_BUILTIN_LVXL: 7472 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl, 7473 arglist, target); 7474 case ALTIVEC_BUILTIN_LVX: 7475 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx, 7476 arglist, target); 7477 default: 7478 break; 7479 /* Fall through. */ 7480 } 7481 7482 *expandedp = false; 7483 return NULL_RTX; 7484} 7485 7486/* Binops that need to be initialized manually, but can be expanded 7487 automagically by rs6000_expand_binop_builtin. */ 7488static struct builtin_description bdesc_2arg_spe[] = 7489{ 7490 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX }, 7491 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX }, 7492 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX }, 7493 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX }, 7494 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX }, 7495 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX }, 7496 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX }, 7497 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX }, 7498 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX }, 7499 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX }, 7500 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX }, 7501 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD }, 7502 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW }, 7503 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH }, 7504 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE }, 7505 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU }, 7506 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS }, 7507 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT }, 7508 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT }, 7509 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT }, 7510 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT }, 7511 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT } 7512}; 7513 7514/* Expand the builtin in EXP and store the result in TARGET. Store 7515 true in *EXPANDEDP if we found a builtin to expand. 7516 7517 This expands the SPE builtins that are not simple unary and binary 7518 operations. */ 7519static rtx 7520spe_expand_builtin (tree exp, rtx target, bool *expandedp) 7521{ 7522 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); 7523 tree arglist = TREE_OPERAND (exp, 1); 7524 tree arg1, arg0; 7525 unsigned int fcode = DECL_FUNCTION_CODE (fndecl); 7526 enum insn_code icode; 7527 enum machine_mode tmode, mode0; 7528 rtx pat, op0; 7529 struct builtin_description *d; 7530 size_t i; 7531 7532 *expandedp = true; 7533 7534 /* Syntax check for a 5-bit unsigned immediate. */ 7535 switch (fcode) 7536 { 7537 case SPE_BUILTIN_EVSTDD: 7538 case SPE_BUILTIN_EVSTDH: 7539 case SPE_BUILTIN_EVSTDW: 7540 case SPE_BUILTIN_EVSTWHE: 7541 case SPE_BUILTIN_EVSTWHO: 7542 case SPE_BUILTIN_EVSTWWE: 7543 case SPE_BUILTIN_EVSTWWO: 7544 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); 7545 if (TREE_CODE (arg1) != INTEGER_CST 7546 || TREE_INT_CST_LOW (arg1) & ~0x1f) 7547 { 7548 error ("argument 2 must be a 5-bit unsigned literal"); 7549 return const0_rtx; 7550 } 7551 break; 7552 default: 7553 break; 7554 } 7555 7556 /* The evsplat*i instructions are not quite generic. */ 7557 switch (fcode) 7558 { 7559 case SPE_BUILTIN_EVSPLATFI: 7560 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi, 7561 arglist, target); 7562 case SPE_BUILTIN_EVSPLATI: 7563 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati, 7564 arglist, target); 7565 default: 7566 break; 7567 } 7568 7569 d = (struct builtin_description *) bdesc_2arg_spe; 7570 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d) 7571 if (d->code == fcode) 7572 return rs6000_expand_binop_builtin (d->icode, arglist, target); 7573 7574 d = (struct builtin_description *) bdesc_spe_predicates; 7575 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d) 7576 if (d->code == fcode) 7577 return spe_expand_predicate_builtin (d->icode, arglist, target); 7578 7579 d = (struct builtin_description *) bdesc_spe_evsel; 7580 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d) 7581 if (d->code == fcode) 7582 return spe_expand_evsel_builtin (d->icode, arglist, target); 7583 7584 switch (fcode) 7585 { 7586 case SPE_BUILTIN_EVSTDDX: 7587 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist); 7588 case SPE_BUILTIN_EVSTDHX: 7589 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist); 7590 case SPE_BUILTIN_EVSTDWX: 7591 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist); 7592 case SPE_BUILTIN_EVSTWHEX: 7593 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist); 7594 case SPE_BUILTIN_EVSTWHOX: 7595 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist); 7596 case SPE_BUILTIN_EVSTWWEX: 7597 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist); 7598 case SPE_BUILTIN_EVSTWWOX: 7599 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist); 7600 case SPE_BUILTIN_EVSTDD: 7601 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist); 7602 case SPE_BUILTIN_EVSTDH: 7603 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist); 7604 case SPE_BUILTIN_EVSTDW: 7605 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist); 7606 case SPE_BUILTIN_EVSTWHE: 7607 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist); 7608 case SPE_BUILTIN_EVSTWHO: 7609 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist); 7610 case SPE_BUILTIN_EVSTWWE: 7611 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist); 7612 case SPE_BUILTIN_EVSTWWO: 7613 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist); 7614 case SPE_BUILTIN_MFSPEFSCR: 7615 icode = CODE_FOR_spe_mfspefscr; 7616 tmode = insn_data[icode].operand[0].mode; 7617 7618 if (target == 0 7619 || GET_MODE (target) != tmode 7620 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 7621 target = gen_reg_rtx (tmode); 7622 7623 pat = GEN_FCN (icode) (target); 7624 if (! pat) 7625 return 0; 7626 emit_insn (pat); 7627 return target; 7628 case SPE_BUILTIN_MTSPEFSCR: 7629 icode = CODE_FOR_spe_mtspefscr; 7630 arg0 = TREE_VALUE (arglist); 7631 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); 7632 mode0 = insn_data[icode].operand[0].mode; 7633 7634 if (arg0 == error_mark_node) 7635 return const0_rtx; 7636 7637 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) 7638 op0 = copy_to_mode_reg (mode0, op0); 7639 7640 pat = GEN_FCN (icode) (op0); 7641 if (pat) 7642 emit_insn (pat); 7643 return NULL_RTX; 7644 default: 7645 break; 7646 } 7647 7648 *expandedp = false; 7649 return NULL_RTX; 7650} 7651 7652static rtx 7653spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target) 7654{ 7655 rtx pat, scratch, tmp; 7656 tree form = TREE_VALUE (arglist); 7657 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); 7658 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); 7659 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); 7660 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); 7661 enum machine_mode mode0 = insn_data[icode].operand[1].mode; 7662 enum machine_mode mode1 = insn_data[icode].operand[2].mode; 7663 int form_int; 7664 enum rtx_code code; 7665 7666 if (TREE_CODE (form) != INTEGER_CST) 7667 { 7668 error ("argument 1 of __builtin_spe_predicate must be a constant"); 7669 return const0_rtx; 7670 } 7671 else 7672 form_int = TREE_INT_CST_LOW (form); 7673 7674 gcc_assert (mode0 == mode1); 7675 7676 if (arg0 == error_mark_node || arg1 == error_mark_node) 7677 return const0_rtx; 7678 7679 if (target == 0 7680 || GET_MODE (target) != SImode 7681 || ! (*insn_data[icode].operand[0].predicate) (target, SImode)) 7682 target = gen_reg_rtx (SImode); 7683 7684 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 7685 op0 = copy_to_mode_reg (mode0, op0); 7686 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) 7687 op1 = copy_to_mode_reg (mode1, op1); 7688 7689 scratch = gen_reg_rtx (CCmode); 7690 7691 pat = GEN_FCN (icode) (scratch, op0, op1); 7692 if (! pat) 7693 return const0_rtx; 7694 emit_insn (pat); 7695 7696 /* There are 4 variants for each predicate: _any_, _all_, _upper_, 7697 _lower_. We use one compare, but look in different bits of the 7698 CR for each variant. 7699 7700 There are 2 elements in each SPE simd type (upper/lower). The CR 7701 bits are set as follows: 7702 7703 BIT0 | BIT 1 | BIT 2 | BIT 3 7704 U | L | (U | L) | (U & L) 7705 7706 So, for an "all" relationship, BIT 3 would be set. 7707 For an "any" relationship, BIT 2 would be set. Etc. 7708 7709 Following traditional nomenclature, these bits map to: 7710 7711 BIT0 | BIT 1 | BIT 2 | BIT 3 7712 LT | GT | EQ | OV 7713 7714 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits. 7715 */ 7716 7717 switch (form_int) 7718 { 7719 /* All variant. OV bit. */ 7720 case 0: 7721 /* We need to get to the OV bit, which is the ORDERED bit. We 7722 could generate (ordered:SI (reg:CC xx) (const_int 0)), but 7723 that's ugly and will make validate_condition_mode die. 7724 So let's just use another pattern. */ 7725 emit_insn (gen_move_from_CR_ov_bit (target, scratch)); 7726 return target; 7727 /* Any variant. EQ bit. */ 7728 case 1: 7729 code = EQ; 7730 break; 7731 /* Upper variant. LT bit. */ 7732 case 2: 7733 code = LT; 7734 break; 7735 /* Lower variant. GT bit. */ 7736 case 3: 7737 code = GT; 7738 break; 7739 default: 7740 error ("argument 1 of __builtin_spe_predicate is out of range"); 7741 return const0_rtx; 7742 } 7743 7744 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx); 7745 emit_move_insn (target, tmp); 7746 7747 return target; 7748} 7749 7750/* The evsel builtins look like this: 7751 7752 e = __builtin_spe_evsel_OP (a, b, c, d); 7753 7754 and work like this: 7755 7756 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper]; 7757 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower]; 7758*/ 7759 7760static rtx 7761spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target) 7762{ 7763 rtx pat, scratch; 7764 tree arg0 = TREE_VALUE (arglist); 7765 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); 7766 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); 7767 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist)))); 7768 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); 7769 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); 7770 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); 7771 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0); 7772 enum machine_mode mode0 = insn_data[icode].operand[1].mode; 7773 enum machine_mode mode1 = insn_data[icode].operand[2].mode; 7774 7775 gcc_assert (mode0 == mode1); 7776 7777 if (arg0 == error_mark_node || arg1 == error_mark_node 7778 || arg2 == error_mark_node || arg3 == error_mark_node) 7779 return const0_rtx; 7780 7781 if (target == 0 7782 || GET_MODE (target) != mode0 7783 || ! (*insn_data[icode].operand[0].predicate) (target, mode0)) 7784 target = gen_reg_rtx (mode0); 7785 7786 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 7787 op0 = copy_to_mode_reg (mode0, op0); 7788 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) 7789 op1 = copy_to_mode_reg (mode0, op1); 7790 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) 7791 op2 = copy_to_mode_reg (mode0, op2); 7792 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1)) 7793 op3 = copy_to_mode_reg (mode0, op3); 7794 7795 /* Generate the compare. */ 7796 scratch = gen_reg_rtx (CCmode); 7797 pat = GEN_FCN (icode) (scratch, op0, op1); 7798 if (! pat) 7799 return const0_rtx; 7800 emit_insn (pat); 7801 7802 if (mode0 == V2SImode) 7803 emit_insn (gen_spe_evsel (target, op2, op3, scratch)); 7804 else 7805 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch)); 7806 7807 return target; 7808} 7809 7810/* Expand an expression EXP that calls a built-in function, 7811 with result going to TARGET if that's convenient 7812 (and in mode MODE if that's convenient). 7813 SUBTARGET may be used as the target for computing one of EXP's operands. 7814 IGNORE is nonzero if the value is to be ignored. */ 7815 7816static rtx 7817rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, 7818 enum machine_mode mode ATTRIBUTE_UNUSED, 7819 int ignore ATTRIBUTE_UNUSED) 7820{ 7821 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); 7822 tree arglist = TREE_OPERAND (exp, 1); 7823 unsigned int fcode = DECL_FUNCTION_CODE (fndecl); 7824 struct builtin_description *d; 7825 size_t i; 7826 rtx ret; 7827 bool success; 7828 7829 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD 7830 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE) 7831 { 7832 int icode = (int) CODE_FOR_altivec_lvsr; 7833 enum machine_mode tmode = insn_data[icode].operand[0].mode; 7834 enum machine_mode mode = insn_data[icode].operand[1].mode; 7835 tree arg; 7836 rtx op, addr, pat; 7837 7838 gcc_assert (TARGET_ALTIVEC); 7839 7840 arg = TREE_VALUE (arglist); 7841 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE); 7842 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL); 7843 addr = memory_address (mode, op); 7844 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE) 7845 op = addr; 7846 else 7847 { 7848 /* For the load case need to negate the address. */ 7849 op = gen_reg_rtx (GET_MODE (addr)); 7850 emit_insn (gen_rtx_SET (VOIDmode, op, 7851 gen_rtx_NEG (GET_MODE (addr), addr))); 7852 } 7853 op = gen_rtx_MEM (mode, op); 7854 7855 if (target == 0 7856 || GET_MODE (target) != tmode 7857 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 7858 target = gen_reg_rtx (tmode); 7859 7860 /*pat = gen_altivec_lvsr (target, op);*/ 7861 pat = GEN_FCN (icode) (target, op); 7862 if (!pat) 7863 return 0; 7864 emit_insn (pat); 7865 7866 return target; 7867 } 7868 7869 if (TARGET_ALTIVEC) 7870 { 7871 ret = altivec_expand_builtin (exp, target, &success); 7872 7873 if (success) 7874 return ret; 7875 } 7876 if (TARGET_SPE) 7877 { 7878 ret = spe_expand_builtin (exp, target, &success); 7879 7880 if (success) 7881 return ret; 7882 } 7883 7884 gcc_assert (TARGET_ALTIVEC || TARGET_SPE); 7885 7886 /* Handle simple unary operations. */ 7887 d = (struct builtin_description *) bdesc_1arg; 7888 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) 7889 if (d->code == fcode) 7890 return rs6000_expand_unop_builtin (d->icode, arglist, target); 7891 7892 /* Handle simple binary operations. */ 7893 d = (struct builtin_description *) bdesc_2arg; 7894 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) 7895 if (d->code == fcode) 7896 return rs6000_expand_binop_builtin (d->icode, arglist, target); 7897 7898 /* Handle simple ternary operations. */ 7899 d = (struct builtin_description *) bdesc_3arg; 7900 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) 7901 if (d->code == fcode) 7902 return rs6000_expand_ternop_builtin (d->icode, arglist, target); 7903 7904 gcc_unreachable (); 7905} 7906 7907static tree 7908build_opaque_vector_type (tree node, int nunits) 7909{ 7910 node = copy_node (node); 7911 TYPE_MAIN_VARIANT (node) = node; 7912 return build_vector_type (node, nunits); 7913} 7914 7915static void 7916rs6000_init_builtins (void) 7917{ 7918 V2SI_type_node = build_vector_type (intSI_type_node, 2); 7919 V2SF_type_node = build_vector_type (float_type_node, 2); 7920 V4HI_type_node = build_vector_type (intHI_type_node, 4); 7921 V4SI_type_node = build_vector_type (intSI_type_node, 4); 7922 V4SF_type_node = build_vector_type (float_type_node, 4); 7923 V8HI_type_node = build_vector_type (intHI_type_node, 8); 7924 V16QI_type_node = build_vector_type (intQI_type_node, 16); 7925 7926 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16); 7927 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8); 7928 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4); 7929 7930 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2); 7931 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2); 7932 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node); 7933 opaque_V4SI_type_node = copy_node (V4SI_type_node); 7934 7935 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...' 7936 types, especially in C++ land. Similarly, 'vector pixel' is distinct from 7937 'vector unsigned short'. */ 7938 7939 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node); 7940 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node); 7941 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node); 7942 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node); 7943 7944 long_integer_type_internal_node = long_integer_type_node; 7945 long_unsigned_type_internal_node = long_unsigned_type_node; 7946 intQI_type_internal_node = intQI_type_node; 7947 uintQI_type_internal_node = unsigned_intQI_type_node; 7948 intHI_type_internal_node = intHI_type_node; 7949 uintHI_type_internal_node = unsigned_intHI_type_node; 7950 intSI_type_internal_node = intSI_type_node; 7951 uintSI_type_internal_node = unsigned_intSI_type_node; 7952 float_type_internal_node = float_type_node; 7953 void_type_internal_node = void_type_node; 7954 7955 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, 7956 get_identifier ("__bool char"), 7957 bool_char_type_node)); 7958 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, 7959 get_identifier ("__bool short"), 7960 bool_short_type_node)); 7961 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, 7962 get_identifier ("__bool int"), 7963 bool_int_type_node)); 7964 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, 7965 get_identifier ("__pixel"), 7966 pixel_type_node)); 7967 7968 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16); 7969 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8); 7970 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4); 7971 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8); 7972 7973 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, 7974 get_identifier ("__vector unsigned char"), 7975 unsigned_V16QI_type_node)); 7976 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, 7977 get_identifier ("__vector signed char"), 7978 V16QI_type_node)); 7979 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, 7980 get_identifier ("__vector __bool char"), 7981 bool_V16QI_type_node)); 7982 7983 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, 7984 get_identifier ("__vector unsigned short"), 7985 unsigned_V8HI_type_node)); 7986 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, 7987 get_identifier ("__vector signed short"), 7988 V8HI_type_node)); 7989 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, 7990 get_identifier ("__vector __bool short"), 7991 bool_V8HI_type_node)); 7992 7993 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, 7994 get_identifier ("__vector unsigned int"), 7995 unsigned_V4SI_type_node)); 7996 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, 7997 get_identifier ("__vector signed int"), 7998 V4SI_type_node)); 7999 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, 8000 get_identifier ("__vector __bool int"), 8001 bool_V4SI_type_node)); 8002 8003 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, 8004 get_identifier ("__vector float"), 8005 V4SF_type_node)); 8006 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, 8007 get_identifier ("__vector __pixel"), 8008 pixel_V8HI_type_node)); 8009 8010 if (TARGET_SPE) 8011 spe_init_builtins (); 8012 if (TARGET_ALTIVEC) 8013 altivec_init_builtins (); 8014 if (TARGET_ALTIVEC || TARGET_SPE) 8015 rs6000_common_init_builtins (); 8016 8017#if TARGET_XCOFF 8018 /* AIX libm provides clog as __clog. */ 8019 if (built_in_decls [BUILT_IN_CLOG]) 8020 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog"); 8021#endif 8022} 8023 8024/* Search through a set of builtins and enable the mask bits. 8025 DESC is an array of builtins. 8026 SIZE is the total number of builtins. 8027 START is the builtin enum at which to start. 8028 END is the builtin enum at which to end. */ 8029static void 8030enable_mask_for_builtins (struct builtin_description *desc, int size, 8031 enum rs6000_builtins start, 8032 enum rs6000_builtins end) 8033{ 8034 int i; 8035 8036 for (i = 0; i < size; ++i) 8037 if (desc[i].code == start) 8038 break; 8039 8040 if (i == size) 8041 return; 8042 8043 for (; i < size; ++i) 8044 { 8045 /* Flip all the bits on. */ 8046 desc[i].mask = target_flags; 8047 if (desc[i].code == end) 8048 break; 8049 } 8050} 8051 8052static void 8053spe_init_builtins (void) 8054{ 8055 tree endlink = void_list_node; 8056 tree puint_type_node = build_pointer_type (unsigned_type_node); 8057 tree pushort_type_node = build_pointer_type (short_unsigned_type_node); 8058 struct builtin_description *d; 8059 size_t i; 8060 8061 tree v2si_ftype_4_v2si 8062 = build_function_type 8063 (opaque_V2SI_type_node, 8064 tree_cons (NULL_TREE, opaque_V2SI_type_node, 8065 tree_cons (NULL_TREE, opaque_V2SI_type_node, 8066 tree_cons (NULL_TREE, opaque_V2SI_type_node, 8067 tree_cons (NULL_TREE, opaque_V2SI_type_node, 8068 endlink))))); 8069 8070 tree v2sf_ftype_4_v2sf 8071 = build_function_type 8072 (opaque_V2SF_type_node, 8073 tree_cons (NULL_TREE, opaque_V2SF_type_node, 8074 tree_cons (NULL_TREE, opaque_V2SF_type_node, 8075 tree_cons (NULL_TREE, opaque_V2SF_type_node, 8076 tree_cons (NULL_TREE, opaque_V2SF_type_node, 8077 endlink))))); 8078 8079 tree int_ftype_int_v2si_v2si 8080 = build_function_type 8081 (integer_type_node, 8082 tree_cons (NULL_TREE, integer_type_node, 8083 tree_cons (NULL_TREE, opaque_V2SI_type_node, 8084 tree_cons (NULL_TREE, opaque_V2SI_type_node, 8085 endlink)))); 8086 8087 tree int_ftype_int_v2sf_v2sf 8088 = build_function_type 8089 (integer_type_node, 8090 tree_cons (NULL_TREE, integer_type_node, 8091 tree_cons (NULL_TREE, opaque_V2SF_type_node, 8092 tree_cons (NULL_TREE, opaque_V2SF_type_node, 8093 endlink)))); 8094 8095 tree void_ftype_v2si_puint_int 8096 = build_function_type (void_type_node, 8097 tree_cons (NULL_TREE, opaque_V2SI_type_node, 8098 tree_cons (NULL_TREE, puint_type_node, 8099 tree_cons (NULL_TREE, 8100 integer_type_node, 8101 endlink)))); 8102 8103 tree void_ftype_v2si_puint_char 8104 = build_function_type (void_type_node, 8105 tree_cons (NULL_TREE, opaque_V2SI_type_node, 8106 tree_cons (NULL_TREE, puint_type_node, 8107 tree_cons (NULL_TREE, 8108 char_type_node, 8109 endlink)))); 8110 8111 tree void_ftype_v2si_pv2si_int 8112 = build_function_type (void_type_node, 8113 tree_cons (NULL_TREE, opaque_V2SI_type_node, 8114 tree_cons (NULL_TREE, opaque_p_V2SI_type_node, 8115 tree_cons (NULL_TREE, 8116 integer_type_node, 8117 endlink)))); 8118 8119 tree void_ftype_v2si_pv2si_char 8120 = build_function_type (void_type_node, 8121 tree_cons (NULL_TREE, opaque_V2SI_type_node, 8122 tree_cons (NULL_TREE, opaque_p_V2SI_type_node, 8123 tree_cons (NULL_TREE, 8124 char_type_node, 8125 endlink)))); 8126 8127 tree void_ftype_int 8128 = build_function_type (void_type_node, 8129 tree_cons (NULL_TREE, integer_type_node, endlink)); 8130 8131 tree int_ftype_void 8132 = build_function_type (integer_type_node, endlink); 8133 8134 tree v2si_ftype_pv2si_int 8135 = build_function_type (opaque_V2SI_type_node, 8136 tree_cons (NULL_TREE, opaque_p_V2SI_type_node, 8137 tree_cons (NULL_TREE, integer_type_node, 8138 endlink))); 8139 8140 tree v2si_ftype_puint_int 8141 = build_function_type (opaque_V2SI_type_node, 8142 tree_cons (NULL_TREE, puint_type_node, 8143 tree_cons (NULL_TREE, integer_type_node, 8144 endlink))); 8145 8146 tree v2si_ftype_pushort_int 8147 = build_function_type (opaque_V2SI_type_node, 8148 tree_cons (NULL_TREE, pushort_type_node, 8149 tree_cons (NULL_TREE, integer_type_node, 8150 endlink))); 8151 8152 tree v2si_ftype_signed_char 8153 = build_function_type (opaque_V2SI_type_node, 8154 tree_cons (NULL_TREE, signed_char_type_node, 8155 endlink)); 8156 8157 /* The initialization of the simple binary and unary builtins is 8158 done in rs6000_common_init_builtins, but we have to enable the 8159 mask bits here manually because we have run out of `target_flags' 8160 bits. We really need to redesign this mask business. */ 8161 8162 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg, 8163 ARRAY_SIZE (bdesc_2arg), 8164 SPE_BUILTIN_EVADDW, 8165 SPE_BUILTIN_EVXOR); 8166 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg, 8167 ARRAY_SIZE (bdesc_1arg), 8168 SPE_BUILTIN_EVABS, 8169 SPE_BUILTIN_EVSUBFUSIAAW); 8170 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates, 8171 ARRAY_SIZE (bdesc_spe_predicates), 8172 SPE_BUILTIN_EVCMPEQ, 8173 SPE_BUILTIN_EVFSTSTLT); 8174 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel, 8175 ARRAY_SIZE (bdesc_spe_evsel), 8176 SPE_BUILTIN_EVSEL_CMPGTS, 8177 SPE_BUILTIN_EVSEL_FSTSTEQ); 8178 8179 (*lang_hooks.decls.pushdecl) 8180 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"), 8181 opaque_V2SI_type_node)); 8182 8183 /* Initialize irregular SPE builtins. */ 8184 8185 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR); 8186 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR); 8187 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX); 8188 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX); 8189 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX); 8190 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX); 8191 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX); 8192 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX); 8193 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX); 8194 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD); 8195 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH); 8196 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW); 8197 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE); 8198 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO); 8199 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE); 8200 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO); 8201 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI); 8202 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI); 8203 8204 /* Loads. */ 8205 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX); 8206 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX); 8207 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX); 8208 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX); 8209 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX); 8210 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX); 8211 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX); 8212 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX); 8213 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX); 8214 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX); 8215 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX); 8216 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD); 8217 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW); 8218 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH); 8219 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT); 8220 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT); 8221 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT); 8222 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE); 8223 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS); 8224 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU); 8225 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT); 8226 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT); 8227 8228 /* Predicates. */ 8229 d = (struct builtin_description *) bdesc_spe_predicates; 8230 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++) 8231 { 8232 tree type; 8233 8234 switch (insn_data[d->icode].operand[1].mode) 8235 { 8236 case V2SImode: 8237 type = int_ftype_int_v2si_v2si; 8238 break; 8239 case V2SFmode: 8240 type = int_ftype_int_v2sf_v2sf; 8241 break; 8242 default: 8243 gcc_unreachable (); 8244 } 8245 8246 def_builtin (d->mask, d->name, type, d->code); 8247 } 8248 8249 /* Evsel predicates. */ 8250 d = (struct builtin_description *) bdesc_spe_evsel; 8251 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++) 8252 { 8253 tree type; 8254 8255 switch (insn_data[d->icode].operand[1].mode) 8256 { 8257 case V2SImode: 8258 type = v2si_ftype_4_v2si; 8259 break; 8260 case V2SFmode: 8261 type = v2sf_ftype_4_v2sf; 8262 break; 8263 default: 8264 gcc_unreachable (); 8265 } 8266 8267 def_builtin (d->mask, d->name, type, d->code); 8268 } 8269} 8270 8271static void 8272altivec_init_builtins (void) 8273{ 8274 struct builtin_description *d; 8275 struct builtin_description_predicates *dp; 8276 size_t i; 8277 tree ftype; 8278 8279 tree pfloat_type_node = build_pointer_type (float_type_node); 8280 tree pint_type_node = build_pointer_type (integer_type_node); 8281 tree pshort_type_node = build_pointer_type (short_integer_type_node); 8282 tree pchar_type_node = build_pointer_type (char_type_node); 8283 8284 tree pvoid_type_node = build_pointer_type (void_type_node); 8285 8286 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST)); 8287 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST)); 8288 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST)); 8289 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST)); 8290 8291 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST)); 8292 8293 tree int_ftype_opaque 8294 = build_function_type_list (integer_type_node, 8295 opaque_V4SI_type_node, NULL_TREE); 8296 8297 tree opaque_ftype_opaque_int 8298 = build_function_type_list (opaque_V4SI_type_node, 8299 opaque_V4SI_type_node, integer_type_node, NULL_TREE); 8300 tree opaque_ftype_opaque_opaque_int 8301 = build_function_type_list (opaque_V4SI_type_node, 8302 opaque_V4SI_type_node, opaque_V4SI_type_node, 8303 integer_type_node, NULL_TREE); 8304 tree int_ftype_int_opaque_opaque 8305 = build_function_type_list (integer_type_node, 8306 integer_type_node, opaque_V4SI_type_node, 8307 opaque_V4SI_type_node, NULL_TREE); 8308 tree int_ftype_int_v4si_v4si 8309 = build_function_type_list (integer_type_node, 8310 integer_type_node, V4SI_type_node, 8311 V4SI_type_node, NULL_TREE); 8312 tree v4sf_ftype_pcfloat 8313 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE); 8314 tree void_ftype_pfloat_v4sf 8315 = build_function_type_list (void_type_node, 8316 pfloat_type_node, V4SF_type_node, NULL_TREE); 8317 tree v4si_ftype_pcint 8318 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE); 8319 tree void_ftype_pint_v4si 8320 = build_function_type_list (void_type_node, 8321 pint_type_node, V4SI_type_node, NULL_TREE); 8322 tree v8hi_ftype_pcshort 8323 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE); 8324 tree void_ftype_pshort_v8hi 8325 = build_function_type_list (void_type_node, 8326 pshort_type_node, V8HI_type_node, NULL_TREE); 8327 tree v16qi_ftype_pcchar 8328 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE); 8329 tree void_ftype_pchar_v16qi 8330 = build_function_type_list (void_type_node, 8331 pchar_type_node, V16QI_type_node, NULL_TREE); 8332 tree void_ftype_v4si 8333 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE); 8334 tree v8hi_ftype_void 8335 = build_function_type (V8HI_type_node, void_list_node); 8336 tree void_ftype_void 8337 = build_function_type (void_type_node, void_list_node); 8338 tree void_ftype_int 8339 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE); 8340 8341 tree opaque_ftype_long_pcvoid 8342 = build_function_type_list (opaque_V4SI_type_node, 8343 long_integer_type_node, pcvoid_type_node, NULL_TREE); 8344 tree v16qi_ftype_long_pcvoid 8345 = build_function_type_list (V16QI_type_node, 8346 long_integer_type_node, pcvoid_type_node, NULL_TREE); 8347 tree v8hi_ftype_long_pcvoid 8348 = build_function_type_list (V8HI_type_node, 8349 long_integer_type_node, pcvoid_type_node, NULL_TREE); 8350 tree v4si_ftype_long_pcvoid 8351 = build_function_type_list (V4SI_type_node, 8352 long_integer_type_node, pcvoid_type_node, NULL_TREE); 8353 8354 tree void_ftype_opaque_long_pvoid 8355 = build_function_type_list (void_type_node, 8356 opaque_V4SI_type_node, long_integer_type_node, 8357 pvoid_type_node, NULL_TREE); 8358 tree void_ftype_v4si_long_pvoid 8359 = build_function_type_list (void_type_node, 8360 V4SI_type_node, long_integer_type_node, 8361 pvoid_type_node, NULL_TREE); 8362 tree void_ftype_v16qi_long_pvoid 8363 = build_function_type_list (void_type_node, 8364 V16QI_type_node, long_integer_type_node, 8365 pvoid_type_node, NULL_TREE); 8366 tree void_ftype_v8hi_long_pvoid 8367 = build_function_type_list (void_type_node, 8368 V8HI_type_node, long_integer_type_node, 8369 pvoid_type_node, NULL_TREE); 8370 tree int_ftype_int_v8hi_v8hi 8371 = build_function_type_list (integer_type_node, 8372 integer_type_node, V8HI_type_node, 8373 V8HI_type_node, NULL_TREE); 8374 tree int_ftype_int_v16qi_v16qi 8375 = build_function_type_list (integer_type_node, 8376 integer_type_node, V16QI_type_node, 8377 V16QI_type_node, NULL_TREE); 8378 tree int_ftype_int_v4sf_v4sf 8379 = build_function_type_list (integer_type_node, 8380 integer_type_node, V4SF_type_node, 8381 V4SF_type_node, NULL_TREE); 8382 tree v4si_ftype_v4si 8383 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE); 8384 tree v8hi_ftype_v8hi 8385 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE); 8386 tree v16qi_ftype_v16qi 8387 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE); 8388 tree v4sf_ftype_v4sf 8389 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); 8390 tree void_ftype_pcvoid_int_int 8391 = build_function_type_list (void_type_node, 8392 pcvoid_type_node, integer_type_node, 8393 integer_type_node, NULL_TREE); 8394 8395 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat, 8396 ALTIVEC_BUILTIN_LD_INTERNAL_4sf); 8397 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, 8398 ALTIVEC_BUILTIN_ST_INTERNAL_4sf); 8399 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint, 8400 ALTIVEC_BUILTIN_LD_INTERNAL_4si); 8401 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, 8402 ALTIVEC_BUILTIN_ST_INTERNAL_4si); 8403 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort, 8404 ALTIVEC_BUILTIN_LD_INTERNAL_8hi); 8405 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, 8406 ALTIVEC_BUILTIN_ST_INTERNAL_8hi); 8407 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar, 8408 ALTIVEC_BUILTIN_LD_INTERNAL_16qi); 8409 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, 8410 ALTIVEC_BUILTIN_ST_INTERNAL_16qi); 8411 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); 8412 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); 8413 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); 8414 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS); 8415 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL); 8416 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR); 8417 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX); 8418 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX); 8419 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX); 8420 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL); 8421 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX); 8422 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX); 8423 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX); 8424 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL); 8425 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX); 8426 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX); 8427 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD); 8428 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE); 8429 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL); 8430 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL); 8431 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR); 8432 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX); 8433 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX); 8434 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX); 8435 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST); 8436 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE); 8437 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL); 8438 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX); 8439 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX); 8440 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX); 8441 8442 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP); 8443 8444 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD); 8445 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT); 8446 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW); 8447 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH); 8448 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB); 8449 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF); 8450 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX); 8451 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX); 8452 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS); 8453 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU); 8454 8455 /* Add the DST variants. */ 8456 d = (struct builtin_description *) bdesc_dst; 8457 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) 8458 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code); 8459 8460 /* Initialize the predicates. */ 8461 dp = (struct builtin_description_predicates *) bdesc_altivec_preds; 8462 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) 8463 { 8464 enum machine_mode mode1; 8465 tree type; 8466 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST 8467 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST; 8468 8469 if (is_overloaded) 8470 mode1 = VOIDmode; 8471 else 8472 mode1 = insn_data[dp->icode].operand[1].mode; 8473 8474 switch (mode1) 8475 { 8476 case VOIDmode: 8477 type = int_ftype_int_opaque_opaque; 8478 break; 8479 case V4SImode: 8480 type = int_ftype_int_v4si_v4si; 8481 break; 8482 case V8HImode: 8483 type = int_ftype_int_v8hi_v8hi; 8484 break; 8485 case V16QImode: 8486 type = int_ftype_int_v16qi_v16qi; 8487 break; 8488 case V4SFmode: 8489 type = int_ftype_int_v4sf_v4sf; 8490 break; 8491 default: 8492 gcc_unreachable (); 8493 } 8494 8495 def_builtin (dp->mask, dp->name, type, dp->code); 8496 } 8497 8498 /* Initialize the abs* operators. */ 8499 d = (struct builtin_description *) bdesc_abs; 8500 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) 8501 { 8502 enum machine_mode mode0; 8503 tree type; 8504 8505 mode0 = insn_data[d->icode].operand[0].mode; 8506 8507 switch (mode0) 8508 { 8509 case V4SImode: 8510 type = v4si_ftype_v4si; 8511 break; 8512 case V8HImode: 8513 type = v8hi_ftype_v8hi; 8514 break; 8515 case V16QImode: 8516 type = v16qi_ftype_v16qi; 8517 break; 8518 case V4SFmode: 8519 type = v4sf_ftype_v4sf; 8520 break; 8521 default: 8522 gcc_unreachable (); 8523 } 8524 8525 def_builtin (d->mask, d->name, type, d->code); 8526 } 8527 8528 if (TARGET_ALTIVEC) 8529 { 8530 tree decl; 8531 8532 /* Initialize target builtin that implements 8533 targetm.vectorize.builtin_mask_for_load. */ 8534 8535 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load", 8536 v16qi_ftype_long_pcvoid, 8537 ALTIVEC_BUILTIN_MASK_FOR_LOAD, 8538 BUILT_IN_MD, NULL, 8539 tree_cons (get_identifier ("const"), 8540 NULL_TREE, NULL_TREE)); 8541 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */ 8542 altivec_builtin_mask_for_load = decl; 8543 } 8544 8545 /* Access to the vec_init patterns. */ 8546 ftype = build_function_type_list (V4SI_type_node, integer_type_node, 8547 integer_type_node, integer_type_node, 8548 integer_type_node, NULL_TREE); 8549 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype, 8550 ALTIVEC_BUILTIN_VEC_INIT_V4SI); 8551 8552 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node, 8553 short_integer_type_node, 8554 short_integer_type_node, 8555 short_integer_type_node, 8556 short_integer_type_node, 8557 short_integer_type_node, 8558 short_integer_type_node, 8559 short_integer_type_node, NULL_TREE); 8560 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype, 8561 ALTIVEC_BUILTIN_VEC_INIT_V8HI); 8562 8563 ftype = build_function_type_list (V16QI_type_node, char_type_node, 8564 char_type_node, char_type_node, 8565 char_type_node, char_type_node, 8566 char_type_node, char_type_node, 8567 char_type_node, char_type_node, 8568 char_type_node, char_type_node, 8569 char_type_node, char_type_node, 8570 char_type_node, char_type_node, 8571 char_type_node, NULL_TREE); 8572 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype, 8573 ALTIVEC_BUILTIN_VEC_INIT_V16QI); 8574 8575 ftype = build_function_type_list (V4SF_type_node, float_type_node, 8576 float_type_node, float_type_node, 8577 float_type_node, NULL_TREE); 8578 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype, 8579 ALTIVEC_BUILTIN_VEC_INIT_V4SF); 8580 8581 /* Access to the vec_set patterns. */ 8582 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node, 8583 intSI_type_node, 8584 integer_type_node, NULL_TREE); 8585 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype, 8586 ALTIVEC_BUILTIN_VEC_SET_V4SI); 8587 8588 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node, 8589 intHI_type_node, 8590 integer_type_node, NULL_TREE); 8591 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype, 8592 ALTIVEC_BUILTIN_VEC_SET_V8HI); 8593 8594 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node, 8595 intQI_type_node, 8596 integer_type_node, NULL_TREE); 8597 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype, 8598 ALTIVEC_BUILTIN_VEC_SET_V16QI); 8599 8600 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node, 8601 float_type_node, 8602 integer_type_node, NULL_TREE); 8603 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype, 8604 ALTIVEC_BUILTIN_VEC_SET_V4SF); 8605 8606 /* Access to the vec_extract patterns. */ 8607 ftype = build_function_type_list (intSI_type_node, V4SI_type_node, 8608 integer_type_node, NULL_TREE); 8609 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype, 8610 ALTIVEC_BUILTIN_VEC_EXT_V4SI); 8611 8612 ftype = build_function_type_list (intHI_type_node, V8HI_type_node, 8613 integer_type_node, NULL_TREE); 8614 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype, 8615 ALTIVEC_BUILTIN_VEC_EXT_V8HI); 8616 8617 ftype = build_function_type_list (intQI_type_node, V16QI_type_node, 8618 integer_type_node, NULL_TREE); 8619 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype, 8620 ALTIVEC_BUILTIN_VEC_EXT_V16QI); 8621 8622 ftype = build_function_type_list (float_type_node, V4SF_type_node, 8623 integer_type_node, NULL_TREE); 8624 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype, 8625 ALTIVEC_BUILTIN_VEC_EXT_V4SF); 8626} 8627 8628static void 8629rs6000_common_init_builtins (void) 8630{ 8631 struct builtin_description *d; 8632 size_t i; 8633 8634 tree v4sf_ftype_v4sf_v4sf_v16qi 8635 = build_function_type_list (V4SF_type_node, 8636 V4SF_type_node, V4SF_type_node, 8637 V16QI_type_node, NULL_TREE); 8638 tree v4si_ftype_v4si_v4si_v16qi 8639 = build_function_type_list (V4SI_type_node, 8640 V4SI_type_node, V4SI_type_node, 8641 V16QI_type_node, NULL_TREE); 8642 tree v8hi_ftype_v8hi_v8hi_v16qi 8643 = build_function_type_list (V8HI_type_node, 8644 V8HI_type_node, V8HI_type_node, 8645 V16QI_type_node, NULL_TREE); 8646 tree v16qi_ftype_v16qi_v16qi_v16qi 8647 = build_function_type_list (V16QI_type_node, 8648 V16QI_type_node, V16QI_type_node, 8649 V16QI_type_node, NULL_TREE); 8650 tree v4si_ftype_int 8651 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE); 8652 tree v8hi_ftype_int 8653 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE); 8654 tree v16qi_ftype_int 8655 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE); 8656 tree v8hi_ftype_v16qi 8657 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE); 8658 tree v4sf_ftype_v4sf 8659 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); 8660 8661 tree v2si_ftype_v2si_v2si 8662 = build_function_type_list (opaque_V2SI_type_node, 8663 opaque_V2SI_type_node, 8664 opaque_V2SI_type_node, NULL_TREE); 8665 8666 tree v2sf_ftype_v2sf_v2sf 8667 = build_function_type_list (opaque_V2SF_type_node, 8668 opaque_V2SF_type_node, 8669 opaque_V2SF_type_node, NULL_TREE); 8670 8671 tree v2si_ftype_int_int 8672 = build_function_type_list (opaque_V2SI_type_node, 8673 integer_type_node, integer_type_node, 8674 NULL_TREE); 8675 8676 tree opaque_ftype_opaque 8677 = build_function_type_list (opaque_V4SI_type_node, 8678 opaque_V4SI_type_node, NULL_TREE); 8679 8680 tree v2si_ftype_v2si 8681 = build_function_type_list (opaque_V2SI_type_node, 8682 opaque_V2SI_type_node, NULL_TREE); 8683 8684 tree v2sf_ftype_v2sf 8685 = build_function_type_list (opaque_V2SF_type_node, 8686 opaque_V2SF_type_node, NULL_TREE); 8687 8688 tree v2sf_ftype_v2si 8689 = build_function_type_list (opaque_V2SF_type_node, 8690 opaque_V2SI_type_node, NULL_TREE); 8691 8692 tree v2si_ftype_v2sf 8693 = build_function_type_list (opaque_V2SI_type_node, 8694 opaque_V2SF_type_node, NULL_TREE); 8695 8696 tree v2si_ftype_v2si_char 8697 = build_function_type_list (opaque_V2SI_type_node, 8698 opaque_V2SI_type_node, 8699 char_type_node, NULL_TREE); 8700 8701 tree v2si_ftype_int_char 8702 = build_function_type_list (opaque_V2SI_type_node, 8703 integer_type_node, char_type_node, NULL_TREE); 8704 8705 tree v2si_ftype_char 8706 = build_function_type_list (opaque_V2SI_type_node, 8707 char_type_node, NULL_TREE); 8708 8709 tree int_ftype_int_int 8710 = build_function_type_list (integer_type_node, 8711 integer_type_node, integer_type_node, 8712 NULL_TREE); 8713 8714 tree opaque_ftype_opaque_opaque 8715 = build_function_type_list (opaque_V4SI_type_node, 8716 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE); 8717 tree v4si_ftype_v4si_v4si 8718 = build_function_type_list (V4SI_type_node, 8719 V4SI_type_node, V4SI_type_node, NULL_TREE); 8720 tree v4sf_ftype_v4si_int 8721 = build_function_type_list (V4SF_type_node, 8722 V4SI_type_node, integer_type_node, NULL_TREE); 8723 tree v4si_ftype_v4sf_int 8724 = build_function_type_list (V4SI_type_node, 8725 V4SF_type_node, integer_type_node, NULL_TREE); 8726 tree v4si_ftype_v4si_int 8727 = build_function_type_list (V4SI_type_node, 8728 V4SI_type_node, integer_type_node, NULL_TREE); 8729 tree v8hi_ftype_v8hi_int 8730 = build_function_type_list (V8HI_type_node, 8731 V8HI_type_node, integer_type_node, NULL_TREE); 8732 tree v16qi_ftype_v16qi_int 8733 = build_function_type_list (V16QI_type_node, 8734 V16QI_type_node, integer_type_node, NULL_TREE); 8735 tree v16qi_ftype_v16qi_v16qi_int 8736 = build_function_type_list (V16QI_type_node, 8737 V16QI_type_node, V16QI_type_node, 8738 integer_type_node, NULL_TREE); 8739 tree v8hi_ftype_v8hi_v8hi_int 8740 = build_function_type_list (V8HI_type_node, 8741 V8HI_type_node, V8HI_type_node, 8742 integer_type_node, NULL_TREE); 8743 tree v4si_ftype_v4si_v4si_int 8744 = build_function_type_list (V4SI_type_node, 8745 V4SI_type_node, V4SI_type_node, 8746 integer_type_node, NULL_TREE); 8747 tree v4sf_ftype_v4sf_v4sf_int 8748 = build_function_type_list (V4SF_type_node, 8749 V4SF_type_node, V4SF_type_node, 8750 integer_type_node, NULL_TREE); 8751 tree v4sf_ftype_v4sf_v4sf 8752 = build_function_type_list (V4SF_type_node, 8753 V4SF_type_node, V4SF_type_node, NULL_TREE); 8754 tree opaque_ftype_opaque_opaque_opaque 8755 = build_function_type_list (opaque_V4SI_type_node, 8756 opaque_V4SI_type_node, opaque_V4SI_type_node, 8757 opaque_V4SI_type_node, NULL_TREE); 8758 tree v4sf_ftype_v4sf_v4sf_v4si 8759 = build_function_type_list (V4SF_type_node, 8760 V4SF_type_node, V4SF_type_node, 8761 V4SI_type_node, NULL_TREE); 8762 tree v4sf_ftype_v4sf_v4sf_v4sf 8763 = build_function_type_list (V4SF_type_node, 8764 V4SF_type_node, V4SF_type_node, 8765 V4SF_type_node, NULL_TREE); 8766 tree v4si_ftype_v4si_v4si_v4si 8767 = build_function_type_list (V4SI_type_node, 8768 V4SI_type_node, V4SI_type_node, 8769 V4SI_type_node, NULL_TREE); 8770 tree v8hi_ftype_v8hi_v8hi 8771 = build_function_type_list (V8HI_type_node, 8772 V8HI_type_node, V8HI_type_node, NULL_TREE); 8773 tree v8hi_ftype_v8hi_v8hi_v8hi 8774 = build_function_type_list (V8HI_type_node, 8775 V8HI_type_node, V8HI_type_node, 8776 V8HI_type_node, NULL_TREE); 8777 tree v4si_ftype_v8hi_v8hi_v4si 8778 = build_function_type_list (V4SI_type_node, 8779 V8HI_type_node, V8HI_type_node, 8780 V4SI_type_node, NULL_TREE); 8781 tree v4si_ftype_v16qi_v16qi_v4si 8782 = build_function_type_list (V4SI_type_node, 8783 V16QI_type_node, V16QI_type_node, 8784 V4SI_type_node, NULL_TREE); 8785 tree v16qi_ftype_v16qi_v16qi 8786 = build_function_type_list (V16QI_type_node, 8787 V16QI_type_node, V16QI_type_node, NULL_TREE); 8788 tree v4si_ftype_v4sf_v4sf 8789 = build_function_type_list (V4SI_type_node, 8790 V4SF_type_node, V4SF_type_node, NULL_TREE); 8791 tree v8hi_ftype_v16qi_v16qi 8792 = build_function_type_list (V8HI_type_node, 8793 V16QI_type_node, V16QI_type_node, NULL_TREE); 8794 tree v4si_ftype_v8hi_v8hi 8795 = build_function_type_list (V4SI_type_node, 8796 V8HI_type_node, V8HI_type_node, NULL_TREE); 8797 tree v8hi_ftype_v4si_v4si 8798 = build_function_type_list (V8HI_type_node, 8799 V4SI_type_node, V4SI_type_node, NULL_TREE); 8800 tree v16qi_ftype_v8hi_v8hi 8801 = build_function_type_list (V16QI_type_node, 8802 V8HI_type_node, V8HI_type_node, NULL_TREE); 8803 tree v4si_ftype_v16qi_v4si 8804 = build_function_type_list (V4SI_type_node, 8805 V16QI_type_node, V4SI_type_node, NULL_TREE); 8806 tree v4si_ftype_v16qi_v16qi 8807 = build_function_type_list (V4SI_type_node, 8808 V16QI_type_node, V16QI_type_node, NULL_TREE); 8809 tree v4si_ftype_v8hi_v4si 8810 = build_function_type_list (V4SI_type_node, 8811 V8HI_type_node, V4SI_type_node, NULL_TREE); 8812 tree v4si_ftype_v8hi 8813 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE); 8814 tree int_ftype_v4si_v4si 8815 = build_function_type_list (integer_type_node, 8816 V4SI_type_node, V4SI_type_node, NULL_TREE); 8817 tree int_ftype_v4sf_v4sf 8818 = build_function_type_list (integer_type_node, 8819 V4SF_type_node, V4SF_type_node, NULL_TREE); 8820 tree int_ftype_v16qi_v16qi 8821 = build_function_type_list (integer_type_node, 8822 V16QI_type_node, V16QI_type_node, NULL_TREE); 8823 tree int_ftype_v8hi_v8hi 8824 = build_function_type_list (integer_type_node, 8825 V8HI_type_node, V8HI_type_node, NULL_TREE); 8826 8827 /* Add the simple ternary operators. */ 8828 d = (struct builtin_description *) bdesc_3arg; 8829 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) 8830 { 8831 enum machine_mode mode0, mode1, mode2, mode3; 8832 tree type; 8833 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST 8834 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST; 8835 8836 if (is_overloaded) 8837 { 8838 mode0 = VOIDmode; 8839 mode1 = VOIDmode; 8840 mode2 = VOIDmode; 8841 mode3 = VOIDmode; 8842 } 8843 else 8844 { 8845 if (d->name == 0 || d->icode == CODE_FOR_nothing) 8846 continue; 8847 8848 mode0 = insn_data[d->icode].operand[0].mode; 8849 mode1 = insn_data[d->icode].operand[1].mode; 8850 mode2 = insn_data[d->icode].operand[2].mode; 8851 mode3 = insn_data[d->icode].operand[3].mode; 8852 } 8853 8854 /* When all four are of the same mode. */ 8855 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3) 8856 { 8857 switch (mode0) 8858 { 8859 case VOIDmode: 8860 type = opaque_ftype_opaque_opaque_opaque; 8861 break; 8862 case V4SImode: 8863 type = v4si_ftype_v4si_v4si_v4si; 8864 break; 8865 case V4SFmode: 8866 type = v4sf_ftype_v4sf_v4sf_v4sf; 8867 break; 8868 case V8HImode: 8869 type = v8hi_ftype_v8hi_v8hi_v8hi; 8870 break; 8871 case V16QImode: 8872 type = v16qi_ftype_v16qi_v16qi_v16qi; 8873 break; 8874 default: 8875 gcc_unreachable (); 8876 } 8877 } 8878 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode) 8879 { 8880 switch (mode0) 8881 { 8882 case V4SImode: 8883 type = v4si_ftype_v4si_v4si_v16qi; 8884 break; 8885 case V4SFmode: 8886 type = v4sf_ftype_v4sf_v4sf_v16qi; 8887 break; 8888 case V8HImode: 8889 type = v8hi_ftype_v8hi_v8hi_v16qi; 8890 break; 8891 case V16QImode: 8892 type = v16qi_ftype_v16qi_v16qi_v16qi; 8893 break; 8894 default: 8895 gcc_unreachable (); 8896 } 8897 } 8898 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode 8899 && mode3 == V4SImode) 8900 type = v4si_ftype_v16qi_v16qi_v4si; 8901 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode 8902 && mode3 == V4SImode) 8903 type = v4si_ftype_v8hi_v8hi_v4si; 8904 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode 8905 && mode3 == V4SImode) 8906 type = v4sf_ftype_v4sf_v4sf_v4si; 8907 8908 /* vchar, vchar, vchar, 4 bit literal. */ 8909 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0 8910 && mode3 == QImode) 8911 type = v16qi_ftype_v16qi_v16qi_int; 8912 8913 /* vshort, vshort, vshort, 4 bit literal. */ 8914 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0 8915 && mode3 == QImode) 8916 type = v8hi_ftype_v8hi_v8hi_int; 8917 8918 /* vint, vint, vint, 4 bit literal. */ 8919 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0 8920 && mode3 == QImode) 8921 type = v4si_ftype_v4si_v4si_int; 8922 8923 /* vfloat, vfloat, vfloat, 4 bit literal. */ 8924 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0 8925 && mode3 == QImode) 8926 type = v4sf_ftype_v4sf_v4sf_int; 8927 8928 else 8929 gcc_unreachable (); 8930 8931 def_builtin (d->mask, d->name, type, d->code); 8932 } 8933 8934 /* Add the simple binary operators. */ 8935 d = (struct builtin_description *) bdesc_2arg; 8936 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) 8937 { 8938 enum machine_mode mode0, mode1, mode2; 8939 tree type; 8940 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST 8941 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST; 8942 8943 if (is_overloaded) 8944 { 8945 mode0 = VOIDmode; 8946 mode1 = VOIDmode; 8947 mode2 = VOIDmode; 8948 } 8949 else 8950 { 8951 if (d->name == 0 || d->icode == CODE_FOR_nothing) 8952 continue; 8953 8954 mode0 = insn_data[d->icode].operand[0].mode; 8955 mode1 = insn_data[d->icode].operand[1].mode; 8956 mode2 = insn_data[d->icode].operand[2].mode; 8957 } 8958 8959 /* When all three operands are of the same mode. */ 8960 if (mode0 == mode1 && mode1 == mode2) 8961 { 8962 switch (mode0) 8963 { 8964 case VOIDmode: 8965 type = opaque_ftype_opaque_opaque; 8966 break; 8967 case V4SFmode: 8968 type = v4sf_ftype_v4sf_v4sf; 8969 break; 8970 case V4SImode: 8971 type = v4si_ftype_v4si_v4si; 8972 break; 8973 case V16QImode: 8974 type = v16qi_ftype_v16qi_v16qi; 8975 break; 8976 case V8HImode: 8977 type = v8hi_ftype_v8hi_v8hi; 8978 break; 8979 case V2SImode: 8980 type = v2si_ftype_v2si_v2si; 8981 break; 8982 case V2SFmode: 8983 type = v2sf_ftype_v2sf_v2sf; 8984 break; 8985 case SImode: 8986 type = int_ftype_int_int; 8987 break; 8988 default: 8989 gcc_unreachable (); 8990 } 8991 } 8992 8993 /* A few other combos we really don't want to do manually. */ 8994 8995 /* vint, vfloat, vfloat. */ 8996 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode) 8997 type = v4si_ftype_v4sf_v4sf; 8998 8999 /* vshort, vchar, vchar. */ 9000 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode) 9001 type = v8hi_ftype_v16qi_v16qi; 9002 9003 /* vint, vshort, vshort. */ 9004 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode) 9005 type = v4si_ftype_v8hi_v8hi; 9006 9007 /* vshort, vint, vint. */ 9008 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode) 9009 type = v8hi_ftype_v4si_v4si; 9010 9011 /* vchar, vshort, vshort. */ 9012 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode) 9013 type = v16qi_ftype_v8hi_v8hi; 9014 9015 /* vint, vchar, vint. */ 9016 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode) 9017 type = v4si_ftype_v16qi_v4si; 9018 9019 /* vint, vchar, vchar. */ 9020 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode) 9021 type = v4si_ftype_v16qi_v16qi; 9022 9023 /* vint, vshort, vint. */ 9024 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) 9025 type = v4si_ftype_v8hi_v4si; 9026 9027 /* vint, vint, 5 bit literal. */ 9028 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode) 9029 type = v4si_ftype_v4si_int; 9030 9031 /* vshort, vshort, 5 bit literal. */ 9032 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode) 9033 type = v8hi_ftype_v8hi_int; 9034 9035 /* vchar, vchar, 5 bit literal. */ 9036 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode) 9037 type = v16qi_ftype_v16qi_int; 9038 9039 /* vfloat, vint, 5 bit literal. */ 9040 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode) 9041 type = v4sf_ftype_v4si_int; 9042 9043 /* vint, vfloat, 5 bit literal. */ 9044 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) 9045 type = v4si_ftype_v4sf_int; 9046 9047 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode) 9048 type = v2si_ftype_int_int; 9049 9050 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode) 9051 type = v2si_ftype_v2si_char; 9052 9053 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode) 9054 type = v2si_ftype_int_char; 9055 9056 else 9057 { 9058 /* int, x, x. */ 9059 gcc_assert (mode0 == SImode); 9060 switch (mode1) 9061 { 9062 case V4SImode: 9063 type = int_ftype_v4si_v4si; 9064 break; 9065 case V4SFmode: 9066 type = int_ftype_v4sf_v4sf; 9067 break; 9068 case V16QImode: 9069 type = int_ftype_v16qi_v16qi; 9070 break; 9071 case V8HImode: 9072 type = int_ftype_v8hi_v8hi; 9073 break; 9074 default: 9075 gcc_unreachable (); 9076 } 9077 } 9078 9079 def_builtin (d->mask, d->name, type, d->code); 9080 } 9081 9082 /* Add the simple unary operators. */ 9083 d = (struct builtin_description *) bdesc_1arg; 9084 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) 9085 { 9086 enum machine_mode mode0, mode1; 9087 tree type; 9088 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST 9089 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST; 9090 9091 if (is_overloaded) 9092 { 9093 mode0 = VOIDmode; 9094 mode1 = VOIDmode; 9095 } 9096 else 9097 { 9098 if (d->name == 0 || d->icode == CODE_FOR_nothing) 9099 continue; 9100 9101 mode0 = insn_data[d->icode].operand[0].mode; 9102 mode1 = insn_data[d->icode].operand[1].mode; 9103 } 9104 9105 if (mode0 == V4SImode && mode1 == QImode) 9106 type = v4si_ftype_int; 9107 else if (mode0 == V8HImode && mode1 == QImode) 9108 type = v8hi_ftype_int; 9109 else if (mode0 == V16QImode && mode1 == QImode) 9110 type = v16qi_ftype_int; 9111 else if (mode0 == VOIDmode && mode1 == VOIDmode) 9112 type = opaque_ftype_opaque; 9113 else if (mode0 == V4SFmode && mode1 == V4SFmode) 9114 type = v4sf_ftype_v4sf; 9115 else if (mode0 == V8HImode && mode1 == V16QImode) 9116 type = v8hi_ftype_v16qi; 9117 else if (mode0 == V4SImode && mode1 == V8HImode) 9118 type = v4si_ftype_v8hi; 9119 else if (mode0 == V2SImode && mode1 == V2SImode) 9120 type = v2si_ftype_v2si; 9121 else if (mode0 == V2SFmode && mode1 == V2SFmode) 9122 type = v2sf_ftype_v2sf; 9123 else if (mode0 == V2SFmode && mode1 == V2SImode) 9124 type = v2sf_ftype_v2si; 9125 else if (mode0 == V2SImode && mode1 == V2SFmode) 9126 type = v2si_ftype_v2sf; 9127 else if (mode0 == V2SImode && mode1 == QImode) 9128 type = v2si_ftype_char; 9129 else 9130 gcc_unreachable (); 9131 9132 def_builtin (d->mask, d->name, type, d->code); 9133 } 9134} 9135 9136static void 9137rs6000_init_libfuncs (void) 9138{ 9139 if (!TARGET_HARD_FLOAT) 9140 return; 9141 9142 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF 9143 && !TARGET_POWER2 && !TARGET_POWERPC) 9144 { 9145 /* AIX library routines for float->int conversion. */ 9146 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc"); 9147 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc"); 9148 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc"); 9149 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc"); 9150 } 9151 9152 if (!TARGET_IEEEQUAD) 9153 /* AIX/Darwin/64-bit Linux quad floating point routines. */ 9154 if (!TARGET_XL_COMPAT) 9155 { 9156 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd"); 9157 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub"); 9158 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul"); 9159 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv"); 9160 } 9161 else 9162 { 9163 set_optab_libfunc (add_optab, TFmode, "_xlqadd"); 9164 set_optab_libfunc (sub_optab, TFmode, "_xlqsub"); 9165 set_optab_libfunc (smul_optab, TFmode, "_xlqmul"); 9166 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv"); 9167 } 9168 else 9169 { 9170 /* 32-bit SVR4 quad floating point routines. */ 9171 9172 set_optab_libfunc (add_optab, TFmode, "_q_add"); 9173 set_optab_libfunc (sub_optab, TFmode, "_q_sub"); 9174 set_optab_libfunc (neg_optab, TFmode, "_q_neg"); 9175 set_optab_libfunc (smul_optab, TFmode, "_q_mul"); 9176 set_optab_libfunc (sdiv_optab, TFmode, "_q_div"); 9177 if (TARGET_PPC_GPOPT || TARGET_POWER2) 9178 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt"); 9179 9180 set_optab_libfunc (eq_optab, TFmode, "_q_feq"); 9181 set_optab_libfunc (ne_optab, TFmode, "_q_fne"); 9182 set_optab_libfunc (gt_optab, TFmode, "_q_fgt"); 9183 set_optab_libfunc (ge_optab, TFmode, "_q_fge"); 9184 set_optab_libfunc (lt_optab, TFmode, "_q_flt"); 9185 set_optab_libfunc (le_optab, TFmode, "_q_fle"); 9186 9187 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq"); 9188 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq"); 9189 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos"); 9190 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod"); 9191 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi"); 9192 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou"); 9193 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq"); 9194 } 9195} 9196 9197 9198/* Expand a block clear operation, and return 1 if successful. Return 0 9199 if we should let the compiler generate normal code. 9200 9201 operands[0] is the destination 9202 operands[1] is the length 9203 operands[3] is the alignment */ 9204 9205int 9206expand_block_clear (rtx operands[]) 9207{ 9208 rtx orig_dest = operands[0]; 9209 rtx bytes_rtx = operands[1]; 9210 rtx align_rtx = operands[3]; 9211 bool constp = (GET_CODE (bytes_rtx) == CONST_INT); 9212 HOST_WIDE_INT align; 9213 HOST_WIDE_INT bytes; 9214 int offset; 9215 int clear_bytes; 9216 int clear_step; 9217 9218 /* If this is not a fixed size move, just call memcpy */ 9219 if (! constp) 9220 return 0; 9221 9222 /* This must be a fixed size alignment */ 9223 gcc_assert (GET_CODE (align_rtx) == CONST_INT); 9224 align = INTVAL (align_rtx) * BITS_PER_UNIT; 9225 9226 /* Anything to clear? */ 9227 bytes = INTVAL (bytes_rtx); 9228 if (bytes <= 0) 9229 return 1; 9230 9231 /* Use the builtin memset after a point, to avoid huge code bloat. 9232 When optimize_size, avoid any significant code bloat; calling 9233 memset is about 4 instructions, so allow for one instruction to 9234 load zero and three to do clearing. */ 9235 if (TARGET_ALTIVEC && align >= 128) 9236 clear_step = 16; 9237 else if (TARGET_POWERPC64 && align >= 32) 9238 clear_step = 8; 9239 else 9240 clear_step = 4; 9241 9242 if (optimize_size && bytes > 3 * clear_step) 9243 return 0; 9244 if (! optimize_size && bytes > 8 * clear_step) 9245 return 0; 9246 9247 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes) 9248 { 9249 enum machine_mode mode = BLKmode; 9250 rtx dest; 9251 9252 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128) 9253 { 9254 clear_bytes = 16; 9255 mode = V4SImode; 9256 } 9257 else if (bytes >= 8 && TARGET_POWERPC64 9258 /* 64-bit loads and stores require word-aligned 9259 displacements. */ 9260 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32))) 9261 { 9262 clear_bytes = 8; 9263 mode = DImode; 9264 } 9265 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) 9266 { /* move 4 bytes */ 9267 clear_bytes = 4; 9268 mode = SImode; 9269 } 9270 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT)) 9271 { /* move 2 bytes */ 9272 clear_bytes = 2; 9273 mode = HImode; 9274 } 9275 else /* move 1 byte at a time */ 9276 { 9277 clear_bytes = 1; 9278 mode = QImode; 9279 } 9280 9281 dest = adjust_address (orig_dest, mode, offset); 9282 9283 emit_move_insn (dest, CONST0_RTX (mode)); 9284 } 9285 9286 return 1; 9287} 9288 9289 9290/* Expand a block move operation, and return 1 if successful. Return 0 9291 if we should let the compiler generate normal code. 9292 9293 operands[0] is the destination 9294 operands[1] is the source 9295 operands[2] is the length 9296 operands[3] is the alignment */ 9297 9298#define MAX_MOVE_REG 4 9299 9300int 9301expand_block_move (rtx operands[]) 9302{ 9303 rtx orig_dest = operands[0]; 9304 rtx orig_src = operands[1]; 9305 rtx bytes_rtx = operands[2]; 9306 rtx align_rtx = operands[3]; 9307 int constp = (GET_CODE (bytes_rtx) == CONST_INT); 9308 int align; 9309 int bytes; 9310 int offset; 9311 int move_bytes; 9312 rtx stores[MAX_MOVE_REG]; 9313 int num_reg = 0; 9314 9315 /* If this is not a fixed size move, just call memcpy */ 9316 if (! constp) 9317 return 0; 9318 9319 /* This must be a fixed size alignment */ 9320 gcc_assert (GET_CODE (align_rtx) == CONST_INT); 9321 align = INTVAL (align_rtx) * BITS_PER_UNIT; 9322 9323 /* Anything to move? */ 9324 bytes = INTVAL (bytes_rtx); 9325 if (bytes <= 0) 9326 return 1; 9327 9328 /* store_one_arg depends on expand_block_move to handle at least the size of 9329 reg_parm_stack_space. */ 9330 if (bytes > (TARGET_POWERPC64 ? 64 : 32)) 9331 return 0; 9332 9333 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) 9334 { 9335 union { 9336 rtx (*movmemsi) (rtx, rtx, rtx, rtx); 9337 rtx (*mov) (rtx, rtx); 9338 } gen_func; 9339 enum machine_mode mode = BLKmode; 9340 rtx src, dest; 9341 9342 /* Altivec first, since it will be faster than a string move 9343 when it applies, and usually not significantly larger. */ 9344 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128) 9345 { 9346 move_bytes = 16; 9347 mode = V4SImode; 9348 gen_func.mov = gen_movv4si; 9349 } 9350 else if (TARGET_STRING 9351 && bytes > 24 /* move up to 32 bytes at a time */ 9352 && ! fixed_regs[5] 9353 && ! fixed_regs[6] 9354 && ! fixed_regs[7] 9355 && ! fixed_regs[8] 9356 && ! fixed_regs[9] 9357 && ! fixed_regs[10] 9358 && ! fixed_regs[11] 9359 && ! fixed_regs[12]) 9360 { 9361 move_bytes = (bytes > 32) ? 32 : bytes; 9362 gen_func.movmemsi = gen_movmemsi_8reg; 9363 } 9364 else if (TARGET_STRING 9365 && bytes > 16 /* move up to 24 bytes at a time */ 9366 && ! fixed_regs[5] 9367 && ! fixed_regs[6] 9368 && ! fixed_regs[7] 9369 && ! fixed_regs[8] 9370 && ! fixed_regs[9] 9371 && ! fixed_regs[10]) 9372 { 9373 move_bytes = (bytes > 24) ? 24 : bytes; 9374 gen_func.movmemsi = gen_movmemsi_6reg; 9375 } 9376 else if (TARGET_STRING 9377 && bytes > 8 /* move up to 16 bytes at a time */ 9378 && ! fixed_regs[5] 9379 && ! fixed_regs[6] 9380 && ! fixed_regs[7] 9381 && ! fixed_regs[8]) 9382 { 9383 move_bytes = (bytes > 16) ? 16 : bytes; 9384 gen_func.movmemsi = gen_movmemsi_4reg; 9385 } 9386 else if (bytes >= 8 && TARGET_POWERPC64 9387 /* 64-bit loads and stores require word-aligned 9388 displacements. */ 9389 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32))) 9390 { 9391 move_bytes = 8; 9392 mode = DImode; 9393 gen_func.mov = gen_movdi; 9394 } 9395 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64) 9396 { /* move up to 8 bytes at a time */ 9397 move_bytes = (bytes > 8) ? 8 : bytes; 9398 gen_func.movmemsi = gen_movmemsi_2reg; 9399 } 9400 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) 9401 { /* move 4 bytes */ 9402 move_bytes = 4; 9403 mode = SImode; 9404 gen_func.mov = gen_movsi; 9405 } 9406 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT)) 9407 { /* move 2 bytes */ 9408 move_bytes = 2; 9409 mode = HImode; 9410 gen_func.mov = gen_movhi; 9411 } 9412 else if (TARGET_STRING && bytes > 1) 9413 { /* move up to 4 bytes at a time */ 9414 move_bytes = (bytes > 4) ? 4 : bytes; 9415 gen_func.movmemsi = gen_movmemsi_1reg; 9416 } 9417 else /* move 1 byte at a time */ 9418 { 9419 move_bytes = 1; 9420 mode = QImode; 9421 gen_func.mov = gen_movqi; 9422 } 9423 9424 src = adjust_address (orig_src, mode, offset); 9425 dest = adjust_address (orig_dest, mode, offset); 9426 9427 if (mode != BLKmode) 9428 { 9429 rtx tmp_reg = gen_reg_rtx (mode); 9430 9431 emit_insn ((*gen_func.mov) (tmp_reg, src)); 9432 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg); 9433 } 9434 9435 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes) 9436 { 9437 int i; 9438 for (i = 0; i < num_reg; i++) 9439 emit_insn (stores[i]); 9440 num_reg = 0; 9441 } 9442 9443 if (mode == BLKmode) 9444 { 9445 /* Move the address into scratch registers. The movmemsi 9446 patterns require zero offset. */ 9447 if (!REG_P (XEXP (src, 0))) 9448 { 9449 rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); 9450 src = replace_equiv_address (src, src_reg); 9451 } 9452 set_mem_size (src, GEN_INT (move_bytes)); 9453 9454 if (!REG_P (XEXP (dest, 0))) 9455 { 9456 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0)); 9457 dest = replace_equiv_address (dest, dest_reg); 9458 } 9459 set_mem_size (dest, GEN_INT (move_bytes)); 9460 9461 emit_insn ((*gen_func.movmemsi) (dest, src, 9462 GEN_INT (move_bytes & 31), 9463 align_rtx)); 9464 } 9465 } 9466 9467 return 1; 9468} 9469 9470 9471/* Return a string to perform a load_multiple operation. 9472 operands[0] is the vector. 9473 operands[1] is the source address. 9474 operands[2] is the first destination register. */ 9475 9476const char * 9477rs6000_output_load_multiple (rtx operands[3]) 9478{ 9479 /* We have to handle the case where the pseudo used to contain the address 9480 is assigned to one of the output registers. */ 9481 int i, j; 9482 int words = XVECLEN (operands[0], 0); 9483 rtx xop[10]; 9484 9485 if (XVECLEN (operands[0], 0) == 1) 9486 return "{l|lwz} %2,0(%1)"; 9487 9488 for (i = 0; i < words; i++) 9489 if (refers_to_regno_p (REGNO (operands[2]) + i, 9490 REGNO (operands[2]) + i + 1, operands[1], 0)) 9491 { 9492 if (i == words-1) 9493 { 9494 xop[0] = GEN_INT (4 * (words-1)); 9495 xop[1] = operands[1]; 9496 xop[2] = operands[2]; 9497 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop); 9498 return ""; 9499 } 9500 else if (i == 0) 9501 { 9502 xop[0] = GEN_INT (4 * (words-1)); 9503 xop[1] = operands[1]; 9504 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); 9505 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop); 9506 return ""; 9507 } 9508 else 9509 { 9510 for (j = 0; j < words; j++) 9511 if (j != i) 9512 { 9513 xop[0] = GEN_INT (j * 4); 9514 xop[1] = operands[1]; 9515 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j); 9516 output_asm_insn ("{l|lwz} %2,%0(%1)", xop); 9517 } 9518 xop[0] = GEN_INT (i * 4); 9519 xop[1] = operands[1]; 9520 output_asm_insn ("{l|lwz} %1,%0(%1)", xop); 9521 return ""; 9522 } 9523 } 9524 9525 return "{lsi|lswi} %2,%1,%N0"; 9526} 9527 9528 9529/* A validation routine: say whether CODE, a condition code, and MODE 9530 match. The other alternatives either don't make sense or should 9531 never be generated. */ 9532 9533void 9534validate_condition_mode (enum rtx_code code, enum machine_mode mode) 9535{ 9536 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE 9537 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE) 9538 && GET_MODE_CLASS (mode) == MODE_CC); 9539 9540 /* These don't make sense. */ 9541 gcc_assert ((code != GT && code != LT && code != GE && code != LE) 9542 || mode != CCUNSmode); 9543 9544 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU) 9545 || mode == CCUNSmode); 9546 9547 gcc_assert (mode == CCFPmode 9548 || (code != ORDERED && code != UNORDERED 9549 && code != UNEQ && code != LTGT 9550 && code != UNGT && code != UNLT 9551 && code != UNGE && code != UNLE)); 9552 9553 /* These should never be generated except for 9554 flag_finite_math_only. */ 9555 gcc_assert (mode != CCFPmode 9556 || flag_finite_math_only 9557 || (code != LE && code != GE 9558 && code != UNEQ && code != LTGT 9559 && code != UNGT && code != UNLT)); 9560 9561 /* These are invalid; the information is not there. */ 9562 gcc_assert (mode != CCEQmode || code == EQ || code == NE); 9563} 9564 9565 9566/* Return 1 if ANDOP is a mask that has no bits on that are not in the 9567 mask required to convert the result of a rotate insn into a shift 9568 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */ 9569 9570int 9571includes_lshift_p (rtx shiftop, rtx andop) 9572{ 9573 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; 9574 9575 shift_mask <<= INTVAL (shiftop); 9576 9577 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; 9578} 9579 9580/* Similar, but for right shift. */ 9581 9582int 9583includes_rshift_p (rtx shiftop, rtx andop) 9584{ 9585 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; 9586 9587 shift_mask >>= INTVAL (shiftop); 9588 9589 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; 9590} 9591 9592/* Return 1 if ANDOP is a mask suitable for use with an rldic insn 9593 to perform a left shift. It must have exactly SHIFTOP least 9594 significant 0's, then one or more 1's, then zero or more 0's. */ 9595 9596int 9597includes_rldic_lshift_p (rtx shiftop, rtx andop) 9598{ 9599 if (GET_CODE (andop) == CONST_INT) 9600 { 9601 HOST_WIDE_INT c, lsb, shift_mask; 9602 9603 c = INTVAL (andop); 9604 if (c == 0 || c == ~0) 9605 return 0; 9606 9607 shift_mask = ~0; 9608 shift_mask <<= INTVAL (shiftop); 9609 9610 /* Find the least significant one bit. */ 9611 lsb = c & -c; 9612 9613 /* It must coincide with the LSB of the shift mask. */ 9614 if (-lsb != shift_mask) 9615 return 0; 9616 9617 /* Invert to look for the next transition (if any). */ 9618 c = ~c; 9619 9620 /* Remove the low group of ones (originally low group of zeros). */ 9621 c &= -lsb; 9622 9623 /* Again find the lsb, and check we have all 1's above. */ 9624 lsb = c & -c; 9625 return c == -lsb; 9626 } 9627 else if (GET_CODE (andop) == CONST_DOUBLE 9628 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) 9629 { 9630 HOST_WIDE_INT low, high, lsb; 9631 HOST_WIDE_INT shift_mask_low, shift_mask_high; 9632 9633 low = CONST_DOUBLE_LOW (andop); 9634 if (HOST_BITS_PER_WIDE_INT < 64) 9635 high = CONST_DOUBLE_HIGH (andop); 9636 9637 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) 9638 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) 9639 return 0; 9640 9641 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) 9642 { 9643 shift_mask_high = ~0; 9644 if (INTVAL (shiftop) > 32) 9645 shift_mask_high <<= INTVAL (shiftop) - 32; 9646 9647 lsb = high & -high; 9648 9649 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) 9650 return 0; 9651 9652 high = ~high; 9653 high &= -lsb; 9654 9655 lsb = high & -high; 9656 return high == -lsb; 9657 } 9658 9659 shift_mask_low = ~0; 9660 shift_mask_low <<= INTVAL (shiftop); 9661 9662 lsb = low & -low; 9663 9664 if (-lsb != shift_mask_low) 9665 return 0; 9666 9667 if (HOST_BITS_PER_WIDE_INT < 64) 9668 high = ~high; 9669 low = ~low; 9670 low &= -lsb; 9671 9672 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) 9673 { 9674 lsb = high & -high; 9675 return high == -lsb; 9676 } 9677 9678 lsb = low & -low; 9679 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); 9680 } 9681 else 9682 return 0; 9683} 9684 9685/* Return 1 if ANDOP is a mask suitable for use with an rldicr insn 9686 to perform a left shift. It must have SHIFTOP or more least 9687 significant 0's, with the remainder of the word 1's. */ 9688 9689int 9690includes_rldicr_lshift_p (rtx shiftop, rtx andop) 9691{ 9692 if (GET_CODE (andop) == CONST_INT) 9693 { 9694 HOST_WIDE_INT c, lsb, shift_mask; 9695 9696 shift_mask = ~0; 9697 shift_mask <<= INTVAL (shiftop); 9698 c = INTVAL (andop); 9699 9700 /* Find the least significant one bit. */ 9701 lsb = c & -c; 9702 9703 /* It must be covered by the shift mask. 9704 This test also rejects c == 0. */ 9705 if ((lsb & shift_mask) == 0) 9706 return 0; 9707 9708 /* Check we have all 1's above the transition, and reject all 1's. */ 9709 return c == -lsb && lsb != 1; 9710 } 9711 else if (GET_CODE (andop) == CONST_DOUBLE 9712 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) 9713 { 9714 HOST_WIDE_INT low, lsb, shift_mask_low; 9715 9716 low = CONST_DOUBLE_LOW (andop); 9717 9718 if (HOST_BITS_PER_WIDE_INT < 64) 9719 { 9720 HOST_WIDE_INT high, shift_mask_high; 9721 9722 high = CONST_DOUBLE_HIGH (andop); 9723 9724 if (low == 0) 9725 { 9726 shift_mask_high = ~0; 9727 if (INTVAL (shiftop) > 32) 9728 shift_mask_high <<= INTVAL (shiftop) - 32; 9729 9730 lsb = high & -high; 9731 9732 if ((lsb & shift_mask_high) == 0) 9733 return 0; 9734 9735 return high == -lsb; 9736 } 9737 if (high != ~0) 9738 return 0; 9739 } 9740 9741 shift_mask_low = ~0; 9742 shift_mask_low <<= INTVAL (shiftop); 9743 9744 lsb = low & -low; 9745 9746 if ((lsb & shift_mask_low) == 0) 9747 return 0; 9748 9749 return low == -lsb && lsb != 1; 9750 } 9751 else 9752 return 0; 9753} 9754 9755/* Return 1 if operands will generate a valid arguments to rlwimi 9756instruction for insert with right shift in 64-bit mode. The mask may 9757not start on the first bit or stop on the last bit because wrap-around 9758effects of instruction do not correspond to semantics of RTL insn. */ 9759 9760int 9761insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop) 9762{ 9763 if (INTVAL (startop) > 32 9764 && INTVAL (startop) < 64 9765 && INTVAL (sizeop) > 1 9766 && INTVAL (sizeop) + INTVAL (startop) < 64 9767 && INTVAL (shiftop) > 0 9768 && INTVAL (sizeop) + INTVAL (shiftop) < 32 9769 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop)) 9770 return 1; 9771 9772 return 0; 9773} 9774 9775/* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates 9776 for lfq and stfq insns iff the registers are hard registers. */ 9777 9778int 9779registers_ok_for_quad_peep (rtx reg1, rtx reg2) 9780{ 9781 /* We might have been passed a SUBREG. */ 9782 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) 9783 return 0; 9784 9785 /* We might have been passed non floating point registers. */ 9786 if (!FP_REGNO_P (REGNO (reg1)) 9787 || !FP_REGNO_P (REGNO (reg2))) 9788 return 0; 9789 9790 return (REGNO (reg1) == REGNO (reg2) - 1); 9791} 9792 9793/* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. 9794 addr1 and addr2 must be in consecutive memory locations 9795 (addr2 == addr1 + 8). */ 9796 9797int 9798mems_ok_for_quad_peep (rtx mem1, rtx mem2) 9799{ 9800 rtx addr1, addr2; 9801 unsigned int reg1, reg2; 9802 int offset1, offset2; 9803 9804 /* The mems cannot be volatile. */ 9805 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) 9806 return 0; 9807 9808 addr1 = XEXP (mem1, 0); 9809 addr2 = XEXP (mem2, 0); 9810 9811 /* Extract an offset (if used) from the first addr. */ 9812 if (GET_CODE (addr1) == PLUS) 9813 { 9814 /* If not a REG, return zero. */ 9815 if (GET_CODE (XEXP (addr1, 0)) != REG) 9816 return 0; 9817 else 9818 { 9819 reg1 = REGNO (XEXP (addr1, 0)); 9820 /* The offset must be constant! */ 9821 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) 9822 return 0; 9823 offset1 = INTVAL (XEXP (addr1, 1)); 9824 } 9825 } 9826 else if (GET_CODE (addr1) != REG) 9827 return 0; 9828 else 9829 { 9830 reg1 = REGNO (addr1); 9831 /* This was a simple (mem (reg)) expression. Offset is 0. */ 9832 offset1 = 0; 9833 } 9834 9835 /* And now for the second addr. */ 9836 if (GET_CODE (addr2) == PLUS) 9837 { 9838 /* If not a REG, return zero. */ 9839 if (GET_CODE (XEXP (addr2, 0)) != REG) 9840 return 0; 9841 else 9842 { 9843 reg2 = REGNO (XEXP (addr2, 0)); 9844 /* The offset must be constant. */ 9845 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT) 9846 return 0; 9847 offset2 = INTVAL (XEXP (addr2, 1)); 9848 } 9849 } 9850 else if (GET_CODE (addr2) != REG) 9851 return 0; 9852 else 9853 { 9854 reg2 = REGNO (addr2); 9855 /* This was a simple (mem (reg)) expression. Offset is 0. */ 9856 offset2 = 0; 9857 } 9858 9859 /* Both of these must have the same base register. */ 9860 if (reg1 != reg2) 9861 return 0; 9862 9863 /* The offset for the second addr must be 8 more than the first addr. */ 9864 if (offset2 != offset1 + 8) 9865 return 0; 9866 9867 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq 9868 instructions. */ 9869 return 1; 9870} 9871 9872/* Return the register class of a scratch register needed to copy IN into 9873 or out of a register in CLASS in MODE. If it can be done directly, 9874 NO_REGS is returned. */ 9875 9876enum reg_class 9877secondary_reload_class (enum reg_class class, 9878 enum machine_mode mode ATTRIBUTE_UNUSED, 9879 rtx in) 9880{ 9881 int regno; 9882 9883 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN 9884#if TARGET_MACHO 9885 && MACHOPIC_INDIRECT 9886#endif 9887 )) 9888 { 9889 /* We cannot copy a symbolic operand directly into anything 9890 other than BASE_REGS for TARGET_ELF. So indicate that a 9891 register from BASE_REGS is needed as an intermediate 9892 register. 9893 9894 On Darwin, pic addresses require a load from memory, which 9895 needs a base register. */ 9896 if (class != BASE_REGS 9897 && (GET_CODE (in) == SYMBOL_REF 9898 || GET_CODE (in) == HIGH 9899 || GET_CODE (in) == LABEL_REF 9900 || GET_CODE (in) == CONST)) 9901 return BASE_REGS; 9902 } 9903 9904 if (GET_CODE (in) == REG) 9905 { 9906 regno = REGNO (in); 9907 if (regno >= FIRST_PSEUDO_REGISTER) 9908 { 9909 regno = true_regnum (in); 9910 if (regno >= FIRST_PSEUDO_REGISTER) 9911 regno = -1; 9912 } 9913 } 9914 else if (GET_CODE (in) == SUBREG) 9915 { 9916 regno = true_regnum (in); 9917 if (regno >= FIRST_PSEUDO_REGISTER) 9918 regno = -1; 9919 } 9920 else 9921 regno = -1; 9922 9923 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS 9924 into anything. */ 9925 if (class == GENERAL_REGS || class == BASE_REGS 9926 || (regno >= 0 && INT_REGNO_P (regno))) 9927 return NO_REGS; 9928 9929 /* Constants, memory, and FP registers can go into FP registers. */ 9930 if ((regno == -1 || FP_REGNO_P (regno)) 9931 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) 9932 return NO_REGS; 9933 9934 /* Memory, and AltiVec registers can go into AltiVec registers. */ 9935 if ((regno == -1 || ALTIVEC_REGNO_P (regno)) 9936 && class == ALTIVEC_REGS) 9937 return NO_REGS; 9938 9939 /* We can copy among the CR registers. */ 9940 if ((class == CR_REGS || class == CR0_REGS) 9941 && regno >= 0 && CR_REGNO_P (regno)) 9942 return NO_REGS; 9943 9944 /* Otherwise, we need GENERAL_REGS. */ 9945 return GENERAL_REGS; 9946} 9947 9948/* Given a comparison operation, return the bit number in CCR to test. We 9949 know this is a valid comparison. 9950 9951 SCC_P is 1 if this is for an scc. That means that %D will have been 9952 used instead of %C, so the bits will be in different places. 9953 9954 Return -1 if OP isn't a valid comparison for some reason. */ 9955 9956int 9957ccr_bit (rtx op, int scc_p) 9958{ 9959 enum rtx_code code = GET_CODE (op); 9960 enum machine_mode cc_mode; 9961 int cc_regnum; 9962 int base_bit; 9963 rtx reg; 9964 9965 if (!COMPARISON_P (op)) 9966 return -1; 9967 9968 reg = XEXP (op, 0); 9969 9970 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg))); 9971 9972 cc_mode = GET_MODE (reg); 9973 cc_regnum = REGNO (reg); 9974 base_bit = 4 * (cc_regnum - CR0_REGNO); 9975 9976 validate_condition_mode (code, cc_mode); 9977 9978 /* When generating a sCOND operation, only positive conditions are 9979 allowed. */ 9980 gcc_assert (!scc_p 9981 || code == EQ || code == GT || code == LT || code == UNORDERED 9982 || code == GTU || code == LTU); 9983 9984 switch (code) 9985 { 9986 case NE: 9987 return scc_p ? base_bit + 3 : base_bit + 2; 9988 case EQ: 9989 return base_bit + 2; 9990 case GT: case GTU: case UNLE: 9991 return base_bit + 1; 9992 case LT: case LTU: case UNGE: 9993 return base_bit; 9994 case ORDERED: case UNORDERED: 9995 return base_bit + 3; 9996 9997 case GE: case GEU: 9998 /* If scc, we will have done a cror to put the bit in the 9999 unordered position. So test that bit. For integer, this is ! LT 10000 unless this is an scc insn. */ 10001 return scc_p ? base_bit + 3 : base_bit; 10002 10003 case LE: case LEU: 10004 return scc_p ? base_bit + 3 : base_bit + 1; 10005 10006 default: 10007 gcc_unreachable (); 10008 } 10009} 10010 10011/* Return the GOT register. */ 10012 10013rtx 10014rs6000_got_register (rtx value ATTRIBUTE_UNUSED) 10015{ 10016 /* The second flow pass currently (June 1999) can't update 10017 regs_ever_live without disturbing other parts of the compiler, so 10018 update it here to make the prolog/epilogue code happy. */ 10019 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]) 10020 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; 10021 10022 current_function_uses_pic_offset_table = 1; 10023 10024 return pic_offset_table_rtx; 10025} 10026 10027/* Function to init struct machine_function. 10028 This will be called, via a pointer variable, 10029 from push_function_context. */ 10030 10031static struct machine_function * 10032rs6000_init_machine_status (void) 10033{ 10034 return ggc_alloc_cleared (sizeof (machine_function)); 10035} 10036 10037/* These macros test for integers and extract the low-order bits. */ 10038#define INT_P(X) \ 10039((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ 10040 && GET_MODE (X) == VOIDmode) 10041 10042#define INT_LOWPART(X) \ 10043 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) 10044 10045int 10046extract_MB (rtx op) 10047{ 10048 int i; 10049 unsigned long val = INT_LOWPART (op); 10050 10051 /* If the high bit is zero, the value is the first 1 bit we find 10052 from the left. */ 10053 if ((val & 0x80000000) == 0) 10054 { 10055 gcc_assert (val & 0xffffffff); 10056 10057 i = 1; 10058 while (((val <<= 1) & 0x80000000) == 0) 10059 ++i; 10060 return i; 10061 } 10062 10063 /* If the high bit is set and the low bit is not, or the mask is all 10064 1's, the value is zero. */ 10065 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff) 10066 return 0; 10067 10068 /* Otherwise we have a wrap-around mask. Look for the first 0 bit 10069 from the right. */ 10070 i = 31; 10071 while (((val >>= 1) & 1) != 0) 10072 --i; 10073 10074 return i; 10075} 10076 10077int 10078extract_ME (rtx op) 10079{ 10080 int i; 10081 unsigned long val = INT_LOWPART (op); 10082 10083 /* If the low bit is zero, the value is the first 1 bit we find from 10084 the right. */ 10085 if ((val & 1) == 0) 10086 { 10087 gcc_assert (val & 0xffffffff); 10088 10089 i = 30; 10090 while (((val >>= 1) & 1) == 0) 10091 --i; 10092 10093 return i; 10094 } 10095 10096 /* If the low bit is set and the high bit is not, or the mask is all 10097 1's, the value is 31. */ 10098 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff) 10099 return 31; 10100 10101 /* Otherwise we have a wrap-around mask. Look for the first 0 bit 10102 from the left. */ 10103 i = 0; 10104 while (((val <<= 1) & 0x80000000) != 0) 10105 ++i; 10106 10107 return i; 10108} 10109 10110/* Locate some local-dynamic symbol still in use by this function 10111 so that we can print its name in some tls_ld pattern. */ 10112 10113static const char * 10114rs6000_get_some_local_dynamic_name (void) 10115{ 10116 rtx insn; 10117 10118 if (cfun->machine->some_ld_name) 10119 return cfun->machine->some_ld_name; 10120 10121 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) 10122 if (INSN_P (insn) 10123 && for_each_rtx (&PATTERN (insn), 10124 rs6000_get_some_local_dynamic_name_1, 0)) 10125 return cfun->machine->some_ld_name; 10126 10127 gcc_unreachable (); 10128} 10129 10130/* Helper function for rs6000_get_some_local_dynamic_name. */ 10131 10132static int 10133rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) 10134{ 10135 rtx x = *px; 10136 10137 if (GET_CODE (x) == SYMBOL_REF) 10138 { 10139 const char *str = XSTR (x, 0); 10140 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) 10141 { 10142 cfun->machine->some_ld_name = str; 10143 return 1; 10144 } 10145 } 10146 10147 return 0; 10148} 10149 10150/* Write out a function code label. */ 10151 10152void 10153rs6000_output_function_entry (FILE *file, const char *fname) 10154{ 10155 if (fname[0] != '.') 10156 { 10157 switch (DEFAULT_ABI) 10158 { 10159 default: 10160 gcc_unreachable (); 10161 10162 case ABI_AIX: 10163 if (DOT_SYMBOLS) 10164 putc ('.', file); 10165 else 10166 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L."); 10167 break; 10168 10169 case ABI_V4: 10170 case ABI_DARWIN: 10171 break; 10172 } 10173 } 10174 if (TARGET_AIX) 10175 RS6000_OUTPUT_BASENAME (file, fname); 10176 else 10177 assemble_name (file, fname); 10178} 10179 10180/* Print an operand. Recognize special options, documented below. */ 10181 10182#if TARGET_ELF 10183#define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") 10184#define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) 10185#else 10186#define SMALL_DATA_RELOC "sda21" 10187#define SMALL_DATA_REG 0 10188#endif 10189 10190void 10191print_operand (FILE *file, rtx x, int code) 10192{ 10193 int i; 10194 HOST_WIDE_INT val; 10195 unsigned HOST_WIDE_INT uval; 10196 10197 switch (code) 10198 { 10199 case '.': 10200 /* Write out an instruction after the call which may be replaced 10201 with glue code by the loader. This depends on the AIX version. */ 10202 asm_fprintf (file, RS6000_CALL_GLUE); 10203 return; 10204 10205 /* %a is output_address. */ 10206 10207 case 'A': 10208 /* If X is a constant integer whose low-order 5 bits are zero, 10209 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug 10210 in the AIX assembler where "sri" with a zero shift count 10211 writes a trash instruction. */ 10212 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) 10213 putc ('l', file); 10214 else 10215 putc ('r', file); 10216 return; 10217 10218 case 'b': 10219 /* If constant, low-order 16 bits of constant, unsigned. 10220 Otherwise, write normally. */ 10221 if (INT_P (x)) 10222 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); 10223 else 10224 print_operand (file, x, 0); 10225 return; 10226 10227 case 'B': 10228 /* If the low-order bit is zero, write 'r'; otherwise, write 'l' 10229 for 64-bit mask direction. */ 10230 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file); 10231 return; 10232 10233 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise 10234 output_operand. */ 10235 10236 case 'c': 10237 /* X is a CR register. Print the number of the GT bit of the CR. */ 10238 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) 10239 output_operand_lossage ("invalid %%E value"); 10240 else 10241 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1); 10242 return; 10243 10244 case 'D': 10245 /* Like 'J' but get to the EQ bit. */ 10246 gcc_assert (GET_CODE (x) == REG); 10247 10248 /* Bit 1 is EQ bit. */ 10249 i = 4 * (REGNO (x) - CR0_REGNO) + 2; 10250 10251 fprintf (file, "%d", i); 10252 return; 10253 10254 case 'E': 10255 /* X is a CR register. Print the number of the EQ bit of the CR */ 10256 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) 10257 output_operand_lossage ("invalid %%E value"); 10258 else 10259 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); 10260 return; 10261 10262 case 'f': 10263 /* X is a CR register. Print the shift count needed to move it 10264 to the high-order four bits. */ 10265 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) 10266 output_operand_lossage ("invalid %%f value"); 10267 else 10268 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); 10269 return; 10270 10271 case 'F': 10272 /* Similar, but print the count for the rotate in the opposite 10273 direction. */ 10274 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) 10275 output_operand_lossage ("invalid %%F value"); 10276 else 10277 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); 10278 return; 10279 10280 case 'G': 10281 /* X is a constant integer. If it is negative, print "m", 10282 otherwise print "z". This is to make an aze or ame insn. */ 10283 if (GET_CODE (x) != CONST_INT) 10284 output_operand_lossage ("invalid %%G value"); 10285 else if (INTVAL (x) >= 0) 10286 putc ('z', file); 10287 else 10288 putc ('m', file); 10289 return; 10290 10291 case 'h': 10292 /* If constant, output low-order five bits. Otherwise, write 10293 normally. */ 10294 if (INT_P (x)) 10295 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); 10296 else 10297 print_operand (file, x, 0); 10298 return; 10299 10300 case 'H': 10301 /* If constant, output low-order six bits. Otherwise, write 10302 normally. */ 10303 if (INT_P (x)) 10304 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); 10305 else 10306 print_operand (file, x, 0); 10307 return; 10308 10309 case 'I': 10310 /* Print `i' if this is a constant, else nothing. */ 10311 if (INT_P (x)) 10312 putc ('i', file); 10313 return; 10314 10315 case 'j': 10316 /* Write the bit number in CCR for jump. */ 10317 i = ccr_bit (x, 0); 10318 if (i == -1) 10319 output_operand_lossage ("invalid %%j code"); 10320 else 10321 fprintf (file, "%d", i); 10322 return; 10323 10324 case 'J': 10325 /* Similar, but add one for shift count in rlinm for scc and pass 10326 scc flag to `ccr_bit'. */ 10327 i = ccr_bit (x, 1); 10328 if (i == -1) 10329 output_operand_lossage ("invalid %%J code"); 10330 else 10331 /* If we want bit 31, write a shift count of zero, not 32. */ 10332 fprintf (file, "%d", i == 31 ? 0 : i + 1); 10333 return; 10334 10335 case 'k': 10336 /* X must be a constant. Write the 1's complement of the 10337 constant. */ 10338 if (! INT_P (x)) 10339 output_operand_lossage ("invalid %%k value"); 10340 else 10341 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); 10342 return; 10343 10344 case 'K': 10345 /* X must be a symbolic constant on ELF. Write an 10346 expression suitable for an 'addi' that adds in the low 16 10347 bits of the MEM. */ 10348 if (GET_CODE (x) != CONST) 10349 { 10350 print_operand_address (file, x); 10351 fputs ("@l", file); 10352 } 10353 else 10354 { 10355 if (GET_CODE (XEXP (x, 0)) != PLUS 10356 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF 10357 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) 10358 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) 10359 output_operand_lossage ("invalid %%K value"); 10360 print_operand_address (file, XEXP (XEXP (x, 0), 0)); 10361 fputs ("@l", file); 10362 /* For GNU as, there must be a non-alphanumeric character 10363 between 'l' and the number. The '-' is added by 10364 print_operand() already. */ 10365 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0) 10366 fputs ("+", file); 10367 print_operand (file, XEXP (XEXP (x, 0), 1), 0); 10368 } 10369 return; 10370 10371 /* %l is output_asm_label. */ 10372 10373 case 'L': 10374 /* Write second word of DImode or DFmode reference. Works on register 10375 or non-indexed memory only. */ 10376 if (GET_CODE (x) == REG) 10377 fputs (reg_names[REGNO (x) + 1], file); 10378 else if (GET_CODE (x) == MEM) 10379 { 10380 /* Handle possible auto-increment. Since it is pre-increment and 10381 we have already done it, we can just use an offset of word. */ 10382 if (GET_CODE (XEXP (x, 0)) == PRE_INC 10383 || GET_CODE (XEXP (x, 0)) == PRE_DEC) 10384 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 10385 UNITS_PER_WORD)); 10386 else 10387 output_address (XEXP (adjust_address_nv (x, SImode, 10388 UNITS_PER_WORD), 10389 0)); 10390 10391 if (small_data_operand (x, GET_MODE (x))) 10392 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, 10393 reg_names[SMALL_DATA_REG]); 10394 } 10395 return; 10396 10397 case 'm': 10398 /* MB value for a mask operand. */ 10399 if (! mask_operand (x, SImode)) 10400 output_operand_lossage ("invalid %%m value"); 10401 10402 fprintf (file, "%d", extract_MB (x)); 10403 return; 10404 10405 case 'M': 10406 /* ME value for a mask operand. */ 10407 if (! mask_operand (x, SImode)) 10408 output_operand_lossage ("invalid %%M value"); 10409 10410 fprintf (file, "%d", extract_ME (x)); 10411 return; 10412 10413 /* %n outputs the negative of its operand. */ 10414 10415 case 'N': 10416 /* Write the number of elements in the vector times 4. */ 10417 if (GET_CODE (x) != PARALLEL) 10418 output_operand_lossage ("invalid %%N value"); 10419 else 10420 fprintf (file, "%d", XVECLEN (x, 0) * 4); 10421 return; 10422 10423 case 'O': 10424 /* Similar, but subtract 1 first. */ 10425 if (GET_CODE (x) != PARALLEL) 10426 output_operand_lossage ("invalid %%O value"); 10427 else 10428 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); 10429 return; 10430 10431 case 'p': 10432 /* X is a CONST_INT that is a power of two. Output the logarithm. */ 10433 if (! INT_P (x) 10434 || INT_LOWPART (x) < 0 10435 || (i = exact_log2 (INT_LOWPART (x))) < 0) 10436 output_operand_lossage ("invalid %%p value"); 10437 else 10438 fprintf (file, "%d", i); 10439 return; 10440 10441 case 'P': 10442 /* The operand must be an indirect memory reference. The result 10443 is the register name. */ 10444 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG 10445 || REGNO (XEXP (x, 0)) >= 32) 10446 output_operand_lossage ("invalid %%P value"); 10447 else 10448 fputs (reg_names[REGNO (XEXP (x, 0))], file); 10449 return; 10450 10451 case 'q': 10452 /* This outputs the logical code corresponding to a boolean 10453 expression. The expression may have one or both operands 10454 negated (if one, only the first one). For condition register 10455 logical operations, it will also treat the negated 10456 CR codes as NOTs, but not handle NOTs of them. */ 10457 { 10458 const char *const *t = 0; 10459 const char *s; 10460 enum rtx_code code = GET_CODE (x); 10461 static const char * const tbl[3][3] = { 10462 { "and", "andc", "nor" }, 10463 { "or", "orc", "nand" }, 10464 { "xor", "eqv", "xor" } }; 10465 10466 if (code == AND) 10467 t = tbl[0]; 10468 else if (code == IOR) 10469 t = tbl[1]; 10470 else if (code == XOR) 10471 t = tbl[2]; 10472 else 10473 output_operand_lossage ("invalid %%q value"); 10474 10475 if (GET_CODE (XEXP (x, 0)) != NOT) 10476 s = t[0]; 10477 else 10478 { 10479 if (GET_CODE (XEXP (x, 1)) == NOT) 10480 s = t[2]; 10481 else 10482 s = t[1]; 10483 } 10484 10485 fputs (s, file); 10486 } 10487 return; 10488 10489 case 'Q': 10490 if (TARGET_MFCRF) 10491 fputc (',', file); 10492 /* FALLTHRU */ 10493 else 10494 return; 10495 10496 case 'R': 10497 /* X is a CR register. Print the mask for `mtcrf'. */ 10498 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) 10499 output_operand_lossage ("invalid %%R value"); 10500 else 10501 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); 10502 return; 10503 10504 case 's': 10505 /* Low 5 bits of 32 - value */ 10506 if (! INT_P (x)) 10507 output_operand_lossage ("invalid %%s value"); 10508 else 10509 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); 10510 return; 10511 10512 case 'S': 10513 /* PowerPC64 mask position. All 0's is excluded. 10514 CONST_INT 32-bit mask is considered sign-extended so any 10515 transition must occur within the CONST_INT, not on the boundary. */ 10516 if (! mask64_operand (x, DImode)) 10517 output_operand_lossage ("invalid %%S value"); 10518 10519 uval = INT_LOWPART (x); 10520 10521 if (uval & 1) /* Clear Left */ 10522 { 10523#if HOST_BITS_PER_WIDE_INT > 64 10524 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; 10525#endif 10526 i = 64; 10527 } 10528 else /* Clear Right */ 10529 { 10530 uval = ~uval; 10531#if HOST_BITS_PER_WIDE_INT > 64 10532 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; 10533#endif 10534 i = 63; 10535 } 10536 while (uval != 0) 10537 --i, uval >>= 1; 10538 gcc_assert (i >= 0); 10539 fprintf (file, "%d", i); 10540 return; 10541 10542 case 't': 10543 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */ 10544 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode); 10545 10546 /* Bit 3 is OV bit. */ 10547 i = 4 * (REGNO (x) - CR0_REGNO) + 3; 10548 10549 /* If we want bit 31, write a shift count of zero, not 32. */ 10550 fprintf (file, "%d", i == 31 ? 0 : i + 1); 10551 return; 10552 10553 case 'T': 10554 /* Print the symbolic name of a branch target register. */ 10555 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM 10556 && REGNO (x) != COUNT_REGISTER_REGNUM)) 10557 output_operand_lossage ("invalid %%T value"); 10558 else if (REGNO (x) == LINK_REGISTER_REGNUM) 10559 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); 10560 else 10561 fputs ("ctr", file); 10562 return; 10563 10564 case 'u': 10565 /* High-order 16 bits of constant for use in unsigned operand. */ 10566 if (! INT_P (x)) 10567 output_operand_lossage ("invalid %%u value"); 10568 else 10569 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 10570 (INT_LOWPART (x) >> 16) & 0xffff); 10571 return; 10572 10573 case 'v': 10574 /* High-order 16 bits of constant for use in signed operand. */ 10575 if (! INT_P (x)) 10576 output_operand_lossage ("invalid %%v value"); 10577 else 10578 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 10579 (INT_LOWPART (x) >> 16) & 0xffff); 10580 return; 10581 10582 case 'U': 10583 /* Print `u' if this has an auto-increment or auto-decrement. */ 10584 if (GET_CODE (x) == MEM 10585 && (GET_CODE (XEXP (x, 0)) == PRE_INC 10586 || GET_CODE (XEXP (x, 0)) == PRE_DEC)) 10587 putc ('u', file); 10588 return; 10589 10590 case 'V': 10591 /* Print the trap code for this operand. */ 10592 switch (GET_CODE (x)) 10593 { 10594 case EQ: 10595 fputs ("eq", file); /* 4 */ 10596 break; 10597 case NE: 10598 fputs ("ne", file); /* 24 */ 10599 break; 10600 case LT: 10601 fputs ("lt", file); /* 16 */ 10602 break; 10603 case LE: 10604 fputs ("le", file); /* 20 */ 10605 break; 10606 case GT: 10607 fputs ("gt", file); /* 8 */ 10608 break; 10609 case GE: 10610 fputs ("ge", file); /* 12 */ 10611 break; 10612 case LTU: 10613 fputs ("llt", file); /* 2 */ 10614 break; 10615 case LEU: 10616 fputs ("lle", file); /* 6 */ 10617 break; 10618 case GTU: 10619 fputs ("lgt", file); /* 1 */ 10620 break; 10621 case GEU: 10622 fputs ("lge", file); /* 5 */ 10623 break; 10624 default: 10625 gcc_unreachable (); 10626 } 10627 break; 10628 10629 case 'w': 10630 /* If constant, low-order 16 bits of constant, signed. Otherwise, write 10631 normally. */ 10632 if (INT_P (x)) 10633 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 10634 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); 10635 else 10636 print_operand (file, x, 0); 10637 return; 10638 10639 case 'W': 10640 /* MB value for a PowerPC64 rldic operand. */ 10641 val = (GET_CODE (x) == CONST_INT 10642 ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); 10643 10644 if (val < 0) 10645 i = -1; 10646 else 10647 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) 10648 if ((val <<= 1) < 0) 10649 break; 10650 10651#if HOST_BITS_PER_WIDE_INT == 32 10652 if (GET_CODE (x) == CONST_INT && i >= 0) 10653 i += 32; /* zero-extend high-part was all 0's */ 10654 else if (GET_CODE (x) == CONST_DOUBLE && i == 32) 10655 { 10656 val = CONST_DOUBLE_LOW (x); 10657 10658 gcc_assert (val); 10659 if (val < 0) 10660 --i; 10661 else 10662 for ( ; i < 64; i++) 10663 if ((val <<= 1) < 0) 10664 break; 10665 } 10666#endif 10667 10668 fprintf (file, "%d", i + 1); 10669 return; 10670 10671 case 'X': 10672 if (GET_CODE (x) == MEM 10673 && legitimate_indexed_address_p (XEXP (x, 0), 0)) 10674 putc ('x', file); 10675 return; 10676 10677 case 'Y': 10678 /* Like 'L', for third word of TImode */ 10679 if (GET_CODE (x) == REG) 10680 fputs (reg_names[REGNO (x) + 2], file); 10681 else if (GET_CODE (x) == MEM) 10682 { 10683 if (GET_CODE (XEXP (x, 0)) == PRE_INC 10684 || GET_CODE (XEXP (x, 0)) == PRE_DEC) 10685 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); 10686 else 10687 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); 10688 if (small_data_operand (x, GET_MODE (x))) 10689 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, 10690 reg_names[SMALL_DATA_REG]); 10691 } 10692 return; 10693 10694 case 'z': 10695 /* X is a SYMBOL_REF. Write out the name preceded by a 10696 period and without any trailing data in brackets. Used for function 10697 names. If we are configured for System V (or the embedded ABI) on 10698 the PowerPC, do not emit the period, since those systems do not use 10699 TOCs and the like. */ 10700 gcc_assert (GET_CODE (x) == SYMBOL_REF); 10701 10702 /* Mark the decl as referenced so that cgraph will output the 10703 function. */ 10704 if (SYMBOL_REF_DECL (x)) 10705 mark_decl_referenced (SYMBOL_REF_DECL (x)); 10706 10707 /* For macho, check to see if we need a stub. */ 10708 if (TARGET_MACHO) 10709 { 10710 const char *name = XSTR (x, 0); 10711#if TARGET_MACHO 10712 if (MACHOPIC_INDIRECT 10713 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION) 10714 name = machopic_indirection_name (x, /*stub_p=*/true); 10715#endif 10716 assemble_name (file, name); 10717 } 10718 else if (!DOT_SYMBOLS) 10719 assemble_name (file, XSTR (x, 0)); 10720 else 10721 rs6000_output_function_entry (file, XSTR (x, 0)); 10722 return; 10723 10724 case 'Z': 10725 /* Like 'L', for last word of TImode. */ 10726 if (GET_CODE (x) == REG) 10727 fputs (reg_names[REGNO (x) + 3], file); 10728 else if (GET_CODE (x) == MEM) 10729 { 10730 if (GET_CODE (XEXP (x, 0)) == PRE_INC 10731 || GET_CODE (XEXP (x, 0)) == PRE_DEC) 10732 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); 10733 else 10734 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); 10735 if (small_data_operand (x, GET_MODE (x))) 10736 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, 10737 reg_names[SMALL_DATA_REG]); 10738 } 10739 return; 10740 10741 /* Print AltiVec or SPE memory operand. */ 10742 case 'y': 10743 { 10744 rtx tmp; 10745 10746 gcc_assert (GET_CODE (x) == MEM); 10747 10748 tmp = XEXP (x, 0); 10749 10750 /* Ugly hack because %y is overloaded. */ 10751 if (TARGET_E500 && GET_MODE_SIZE (GET_MODE (x)) == 8) 10752 { 10753 /* Handle [reg]. */ 10754 if (GET_CODE (tmp) == REG) 10755 { 10756 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]); 10757 break; 10758 } 10759 /* Handle [reg+UIMM]. */ 10760 else if (GET_CODE (tmp) == PLUS && 10761 GET_CODE (XEXP (tmp, 1)) == CONST_INT) 10762 { 10763 int x; 10764 10765 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG); 10766 10767 x = INTVAL (XEXP (tmp, 1)); 10768 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]); 10769 break; 10770 } 10771 10772 /* Fall through. Must be [reg+reg]. */ 10773 } 10774 if (TARGET_ALTIVEC 10775 && GET_CODE (tmp) == AND 10776 && GET_CODE (XEXP (tmp, 1)) == CONST_INT 10777 && INTVAL (XEXP (tmp, 1)) == -16) 10778 tmp = XEXP (tmp, 0); 10779 if (GET_CODE (tmp) == REG) 10780 fprintf (file, "0,%s", reg_names[REGNO (tmp)]); 10781 else 10782 { 10783 gcc_assert (GET_CODE (tmp) == PLUS 10784 && REG_P (XEXP (tmp, 0)) 10785 && REG_P (XEXP (tmp, 1))); 10786 10787 if (REGNO (XEXP (tmp, 0)) == 0) 10788 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ], 10789 reg_names[ REGNO (XEXP (tmp, 0)) ]); 10790 else 10791 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ], 10792 reg_names[ REGNO (XEXP (tmp, 1)) ]); 10793 } 10794 break; 10795 } 10796 10797 case 0: 10798 if (GET_CODE (x) == REG) 10799 fprintf (file, "%s", reg_names[REGNO (x)]); 10800 else if (GET_CODE (x) == MEM) 10801 { 10802 /* We need to handle PRE_INC and PRE_DEC here, since we need to 10803 know the width from the mode. */ 10804 if (GET_CODE (XEXP (x, 0)) == PRE_INC) 10805 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), 10806 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); 10807 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) 10808 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), 10809 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); 10810 else 10811 output_address (XEXP (x, 0)); 10812 } 10813 else 10814 output_addr_const (file, x); 10815 return; 10816 10817 case '&': 10818 assemble_name (file, rs6000_get_some_local_dynamic_name ()); 10819 return; 10820 10821 default: 10822 output_operand_lossage ("invalid %%xn code"); 10823 } 10824} 10825 10826/* Print the address of an operand. */ 10827 10828void 10829print_operand_address (FILE *file, rtx x) 10830{ 10831 if (GET_CODE (x) == REG) 10832 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); 10833 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST 10834 || GET_CODE (x) == LABEL_REF) 10835 { 10836 output_addr_const (file, x); 10837 if (small_data_operand (x, GET_MODE (x))) 10838 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, 10839 reg_names[SMALL_DATA_REG]); 10840 else 10841 gcc_assert (!TARGET_TOC); 10842 } 10843 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) 10844 { 10845 gcc_assert (REG_P (XEXP (x, 0))); 10846 if (REGNO (XEXP (x, 0)) == 0) 10847 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], 10848 reg_names[ REGNO (XEXP (x, 0)) ]); 10849 else 10850 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], 10851 reg_names[ REGNO (XEXP (x, 1)) ]); 10852 } 10853 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) 10854 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)", 10855 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]); 10856#if TARGET_ELF 10857 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG 10858 && CONSTANT_P (XEXP (x, 1))) 10859 { 10860 output_addr_const (file, XEXP (x, 1)); 10861 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); 10862 } 10863#endif 10864#if TARGET_MACHO 10865 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG 10866 && CONSTANT_P (XEXP (x, 1))) 10867 { 10868 fprintf (file, "lo16("); 10869 output_addr_const (file, XEXP (x, 1)); 10870 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); 10871 } 10872#endif 10873 else if (legitimate_constant_pool_address_p (x)) 10874 { 10875 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) 10876 { 10877 rtx contains_minus = XEXP (x, 1); 10878 rtx minus, symref; 10879 const char *name; 10880 10881 /* Find the (minus (sym) (toc)) buried in X, and temporarily 10882 turn it into (sym) for output_addr_const. */ 10883 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) 10884 contains_minus = XEXP (contains_minus, 0); 10885 10886 minus = XEXP (contains_minus, 0); 10887 symref = XEXP (minus, 0); 10888 XEXP (contains_minus, 0) = symref; 10889 if (TARGET_ELF) 10890 { 10891 char *newname; 10892 10893 name = XSTR (symref, 0); 10894 newname = alloca (strlen (name) + sizeof ("@toc")); 10895 strcpy (newname, name); 10896 strcat (newname, "@toc"); 10897 XSTR (symref, 0) = newname; 10898 } 10899 output_addr_const (file, XEXP (x, 1)); 10900 if (TARGET_ELF) 10901 XSTR (symref, 0) = name; 10902 XEXP (contains_minus, 0) = minus; 10903 } 10904 else 10905 output_addr_const (file, XEXP (x, 1)); 10906 10907 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); 10908 } 10909 else 10910 gcc_unreachable (); 10911} 10912 10913/* Target hook for assembling integer objects. The PowerPC version has 10914 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP 10915 is defined. It also needs to handle DI-mode objects on 64-bit 10916 targets. */ 10917 10918static bool 10919rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p) 10920{ 10921#ifdef RELOCATABLE_NEEDS_FIXUP 10922 /* Special handling for SI values. */ 10923 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p) 10924 { 10925 extern int in_toc_section (void); 10926 static int recurse = 0; 10927 10928 /* For -mrelocatable, we mark all addresses that need to be fixed up 10929 in the .fixup section. */ 10930 if (TARGET_RELOCATABLE 10931 && !in_toc_section () 10932 && !in_text_section () 10933 && !in_unlikely_text_section () 10934 && !recurse 10935 && GET_CODE (x) != CONST_INT 10936 && GET_CODE (x) != CONST_DOUBLE 10937 && CONSTANT_P (x)) 10938 { 10939 char buf[256]; 10940 10941 recurse = 1; 10942 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno); 10943 fixuplabelno++; 10944 ASM_OUTPUT_LABEL (asm_out_file, buf); 10945 fprintf (asm_out_file, "\t.long\t("); 10946 output_addr_const (asm_out_file, x); 10947 fprintf (asm_out_file, ")@fixup\n"); 10948 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n"); 10949 ASM_OUTPUT_ALIGN (asm_out_file, 2); 10950 fprintf (asm_out_file, "\t.long\t"); 10951 assemble_name (asm_out_file, buf); 10952 fprintf (asm_out_file, "\n\t.previous\n"); 10953 recurse = 0; 10954 return true; 10955 } 10956 /* Remove initial .'s to turn a -mcall-aixdesc function 10957 address into the address of the descriptor, not the function 10958 itself. */ 10959 else if (GET_CODE (x) == SYMBOL_REF 10960 && XSTR (x, 0)[0] == '.' 10961 && DEFAULT_ABI == ABI_AIX) 10962 { 10963 const char *name = XSTR (x, 0); 10964 while (*name == '.') 10965 name++; 10966 10967 fprintf (asm_out_file, "\t.long\t%s\n", name); 10968 return true; 10969 } 10970 } 10971#endif /* RELOCATABLE_NEEDS_FIXUP */ 10972 return default_assemble_integer (x, size, aligned_p); 10973} 10974 10975#ifdef HAVE_GAS_HIDDEN 10976/* Emit an assembler directive to set symbol visibility for DECL to 10977 VISIBILITY_TYPE. */ 10978 10979static void 10980rs6000_assemble_visibility (tree decl, int vis) 10981{ 10982 /* Functions need to have their entry point symbol visibility set as 10983 well as their descriptor symbol visibility. */ 10984 if (DEFAULT_ABI == ABI_AIX 10985 && DOT_SYMBOLS 10986 && TREE_CODE (decl) == FUNCTION_DECL) 10987 { 10988 static const char * const visibility_types[] = { 10989 NULL, "internal", "hidden", "protected" 10990 }; 10991 10992 const char *name, *type; 10993 10994 name = ((* targetm.strip_name_encoding) 10995 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)))); 10996 type = visibility_types[vis]; 10997 10998 fprintf (asm_out_file, "\t.%s\t%s\n", type, name); 10999 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name); 11000 } 11001 else 11002 default_assemble_visibility (decl, vis); 11003} 11004#endif 11005 11006enum rtx_code 11007rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code) 11008{ 11009 /* Reversal of FP compares takes care -- an ordered compare 11010 becomes an unordered compare and vice versa. */ 11011 if (mode == CCFPmode 11012 && (!flag_finite_math_only 11013 || code == UNLT || code == UNLE || code == UNGT || code == UNGE 11014 || code == UNEQ || code == LTGT)) 11015 return reverse_condition_maybe_unordered (code); 11016 else 11017 return reverse_condition (code); 11018} 11019 11020/* Generate a compare for CODE. Return a brand-new rtx that 11021 represents the result of the compare. */ 11022 11023static rtx 11024rs6000_generate_compare (enum rtx_code code) 11025{ 11026 enum machine_mode comp_mode; 11027 rtx compare_result; 11028 11029 if (rs6000_compare_fp_p) 11030 comp_mode = CCFPmode; 11031 else if (code == GTU || code == LTU 11032 || code == GEU || code == LEU) 11033 comp_mode = CCUNSmode; 11034 else if ((code == EQ || code == NE) 11035 && GET_CODE (rs6000_compare_op0) == SUBREG 11036 && GET_CODE (rs6000_compare_op1) == SUBREG 11037 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0) 11038 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1)) 11039 /* These are unsigned values, perhaps there will be a later 11040 ordering compare that can be shared with this one. 11041 Unfortunately we cannot detect the signedness of the operands 11042 for non-subregs. */ 11043 comp_mode = CCUNSmode; 11044 else 11045 comp_mode = CCmode; 11046 11047 /* First, the compare. */ 11048 compare_result = gen_reg_rtx (comp_mode); 11049 11050 /* SPE FP compare instructions on the GPRs. Yuck! */ 11051 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) 11052 && rs6000_compare_fp_p) 11053 { 11054 rtx cmp, or_result, compare_result2; 11055 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0); 11056 11057 if (op_mode == VOIDmode) 11058 op_mode = GET_MODE (rs6000_compare_op1); 11059 11060 /* Note: The E500 comparison instructions set the GT bit (x + 11061 1), on success. This explains the mess. */ 11062 11063 switch (code) 11064 { 11065 case EQ: case UNEQ: case NE: case LTGT: 11066 switch (op_mode) 11067 { 11068 case SFmode: 11069 cmp = flag_unsafe_math_optimizations 11070 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0, 11071 rs6000_compare_op1) 11072 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0, 11073 rs6000_compare_op1); 11074 break; 11075 11076 case DFmode: 11077 cmp = flag_unsafe_math_optimizations 11078 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0, 11079 rs6000_compare_op1) 11080 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0, 11081 rs6000_compare_op1); 11082 break; 11083 11084 default: 11085 gcc_unreachable (); 11086 } 11087 break; 11088 11089 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU: 11090 switch (op_mode) 11091 { 11092 case SFmode: 11093 cmp = flag_unsafe_math_optimizations 11094 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0, 11095 rs6000_compare_op1) 11096 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0, 11097 rs6000_compare_op1); 11098 break; 11099 11100 case DFmode: 11101 cmp = flag_unsafe_math_optimizations 11102 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0, 11103 rs6000_compare_op1) 11104 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0, 11105 rs6000_compare_op1); 11106 break; 11107 11108 default: 11109 gcc_unreachable (); 11110 } 11111 break; 11112 11113 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU: 11114 switch (op_mode) 11115 { 11116 case SFmode: 11117 cmp = flag_unsafe_math_optimizations 11118 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0, 11119 rs6000_compare_op1) 11120 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0, 11121 rs6000_compare_op1); 11122 break; 11123 11124 case DFmode: 11125 cmp = flag_unsafe_math_optimizations 11126 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0, 11127 rs6000_compare_op1) 11128 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0, 11129 rs6000_compare_op1); 11130 break; 11131 11132 default: 11133 gcc_unreachable (); 11134 } 11135 break; 11136 default: 11137 gcc_unreachable (); 11138 } 11139 11140 /* Synthesize LE and GE from LT/GT || EQ. */ 11141 if (code == LE || code == GE || code == LEU || code == GEU) 11142 { 11143 emit_insn (cmp); 11144 11145 switch (code) 11146 { 11147 case LE: code = LT; break; 11148 case GE: code = GT; break; 11149 case LEU: code = LT; break; 11150 case GEU: code = GT; break; 11151 default: gcc_unreachable (); 11152 } 11153 11154 compare_result2 = gen_reg_rtx (CCFPmode); 11155 11156 /* Do the EQ. */ 11157 switch (op_mode) 11158 { 11159 case SFmode: 11160 cmp = flag_unsafe_math_optimizations 11161 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0, 11162 rs6000_compare_op1) 11163 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0, 11164 rs6000_compare_op1); 11165 break; 11166 11167 case DFmode: 11168 cmp = flag_unsafe_math_optimizations 11169 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0, 11170 rs6000_compare_op1) 11171 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0, 11172 rs6000_compare_op1); 11173 break; 11174 11175 default: 11176 gcc_unreachable (); 11177 } 11178 emit_insn (cmp); 11179 11180 /* OR them together. */ 11181 or_result = gen_reg_rtx (CCFPmode); 11182 cmp = gen_e500_cr_ior_compare (or_result, compare_result, 11183 compare_result2); 11184 compare_result = or_result; 11185 code = EQ; 11186 } 11187 else 11188 { 11189 if (code == NE || code == LTGT) 11190 code = NE; 11191 else 11192 code = EQ; 11193 } 11194 11195 emit_insn (cmp); 11196 } 11197 else 11198 { 11199 /* Generate XLC-compatible TFmode compare as PARALLEL with extra 11200 CLOBBERs to match cmptf_internal2 pattern. */ 11201 if (comp_mode == CCFPmode && TARGET_XL_COMPAT 11202 && GET_MODE (rs6000_compare_op0) == TFmode 11203 && !TARGET_IEEEQUAD 11204 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128) 11205 emit_insn (gen_rtx_PARALLEL (VOIDmode, 11206 gen_rtvec (9, 11207 gen_rtx_SET (VOIDmode, 11208 compare_result, 11209 gen_rtx_COMPARE (comp_mode, 11210 rs6000_compare_op0, 11211 rs6000_compare_op1)), 11212 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), 11213 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), 11214 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), 11215 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), 11216 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), 11217 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), 11218 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), 11219 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode))))); 11220 else if (GET_CODE (rs6000_compare_op1) == UNSPEC 11221 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST) 11222 { 11223 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0); 11224 comp_mode = CCEQmode; 11225 compare_result = gen_reg_rtx (CCEQmode); 11226 if (TARGET_64BIT) 11227 emit_insn (gen_stack_protect_testdi (compare_result, 11228 rs6000_compare_op0, op1)); 11229 else 11230 emit_insn (gen_stack_protect_testsi (compare_result, 11231 rs6000_compare_op0, op1)); 11232 } 11233 else 11234 emit_insn (gen_rtx_SET (VOIDmode, compare_result, 11235 gen_rtx_COMPARE (comp_mode, 11236 rs6000_compare_op0, 11237 rs6000_compare_op1))); 11238 } 11239 11240 /* Some kinds of FP comparisons need an OR operation; 11241 under flag_finite_math_only we don't bother. */ 11242 if (rs6000_compare_fp_p 11243 && !flag_finite_math_only 11244 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS) 11245 && (code == LE || code == GE 11246 || code == UNEQ || code == LTGT 11247 || code == UNGT || code == UNLT)) 11248 { 11249 enum rtx_code or1, or2; 11250 rtx or1_rtx, or2_rtx, compare2_rtx; 11251 rtx or_result = gen_reg_rtx (CCEQmode); 11252 11253 switch (code) 11254 { 11255 case LE: or1 = LT; or2 = EQ; break; 11256 case GE: or1 = GT; or2 = EQ; break; 11257 case UNEQ: or1 = UNORDERED; or2 = EQ; break; 11258 case LTGT: or1 = LT; or2 = GT; break; 11259 case UNGT: or1 = UNORDERED; or2 = GT; break; 11260 case UNLT: or1 = UNORDERED; or2 = LT; break; 11261 default: gcc_unreachable (); 11262 } 11263 validate_condition_mode (or1, comp_mode); 11264 validate_condition_mode (or2, comp_mode); 11265 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx); 11266 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx); 11267 compare2_rtx = gen_rtx_COMPARE (CCEQmode, 11268 gen_rtx_IOR (SImode, or1_rtx, or2_rtx), 11269 const_true_rtx); 11270 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); 11271 11272 compare_result = or_result; 11273 code = EQ; 11274 } 11275 11276 validate_condition_mode (code, GET_MODE (compare_result)); 11277 11278 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx); 11279} 11280 11281 11282/* Emit the RTL for an sCOND pattern. */ 11283 11284void 11285rs6000_emit_sCOND (enum rtx_code code, rtx result) 11286{ 11287 rtx condition_rtx; 11288 enum machine_mode op_mode; 11289 enum rtx_code cond_code; 11290 11291 condition_rtx = rs6000_generate_compare (code); 11292 cond_code = GET_CODE (condition_rtx); 11293 11294 if (TARGET_E500 && rs6000_compare_fp_p 11295 && !TARGET_FPRS && TARGET_HARD_FLOAT) 11296 { 11297 rtx t; 11298 11299 PUT_MODE (condition_rtx, SImode); 11300 t = XEXP (condition_rtx, 0); 11301 11302 gcc_assert (cond_code == NE || cond_code == EQ); 11303 11304 if (cond_code == NE) 11305 emit_insn (gen_e500_flip_gt_bit (t, t)); 11306 11307 emit_insn (gen_move_from_CR_gt_bit (result, t)); 11308 return; 11309 } 11310 11311 if (cond_code == NE 11312 || cond_code == GE || cond_code == LE 11313 || cond_code == GEU || cond_code == LEU 11314 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE) 11315 { 11316 rtx not_result = gen_reg_rtx (CCEQmode); 11317 rtx not_op, rev_cond_rtx; 11318 enum machine_mode cc_mode; 11319 11320 cc_mode = GET_MODE (XEXP (condition_rtx, 0)); 11321 11322 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code), 11323 SImode, XEXP (condition_rtx, 0), const0_rtx); 11324 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx); 11325 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op)); 11326 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx); 11327 } 11328 11329 op_mode = GET_MODE (rs6000_compare_op0); 11330 if (op_mode == VOIDmode) 11331 op_mode = GET_MODE (rs6000_compare_op1); 11332 11333 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) 11334 { 11335 PUT_MODE (condition_rtx, DImode); 11336 convert_move (result, condition_rtx, 0); 11337 } 11338 else 11339 { 11340 PUT_MODE (condition_rtx, SImode); 11341 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); 11342 } 11343} 11344 11345/* Emit a branch of kind CODE to location LOC. */ 11346 11347void 11348rs6000_emit_cbranch (enum rtx_code code, rtx loc) 11349{ 11350 rtx condition_rtx, loc_ref; 11351 11352 condition_rtx = rs6000_generate_compare (code); 11353 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); 11354 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, 11355 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, 11356 loc_ref, pc_rtx))); 11357} 11358 11359/* Return the string to output a conditional branch to LABEL, which is 11360 the operand number of the label, or -1 if the branch is really a 11361 conditional return. 11362 11363 OP is the conditional expression. XEXP (OP, 0) is assumed to be a 11364 condition code register and its mode specifies what kind of 11365 comparison we made. 11366 11367 REVERSED is nonzero if we should reverse the sense of the comparison. 11368 11369 INSN is the insn. */ 11370 11371char * 11372output_cbranch (rtx op, const char *label, int reversed, rtx insn) 11373{ 11374 static char string[64]; 11375 enum rtx_code code = GET_CODE (op); 11376 rtx cc_reg = XEXP (op, 0); 11377 enum machine_mode mode = GET_MODE (cc_reg); 11378 int cc_regno = REGNO (cc_reg) - CR0_REGNO; 11379 int need_longbranch = label != NULL && get_attr_length (insn) == 8; 11380 int really_reversed = reversed ^ need_longbranch; 11381 char *s = string; 11382 const char *ccode; 11383 const char *pred; 11384 rtx note; 11385 11386 validate_condition_mode (code, mode); 11387 11388 /* Work out which way this really branches. We could use 11389 reverse_condition_maybe_unordered here always but this 11390 makes the resulting assembler clearer. */ 11391 if (really_reversed) 11392 { 11393 /* Reversal of FP compares takes care -- an ordered compare 11394 becomes an unordered compare and vice versa. */ 11395 if (mode == CCFPmode) 11396 code = reverse_condition_maybe_unordered (code); 11397 else 11398 code = reverse_condition (code); 11399 } 11400 11401 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode) 11402 { 11403 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely 11404 to the GT bit. */ 11405 switch (code) 11406 { 11407 case EQ: 11408 /* Opposite of GT. */ 11409 code = GT; 11410 break; 11411 11412 case NE: 11413 code = UNLE; 11414 break; 11415 11416 default: 11417 gcc_unreachable (); 11418 } 11419 } 11420 11421 switch (code) 11422 { 11423 /* Not all of these are actually distinct opcodes, but 11424 we distinguish them for clarity of the resulting assembler. */ 11425 case NE: case LTGT: 11426 ccode = "ne"; break; 11427 case EQ: case UNEQ: 11428 ccode = "eq"; break; 11429 case GE: case GEU: 11430 ccode = "ge"; break; 11431 case GT: case GTU: case UNGT: 11432 ccode = "gt"; break; 11433 case LE: case LEU: 11434 ccode = "le"; break; 11435 case LT: case LTU: case UNLT: 11436 ccode = "lt"; break; 11437 case UNORDERED: ccode = "un"; break; 11438 case ORDERED: ccode = "nu"; break; 11439 case UNGE: ccode = "nl"; break; 11440 case UNLE: ccode = "ng"; break; 11441 default: 11442 gcc_unreachable (); 11443 } 11444 11445 /* Maybe we have a guess as to how likely the branch is. 11446 The old mnemonics don't have a way to specify this information. */ 11447 pred = ""; 11448 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); 11449 if (note != NULL_RTX) 11450 { 11451 /* PROB is the difference from 50%. */ 11452 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; 11453 11454 /* Only hint for highly probable/improbable branches on newer 11455 cpus as static prediction overrides processor dynamic 11456 prediction. For older cpus we may as well always hint, but 11457 assume not taken for branches that are very close to 50% as a 11458 mispredicted taken branch is more expensive than a 11459 mispredicted not-taken branch. */ 11460 if (rs6000_always_hint 11461 || abs (prob) > REG_BR_PROB_BASE / 100 * 48) 11462 { 11463 if (abs (prob) > REG_BR_PROB_BASE / 20 11464 && ((prob > 0) ^ need_longbranch)) 11465 pred = "+"; 11466 else 11467 pred = "-"; 11468 } 11469 } 11470 11471 if (label == NULL) 11472 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); 11473 else 11474 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); 11475 11476 /* We need to escape any '%' characters in the reg_names string. 11477 Assume they'd only be the first character.... */ 11478 if (reg_names[cc_regno + CR0_REGNO][0] == '%') 11479 *s++ = '%'; 11480 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); 11481 11482 if (label != NULL) 11483 { 11484 /* If the branch distance was too far, we may have to use an 11485 unconditional branch to go the distance. */ 11486 if (need_longbranch) 11487 s += sprintf (s, ",$+8\n\tb %s", label); 11488 else 11489 s += sprintf (s, ",%s", label); 11490 } 11491 11492 return string; 11493} 11494 11495/* Return the string to flip the GT bit on a CR. */ 11496char * 11497output_e500_flip_gt_bit (rtx dst, rtx src) 11498{ 11499 static char string[64]; 11500 int a, b; 11501 11502 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst)) 11503 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src))); 11504 11505 /* GT bit. */ 11506 a = 4 * (REGNO (dst) - CR0_REGNO) + 1; 11507 b = 4 * (REGNO (src) - CR0_REGNO) + 1; 11508 11509 sprintf (string, "crnot %d,%d", a, b); 11510 return string; 11511} 11512 11513/* Return insn index for the vector compare instruction for given CODE, 11514 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is 11515 not available. */ 11516 11517static int 11518get_vec_cmp_insn (enum rtx_code code, 11519 enum machine_mode dest_mode, 11520 enum machine_mode op_mode) 11521{ 11522 if (!TARGET_ALTIVEC) 11523 return INSN_NOT_AVAILABLE; 11524 11525 switch (code) 11526 { 11527 case EQ: 11528 if (dest_mode == V16QImode && op_mode == V16QImode) 11529 return UNSPEC_VCMPEQUB; 11530 if (dest_mode == V8HImode && op_mode == V8HImode) 11531 return UNSPEC_VCMPEQUH; 11532 if (dest_mode == V4SImode && op_mode == V4SImode) 11533 return UNSPEC_VCMPEQUW; 11534 if (dest_mode == V4SImode && op_mode == V4SFmode) 11535 return UNSPEC_VCMPEQFP; 11536 break; 11537 case GE: 11538 if (dest_mode == V4SImode && op_mode == V4SFmode) 11539 return UNSPEC_VCMPGEFP; 11540 case GT: 11541 if (dest_mode == V16QImode && op_mode == V16QImode) 11542 return UNSPEC_VCMPGTSB; 11543 if (dest_mode == V8HImode && op_mode == V8HImode) 11544 return UNSPEC_VCMPGTSH; 11545 if (dest_mode == V4SImode && op_mode == V4SImode) 11546 return UNSPEC_VCMPGTSW; 11547 if (dest_mode == V4SImode && op_mode == V4SFmode) 11548 return UNSPEC_VCMPGTFP; 11549 break; 11550 case GTU: 11551 if (dest_mode == V16QImode && op_mode == V16QImode) 11552 return UNSPEC_VCMPGTUB; 11553 if (dest_mode == V8HImode && op_mode == V8HImode) 11554 return UNSPEC_VCMPGTUH; 11555 if (dest_mode == V4SImode && op_mode == V4SImode) 11556 return UNSPEC_VCMPGTUW; 11557 break; 11558 default: 11559 break; 11560 } 11561 return INSN_NOT_AVAILABLE; 11562} 11563 11564/* Emit vector compare for operands OP0 and OP1 using code RCODE. 11565 DMODE is expected destination mode. This is a recursive function. */ 11566 11567static rtx 11568rs6000_emit_vector_compare (enum rtx_code rcode, 11569 rtx op0, rtx op1, 11570 enum machine_mode dmode) 11571{ 11572 int vec_cmp_insn; 11573 rtx mask; 11574 enum machine_mode dest_mode; 11575 enum machine_mode op_mode = GET_MODE (op1); 11576 11577 gcc_assert (TARGET_ALTIVEC); 11578 gcc_assert (GET_MODE (op0) == GET_MODE (op1)); 11579 11580 /* Floating point vector compare instructions uses destination V4SImode. 11581 Move destination to appropriate mode later. */ 11582 if (dmode == V4SFmode) 11583 dest_mode = V4SImode; 11584 else 11585 dest_mode = dmode; 11586 11587 mask = gen_reg_rtx (dest_mode); 11588 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode); 11589 11590 if (vec_cmp_insn == INSN_NOT_AVAILABLE) 11591 { 11592 bool swap_operands = false; 11593 bool try_again = false; 11594 switch (rcode) 11595 { 11596 case LT: 11597 rcode = GT; 11598 swap_operands = true; 11599 try_again = true; 11600 break; 11601 case LTU: 11602 rcode = GTU; 11603 swap_operands = true; 11604 try_again = true; 11605 break; 11606 case NE: 11607 /* Treat A != B as ~(A==B). */ 11608 { 11609 enum insn_code nor_code; 11610 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, 11611 dest_mode); 11612 11613 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code; 11614 gcc_assert (nor_code != CODE_FOR_nothing); 11615 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx)); 11616 11617 if (dmode != dest_mode) 11618 { 11619 rtx temp = gen_reg_rtx (dest_mode); 11620 convert_move (temp, mask, 0); 11621 return temp; 11622 } 11623 return mask; 11624 } 11625 break; 11626 case GE: 11627 case GEU: 11628 case LE: 11629 case LEU: 11630 /* Try GT/GTU/LT/LTU OR EQ */ 11631 { 11632 rtx c_rtx, eq_rtx; 11633 enum insn_code ior_code; 11634 enum rtx_code new_code; 11635 11636 switch (rcode) 11637 { 11638 case GE: 11639 new_code = GT; 11640 break; 11641 11642 case GEU: 11643 new_code = GTU; 11644 break; 11645 11646 case LE: 11647 new_code = LT; 11648 break; 11649 11650 case LEU: 11651 new_code = LTU; 11652 break; 11653 11654 default: 11655 gcc_unreachable (); 11656 } 11657 11658 c_rtx = rs6000_emit_vector_compare (new_code, 11659 op0, op1, dest_mode); 11660 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, 11661 dest_mode); 11662 11663 ior_code = ior_optab->handlers[(int)dest_mode].insn_code; 11664 gcc_assert (ior_code != CODE_FOR_nothing); 11665 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx)); 11666 if (dmode != dest_mode) 11667 { 11668 rtx temp = gen_reg_rtx (dest_mode); 11669 convert_move (temp, mask, 0); 11670 return temp; 11671 } 11672 return mask; 11673 } 11674 break; 11675 default: 11676 gcc_unreachable (); 11677 } 11678 11679 if (try_again) 11680 { 11681 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode); 11682 /* You only get two chances. */ 11683 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE); 11684 } 11685 11686 if (swap_operands) 11687 { 11688 rtx tmp; 11689 tmp = op0; 11690 op0 = op1; 11691 op1 = tmp; 11692 } 11693 } 11694 11695 emit_insn (gen_rtx_SET (VOIDmode, mask, 11696 gen_rtx_UNSPEC (dest_mode, 11697 gen_rtvec (2, op0, op1), 11698 vec_cmp_insn))); 11699 if (dmode != dest_mode) 11700 { 11701 rtx temp = gen_reg_rtx (dest_mode); 11702 convert_move (temp, mask, 0); 11703 return temp; 11704 } 11705 return mask; 11706} 11707 11708/* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if 11709 valid insn doesn exist for given mode. */ 11710 11711static int 11712get_vsel_insn (enum machine_mode mode) 11713{ 11714 switch (mode) 11715 { 11716 case V4SImode: 11717 return UNSPEC_VSEL4SI; 11718 break; 11719 case V4SFmode: 11720 return UNSPEC_VSEL4SF; 11721 break; 11722 case V8HImode: 11723 return UNSPEC_VSEL8HI; 11724 break; 11725 case V16QImode: 11726 return UNSPEC_VSEL16QI; 11727 break; 11728 default: 11729 return INSN_NOT_AVAILABLE; 11730 break; 11731 } 11732 return INSN_NOT_AVAILABLE; 11733} 11734 11735/* Emit vector select insn where DEST is destination using 11736 operands OP1, OP2 and MASK. */ 11737 11738static void 11739rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask) 11740{ 11741 rtx t, temp; 11742 enum machine_mode dest_mode = GET_MODE (dest); 11743 int vsel_insn_index = get_vsel_insn (GET_MODE (dest)); 11744 11745 temp = gen_reg_rtx (dest_mode); 11746 11747 /* For each vector element, select op1 when mask is 1 otherwise 11748 select op2. */ 11749 t = gen_rtx_SET (VOIDmode, temp, 11750 gen_rtx_UNSPEC (dest_mode, 11751 gen_rtvec (3, op2, op1, mask), 11752 vsel_insn_index)); 11753 emit_insn (t); 11754 emit_move_insn (dest, temp); 11755 return; 11756} 11757 11758/* Emit vector conditional expression. 11759 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands. 11760 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */ 11761 11762int 11763rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2, 11764 rtx cond, rtx cc_op0, rtx cc_op1) 11765{ 11766 enum machine_mode dest_mode = GET_MODE (dest); 11767 enum rtx_code rcode = GET_CODE (cond); 11768 rtx mask; 11769 11770 if (!TARGET_ALTIVEC) 11771 return 0; 11772 11773 /* Get the vector mask for the given relational operations. */ 11774 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode); 11775 11776 rs6000_emit_vector_select (dest, op1, op2, mask); 11777 11778 return 1; 11779} 11780 11781/* Emit a conditional move: move TRUE_COND to DEST if OP of the 11782 operands of the last comparison is nonzero/true, FALSE_COND if it 11783 is zero/false. Return 0 if the hardware has no such operation. */ 11784 11785int 11786rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) 11787{ 11788 enum rtx_code code = GET_CODE (op); 11789 rtx op0 = rs6000_compare_op0; 11790 rtx op1 = rs6000_compare_op1; 11791 REAL_VALUE_TYPE c1; 11792 enum machine_mode compare_mode = GET_MODE (op0); 11793 enum machine_mode result_mode = GET_MODE (dest); 11794 rtx temp; 11795 bool is_against_zero; 11796 11797 /* These modes should always match. */ 11798 if (GET_MODE (op1) != compare_mode 11799 /* In the isel case however, we can use a compare immediate, so 11800 op1 may be a small constant. */ 11801 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode))) 11802 return 0; 11803 if (GET_MODE (true_cond) != result_mode) 11804 return 0; 11805 if (GET_MODE (false_cond) != result_mode) 11806 return 0; 11807 11808 /* First, work out if the hardware can do this at all, or 11809 if it's too slow.... */ 11810 if (! rs6000_compare_fp_p) 11811 { 11812 if (TARGET_ISEL) 11813 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond); 11814 return 0; 11815 } 11816 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS 11817 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT) 11818 return 0; 11819 11820 is_against_zero = op1 == CONST0_RTX (compare_mode); 11821 11822 /* A floating-point subtract might overflow, underflow, or produce 11823 an inexact result, thus changing the floating-point flags, so it 11824 can't be generated if we care about that. It's safe if one side 11825 of the construct is zero, since then no subtract will be 11826 generated. */ 11827 if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT 11828 && flag_trapping_math && ! is_against_zero) 11829 return 0; 11830 11831 /* Eliminate half of the comparisons by switching operands, this 11832 makes the remaining code simpler. */ 11833 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE 11834 || code == LTGT || code == LT || code == UNLE) 11835 { 11836 code = reverse_condition_maybe_unordered (code); 11837 temp = true_cond; 11838 true_cond = false_cond; 11839 false_cond = temp; 11840 } 11841 11842 /* UNEQ and LTGT take four instructions for a comparison with zero, 11843 it'll probably be faster to use a branch here too. */ 11844 if (code == UNEQ && HONOR_NANS (compare_mode)) 11845 return 0; 11846 11847 if (GET_CODE (op1) == CONST_DOUBLE) 11848 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); 11849 11850 /* We're going to try to implement comparisons by performing 11851 a subtract, then comparing against zero. Unfortunately, 11852 Inf - Inf is NaN which is not zero, and so if we don't 11853 know that the operand is finite and the comparison 11854 would treat EQ different to UNORDERED, we can't do it. */ 11855 if (HONOR_INFINITIES (compare_mode) 11856 && code != GT && code != UNGE 11857 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1)) 11858 /* Constructs of the form (a OP b ? a : b) are safe. */ 11859 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) 11860 || (! rtx_equal_p (op0, true_cond) 11861 && ! rtx_equal_p (op1, true_cond)))) 11862 return 0; 11863 11864 /* At this point we know we can use fsel. */ 11865 11866 /* Reduce the comparison to a comparison against zero. */ 11867 if (! is_against_zero) 11868 { 11869 temp = gen_reg_rtx (compare_mode); 11870 emit_insn (gen_rtx_SET (VOIDmode, temp, 11871 gen_rtx_MINUS (compare_mode, op0, op1))); 11872 op0 = temp; 11873 op1 = CONST0_RTX (compare_mode); 11874 } 11875 11876 /* If we don't care about NaNs we can reduce some of the comparisons 11877 down to faster ones. */ 11878 if (! HONOR_NANS (compare_mode)) 11879 switch (code) 11880 { 11881 case GT: 11882 code = LE; 11883 temp = true_cond; 11884 true_cond = false_cond; 11885 false_cond = temp; 11886 break; 11887 case UNGE: 11888 code = GE; 11889 break; 11890 case UNEQ: 11891 code = EQ; 11892 break; 11893 default: 11894 break; 11895 } 11896 11897 /* Now, reduce everything down to a GE. */ 11898 switch (code) 11899 { 11900 case GE: 11901 break; 11902 11903 case LE: 11904 temp = gen_reg_rtx (compare_mode); 11905 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); 11906 op0 = temp; 11907 break; 11908 11909 case ORDERED: 11910 temp = gen_reg_rtx (compare_mode); 11911 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0))); 11912 op0 = temp; 11913 break; 11914 11915 case EQ: 11916 temp = gen_reg_rtx (compare_mode); 11917 emit_insn (gen_rtx_SET (VOIDmode, temp, 11918 gen_rtx_NEG (compare_mode, 11919 gen_rtx_ABS (compare_mode, op0)))); 11920 op0 = temp; 11921 break; 11922 11923 case UNGE: 11924 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */ 11925 temp = gen_reg_rtx (result_mode); 11926 emit_insn (gen_rtx_SET (VOIDmode, temp, 11927 gen_rtx_IF_THEN_ELSE (result_mode, 11928 gen_rtx_GE (VOIDmode, 11929 op0, op1), 11930 true_cond, false_cond))); 11931 false_cond = true_cond; 11932 true_cond = temp; 11933 11934 temp = gen_reg_rtx (compare_mode); 11935 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); 11936 op0 = temp; 11937 break; 11938 11939 case GT: 11940 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */ 11941 temp = gen_reg_rtx (result_mode); 11942 emit_insn (gen_rtx_SET (VOIDmode, temp, 11943 gen_rtx_IF_THEN_ELSE (result_mode, 11944 gen_rtx_GE (VOIDmode, 11945 op0, op1), 11946 true_cond, false_cond))); 11947 true_cond = false_cond; 11948 false_cond = temp; 11949 11950 temp = gen_reg_rtx (compare_mode); 11951 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); 11952 op0 = temp; 11953 break; 11954 11955 default: 11956 gcc_unreachable (); 11957 } 11958 11959 emit_insn (gen_rtx_SET (VOIDmode, dest, 11960 gen_rtx_IF_THEN_ELSE (result_mode, 11961 gen_rtx_GE (VOIDmode, 11962 op0, op1), 11963 true_cond, false_cond))); 11964 return 1; 11965} 11966 11967/* Same as above, but for ints (isel). */ 11968 11969static int 11970rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) 11971{ 11972 rtx condition_rtx, cr; 11973 11974 /* All isel implementations thus far are 32-bits. */ 11975 if (GET_MODE (rs6000_compare_op0) != SImode) 11976 return 0; 11977 11978 /* We still have to do the compare, because isel doesn't do a 11979 compare, it just looks at the CRx bits set by a previous compare 11980 instruction. */ 11981 condition_rtx = rs6000_generate_compare (GET_CODE (op)); 11982 cr = XEXP (condition_rtx, 0); 11983 11984 if (GET_MODE (cr) == CCmode) 11985 emit_insn (gen_isel_signed (dest, condition_rtx, 11986 true_cond, false_cond, cr)); 11987 else 11988 emit_insn (gen_isel_unsigned (dest, condition_rtx, 11989 true_cond, false_cond, cr)); 11990 11991 return 1; 11992} 11993 11994const char * 11995output_isel (rtx *operands) 11996{ 11997 enum rtx_code code; 11998 11999 code = GET_CODE (operands[1]); 12000 if (code == GE || code == GEU || code == LE || code == LEU || code == NE) 12001 { 12002 PUT_CODE (operands[1], reverse_condition (code)); 12003 return "isel %0,%3,%2,%j1"; 12004 } 12005 else 12006 return "isel %0,%2,%3,%j1"; 12007} 12008 12009void 12010rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1) 12011{ 12012 enum machine_mode mode = GET_MODE (op0); 12013 enum rtx_code c; 12014 rtx target; 12015 12016 if (code == SMAX || code == SMIN) 12017 c = GE; 12018 else 12019 c = GEU; 12020 12021 if (code == SMAX || code == UMAX) 12022 target = emit_conditional_move (dest, c, op0, op1, mode, 12023 op0, op1, mode, 0); 12024 else 12025 target = emit_conditional_move (dest, c, op0, op1, mode, 12026 op1, op0, mode, 0); 12027 gcc_assert (target); 12028 if (target != dest) 12029 emit_move_insn (dest, target); 12030} 12031 12032/* Emit instructions to perform a load-reserved/store-conditional operation. 12033 The operation performed is an atomic 12034 (set M (CODE:MODE M OP)) 12035 If not NULL, BEFORE is atomically set to M before the operation, and 12036 AFTER is set to M after the operation (that is, (CODE:MODE M OP)). 12037 If SYNC_P then a memory barrier is emitted before the operation. 12038 Either OP or M may be wrapped in a NOT operation. */ 12039 12040void 12041rs6000_emit_sync (enum rtx_code code, enum machine_mode mode, 12042 rtx m, rtx op, rtx before_param, rtx after_param, 12043 bool sync_p) 12044{ 12045 enum machine_mode used_mode; 12046 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after; 12047 rtx used_m; 12048 rtvec vec; 12049 HOST_WIDE_INT imask = GET_MODE_MASK (mode); 12050 rtx shift = NULL_RTX; 12051 12052 if (sync_p) 12053 emit_insn (gen_memory_barrier ()); 12054 12055 if (GET_CODE (m) == NOT) 12056 used_m = XEXP (m, 0); 12057 else 12058 used_m = m; 12059 12060 /* If this is smaller than SImode, we'll have to use SImode with 12061 adjustments. */ 12062 if (mode == QImode || mode == HImode) 12063 { 12064 rtx newop, oldop; 12065 12066 if (MEM_ALIGN (used_m) >= 32) 12067 { 12068 int ishift = 0; 12069 if (BYTES_BIG_ENDIAN) 12070 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode); 12071 12072 shift = GEN_INT (ishift); 12073 } 12074 else 12075 { 12076 rtx addrSI, aligned_addr; 12077 int shift_mask = mode == QImode ? 0x18 : 0x10; 12078 12079 addrSI = force_reg (SImode, gen_lowpart_common (SImode, 12080 XEXP (used_m, 0))); 12081 shift = gen_reg_rtx (SImode); 12082 12083 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3), 12084 GEN_INT (shift_mask))); 12085 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask))); 12086 12087 aligned_addr = expand_binop (Pmode, and_optab, 12088 XEXP (used_m, 0), 12089 GEN_INT (-4), NULL_RTX, 12090 1, OPTAB_LIB_WIDEN); 12091 used_m = change_address (used_m, SImode, aligned_addr); 12092 set_mem_align (used_m, 32); 12093 /* It's safe to keep the old alias set of USED_M, because 12094 the operation is atomic and only affects the original 12095 USED_M. */ 12096 if (GET_CODE (m) == NOT) 12097 m = gen_rtx_NOT (SImode, used_m); 12098 else 12099 m = used_m; 12100 } 12101 12102 if (GET_CODE (op) == NOT) 12103 { 12104 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode); 12105 oldop = gen_rtx_NOT (SImode, oldop); 12106 } 12107 else 12108 oldop = lowpart_subreg (SImode, op, mode); 12109 12110 switch (code) 12111 { 12112 case IOR: 12113 case XOR: 12114 newop = expand_binop (SImode, and_optab, 12115 oldop, GEN_INT (imask), NULL_RTX, 12116 1, OPTAB_LIB_WIDEN); 12117 emit_insn (gen_ashlsi3 (newop, newop, shift)); 12118 break; 12119 12120 case AND: 12121 newop = expand_binop (SImode, ior_optab, 12122 oldop, GEN_INT (~imask), NULL_RTX, 12123 1, OPTAB_LIB_WIDEN); 12124 emit_insn (gen_rotlsi3 (newop, newop, shift)); 12125 break; 12126 12127 case PLUS: 12128 case MINUS: 12129 { 12130 rtx mask; 12131 12132 newop = expand_binop (SImode, and_optab, 12133 oldop, GEN_INT (imask), NULL_RTX, 12134 1, OPTAB_LIB_WIDEN); 12135 emit_insn (gen_ashlsi3 (newop, newop, shift)); 12136 12137 mask = gen_reg_rtx (SImode); 12138 emit_move_insn (mask, GEN_INT (imask)); 12139 emit_insn (gen_ashlsi3 (mask, mask, shift)); 12140 12141 if (code == PLUS) 12142 newop = gen_rtx_PLUS (SImode, m, newop); 12143 else 12144 newop = gen_rtx_MINUS (SImode, m, newop); 12145 newop = gen_rtx_AND (SImode, newop, mask); 12146 newop = gen_rtx_IOR (SImode, newop, 12147 gen_rtx_AND (SImode, 12148 gen_rtx_NOT (SImode, mask), 12149 m)); 12150 break; 12151 } 12152 12153 default: 12154 gcc_unreachable (); 12155 } 12156 12157 if (GET_CODE (m) == NOT) 12158 { 12159 rtx mask, xorm; 12160 12161 mask = gen_reg_rtx (SImode); 12162 emit_move_insn (mask, GEN_INT (imask)); 12163 emit_insn (gen_ashlsi3 (mask, mask, shift)); 12164 12165 xorm = gen_rtx_XOR (SImode, used_m, mask); 12166 /* Depending on the value of 'op', the XOR or the operation might 12167 be able to be simplified away. */ 12168 newop = simplify_gen_binary (code, SImode, xorm, newop); 12169 } 12170 op = newop; 12171 used_mode = SImode; 12172 before = gen_reg_rtx (used_mode); 12173 after = gen_reg_rtx (used_mode); 12174 } 12175 else 12176 { 12177 used_mode = mode; 12178 before = before_param; 12179 after = after_param; 12180 12181 if (before == NULL_RTX) 12182 before = gen_reg_rtx (used_mode); 12183 if (after == NULL_RTX) 12184 after = gen_reg_rtx (used_mode); 12185 } 12186 12187 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT) 12188 && used_mode != mode) 12189 the_op = op; /* Computed above. */ 12190 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT) 12191 the_op = gen_rtx_fmt_ee (code, used_mode, op, m); 12192 else 12193 the_op = gen_rtx_fmt_ee (code, used_mode, m, op); 12194 12195 set_after = gen_rtx_SET (VOIDmode, after, the_op); 12196 set_before = gen_rtx_SET (VOIDmode, before, used_m); 12197 set_atomic = gen_rtx_SET (VOIDmode, used_m, 12198 gen_rtx_UNSPEC (used_mode, 12199 gen_rtvec (1, the_op), 12200 UNSPEC_SYNC_OP)); 12201 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode)); 12202 12203 if ((code == PLUS || code == MINUS) && used_mode != mode) 12204 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch, 12205 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode))); 12206 else 12207 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch); 12208 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec)); 12209 12210 /* Shift and mask the return values properly. */ 12211 if (used_mode != mode && before_param) 12212 { 12213 emit_insn (gen_lshrsi3 (before, before, shift)); 12214 convert_move (before_param, before, 1); 12215 } 12216 12217 if (used_mode != mode && after_param) 12218 { 12219 emit_insn (gen_lshrsi3 (after, after, shift)); 12220 convert_move (after_param, after, 1); 12221 } 12222 12223 /* The previous sequence will end with a branch that's dependent on 12224 the conditional store, so placing an isync will ensure that no 12225 other instructions (especially, no load or store instructions) 12226 can start before the atomic operation completes. */ 12227 if (sync_p) 12228 emit_insn (gen_isync ()); 12229} 12230 12231/* A subroutine of the atomic operation splitters. Jump to LABEL if 12232 COND is true. Mark the jump as unlikely to be taken. */ 12233 12234static void 12235emit_unlikely_jump (rtx cond, rtx label) 12236{ 12237 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1); 12238 rtx x; 12239 12240 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx); 12241 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x)); 12242 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX); 12243} 12244 12245/* A subroutine of the atomic operation splitters. Emit a load-locked 12246 instruction in MODE. */ 12247 12248static void 12249emit_load_locked (enum machine_mode mode, rtx reg, rtx mem) 12250{ 12251 rtx (*fn) (rtx, rtx) = NULL; 12252 if (mode == SImode) 12253 fn = gen_load_locked_si; 12254 else if (mode == DImode) 12255 fn = gen_load_locked_di; 12256 emit_insn (fn (reg, mem)); 12257} 12258 12259/* A subroutine of the atomic operation splitters. Emit a store-conditional 12260 instruction in MODE. */ 12261 12262static void 12263emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val) 12264{ 12265 rtx (*fn) (rtx, rtx, rtx) = NULL; 12266 if (mode == SImode) 12267 fn = gen_store_conditional_si; 12268 else if (mode == DImode) 12269 fn = gen_store_conditional_di; 12270 12271 /* Emit sync before stwcx. to address PPC405 Erratum. */ 12272 if (PPC405_ERRATUM77) 12273 emit_insn (gen_memory_barrier ()); 12274 12275 emit_insn (fn (res, mem, val)); 12276} 12277 12278/* Expand an an atomic fetch-and-operate pattern. CODE is the binary operation 12279 to perform. MEM is the memory on which to operate. VAL is the second 12280 operand of the binary operator. BEFORE and AFTER are optional locations to 12281 return the value of MEM either before of after the operation. SCRATCH is 12282 a scratch register. */ 12283 12284void 12285rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val, 12286 rtx before, rtx after, rtx scratch) 12287{ 12288 enum machine_mode mode = GET_MODE (mem); 12289 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO); 12290 12291 emit_insn (gen_memory_barrier ()); 12292 12293 label = gen_label_rtx (); 12294 emit_label (label); 12295 label = gen_rtx_LABEL_REF (VOIDmode, label); 12296 12297 if (before == NULL_RTX) 12298 before = scratch; 12299 emit_load_locked (mode, before, mem); 12300 12301 if (code == NOT) 12302 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val); 12303 else if (code == AND) 12304 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND); 12305 else 12306 x = gen_rtx_fmt_ee (code, mode, before, val); 12307 12308 if (after != NULL_RTX) 12309 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x))); 12310 emit_insn (gen_rtx_SET (VOIDmode, scratch, x)); 12311 12312 emit_store_conditional (mode, cond, mem, scratch); 12313 12314 x = gen_rtx_NE (VOIDmode, cond, const0_rtx); 12315 emit_unlikely_jump (x, label); 12316 12317 emit_insn (gen_isync ()); 12318} 12319 12320/* Expand an atomic compare and swap operation. MEM is the memory on which 12321 to operate. OLDVAL is the old value to be compared. NEWVAL is the new 12322 value to be stored. SCRATCH is a scratch GPR. */ 12323 12324void 12325rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval, 12326 rtx scratch) 12327{ 12328 enum machine_mode mode = GET_MODE (mem); 12329 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO); 12330 12331 emit_insn (gen_memory_barrier ()); 12332 12333 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); 12334 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); 12335 emit_label (XEXP (label1, 0)); 12336 12337 emit_load_locked (mode, retval, mem); 12338 12339 x = gen_rtx_COMPARE (CCmode, retval, oldval); 12340 emit_insn (gen_rtx_SET (VOIDmode, cond, x)); 12341 12342 x = gen_rtx_NE (VOIDmode, cond, const0_rtx); 12343 emit_unlikely_jump (x, label2); 12344 12345 emit_move_insn (scratch, newval); 12346 emit_store_conditional (mode, cond, mem, scratch); 12347 12348 x = gen_rtx_NE (VOIDmode, cond, const0_rtx); 12349 emit_unlikely_jump (x, label1); 12350 12351 emit_insn (gen_isync ()); 12352 emit_label (XEXP (label2, 0)); 12353} 12354 12355/* Expand an atomic test and set operation. MEM is the memory on which 12356 to operate. VAL is the value set. SCRATCH is a scratch GPR. */ 12357 12358void 12359rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch) 12360{ 12361 enum machine_mode mode = GET_MODE (mem); 12362 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO); 12363 12364 emit_insn (gen_memory_barrier ()); 12365 12366 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); 12367 emit_label (XEXP (label, 0)); 12368 12369 emit_load_locked (mode, retval, mem); 12370 emit_move_insn (scratch, val); 12371 emit_store_conditional (mode, cond, mem, scratch); 12372 12373 x = gen_rtx_NE (VOIDmode, cond, const0_rtx); 12374 emit_unlikely_jump (x, label); 12375 12376 emit_insn (gen_isync ()); 12377} 12378 12379 /* Emit instructions to move SRC to DST. Called by splitters for 12380 multi-register moves. It will emit at most one instruction for 12381 each register that is accessed; that is, it won't emit li/lis pairs 12382 (or equivalent for 64-bit code). One of SRC or DST must be a hard 12383 register. */ 12384 12385void 12386rs6000_split_multireg_move (rtx dst, rtx src) 12387{ 12388 /* The register number of the first register being moved. */ 12389 int reg; 12390 /* The mode that is to be moved. */ 12391 enum machine_mode mode; 12392 /* The mode that the move is being done in, and its size. */ 12393 enum machine_mode reg_mode; 12394 int reg_mode_size; 12395 /* The number of registers that will be moved. */ 12396 int nregs; 12397 12398 reg = REG_P (dst) ? REGNO (dst) : REGNO (src); 12399 mode = GET_MODE (dst); 12400 nregs = hard_regno_nregs[reg][mode]; 12401 if (FP_REGNO_P (reg)) 12402 reg_mode = DFmode; 12403 else if (ALTIVEC_REGNO_P (reg)) 12404 reg_mode = V16QImode; 12405 else if (TARGET_E500_DOUBLE && mode == TFmode) 12406 reg_mode = DFmode; 12407 else 12408 reg_mode = word_mode; 12409 reg_mode_size = GET_MODE_SIZE (reg_mode); 12410 12411 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode)); 12412 12413 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst))) 12414 { 12415 /* Move register range backwards, if we might have destructive 12416 overlap. */ 12417 int i; 12418 for (i = nregs - 1; i >= 0; i--) 12419 emit_insn (gen_rtx_SET (VOIDmode, 12420 simplify_gen_subreg (reg_mode, dst, mode, 12421 i * reg_mode_size), 12422 simplify_gen_subreg (reg_mode, src, mode, 12423 i * reg_mode_size))); 12424 } 12425 else 12426 { 12427 int i; 12428 int j = -1; 12429 bool used_update = false; 12430 12431 if (MEM_P (src) && INT_REGNO_P (reg)) 12432 { 12433 rtx breg; 12434 12435 if (GET_CODE (XEXP (src, 0)) == PRE_INC 12436 || GET_CODE (XEXP (src, 0)) == PRE_DEC) 12437 { 12438 rtx delta_rtx; 12439 breg = XEXP (XEXP (src, 0), 0); 12440 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC 12441 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src))) 12442 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src)))); 12443 emit_insn (TARGET_32BIT 12444 ? gen_addsi3 (breg, breg, delta_rtx) 12445 : gen_adddi3 (breg, breg, delta_rtx)); 12446 src = replace_equiv_address (src, breg); 12447 } 12448 else if (! offsettable_memref_p (src)) 12449 { 12450 rtx basereg; 12451 basereg = gen_rtx_REG (Pmode, reg); 12452 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0))); 12453 src = replace_equiv_address (src, basereg); 12454 } 12455 12456 breg = XEXP (src, 0); 12457 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM) 12458 breg = XEXP (breg, 0); 12459 12460 /* If the base register we are using to address memory is 12461 also a destination reg, then change that register last. */ 12462 if (REG_P (breg) 12463 && REGNO (breg) >= REGNO (dst) 12464 && REGNO (breg) < REGNO (dst) + nregs) 12465 j = REGNO (breg) - REGNO (dst); 12466 } 12467 12468 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg)) 12469 { 12470 rtx breg; 12471 12472 if (GET_CODE (XEXP (dst, 0)) == PRE_INC 12473 || GET_CODE (XEXP (dst, 0)) == PRE_DEC) 12474 { 12475 rtx delta_rtx; 12476 breg = XEXP (XEXP (dst, 0), 0); 12477 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC 12478 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst))) 12479 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst)))); 12480 12481 /* We have to update the breg before doing the store. 12482 Use store with update, if available. */ 12483 12484 if (TARGET_UPDATE) 12485 { 12486 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0); 12487 emit_insn (TARGET_32BIT 12488 ? (TARGET_POWERPC64 12489 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc) 12490 : gen_movsi_update (breg, breg, delta_rtx, nsrc)) 12491 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc)); 12492 used_update = true; 12493 } 12494 else 12495 emit_insn (TARGET_32BIT 12496 ? gen_addsi3 (breg, breg, delta_rtx) 12497 : gen_adddi3 (breg, breg, delta_rtx)); 12498 dst = replace_equiv_address (dst, breg); 12499 } 12500 else 12501 gcc_assert (offsettable_memref_p (dst)); 12502 } 12503 12504 for (i = 0; i < nregs; i++) 12505 { 12506 /* Calculate index to next subword. */ 12507 ++j; 12508 if (j == nregs) 12509 j = 0; 12510 12511 /* If compiler already emitted move of first word by 12512 store with update, no need to do anything. */ 12513 if (j == 0 && used_update) 12514 continue; 12515 12516 emit_insn (gen_rtx_SET (VOIDmode, 12517 simplify_gen_subreg (reg_mode, dst, mode, 12518 j * reg_mode_size), 12519 simplify_gen_subreg (reg_mode, src, mode, 12520 j * reg_mode_size))); 12521 } 12522 } 12523} 12524 12525 12526/* This page contains routines that are used to determine what the 12527 function prologue and epilogue code will do and write them out. */ 12528 12529/* Return the first fixed-point register that is required to be 12530 saved. 32 if none. */ 12531 12532int 12533first_reg_to_save (void) 12534{ 12535 int first_reg; 12536 12537 /* Find lowest numbered live register. */ 12538 for (first_reg = 13; first_reg <= 31; first_reg++) 12539 if (regs_ever_live[first_reg] 12540 && (! call_used_regs[first_reg] 12541 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM 12542 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) 12543 || (DEFAULT_ABI == ABI_DARWIN && flag_pic) 12544 || (TARGET_TOC && TARGET_MINIMAL_TOC))))) 12545 break; 12546 12547#if TARGET_MACHO 12548 if (flag_pic 12549 && current_function_uses_pic_offset_table 12550 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM) 12551 return RS6000_PIC_OFFSET_TABLE_REGNUM; 12552#endif 12553 12554 return first_reg; 12555} 12556 12557/* Similar, for FP regs. */ 12558 12559int 12560first_fp_reg_to_save (void) 12561{ 12562 int first_reg; 12563 12564 /* Find lowest numbered live register. */ 12565 for (first_reg = 14 + 32; first_reg <= 63; first_reg++) 12566 if (regs_ever_live[first_reg]) 12567 break; 12568 12569 return first_reg; 12570} 12571 12572/* Similar, for AltiVec regs. */ 12573 12574static int 12575first_altivec_reg_to_save (void) 12576{ 12577 int i; 12578 12579 /* Stack frame remains as is unless we are in AltiVec ABI. */ 12580 if (! TARGET_ALTIVEC_ABI) 12581 return LAST_ALTIVEC_REGNO + 1; 12582 12583 /* Find lowest numbered live register. */ 12584 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i) 12585 if (regs_ever_live[i]) 12586 break; 12587 12588 return i; 12589} 12590 12591/* Return a 32-bit mask of the AltiVec registers we need to set in 12592 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in 12593 the 32-bit word is 0. */ 12594 12595static unsigned int 12596compute_vrsave_mask (void) 12597{ 12598 unsigned int i, mask = 0; 12599 12600 /* First, find out if we use _any_ altivec registers. */ 12601 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) 12602 if (regs_ever_live[i]) 12603 mask |= ALTIVEC_REG_BIT (i); 12604 12605 if (mask == 0) 12606 return mask; 12607 12608 /* Next, remove the argument registers from the set. These must 12609 be in the VRSAVE mask set by the caller, so we don't need to add 12610 them in again. More importantly, the mask we compute here is 12611 used to generate CLOBBERs in the set_vrsave insn, and we do not 12612 wish the argument registers to die. */ 12613 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i) 12614 mask &= ~ALTIVEC_REG_BIT (i); 12615 12616 /* Similarly, remove the return value from the set. */ 12617 { 12618 bool yes = false; 12619 diddle_return_value (is_altivec_return_reg, &yes); 12620 if (yes) 12621 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN); 12622 } 12623 12624 return mask; 12625} 12626 12627/* For a very restricted set of circumstances, we can cut down the 12628 size of prologues/epilogues by calling our own save/restore-the-world 12629 routines. */ 12630 12631static void 12632compute_save_world_info (rs6000_stack_t *info_ptr) 12633{ 12634 info_ptr->world_save_p = 1; 12635 info_ptr->world_save_p 12636 = (WORLD_SAVE_P (info_ptr) 12637 && DEFAULT_ABI == ABI_DARWIN 12638 && ! (current_function_calls_setjmp && flag_exceptions) 12639 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO 12640 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO 12641 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO 12642 && info_ptr->cr_save_p); 12643 12644 /* This will not work in conjunction with sibcalls. Make sure there 12645 are none. (This check is expensive, but seldom executed.) */ 12646 if (WORLD_SAVE_P (info_ptr)) 12647 { 12648 rtx insn; 12649 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn)) 12650 if ( GET_CODE (insn) == CALL_INSN 12651 && SIBLING_CALL_P (insn)) 12652 { 12653 info_ptr->world_save_p = 0; 12654 break; 12655 } 12656 } 12657 12658 if (WORLD_SAVE_P (info_ptr)) 12659 { 12660 /* Even if we're not touching VRsave, make sure there's room on the 12661 stack for it, if it looks like we're calling SAVE_WORLD, which 12662 will attempt to save it. */ 12663 info_ptr->vrsave_size = 4; 12664 12665 /* "Save" the VRsave register too if we're saving the world. */ 12666 if (info_ptr->vrsave_mask == 0) 12667 info_ptr->vrsave_mask = compute_vrsave_mask (); 12668 12669 /* Because the Darwin register save/restore routines only handle 12670 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency 12671 check. */ 12672 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO 12673 && (info_ptr->first_altivec_reg_save 12674 >= FIRST_SAVED_ALTIVEC_REGNO)); 12675 } 12676 return; 12677} 12678 12679 12680static void 12681is_altivec_return_reg (rtx reg, void *xyes) 12682{ 12683 bool *yes = (bool *) xyes; 12684 if (REGNO (reg) == ALTIVEC_ARG_RETURN) 12685 *yes = true; 12686} 12687 12688 12689/* Calculate the stack information for the current function. This is 12690 complicated by having two separate calling sequences, the AIX calling 12691 sequence and the V.4 calling sequence. 12692 12693 AIX (and Darwin/Mac OS X) stack frames look like: 12694 32-bit 64-bit 12695 SP----> +---------------------------------------+ 12696 | back chain to caller | 0 0 12697 +---------------------------------------+ 12698 | saved CR | 4 8 (8-11) 12699 +---------------------------------------+ 12700 | saved LR | 8 16 12701 +---------------------------------------+ 12702 | reserved for compilers | 12 24 12703 +---------------------------------------+ 12704 | reserved for binders | 16 32 12705 +---------------------------------------+ 12706 | saved TOC pointer | 20 40 12707 +---------------------------------------+ 12708 | Parameter save area (P) | 24 48 12709 +---------------------------------------+ 12710 | Alloca space (A) | 24+P etc. 12711 +---------------------------------------+ 12712 | Local variable space (L) | 24+P+A 12713 +---------------------------------------+ 12714 | Float/int conversion temporary (X) | 24+P+A+L 12715 +---------------------------------------+ 12716 | Save area for AltiVec registers (W) | 24+P+A+L+X 12717 +---------------------------------------+ 12718 | AltiVec alignment padding (Y) | 24+P+A+L+X+W 12719 +---------------------------------------+ 12720 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y 12721 +---------------------------------------+ 12722 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z 12723 +---------------------------------------+ 12724 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G 12725 +---------------------------------------+ 12726 old SP->| back chain to caller's caller | 12727 +---------------------------------------+ 12728 12729 The required alignment for AIX configurations is two words (i.e., 8 12730 or 16 bytes). 12731 12732 12733 V.4 stack frames look like: 12734 12735 SP----> +---------------------------------------+ 12736 | back chain to caller | 0 12737 +---------------------------------------+ 12738 | caller's saved LR | 4 12739 +---------------------------------------+ 12740 | Parameter save area (P) | 8 12741 +---------------------------------------+ 12742 | Alloca space (A) | 8+P 12743 +---------------------------------------+ 12744 | Varargs save area (V) | 8+P+A 12745 +---------------------------------------+ 12746 | Local variable space (L) | 8+P+A+V 12747 +---------------------------------------+ 12748 | Float/int conversion temporary (X) | 8+P+A+V+L 12749 +---------------------------------------+ 12750 | Save area for AltiVec registers (W) | 8+P+A+V+L+X 12751 +---------------------------------------+ 12752 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W 12753 +---------------------------------------+ 12754 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y 12755 +---------------------------------------+ 12756 | SPE: area for 64-bit GP registers | 12757 +---------------------------------------+ 12758 | SPE alignment padding | 12759 +---------------------------------------+ 12760 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z 12761 +---------------------------------------+ 12762 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C 12763 +---------------------------------------+ 12764 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G 12765 +---------------------------------------+ 12766 old SP->| back chain to caller's caller | 12767 +---------------------------------------+ 12768 12769 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is 12770 given. (But note below and in sysv4.h that we require only 8 and 12771 may round up the size of our stack frame anyways. The historical 12772 reason is early versions of powerpc-linux which didn't properly 12773 align the stack at program startup. A happy side-effect is that 12774 -mno-eabi libraries can be used with -meabi programs.) 12775 12776 The EABI configuration defaults to the V.4 layout. However, 12777 the stack alignment requirements may differ. If -mno-eabi is not 12778 given, the required stack alignment is 8 bytes; if -mno-eabi is 12779 given, the required alignment is 16 bytes. (But see V.4 comment 12780 above.) */ 12781 12782#ifndef ABI_STACK_BOUNDARY 12783#define ABI_STACK_BOUNDARY STACK_BOUNDARY 12784#endif 12785 12786static rs6000_stack_t * 12787rs6000_stack_info (void) 12788{ 12789 static rs6000_stack_t info, zero_info; 12790 rs6000_stack_t *info_ptr = &info; 12791 int reg_size = TARGET_32BIT ? 4 : 8; 12792 int ehrd_size; 12793 int save_align; 12794 HOST_WIDE_INT non_fixed_size; 12795 12796 /* Zero all fields portably. */ 12797 info = zero_info; 12798 12799 if (TARGET_SPE) 12800 { 12801 /* Cache value so we don't rescan instruction chain over and over. */ 12802 if (cfun->machine->insn_chain_scanned_p == 0) 12803 cfun->machine->insn_chain_scanned_p 12804 = spe_func_has_64bit_regs_p () + 1; 12805 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1; 12806 } 12807 12808 /* Select which calling sequence. */ 12809 info_ptr->abi = DEFAULT_ABI; 12810 12811 /* Calculate which registers need to be saved & save area size. */ 12812 info_ptr->first_gp_reg_save = first_reg_to_save (); 12813 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM, 12814 even if it currently looks like we won't. */ 12815 if (((TARGET_TOC && TARGET_MINIMAL_TOC) 12816 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4) 12817 || (flag_pic && DEFAULT_ABI == ABI_DARWIN)) 12818 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM) 12819 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM); 12820 else 12821 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); 12822 12823 /* For the SPE, we have an additional upper 32-bits on each GPR. 12824 Ideally we should save the entire 64-bits only when the upper 12825 half is used in SIMD instructions. Since we only record 12826 registers live (not the size they are used in), this proves 12827 difficult because we'd have to traverse the instruction chain at 12828 the right time, taking reload into account. This is a real pain, 12829 so we opt to save the GPRs in 64-bits always if but one register 12830 gets used in 64-bits. Otherwise, all the registers in the frame 12831 get saved in 32-bits. 12832 12833 So... since when we save all GPRs (except the SP) in 64-bits, the 12834 traditional GP save area will be empty. */ 12835 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) 12836 info_ptr->gp_size = 0; 12837 12838 info_ptr->first_fp_reg_save = first_fp_reg_to_save (); 12839 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); 12840 12841 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save (); 12842 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1 12843 - info_ptr->first_altivec_reg_save); 12844 12845 /* Does this function call anything? */ 12846 info_ptr->calls_p = (! current_function_is_leaf 12847 || cfun->machine->ra_needs_full_frame); 12848 12849 /* Determine if we need to save the link register. */ 12850 if (rs6000_ra_ever_killed () 12851 || (DEFAULT_ABI == ABI_AIX 12852 && current_function_profile 12853 && !TARGET_PROFILE_KERNEL) 12854#ifdef TARGET_RELOCATABLE 12855 || (TARGET_RELOCATABLE && (get_pool_size () != 0)) 12856#endif 12857 || (info_ptr->first_fp_reg_save != 64 12858 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) 12859 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO 12860 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca) 12861 || info_ptr->calls_p) 12862 { 12863 info_ptr->lr_save_p = 1; 12864 regs_ever_live[LINK_REGISTER_REGNUM] = 1; 12865 } 12866 12867 /* Determine if we need to save the condition code registers. */ 12868 if (regs_ever_live[CR2_REGNO] 12869 || regs_ever_live[CR3_REGNO] 12870 || regs_ever_live[CR4_REGNO]) 12871 { 12872 info_ptr->cr_save_p = 1; 12873 if (DEFAULT_ABI == ABI_V4) 12874 info_ptr->cr_size = reg_size; 12875 } 12876 12877 /* If the current function calls __builtin_eh_return, then we need 12878 to allocate stack space for registers that will hold data for 12879 the exception handler. */ 12880 if (current_function_calls_eh_return) 12881 { 12882 unsigned int i; 12883 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) 12884 continue; 12885 12886 /* SPE saves EH registers in 64-bits. */ 12887 ehrd_size = i * (TARGET_SPE_ABI 12888 && info_ptr->spe_64bit_regs_used != 0 12889 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD); 12890 } 12891 else 12892 ehrd_size = 0; 12893 12894 /* Determine various sizes. */ 12895 info_ptr->reg_size = reg_size; 12896 info_ptr->fixed_size = RS6000_SAVE_AREA; 12897 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); 12898 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, 12899 TARGET_ALTIVEC ? 16 : 8); 12900 if (FRAME_GROWS_DOWNWARD) 12901 info_ptr->vars_size 12902 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size 12903 + info_ptr->parm_size, 12904 ABI_STACK_BOUNDARY / BITS_PER_UNIT) 12905 - (info_ptr->fixed_size + info_ptr->vars_size 12906 + info_ptr->parm_size); 12907 12908 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) 12909 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save); 12910 else 12911 info_ptr->spe_gp_size = 0; 12912 12913 if (TARGET_ALTIVEC_ABI) 12914 info_ptr->vrsave_mask = compute_vrsave_mask (); 12915 else 12916 info_ptr->vrsave_mask = 0; 12917 12918 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask) 12919 info_ptr->vrsave_size = 4; 12920 else 12921 info_ptr->vrsave_size = 0; 12922 12923 compute_save_world_info (info_ptr); 12924 12925 /* Calculate the offsets. */ 12926 switch (DEFAULT_ABI) 12927 { 12928 case ABI_NONE: 12929 default: 12930 gcc_unreachable (); 12931 12932 case ABI_AIX: 12933 case ABI_DARWIN: 12934 info_ptr->fp_save_offset = - info_ptr->fp_size; 12935 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; 12936 12937 if (TARGET_ALTIVEC_ABI) 12938 { 12939 info_ptr->vrsave_save_offset 12940 = info_ptr->gp_save_offset - info_ptr->vrsave_size; 12941 12942 /* Align stack so vector save area is on a quadword boundary. */ 12943 if (info_ptr->altivec_size != 0) 12944 info_ptr->altivec_padding_size 12945 = 16 - (-info_ptr->vrsave_save_offset % 16); 12946 else 12947 info_ptr->altivec_padding_size = 0; 12948 12949 info_ptr->altivec_save_offset 12950 = info_ptr->vrsave_save_offset 12951 - info_ptr->altivec_padding_size 12952 - info_ptr->altivec_size; 12953 12954 /* Adjust for AltiVec case. */ 12955 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size; 12956 } 12957 else 12958 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; 12959 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ 12960 info_ptr->lr_save_offset = 2*reg_size; 12961 break; 12962 12963 case ABI_V4: 12964 info_ptr->fp_save_offset = - info_ptr->fp_size; 12965 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; 12966 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; 12967 12968 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) 12969 { 12970 /* Align stack so SPE GPR save area is aligned on a 12971 double-word boundary. */ 12972 if (info_ptr->spe_gp_size != 0) 12973 info_ptr->spe_padding_size 12974 = 8 - (-info_ptr->cr_save_offset % 8); 12975 else 12976 info_ptr->spe_padding_size = 0; 12977 12978 info_ptr->spe_gp_save_offset 12979 = info_ptr->cr_save_offset 12980 - info_ptr->spe_padding_size 12981 - info_ptr->spe_gp_size; 12982 12983 /* Adjust for SPE case. */ 12984 info_ptr->toc_save_offset 12985 = info_ptr->spe_gp_save_offset - info_ptr->toc_size; 12986 } 12987 else if (TARGET_ALTIVEC_ABI) 12988 { 12989 info_ptr->vrsave_save_offset 12990 = info_ptr->cr_save_offset - info_ptr->vrsave_size; 12991 12992 /* Align stack so vector save area is on a quadword boundary. */ 12993 if (info_ptr->altivec_size != 0) 12994 info_ptr->altivec_padding_size 12995 = 16 - (-info_ptr->vrsave_save_offset % 16); 12996 else 12997 info_ptr->altivec_padding_size = 0; 12998 12999 info_ptr->altivec_save_offset 13000 = info_ptr->vrsave_save_offset 13001 - info_ptr->altivec_padding_size 13002 - info_ptr->altivec_size; 13003 13004 /* Adjust for AltiVec case. */ 13005 info_ptr->toc_save_offset 13006 = info_ptr->altivec_save_offset - info_ptr->toc_size; 13007 } 13008 else 13009 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; 13010 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; 13011 info_ptr->lr_save_offset = reg_size; 13012 break; 13013 } 13014 13015 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8; 13016 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size 13017 + info_ptr->gp_size 13018 + info_ptr->altivec_size 13019 + info_ptr->altivec_padding_size 13020 + info_ptr->spe_gp_size 13021 + info_ptr->spe_padding_size 13022 + ehrd_size 13023 + info_ptr->cr_size 13024 + info_ptr->lr_size 13025 + info_ptr->vrsave_size 13026 + info_ptr->toc_size, 13027 save_align); 13028 13029 non_fixed_size = (info_ptr->vars_size 13030 + info_ptr->parm_size 13031 + info_ptr->save_size); 13032 13033 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size, 13034 ABI_STACK_BOUNDARY / BITS_PER_UNIT); 13035 13036 /* Determine if we need to allocate any stack frame: 13037 13038 For AIX we need to push the stack if a frame pointer is needed 13039 (because the stack might be dynamically adjusted), if we are 13040 debugging, if we make calls, or if the sum of fp_save, gp_save, 13041 and local variables are more than the space needed to save all 13042 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 13043 + 18*8 = 288 (GPR13 reserved). 13044 13045 For V.4 we don't have the stack cushion that AIX uses, but assume 13046 that the debugger can handle stackless frames. */ 13047 13048 if (info_ptr->calls_p) 13049 info_ptr->push_p = 1; 13050 13051 else if (DEFAULT_ABI == ABI_V4) 13052 info_ptr->push_p = non_fixed_size != 0; 13053 13054 else if (frame_pointer_needed) 13055 info_ptr->push_p = 1; 13056 13057 else if (TARGET_XCOFF && write_symbols != NO_DEBUG) 13058 info_ptr->push_p = 1; 13059 13060 else 13061 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288); 13062 13063 /* Zero offsets if we're not saving those registers. */ 13064 if (info_ptr->fp_size == 0) 13065 info_ptr->fp_save_offset = 0; 13066 13067 if (info_ptr->gp_size == 0) 13068 info_ptr->gp_save_offset = 0; 13069 13070 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0) 13071 info_ptr->altivec_save_offset = 0; 13072 13073 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0) 13074 info_ptr->vrsave_save_offset = 0; 13075 13076 if (! TARGET_SPE_ABI 13077 || info_ptr->spe_64bit_regs_used == 0 13078 || info_ptr->spe_gp_size == 0) 13079 info_ptr->spe_gp_save_offset = 0; 13080 13081 if (! info_ptr->lr_save_p) 13082 info_ptr->lr_save_offset = 0; 13083 13084 if (! info_ptr->cr_save_p) 13085 info_ptr->cr_save_offset = 0; 13086 13087 if (! info_ptr->toc_save_p) 13088 info_ptr->toc_save_offset = 0; 13089 13090 return info_ptr; 13091} 13092 13093/* Return true if the current function uses any GPRs in 64-bit SIMD 13094 mode. */ 13095 13096static bool 13097spe_func_has_64bit_regs_p (void) 13098{ 13099 rtx insns, insn; 13100 13101 /* Functions that save and restore all the call-saved registers will 13102 need to save/restore the registers in 64-bits. */ 13103 if (current_function_calls_eh_return 13104 || current_function_calls_setjmp 13105 || current_function_has_nonlocal_goto) 13106 return true; 13107 13108 insns = get_insns (); 13109 13110 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn)) 13111 { 13112 if (INSN_P (insn)) 13113 { 13114 rtx i; 13115 13116 /* FIXME: This should be implemented with attributes... 13117 13118 (set_attr "spe64" "true")....then, 13119 if (get_spe64(insn)) return true; 13120 13121 It's the only reliable way to do the stuff below. */ 13122 13123 i = PATTERN (insn); 13124 if (GET_CODE (i) == SET) 13125 { 13126 enum machine_mode mode = GET_MODE (SET_SRC (i)); 13127 13128 if (SPE_VECTOR_MODE (mode)) 13129 return true; 13130 if (TARGET_E500_DOUBLE && mode == DFmode) 13131 return true; 13132 } 13133 } 13134 } 13135 13136 return false; 13137} 13138 13139static void 13140debug_stack_info (rs6000_stack_t *info) 13141{ 13142 const char *abi_string; 13143 13144 if (! info) 13145 info = rs6000_stack_info (); 13146 13147 fprintf (stderr, "\nStack information for function %s:\n", 13148 ((current_function_decl && DECL_NAME (current_function_decl)) 13149 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) 13150 : "<unknown>")); 13151 13152 switch (info->abi) 13153 { 13154 default: abi_string = "Unknown"; break; 13155 case ABI_NONE: abi_string = "NONE"; break; 13156 case ABI_AIX: abi_string = "AIX"; break; 13157 case ABI_DARWIN: abi_string = "Darwin"; break; 13158 case ABI_V4: abi_string = "V.4"; break; 13159 } 13160 13161 fprintf (stderr, "\tABI = %5s\n", abi_string); 13162 13163 if (TARGET_ALTIVEC_ABI) 13164 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); 13165 13166 if (TARGET_SPE_ABI) 13167 fprintf (stderr, "\tSPE ABI extensions enabled.\n"); 13168 13169 if (info->first_gp_reg_save != 32) 13170 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); 13171 13172 if (info->first_fp_reg_save != 64) 13173 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); 13174 13175 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO) 13176 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n", 13177 info->first_altivec_reg_save); 13178 13179 if (info->lr_save_p) 13180 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); 13181 13182 if (info->cr_save_p) 13183 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); 13184 13185 if (info->toc_save_p) 13186 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); 13187 13188 if (info->vrsave_mask) 13189 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask); 13190 13191 if (info->push_p) 13192 fprintf (stderr, "\tpush_p = %5d\n", info->push_p); 13193 13194 if (info->calls_p) 13195 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); 13196 13197 if (info->gp_save_offset) 13198 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); 13199 13200 if (info->fp_save_offset) 13201 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); 13202 13203 if (info->altivec_save_offset) 13204 fprintf (stderr, "\taltivec_save_offset = %5d\n", 13205 info->altivec_save_offset); 13206 13207 if (info->spe_gp_save_offset) 13208 fprintf (stderr, "\tspe_gp_save_offset = %5d\n", 13209 info->spe_gp_save_offset); 13210 13211 if (info->vrsave_save_offset) 13212 fprintf (stderr, "\tvrsave_save_offset = %5d\n", 13213 info->vrsave_save_offset); 13214 13215 if (info->lr_save_offset) 13216 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); 13217 13218 if (info->cr_save_offset) 13219 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); 13220 13221 if (info->toc_save_offset) 13222 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); 13223 13224 if (info->varargs_save_offset) 13225 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); 13226 13227 if (info->total_size) 13228 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n", 13229 info->total_size); 13230 13231 if (info->vars_size) 13232 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n", 13233 info->vars_size); 13234 13235 if (info->parm_size) 13236 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); 13237 13238 if (info->fixed_size) 13239 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); 13240 13241 if (info->gp_size) 13242 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); 13243 13244 if (info->spe_gp_size) 13245 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size); 13246 13247 if (info->fp_size) 13248 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); 13249 13250 if (info->altivec_size) 13251 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size); 13252 13253 if (info->vrsave_size) 13254 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size); 13255 13256 if (info->altivec_padding_size) 13257 fprintf (stderr, "\taltivec_padding_size= %5d\n", 13258 info->altivec_padding_size); 13259 13260 if (info->spe_padding_size) 13261 fprintf (stderr, "\tspe_padding_size = %5d\n", 13262 info->spe_padding_size); 13263 13264 if (info->lr_size) 13265 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size); 13266 13267 if (info->cr_size) 13268 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); 13269 13270 if (info->toc_size) 13271 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); 13272 13273 if (info->save_size) 13274 fprintf (stderr, "\tsave_size = %5d\n", info->save_size); 13275 13276 if (info->reg_size != 4) 13277 fprintf (stderr, "\treg_size = %5d\n", info->reg_size); 13278 13279 fprintf (stderr, "\n"); 13280} 13281 13282rtx 13283rs6000_return_addr (int count, rtx frame) 13284{ 13285 /* Currently we don't optimize very well between prolog and body 13286 code and for PIC code the code can be actually quite bad, so 13287 don't try to be too clever here. */ 13288 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic)) 13289 { 13290 cfun->machine->ra_needs_full_frame = 1; 13291 13292 return 13293 gen_rtx_MEM 13294 (Pmode, 13295 memory_address 13296 (Pmode, 13297 plus_constant (copy_to_reg 13298 (gen_rtx_MEM (Pmode, 13299 memory_address (Pmode, frame))), 13300 RETURN_ADDRESS_OFFSET))); 13301 } 13302 13303 cfun->machine->ra_need_lr = 1; 13304 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); 13305} 13306 13307/* Say whether a function is a candidate for sibcall handling or not. 13308 We do not allow indirect calls to be optimized into sibling calls. 13309 Also, we can't do it if there are any vector parameters; there's 13310 nowhere to put the VRsave code so it works; note that functions with 13311 vector parameters are required to have a prototype, so the argument 13312 type info must be available here. (The tail recursion case can work 13313 with vector parameters, but there's no way to distinguish here.) */ 13314static bool 13315rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) 13316{ 13317 tree type; 13318 if (decl) 13319 { 13320 if (TARGET_ALTIVEC_VRSAVE) 13321 { 13322 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl)); 13323 type; type = TREE_CHAIN (type)) 13324 { 13325 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE) 13326 return false; 13327 } 13328 } 13329 if (DEFAULT_ABI == ABI_DARWIN 13330 || ((*targetm.binds_local_p) (decl) 13331 && (DEFAULT_ABI != ABI_AIX || !DECL_EXTERNAL (decl)))) 13332 { 13333 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl)); 13334 13335 if (!lookup_attribute ("longcall", attr_list) 13336 || lookup_attribute ("shortcall", attr_list)) 13337 return true; 13338 } 13339 } 13340 return false; 13341} 13342 13343/* NULL if INSN insn is valid within a low-overhead loop. 13344 Otherwise return why doloop cannot be applied. 13345 PowerPC uses the COUNT register for branch on table instructions. */ 13346 13347static const char * 13348rs6000_invalid_within_doloop (rtx insn) 13349{ 13350 if (CALL_P (insn)) 13351 return "Function call in the loop."; 13352 13353 if (JUMP_P (insn) 13354 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC 13355 || GET_CODE (PATTERN (insn)) == ADDR_VEC)) 13356 return "Computed branch in the loop."; 13357 13358 return NULL; 13359} 13360 13361static int 13362rs6000_ra_ever_killed (void) 13363{ 13364 rtx top; 13365 rtx reg; 13366 rtx insn; 13367 13368 if (current_function_is_thunk) 13369 return 0; 13370 13371 /* regs_ever_live has LR marked as used if any sibcalls are present, 13372 but this should not force saving and restoring in the 13373 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall 13374 clobbers LR, so that is inappropriate. */ 13375 13376 /* Also, the prologue can generate a store into LR that 13377 doesn't really count, like this: 13378 13379 move LR->R0 13380 bcl to set PIC register 13381 move LR->R31 13382 move R0->LR 13383 13384 When we're called from the epilogue, we need to avoid counting 13385 this as a store. */ 13386 13387 push_topmost_sequence (); 13388 top = get_insns (); 13389 pop_topmost_sequence (); 13390 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); 13391 13392 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn)) 13393 { 13394 if (INSN_P (insn)) 13395 { 13396 if (FIND_REG_INC_NOTE (insn, reg)) 13397 return 1; 13398 else if (GET_CODE (insn) == CALL_INSN 13399 && !SIBLING_CALL_P (insn)) 13400 return 1; 13401 else if (set_of (reg, insn) != NULL_RTX 13402 && !prologue_epilogue_contains (insn)) 13403 return 1; 13404 } 13405 } 13406 return 0; 13407} 13408 13409/* Add a REG_MAYBE_DEAD note to the insn. */ 13410static void 13411rs6000_maybe_dead (rtx insn) 13412{ 13413 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, 13414 const0_rtx, 13415 REG_NOTES (insn)); 13416} 13417 13418/* Emit instructions needed to load the TOC register. 13419 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is 13420 a constant pool; or for SVR4 -fpic. */ 13421 13422void 13423rs6000_emit_load_toc_table (int fromprolog) 13424{ 13425 rtx dest, insn; 13426 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); 13427 13428 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic) 13429 { 13430 char buf[30]; 13431 rtx lab, tmp1, tmp2, got, tempLR; 13432 13433 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); 13434 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 13435 if (flag_pic == 2) 13436 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); 13437 else 13438 got = rs6000_got_sym (); 13439 tmp1 = tmp2 = dest; 13440 if (!fromprolog) 13441 { 13442 tmp1 = gen_reg_rtx (Pmode); 13443 tmp2 = gen_reg_rtx (Pmode); 13444 } 13445 tempLR = (fromprolog 13446 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) 13447 : gen_reg_rtx (Pmode)); 13448 insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab)); 13449 if (fromprolog) 13450 rs6000_maybe_dead (insn); 13451 insn = emit_move_insn (tmp1, tempLR); 13452 if (fromprolog) 13453 rs6000_maybe_dead (insn); 13454 insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab)); 13455 if (fromprolog) 13456 rs6000_maybe_dead (insn); 13457 insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab)); 13458 if (fromprolog) 13459 rs6000_maybe_dead (insn); 13460 } 13461 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1) 13462 { 13463 rtx tempLR = (fromprolog 13464 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) 13465 : gen_reg_rtx (Pmode)); 13466 13467 insn = emit_insn (gen_load_toc_v4_pic_si (tempLR)); 13468 if (fromprolog) 13469 rs6000_maybe_dead (insn); 13470 insn = emit_move_insn (dest, tempLR); 13471 if (fromprolog) 13472 rs6000_maybe_dead (insn); 13473 } 13474 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2) 13475 { 13476 char buf[30]; 13477 rtx tempLR = (fromprolog 13478 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) 13479 : gen_reg_rtx (Pmode)); 13480 rtx temp0 = (fromprolog 13481 ? gen_rtx_REG (Pmode, 0) 13482 : gen_reg_rtx (Pmode)); 13483 13484 if (fromprolog) 13485 { 13486 rtx symF, symL; 13487 13488 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); 13489 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 13490 13491 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); 13492 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 13493 13494 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, 13495 symF))); 13496 rs6000_maybe_dead (emit_move_insn (dest, tempLR)); 13497 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, 13498 symL, 13499 symF))); 13500 } 13501 else 13502 { 13503 rtx tocsym; 13504 13505 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); 13506 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym)); 13507 emit_move_insn (dest, tempLR); 13508 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest)); 13509 } 13510 insn = emit_insn (gen_addsi3 (dest, temp0, dest)); 13511 if (fromprolog) 13512 rs6000_maybe_dead (insn); 13513 } 13514 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC) 13515 { 13516 /* This is for AIX code running in non-PIC ELF32. */ 13517 char buf[30]; 13518 rtx realsym; 13519 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); 13520 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 13521 13522 insn = emit_insn (gen_elf_high (dest, realsym)); 13523 if (fromprolog) 13524 rs6000_maybe_dead (insn); 13525 insn = emit_insn (gen_elf_low (dest, dest, realsym)); 13526 if (fromprolog) 13527 rs6000_maybe_dead (insn); 13528 } 13529 else 13530 { 13531 gcc_assert (DEFAULT_ABI == ABI_AIX); 13532 13533 if (TARGET_32BIT) 13534 insn = emit_insn (gen_load_toc_aix_si (dest)); 13535 else 13536 insn = emit_insn (gen_load_toc_aix_di (dest)); 13537 if (fromprolog) 13538 rs6000_maybe_dead (insn); 13539 } 13540} 13541 13542/* Emit instructions to restore the link register after determining where 13543 its value has been stored. */ 13544 13545void 13546rs6000_emit_eh_reg_restore (rtx source, rtx scratch) 13547{ 13548 rs6000_stack_t *info = rs6000_stack_info (); 13549 rtx operands[2]; 13550 13551 operands[0] = source; 13552 operands[1] = scratch; 13553 13554 if (info->lr_save_p) 13555 { 13556 rtx frame_rtx = stack_pointer_rtx; 13557 HOST_WIDE_INT sp_offset = 0; 13558 rtx tmp; 13559 13560 if (frame_pointer_needed 13561 || current_function_calls_alloca 13562 || info->total_size > 32767) 13563 { 13564 tmp = gen_rtx_MEM (Pmode, frame_rtx); 13565 MEM_NOTRAP_P (tmp) = 1; 13566 set_mem_alias_set (tmp, rs6000_sr_alias_set); 13567 emit_move_insn (operands[1], tmp); 13568 frame_rtx = operands[1]; 13569 } 13570 else if (info->push_p) 13571 sp_offset = info->total_size; 13572 13573 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); 13574 tmp = gen_rtx_MEM (Pmode, tmp); 13575 MEM_NOTRAP_P (tmp) = 1; 13576 set_mem_alias_set (tmp, rs6000_sr_alias_set); 13577 emit_move_insn (tmp, operands[0]); 13578 } 13579 else 13580 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); 13581} 13582 13583static GTY(()) int set = -1; 13584 13585int 13586get_TOC_alias_set (void) 13587{ 13588 if (set == -1) 13589 set = new_alias_set (); 13590 return set; 13591} 13592 13593/* This returns nonzero if the current function uses the TOC. This is 13594 determined by the presence of (use (unspec ... UNSPEC_TOC)), which 13595 is generated by the ABI_V4 load_toc_* patterns. */ 13596#if TARGET_ELF 13597static int 13598uses_TOC (void) 13599{ 13600 rtx insn; 13601 13602 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 13603 if (INSN_P (insn)) 13604 { 13605 rtx pat = PATTERN (insn); 13606 int i; 13607 13608 if (GET_CODE (pat) == PARALLEL) 13609 for (i = 0; i < XVECLEN (pat, 0); i++) 13610 { 13611 rtx sub = XVECEXP (pat, 0, i); 13612 if (GET_CODE (sub) == USE) 13613 { 13614 sub = XEXP (sub, 0); 13615 if (GET_CODE (sub) == UNSPEC 13616 && XINT (sub, 1) == UNSPEC_TOC) 13617 return 1; 13618 } 13619 } 13620 } 13621 return 0; 13622} 13623#endif 13624 13625rtx 13626create_TOC_reference (rtx symbol) 13627{ 13628 if (no_new_pseudos) 13629 regs_ever_live[TOC_REGISTER] = 1; 13630 return gen_rtx_PLUS (Pmode, 13631 gen_rtx_REG (Pmode, TOC_REGISTER), 13632 gen_rtx_CONST (Pmode, 13633 gen_rtx_MINUS (Pmode, symbol, 13634 gen_rtx_SYMBOL_REF (Pmode, toc_label_name)))); 13635} 13636 13637/* If _Unwind_* has been called from within the same module, 13638 toc register is not guaranteed to be saved to 40(1) on function 13639 entry. Save it there in that case. */ 13640 13641void 13642rs6000_aix_emit_builtin_unwind_init (void) 13643{ 13644 rtx mem; 13645 rtx stack_top = gen_reg_rtx (Pmode); 13646 rtx opcode_addr = gen_reg_rtx (Pmode); 13647 rtx opcode = gen_reg_rtx (SImode); 13648 rtx tocompare = gen_reg_rtx (SImode); 13649 rtx no_toc_save_needed = gen_label_rtx (); 13650 13651 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx); 13652 emit_move_insn (stack_top, mem); 13653 13654 mem = gen_frame_mem (Pmode, 13655 gen_rtx_PLUS (Pmode, stack_top, 13656 GEN_INT (2 * GET_MODE_SIZE (Pmode)))); 13657 emit_move_insn (opcode_addr, mem); 13658 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); 13659 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014 13660 : 0xE8410028, SImode)); 13661 13662 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1, 13663 SImode, NULL_RTX, NULL_RTX, 13664 no_toc_save_needed); 13665 13666 mem = gen_frame_mem (Pmode, 13667 gen_rtx_PLUS (Pmode, stack_top, 13668 GEN_INT (5 * GET_MODE_SIZE (Pmode)))); 13669 emit_move_insn (mem, gen_rtx_REG (Pmode, 2)); 13670 emit_label (no_toc_save_needed); 13671} 13672 13673/* This ties together stack memory (MEM with an alias set of 13674 rs6000_sr_alias_set) and the change to the stack pointer. */ 13675 13676static void 13677rs6000_emit_stack_tie (void) 13678{ 13679 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); 13680 13681 set_mem_alias_set (mem, rs6000_sr_alias_set); 13682 emit_insn (gen_stack_tie (mem)); 13683} 13684 13685/* Emit the correct code for allocating stack space, as insns. 13686 If COPY_R12, make sure a copy of the old frame is left in r12. 13687 The generated code may use hard register 0 as a temporary. */ 13688 13689static void 13690rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12) 13691{ 13692 rtx insn; 13693 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); 13694 rtx tmp_reg = gen_rtx_REG (Pmode, 0); 13695 rtx todec = gen_int_mode (-size, Pmode); 13696 13697 if (INTVAL (todec) != -size) 13698 { 13699 warning (0, "stack frame too large"); 13700 emit_insn (gen_trap ()); 13701 return; 13702 } 13703 13704 if (current_function_limit_stack) 13705 { 13706 if (REG_P (stack_limit_rtx) 13707 && REGNO (stack_limit_rtx) > 1 13708 && REGNO (stack_limit_rtx) <= 31) 13709 { 13710 emit_insn (TARGET_32BIT 13711 ? gen_addsi3 (tmp_reg, 13712 stack_limit_rtx, 13713 GEN_INT (size)) 13714 : gen_adddi3 (tmp_reg, 13715 stack_limit_rtx, 13716 GEN_INT (size))); 13717 13718 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, 13719 const0_rtx)); 13720 } 13721 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF 13722 && TARGET_32BIT 13723 && DEFAULT_ABI == ABI_V4) 13724 { 13725 rtx toload = gen_rtx_CONST (VOIDmode, 13726 gen_rtx_PLUS (Pmode, 13727 stack_limit_rtx, 13728 GEN_INT (size))); 13729 13730 emit_insn (gen_elf_high (tmp_reg, toload)); 13731 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); 13732 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, 13733 const0_rtx)); 13734 } 13735 else 13736 warning (0, "stack limit expression is not supported"); 13737 } 13738 13739 if (copy_r12 || ! TARGET_UPDATE) 13740 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); 13741 13742 if (TARGET_UPDATE) 13743 { 13744 if (size > 32767) 13745 { 13746 /* Need a note here so that try_split doesn't get confused. */ 13747 if (get_last_insn () == NULL_RTX) 13748 emit_note (NOTE_INSN_DELETED); 13749 insn = emit_move_insn (tmp_reg, todec); 13750 try_split (PATTERN (insn), insn, 0); 13751 todec = tmp_reg; 13752 } 13753 13754 insn = emit_insn (TARGET_32BIT 13755 ? gen_movsi_update (stack_reg, stack_reg, 13756 todec, stack_reg) 13757 : gen_movdi_di_update (stack_reg, stack_reg, 13758 todec, stack_reg)); 13759 } 13760 else 13761 { 13762 insn = emit_insn (TARGET_32BIT 13763 ? gen_addsi3 (stack_reg, stack_reg, todec) 13764 : gen_adddi3 (stack_reg, stack_reg, todec)); 13765 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), 13766 gen_rtx_REG (Pmode, 12)); 13767 } 13768 13769 RTX_FRAME_RELATED_P (insn) = 1; 13770 REG_NOTES (insn) = 13771 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, 13772 gen_rtx_SET (VOIDmode, stack_reg, 13773 gen_rtx_PLUS (Pmode, stack_reg, 13774 GEN_INT (-size))), 13775 REG_NOTES (insn)); 13776} 13777 13778/* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced 13779 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 13780 is not NULL. It would be nice if dwarf2out_frame_debug_expr could 13781 deduce these equivalences by itself so it wasn't necessary to hold 13782 its hand so much. */ 13783 13784static void 13785rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, 13786 rtx reg2, rtx rreg) 13787{ 13788 rtx real, temp; 13789 13790 /* copy_rtx will not make unique copies of registers, so we need to 13791 ensure we don't have unwanted sharing here. */ 13792 if (reg == reg2) 13793 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); 13794 13795 if (reg == rreg) 13796 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); 13797 13798 real = copy_rtx (PATTERN (insn)); 13799 13800 if (reg2 != NULL_RTX) 13801 real = replace_rtx (real, reg2, rreg); 13802 13803 real = replace_rtx (real, reg, 13804 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 13805 STACK_POINTER_REGNUM), 13806 GEN_INT (val))); 13807 13808 /* We expect that 'real' is either a SET or a PARALLEL containing 13809 SETs (and possibly other stuff). In a PARALLEL, all the SETs 13810 are important so they all have to be marked RTX_FRAME_RELATED_P. */ 13811 13812 if (GET_CODE (real) == SET) 13813 { 13814 rtx set = real; 13815 13816 temp = simplify_rtx (SET_SRC (set)); 13817 if (temp) 13818 SET_SRC (set) = temp; 13819 temp = simplify_rtx (SET_DEST (set)); 13820 if (temp) 13821 SET_DEST (set) = temp; 13822 if (GET_CODE (SET_DEST (set)) == MEM) 13823 { 13824 temp = simplify_rtx (XEXP (SET_DEST (set), 0)); 13825 if (temp) 13826 XEXP (SET_DEST (set), 0) = temp; 13827 } 13828 } 13829 else 13830 { 13831 int i; 13832 13833 gcc_assert (GET_CODE (real) == PARALLEL); 13834 for (i = 0; i < XVECLEN (real, 0); i++) 13835 if (GET_CODE (XVECEXP (real, 0, i)) == SET) 13836 { 13837 rtx set = XVECEXP (real, 0, i); 13838 13839 temp = simplify_rtx (SET_SRC (set)); 13840 if (temp) 13841 SET_SRC (set) = temp; 13842 temp = simplify_rtx (SET_DEST (set)); 13843 if (temp) 13844 SET_DEST (set) = temp; 13845 if (GET_CODE (SET_DEST (set)) == MEM) 13846 { 13847 temp = simplify_rtx (XEXP (SET_DEST (set), 0)); 13848 if (temp) 13849 XEXP (SET_DEST (set), 0) = temp; 13850 } 13851 RTX_FRAME_RELATED_P (set) = 1; 13852 } 13853 } 13854 13855 if (TARGET_SPE) 13856 real = spe_synthesize_frame_save (real); 13857 13858 RTX_FRAME_RELATED_P (insn) = 1; 13859 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, 13860 real, 13861 REG_NOTES (insn)); 13862} 13863 13864/* Given an SPE frame note, return a PARALLEL of SETs with the 13865 original note, plus a synthetic register save. */ 13866 13867static rtx 13868spe_synthesize_frame_save (rtx real) 13869{ 13870 rtx synth, offset, reg, real2; 13871 13872 if (GET_CODE (real) != SET 13873 || GET_MODE (SET_SRC (real)) != V2SImode) 13874 return real; 13875 13876 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their 13877 frame related note. The parallel contains a set of the register 13878 being saved, and another set to a synthetic register (n+1200). 13879 This is so we can differentiate between 64-bit and 32-bit saves. 13880 Words cannot describe this nastiness. */ 13881 13882 gcc_assert (GET_CODE (SET_DEST (real)) == MEM 13883 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS 13884 && GET_CODE (SET_SRC (real)) == REG); 13885 13886 /* Transform: 13887 (set (mem (plus (reg x) (const y))) 13888 (reg z)) 13889 into: 13890 (set (mem (plus (reg x) (const y+4))) 13891 (reg z+1200)) 13892 */ 13893 13894 real2 = copy_rtx (real); 13895 PUT_MODE (SET_DEST (real2), SImode); 13896 reg = SET_SRC (real2); 13897 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg))); 13898 synth = copy_rtx (real2); 13899 13900 if (BYTES_BIG_ENDIAN) 13901 { 13902 offset = XEXP (XEXP (SET_DEST (real2), 0), 1); 13903 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4)); 13904 } 13905 13906 reg = SET_SRC (synth); 13907 13908 synth = replace_rtx (synth, reg, 13909 gen_rtx_REG (SImode, REGNO (reg) + 1200)); 13910 13911 offset = XEXP (XEXP (SET_DEST (synth), 0), 1); 13912 synth = replace_rtx (synth, offset, 13913 GEN_INT (INTVAL (offset) 13914 + (BYTES_BIG_ENDIAN ? 0 : 4))); 13915 13916 RTX_FRAME_RELATED_P (synth) = 1; 13917 RTX_FRAME_RELATED_P (real2) = 1; 13918 if (BYTES_BIG_ENDIAN) 13919 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2)); 13920 else 13921 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth)); 13922 13923 return real; 13924} 13925 13926/* Returns an insn that has a vrsave set operation with the 13927 appropriate CLOBBERs. */ 13928 13929static rtx 13930generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep) 13931{ 13932 int nclobs, i; 13933 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1]; 13934 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); 13935 13936 clobs[0] 13937 = gen_rtx_SET (VOIDmode, 13938 vrsave, 13939 gen_rtx_UNSPEC_VOLATILE (SImode, 13940 gen_rtvec (2, reg, vrsave), 13941 UNSPECV_SET_VRSAVE)); 13942 13943 nclobs = 1; 13944 13945 /* We need to clobber the registers in the mask so the scheduler 13946 does not move sets to VRSAVE before sets of AltiVec registers. 13947 13948 However, if the function receives nonlocal gotos, reload will set 13949 all call saved registers live. We will end up with: 13950 13951 (set (reg 999) (mem)) 13952 (parallel [ (set (reg vrsave) (unspec blah)) 13953 (clobber (reg 999))]) 13954 13955 The clobber will cause the store into reg 999 to be dead, and 13956 flow will attempt to delete an epilogue insn. In this case, we 13957 need an unspec use/set of the register. */ 13958 13959 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) 13960 if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) 13961 { 13962 if (!epiloguep || call_used_regs [i]) 13963 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode, 13964 gen_rtx_REG (V4SImode, i)); 13965 else 13966 { 13967 rtx reg = gen_rtx_REG (V4SImode, i); 13968 13969 clobs[nclobs++] 13970 = gen_rtx_SET (VOIDmode, 13971 reg, 13972 gen_rtx_UNSPEC (V4SImode, 13973 gen_rtvec (1, reg), 27)); 13974 } 13975 } 13976 13977 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs)); 13978 13979 for (i = 0; i < nclobs; ++i) 13980 XVECEXP (insn, 0, i) = clobs[i]; 13981 13982 return insn; 13983} 13984 13985/* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes. 13986 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */ 13987 13988static void 13989emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode, 13990 unsigned int regno, int offset, HOST_WIDE_INT total_size) 13991{ 13992 rtx reg, offset_rtx, insn, mem, addr, int_rtx; 13993 rtx replacea, replaceb; 13994 13995 int_rtx = GEN_INT (offset); 13996 13997 /* Some cases that need register indexed addressing. */ 13998 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) 13999 || (TARGET_E500_DOUBLE && mode == DFmode) 14000 || (TARGET_SPE_ABI 14001 && SPE_VECTOR_MODE (mode) 14002 && !SPE_CONST_OFFSET_OK (offset))) 14003 { 14004 /* Whomever calls us must make sure r11 is available in the 14005 flow path of instructions in the prologue. */ 14006 offset_rtx = gen_rtx_REG (Pmode, 11); 14007 emit_move_insn (offset_rtx, int_rtx); 14008 14009 replacea = offset_rtx; 14010 replaceb = int_rtx; 14011 } 14012 else 14013 { 14014 offset_rtx = int_rtx; 14015 replacea = NULL_RTX; 14016 replaceb = NULL_RTX; 14017 } 14018 14019 reg = gen_rtx_REG (mode, regno); 14020 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx); 14021 mem = gen_rtx_MEM (mode, addr); 14022 set_mem_alias_set (mem, rs6000_sr_alias_set); 14023 14024 insn = emit_move_insn (mem, reg); 14025 14026 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb); 14027} 14028 14029/* Emit an offset memory reference suitable for a frame store, while 14030 converting to a valid addressing mode. */ 14031 14032static rtx 14033gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset) 14034{ 14035 rtx int_rtx, offset_rtx; 14036 14037 int_rtx = GEN_INT (offset); 14038 14039 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode)) 14040 || (TARGET_E500_DOUBLE && mode == DFmode)) 14041 { 14042 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH); 14043 emit_move_insn (offset_rtx, int_rtx); 14044 } 14045 else 14046 offset_rtx = int_rtx; 14047 14048 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx)); 14049} 14050 14051/* Look for user-defined global regs. We should not save and restore these, 14052 and cannot use stmw/lmw if there are any in its range. */ 14053 14054static bool 14055no_global_regs_above (int first_greg) 14056{ 14057 int i; 14058 for (i = 0; i < 32 - first_greg; i++) 14059 if (global_regs[first_greg + i]) 14060 return false; 14061 return true; 14062} 14063 14064#ifndef TARGET_FIX_AND_CONTINUE 14065#define TARGET_FIX_AND_CONTINUE 0 14066#endif 14067 14068/* Emit function prologue as insns. */ 14069 14070void 14071rs6000_emit_prologue (void) 14072{ 14073 rs6000_stack_t *info = rs6000_stack_info (); 14074 enum machine_mode reg_mode = Pmode; 14075 int reg_size = TARGET_32BIT ? 4 : 8; 14076 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); 14077 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); 14078 rtx frame_reg_rtx = sp_reg_rtx; 14079 rtx cr_save_rtx = NULL_RTX; 14080 rtx insn; 14081 int saving_FPRs_inline; 14082 int using_store_multiple; 14083 HOST_WIDE_INT sp_offset = 0; 14084 14085 if (TARGET_FIX_AND_CONTINUE) 14086 { 14087 /* gdb on darwin arranges to forward a function from the old 14088 address by modifying the first 5 instructions of the function 14089 to branch to the overriding function. This is necessary to 14090 permit function pointers that point to the old function to 14091 actually forward to the new function. */ 14092 emit_insn (gen_nop ()); 14093 emit_insn (gen_nop ()); 14094 emit_insn (gen_nop ()); 14095 emit_insn (gen_nop ()); 14096 emit_insn (gen_nop ()); 14097 } 14098 14099 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) 14100 { 14101 reg_mode = V2SImode; 14102 reg_size = 8; 14103 } 14104 14105 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 14106 && (!TARGET_SPE_ABI 14107 || info->spe_64bit_regs_used == 0) 14108 && info->first_gp_reg_save < 31 14109 && no_global_regs_above (info->first_gp_reg_save)); 14110 saving_FPRs_inline = (info->first_fp_reg_save == 64 14111 || FP_SAVE_INLINE (info->first_fp_reg_save) 14112 || current_function_calls_eh_return 14113 || cfun->machine->ra_need_lr); 14114 14115 /* For V.4, update stack before we do any saving and set back pointer. */ 14116 if (info->push_p 14117 && (DEFAULT_ABI == ABI_V4 14118 || current_function_calls_eh_return)) 14119 { 14120 if (info->total_size < 32767) 14121 sp_offset = info->total_size; 14122 else 14123 frame_reg_rtx = frame_ptr_rtx; 14124 rs6000_emit_allocate_stack (info->total_size, 14125 (frame_reg_rtx != sp_reg_rtx 14126 && (info->cr_save_p 14127 || info->lr_save_p 14128 || info->first_fp_reg_save < 64 14129 || info->first_gp_reg_save < 32 14130 ))); 14131 if (frame_reg_rtx != sp_reg_rtx) 14132 rs6000_emit_stack_tie (); 14133 } 14134 14135 /* Handle world saves specially here. */ 14136 if (WORLD_SAVE_P (info)) 14137 { 14138 int i, j, sz; 14139 rtx treg; 14140 rtvec p; 14141 14142 /* save_world expects lr in r0. */ 14143 if (info->lr_save_p) 14144 { 14145 insn = emit_move_insn (gen_rtx_REG (Pmode, 0), 14146 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); 14147 RTX_FRAME_RELATED_P (insn) = 1; 14148 } 14149 14150 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of 14151 assumptions about the offsets of various bits of the stack 14152 frame. */ 14153 gcc_assert (info->gp_save_offset == -220 14154 && info->fp_save_offset == -144 14155 && info->lr_save_offset == 8 14156 && info->cr_save_offset == 4 14157 && info->push_p 14158 && info->lr_save_p 14159 && (!current_function_calls_eh_return 14160 || info->ehrd_offset == -432) 14161 && info->vrsave_save_offset == -224 14162 && info->altivec_save_offset == (-224 -16 -192)); 14163 14164 treg = gen_rtx_REG (SImode, 11); 14165 emit_move_insn (treg, GEN_INT (-info->total_size)); 14166 14167 /* SAVE_WORLD takes the caller's LR in R0 and the frame size 14168 in R11. It also clobbers R12, so beware! */ 14169 14170 /* Preserve CR2 for save_world prologues */ 14171 sz = 6; 14172 sz += 32 - info->first_gp_reg_save; 14173 sz += 64 - info->first_fp_reg_save; 14174 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1; 14175 p = rtvec_alloc (sz); 14176 j = 0; 14177 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, 14178 gen_rtx_REG (Pmode, 14179 LINK_REGISTER_REGNUM)); 14180 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, 14181 gen_rtx_SYMBOL_REF (Pmode, 14182 "*save_world")); 14183 /* We do floats first so that the instruction pattern matches 14184 properly. */ 14185 for (i = 0; i < 64 - info->first_fp_reg_save; i++) 14186 { 14187 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); 14188 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 14189 GEN_INT (info->fp_save_offset 14190 + sp_offset + 8 * i)); 14191 rtx mem = gen_rtx_MEM (DFmode, addr); 14192 set_mem_alias_set (mem, rs6000_sr_alias_set); 14193 14194 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); 14195 } 14196 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++) 14197 { 14198 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i); 14199 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 14200 GEN_INT (info->altivec_save_offset 14201 + sp_offset + 16 * i)); 14202 rtx mem = gen_rtx_MEM (V4SImode, addr); 14203 set_mem_alias_set (mem, rs6000_sr_alias_set); 14204 14205 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); 14206 } 14207 for (i = 0; i < 32 - info->first_gp_reg_save; i++) 14208 { 14209 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); 14210 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 14211 GEN_INT (info->gp_save_offset 14212 + sp_offset + reg_size * i)); 14213 rtx mem = gen_rtx_MEM (reg_mode, addr); 14214 set_mem_alias_set (mem, rs6000_sr_alias_set); 14215 14216 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); 14217 } 14218 14219 { 14220 /* CR register traditionally saved as CR2. */ 14221 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO); 14222 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 14223 GEN_INT (info->cr_save_offset 14224 + sp_offset)); 14225 rtx mem = gen_rtx_MEM (reg_mode, addr); 14226 set_mem_alias_set (mem, rs6000_sr_alias_set); 14227 14228 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); 14229 } 14230 /* Prevent any attempt to delete the setting of r0 and treg! */ 14231 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0)); 14232 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg); 14233 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx); 14234 14235 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); 14236 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, 14237 NULL_RTX, NULL_RTX); 14238 14239 if (current_function_calls_eh_return) 14240 { 14241 unsigned int i; 14242 for (i = 0; ; ++i) 14243 { 14244 unsigned int regno = EH_RETURN_DATA_REGNO (i); 14245 if (regno == INVALID_REGNUM) 14246 break; 14247 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, 14248 info->ehrd_offset + sp_offset 14249 + reg_size * (int) i, 14250 info->total_size); 14251 } 14252 } 14253 } 14254 14255 /* Save AltiVec registers if needed. */ 14256 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0) 14257 { 14258 int i; 14259 14260 /* There should be a non inline version of this, for when we 14261 are saving lots of vector registers. */ 14262 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) 14263 if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) 14264 { 14265 rtx areg, savereg, mem; 14266 int offset; 14267 14268 offset = info->altivec_save_offset + sp_offset 14269 + 16 * (i - info->first_altivec_reg_save); 14270 14271 savereg = gen_rtx_REG (V4SImode, i); 14272 14273 areg = gen_rtx_REG (Pmode, 0); 14274 emit_move_insn (areg, GEN_INT (offset)); 14275 14276 /* AltiVec addressing mode is [reg+reg]. */ 14277 mem = gen_rtx_MEM (V4SImode, 14278 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg)); 14279 14280 set_mem_alias_set (mem, rs6000_sr_alias_set); 14281 14282 insn = emit_move_insn (mem, savereg); 14283 14284 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, 14285 areg, GEN_INT (offset)); 14286 } 14287 } 14288 14289 /* VRSAVE is a bit vector representing which AltiVec registers 14290 are used. The OS uses this to determine which vector 14291 registers to save on a context switch. We need to save 14292 VRSAVE on the stack frame, add whatever AltiVec registers we 14293 used in this function, and do the corresponding magic in the 14294 epilogue. */ 14295 14296 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE 14297 && info->vrsave_mask != 0) 14298 { 14299 rtx reg, mem, vrsave; 14300 int offset; 14301 14302 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12 14303 as frame_reg_rtx and r11 as the static chain pointer for 14304 nested functions. */ 14305 reg = gen_rtx_REG (SImode, 0); 14306 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); 14307 if (TARGET_MACHO) 14308 emit_insn (gen_get_vrsave_internal (reg)); 14309 else 14310 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave)); 14311 14312 if (!WORLD_SAVE_P (info)) 14313 { 14314 /* Save VRSAVE. */ 14315 offset = info->vrsave_save_offset + sp_offset; 14316 mem 14317 = gen_rtx_MEM (SImode, 14318 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset))); 14319 set_mem_alias_set (mem, rs6000_sr_alias_set); 14320 insn = emit_move_insn (mem, reg); 14321 } 14322 14323 /* Include the registers in the mask. */ 14324 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask))); 14325 14326 insn = emit_insn (generate_set_vrsave (reg, info, 0)); 14327 } 14328 14329 /* If we use the link register, get it into r0. */ 14330 if (!WORLD_SAVE_P (info) && info->lr_save_p) 14331 { 14332 insn = emit_move_insn (gen_rtx_REG (Pmode, 0), 14333 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); 14334 RTX_FRAME_RELATED_P (insn) = 1; 14335 } 14336 14337 /* If we need to save CR, put it into r12. */ 14338 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) 14339 { 14340 rtx set; 14341 14342 cr_save_rtx = gen_rtx_REG (SImode, 12); 14343 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); 14344 RTX_FRAME_RELATED_P (insn) = 1; 14345 /* Now, there's no way that dwarf2out_frame_debug_expr is going 14346 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'. 14347 But that's OK. All we have to do is specify that _one_ condition 14348 code register is saved in this stack slot. The thrower's epilogue 14349 will then restore all the call-saved registers. 14350 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ 14351 set = gen_rtx_SET (VOIDmode, cr_save_rtx, 14352 gen_rtx_REG (SImode, CR2_REGNO)); 14353 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, 14354 set, 14355 REG_NOTES (insn)); 14356 } 14357 14358 /* Do any required saving of fpr's. If only one or two to save, do 14359 it ourselves. Otherwise, call function. */ 14360 if (!WORLD_SAVE_P (info) && saving_FPRs_inline) 14361 { 14362 int i; 14363 for (i = 0; i < 64 - info->first_fp_reg_save; i++) 14364 if ((regs_ever_live[info->first_fp_reg_save+i] 14365 && ! call_used_regs[info->first_fp_reg_save+i])) 14366 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode, 14367 info->first_fp_reg_save + i, 14368 info->fp_save_offset + sp_offset + 8 * i, 14369 info->total_size); 14370 } 14371 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64) 14372 { 14373 int i; 14374 char rname[30]; 14375 const char *alloc_rname; 14376 rtvec p; 14377 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); 14378 14379 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, 14380 gen_rtx_REG (Pmode, 14381 LINK_REGISTER_REGNUM)); 14382 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, 14383 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); 14384 alloc_rname = ggc_strdup (rname); 14385 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, 14386 gen_rtx_SYMBOL_REF (Pmode, 14387 alloc_rname)); 14388 for (i = 0; i < 64 - info->first_fp_reg_save; i++) 14389 { 14390 rtx addr, reg, mem; 14391 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); 14392 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 14393 GEN_INT (info->fp_save_offset 14394 + sp_offset + 8*i)); 14395 mem = gen_rtx_MEM (DFmode, addr); 14396 set_mem_alias_set (mem, rs6000_sr_alias_set); 14397 14398 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); 14399 } 14400 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); 14401 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, 14402 NULL_RTX, NULL_RTX); 14403 } 14404 14405 /* Save GPRs. This is done as a PARALLEL if we are using 14406 the store-multiple instructions. */ 14407 if (!WORLD_SAVE_P (info) && using_store_multiple) 14408 { 14409 rtvec p; 14410 int i; 14411 p = rtvec_alloc (32 - info->first_gp_reg_save); 14412 for (i = 0; i < 32 - info->first_gp_reg_save; i++) 14413 { 14414 rtx addr, reg, mem; 14415 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); 14416 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 14417 GEN_INT (info->gp_save_offset 14418 + sp_offset 14419 + reg_size * i)); 14420 mem = gen_rtx_MEM (reg_mode, addr); 14421 set_mem_alias_set (mem, rs6000_sr_alias_set); 14422 14423 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); 14424 } 14425 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); 14426 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, 14427 NULL_RTX, NULL_RTX); 14428 } 14429 else if (!WORLD_SAVE_P (info)) 14430 { 14431 int i; 14432 for (i = 0; i < 32 - info->first_gp_reg_save; i++) 14433 if ((regs_ever_live[info->first_gp_reg_save + i] 14434 && (!call_used_regs[info->first_gp_reg_save + i] 14435 || (i + info->first_gp_reg_save 14436 == RS6000_PIC_OFFSET_TABLE_REGNUM 14437 && TARGET_TOC && TARGET_MINIMAL_TOC))) 14438 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM 14439 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) 14440 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) 14441 { 14442 rtx addr, reg, mem; 14443 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); 14444 14445 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) 14446 { 14447 int offset = info->spe_gp_save_offset + sp_offset + 8 * i; 14448 rtx b; 14449 14450 if (!SPE_CONST_OFFSET_OK (offset)) 14451 { 14452 b = gen_rtx_REG (Pmode, FIXED_SCRATCH); 14453 emit_move_insn (b, GEN_INT (offset)); 14454 } 14455 else 14456 b = GEN_INT (offset); 14457 14458 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); 14459 mem = gen_rtx_MEM (V2SImode, addr); 14460 set_mem_alias_set (mem, rs6000_sr_alias_set); 14461 insn = emit_move_insn (mem, reg); 14462 14463 if (GET_CODE (b) == CONST_INT) 14464 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, 14465 NULL_RTX, NULL_RTX); 14466 else 14467 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, 14468 b, GEN_INT (offset)); 14469 } 14470 else 14471 { 14472 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 14473 GEN_INT (info->gp_save_offset 14474 + sp_offset 14475 + reg_size * i)); 14476 mem = gen_rtx_MEM (reg_mode, addr); 14477 set_mem_alias_set (mem, rs6000_sr_alias_set); 14478 14479 insn = emit_move_insn (mem, reg); 14480 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, 14481 NULL_RTX, NULL_RTX); 14482 } 14483 } 14484 } 14485 14486 /* ??? There's no need to emit actual instructions here, but it's the 14487 easiest way to get the frame unwind information emitted. */ 14488 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return) 14489 { 14490 unsigned int i, regno; 14491 14492 /* In AIX ABI we need to pretend we save r2 here. */ 14493 if (TARGET_AIX) 14494 { 14495 rtx addr, reg, mem; 14496 14497 reg = gen_rtx_REG (reg_mode, 2); 14498 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 14499 GEN_INT (sp_offset + 5 * reg_size)); 14500 mem = gen_rtx_MEM (reg_mode, addr); 14501 set_mem_alias_set (mem, rs6000_sr_alias_set); 14502 14503 insn = emit_move_insn (mem, reg); 14504 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, 14505 NULL_RTX, NULL_RTX); 14506 PATTERN (insn) = gen_blockage (); 14507 } 14508 14509 for (i = 0; ; ++i) 14510 { 14511 regno = EH_RETURN_DATA_REGNO (i); 14512 if (regno == INVALID_REGNUM) 14513 break; 14514 14515 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, 14516 info->ehrd_offset + sp_offset 14517 + reg_size * (int) i, 14518 info->total_size); 14519 } 14520 } 14521 14522 /* Save lr if we used it. */ 14523 if (!WORLD_SAVE_P (info) && info->lr_save_p) 14524 { 14525 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 14526 GEN_INT (info->lr_save_offset + sp_offset)); 14527 rtx reg = gen_rtx_REG (Pmode, 0); 14528 rtx mem = gen_rtx_MEM (Pmode, addr); 14529 /* This should not be of rs6000_sr_alias_set, because of 14530 __builtin_return_address. */ 14531 14532 insn = emit_move_insn (mem, reg); 14533 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, 14534 NULL_RTX, NULL_RTX); 14535 } 14536 14537 /* Save CR if we use any that must be preserved. */ 14538 if (!WORLD_SAVE_P (info) && info->cr_save_p) 14539 { 14540 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 14541 GEN_INT (info->cr_save_offset + sp_offset)); 14542 rtx mem = gen_rtx_MEM (SImode, addr); 14543 /* See the large comment above about why CR2_REGNO is used. */ 14544 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO); 14545 14546 set_mem_alias_set (mem, rs6000_sr_alias_set); 14547 14548 /* If r12 was used to hold the original sp, copy cr into r0 now 14549 that it's free. */ 14550 if (REGNO (frame_reg_rtx) == 12) 14551 { 14552 rtx set; 14553 14554 cr_save_rtx = gen_rtx_REG (SImode, 0); 14555 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); 14556 RTX_FRAME_RELATED_P (insn) = 1; 14557 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg); 14558 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, 14559 set, 14560 REG_NOTES (insn)); 14561 14562 } 14563 insn = emit_move_insn (mem, cr_save_rtx); 14564 14565 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, 14566 NULL_RTX, NULL_RTX); 14567 } 14568 14569 /* Update stack and set back pointer unless this is V.4, 14570 for which it was done previously. */ 14571 if (!WORLD_SAVE_P (info) && info->push_p 14572 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return)) 14573 rs6000_emit_allocate_stack (info->total_size, FALSE); 14574 14575 /* Set frame pointer, if needed. */ 14576 if (frame_pointer_needed) 14577 { 14578 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), 14579 sp_reg_rtx); 14580 RTX_FRAME_RELATED_P (insn) = 1; 14581 } 14582 14583 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ 14584 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) 14585 || (DEFAULT_ABI == ABI_V4 14586 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT)) 14587 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])) 14588 { 14589 /* If emit_load_toc_table will use the link register, we need to save 14590 it. We use R12 for this purpose because emit_load_toc_table 14591 can use register 0. This allows us to use a plain 'blr' to return 14592 from the procedure more often. */ 14593 int save_LR_around_toc_setup = (TARGET_ELF 14594 && DEFAULT_ABI != ABI_AIX 14595 && flag_pic 14596 && ! info->lr_save_p 14597 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0); 14598 if (save_LR_around_toc_setup) 14599 { 14600 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); 14601 14602 insn = emit_move_insn (frame_ptr_rtx, lr); 14603 rs6000_maybe_dead (insn); 14604 RTX_FRAME_RELATED_P (insn) = 1; 14605 14606 rs6000_emit_load_toc_table (TRUE); 14607 14608 insn = emit_move_insn (lr, frame_ptr_rtx); 14609 rs6000_maybe_dead (insn); 14610 RTX_FRAME_RELATED_P (insn) = 1; 14611 } 14612 else 14613 rs6000_emit_load_toc_table (TRUE); 14614 } 14615 14616#if TARGET_MACHO 14617 if (DEFAULT_ABI == ABI_DARWIN 14618 && flag_pic && current_function_uses_pic_offset_table) 14619 { 14620 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); 14621 rtx src = machopic_function_base_sym (); 14622 14623 /* Save and restore LR locally around this call (in R0). */ 14624 if (!info->lr_save_p) 14625 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr)); 14626 14627 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src))); 14628 14629 insn = emit_move_insn (gen_rtx_REG (Pmode, 14630 RS6000_PIC_OFFSET_TABLE_REGNUM), 14631 lr); 14632 rs6000_maybe_dead (insn); 14633 14634 if (!info->lr_save_p) 14635 rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0))); 14636 } 14637#endif 14638} 14639 14640/* Write function prologue. */ 14641 14642static void 14643rs6000_output_function_prologue (FILE *file, 14644 HOST_WIDE_INT size ATTRIBUTE_UNUSED) 14645{ 14646 rs6000_stack_t *info = rs6000_stack_info (); 14647 14648 if (TARGET_DEBUG_STACK) 14649 debug_stack_info (info); 14650 14651 /* Write .extern for any function we will call to save and restore 14652 fp values. */ 14653 if (info->first_fp_reg_save < 64 14654 && !FP_SAVE_INLINE (info->first_fp_reg_save)) 14655 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", 14656 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, 14657 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, 14658 RESTORE_FP_SUFFIX); 14659 14660 /* Write .extern for AIX common mode routines, if needed. */ 14661 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) 14662 { 14663 fputs ("\t.extern __mulh\n", file); 14664 fputs ("\t.extern __mull\n", file); 14665 fputs ("\t.extern __divss\n", file); 14666 fputs ("\t.extern __divus\n", file); 14667 fputs ("\t.extern __quoss\n", file); 14668 fputs ("\t.extern __quous\n", file); 14669 common_mode_defined = 1; 14670 } 14671 14672 if (! HAVE_prologue) 14673 { 14674 start_sequence (); 14675 14676 /* A NOTE_INSN_DELETED is supposed to be at the start and end of 14677 the "toplevel" insn chain. */ 14678 emit_note (NOTE_INSN_DELETED); 14679 rs6000_emit_prologue (); 14680 emit_note (NOTE_INSN_DELETED); 14681 14682 /* Expand INSN_ADDRESSES so final() doesn't crash. */ 14683 { 14684 rtx insn; 14685 unsigned addr = 0; 14686 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) 14687 { 14688 INSN_ADDRESSES_NEW (insn, addr); 14689 addr += 4; 14690 } 14691 } 14692 14693 if (TARGET_DEBUG_STACK) 14694 debug_rtx_list (get_insns (), 100); 14695 final (get_insns (), file, FALSE); 14696 end_sequence (); 14697 } 14698 14699 rs6000_pic_labelno++; 14700} 14701 14702/* Emit function epilogue as insns. 14703 14704 At present, dwarf2out_frame_debug_expr doesn't understand 14705 register restores, so we don't bother setting RTX_FRAME_RELATED_P 14706 anywhere in the epilogue. Most of the insns below would in any case 14707 need special notes to explain where r11 is in relation to the stack. */ 14708 14709void 14710rs6000_emit_epilogue (int sibcall) 14711{ 14712 rs6000_stack_t *info; 14713 int restoring_FPRs_inline; 14714 int using_load_multiple; 14715 int using_mfcr_multiple; 14716 int use_backchain_to_restore_sp; 14717 int sp_offset = 0; 14718 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); 14719 rtx frame_reg_rtx = sp_reg_rtx; 14720 enum machine_mode reg_mode = Pmode; 14721 int reg_size = TARGET_32BIT ? 4 : 8; 14722 int i; 14723 14724 info = rs6000_stack_info (); 14725 14726 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) 14727 { 14728 reg_mode = V2SImode; 14729 reg_size = 8; 14730 } 14731 14732 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 14733 && (!TARGET_SPE_ABI 14734 || info->spe_64bit_regs_used == 0) 14735 && info->first_gp_reg_save < 31 14736 && no_global_regs_above (info->first_gp_reg_save)); 14737 restoring_FPRs_inline = (sibcall 14738 || current_function_calls_eh_return 14739 || info->first_fp_reg_save == 64 14740 || FP_SAVE_INLINE (info->first_fp_reg_save)); 14741 use_backchain_to_restore_sp = (frame_pointer_needed 14742 || current_function_calls_alloca 14743 || info->total_size > 32767); 14744 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 14745 || rs6000_cpu == PROCESSOR_PPC603 14746 || rs6000_cpu == PROCESSOR_PPC750 14747 || optimize_size); 14748 14749 if (WORLD_SAVE_P (info)) 14750 { 14751 int i, j; 14752 char rname[30]; 14753 const char *alloc_rname; 14754 rtvec p; 14755 14756 /* eh_rest_world_r10 will return to the location saved in the LR 14757 stack slot (which is not likely to be our caller.) 14758 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8. 14759 rest_world is similar, except any R10 parameter is ignored. 14760 The exception-handling stuff that was here in 2.95 is no 14761 longer necessary. */ 14762 14763 p = rtvec_alloc (9 14764 + 1 14765 + 32 - info->first_gp_reg_save 14766 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save 14767 + 63 + 1 - info->first_fp_reg_save); 14768 14769 strcpy (rname, ((current_function_calls_eh_return) ? 14770 "*eh_rest_world_r10" : "*rest_world")); 14771 alloc_rname = ggc_strdup (rname); 14772 14773 j = 0; 14774 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode); 14775 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, 14776 gen_rtx_REG (Pmode, 14777 LINK_REGISTER_REGNUM)); 14778 RTVEC_ELT (p, j++) 14779 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname)); 14780 /* The instruction pattern requires a clobber here; 14781 it is shared with the restVEC helper. */ 14782 RTVEC_ELT (p, j++) 14783 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11)); 14784 14785 { 14786 /* CR register traditionally saved as CR2. */ 14787 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO); 14788 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 14789 GEN_INT (info->cr_save_offset)); 14790 rtx mem = gen_rtx_MEM (reg_mode, addr); 14791 set_mem_alias_set (mem, rs6000_sr_alias_set); 14792 14793 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); 14794 } 14795 14796 for (i = 0; i < 32 - info->first_gp_reg_save; i++) 14797 { 14798 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); 14799 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 14800 GEN_INT (info->gp_save_offset 14801 + reg_size * i)); 14802 rtx mem = gen_rtx_MEM (reg_mode, addr); 14803 set_mem_alias_set (mem, rs6000_sr_alias_set); 14804 14805 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); 14806 } 14807 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++) 14808 { 14809 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i); 14810 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 14811 GEN_INT (info->altivec_save_offset 14812 + 16 * i)); 14813 rtx mem = gen_rtx_MEM (V4SImode, addr); 14814 set_mem_alias_set (mem, rs6000_sr_alias_set); 14815 14816 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); 14817 } 14818 for (i = 0; info->first_fp_reg_save + i <= 63; i++) 14819 { 14820 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); 14821 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 14822 GEN_INT (info->fp_save_offset 14823 + 8 * i)); 14824 rtx mem = gen_rtx_MEM (DFmode, addr); 14825 set_mem_alias_set (mem, rs6000_sr_alias_set); 14826 14827 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); 14828 } 14829 RTVEC_ELT (p, j++) 14830 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0)); 14831 RTVEC_ELT (p, j++) 14832 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12)); 14833 RTVEC_ELT (p, j++) 14834 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7)); 14835 RTVEC_ELT (p, j++) 14836 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8)); 14837 RTVEC_ELT (p, j++) 14838 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10)); 14839 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); 14840 14841 return; 14842 } 14843 14844 /* If we have a frame pointer, a call to alloca, or a large stack 14845 frame, restore the old stack pointer using the backchain. Otherwise, 14846 we know what size to update it with. */ 14847 if (use_backchain_to_restore_sp) 14848 { 14849 /* Under V.4, don't reset the stack pointer until after we're done 14850 loading the saved registers. */ 14851 if (DEFAULT_ABI == ABI_V4) 14852 frame_reg_rtx = gen_rtx_REG (Pmode, 11); 14853 14854 emit_move_insn (frame_reg_rtx, 14855 gen_rtx_MEM (Pmode, sp_reg_rtx)); 14856 14857 } 14858 else if (info->push_p) 14859 { 14860 if (DEFAULT_ABI == ABI_V4 14861 || current_function_calls_eh_return) 14862 sp_offset = info->total_size; 14863 else 14864 { 14865 emit_insn (TARGET_32BIT 14866 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, 14867 GEN_INT (info->total_size)) 14868 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, 14869 GEN_INT (info->total_size))); 14870 } 14871 } 14872 14873 /* Restore AltiVec registers if needed. */ 14874 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) 14875 { 14876 int i; 14877 14878 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) 14879 if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) 14880 { 14881 rtx addr, areg, mem; 14882 14883 areg = gen_rtx_REG (Pmode, 0); 14884 emit_move_insn 14885 (areg, GEN_INT (info->altivec_save_offset 14886 + sp_offset 14887 + 16 * (i - info->first_altivec_reg_save))); 14888 14889 /* AltiVec addressing mode is [reg+reg]. */ 14890 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); 14891 mem = gen_rtx_MEM (V4SImode, addr); 14892 set_mem_alias_set (mem, rs6000_sr_alias_set); 14893 14894 emit_move_insn (gen_rtx_REG (V4SImode, i), mem); 14895 } 14896 } 14897 14898 /* Restore VRSAVE if needed. */ 14899 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE 14900 && info->vrsave_mask != 0) 14901 { 14902 rtx addr, mem, reg; 14903 14904 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 14905 GEN_INT (info->vrsave_save_offset + sp_offset)); 14906 mem = gen_rtx_MEM (SImode, addr); 14907 set_mem_alias_set (mem, rs6000_sr_alias_set); 14908 reg = gen_rtx_REG (SImode, 12); 14909 emit_move_insn (reg, mem); 14910 14911 emit_insn (generate_set_vrsave (reg, info, 1)); 14912 } 14913 14914 /* Get the old lr if we saved it. */ 14915 if (info->lr_save_p) 14916 { 14917 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, 14918 info->lr_save_offset + sp_offset); 14919 14920 set_mem_alias_set (mem, rs6000_sr_alias_set); 14921 14922 emit_move_insn (gen_rtx_REG (Pmode, 0), mem); 14923 } 14924 14925 /* Get the old cr if we saved it. */ 14926 if (info->cr_save_p) 14927 { 14928 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 14929 GEN_INT (info->cr_save_offset + sp_offset)); 14930 rtx mem = gen_rtx_MEM (SImode, addr); 14931 14932 set_mem_alias_set (mem, rs6000_sr_alias_set); 14933 14934 emit_move_insn (gen_rtx_REG (SImode, 12), mem); 14935 } 14936 14937 /* Set LR here to try to overlap restores below. */ 14938 if (info->lr_save_p) 14939 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), 14940 gen_rtx_REG (Pmode, 0)); 14941 14942 /* Load exception handler data registers, if needed. */ 14943 if (current_function_calls_eh_return) 14944 { 14945 unsigned int i, regno; 14946 14947 if (TARGET_AIX) 14948 { 14949 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 14950 GEN_INT (sp_offset + 5 * reg_size)); 14951 rtx mem = gen_rtx_MEM (reg_mode, addr); 14952 14953 set_mem_alias_set (mem, rs6000_sr_alias_set); 14954 14955 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem); 14956 } 14957 14958 for (i = 0; ; ++i) 14959 { 14960 rtx mem; 14961 14962 regno = EH_RETURN_DATA_REGNO (i); 14963 if (regno == INVALID_REGNUM) 14964 break; 14965 14966 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx, 14967 info->ehrd_offset + sp_offset 14968 + reg_size * (int) i); 14969 set_mem_alias_set (mem, rs6000_sr_alias_set); 14970 14971 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); 14972 } 14973 } 14974 14975 /* Restore GPRs. This is done as a PARALLEL if we are using 14976 the load-multiple instructions. */ 14977 if (using_load_multiple) 14978 { 14979 rtvec p; 14980 p = rtvec_alloc (32 - info->first_gp_reg_save); 14981 for (i = 0; i < 32 - info->first_gp_reg_save; i++) 14982 { 14983 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 14984 GEN_INT (info->gp_save_offset 14985 + sp_offset 14986 + reg_size * i)); 14987 rtx mem = gen_rtx_MEM (reg_mode, addr); 14988 14989 set_mem_alias_set (mem, rs6000_sr_alias_set); 14990 14991 RTVEC_ELT (p, i) = 14992 gen_rtx_SET (VOIDmode, 14993 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), 14994 mem); 14995 } 14996 emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); 14997 } 14998 else 14999 for (i = 0; i < 32 - info->first_gp_reg_save; i++) 15000 if ((regs_ever_live[info->first_gp_reg_save + i] 15001 && (!call_used_regs[info->first_gp_reg_save + i] 15002 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM 15003 && TARGET_TOC && TARGET_MINIMAL_TOC))) 15004 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM 15005 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) 15006 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) 15007 { 15008 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 15009 GEN_INT (info->gp_save_offset 15010 + sp_offset 15011 + reg_size * i)); 15012 rtx mem = gen_rtx_MEM (reg_mode, addr); 15013 15014 /* Restore 64-bit quantities for SPE. */ 15015 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) 15016 { 15017 int offset = info->spe_gp_save_offset + sp_offset + 8 * i; 15018 rtx b; 15019 15020 if (!SPE_CONST_OFFSET_OK (offset)) 15021 { 15022 b = gen_rtx_REG (Pmode, FIXED_SCRATCH); 15023 emit_move_insn (b, GEN_INT (offset)); 15024 } 15025 else 15026 b = GEN_INT (offset); 15027 15028 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); 15029 mem = gen_rtx_MEM (V2SImode, addr); 15030 } 15031 15032 set_mem_alias_set (mem, rs6000_sr_alias_set); 15033 15034 emit_move_insn (gen_rtx_REG (reg_mode, 15035 info->first_gp_reg_save + i), mem); 15036 } 15037 15038 /* Restore fpr's if we need to do it without calling a function. */ 15039 if (restoring_FPRs_inline) 15040 for (i = 0; i < 64 - info->first_fp_reg_save; i++) 15041 if ((regs_ever_live[info->first_fp_reg_save+i] 15042 && ! call_used_regs[info->first_fp_reg_save+i])) 15043 { 15044 rtx addr, mem; 15045 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, 15046 GEN_INT (info->fp_save_offset 15047 + sp_offset 15048 + 8 * i)); 15049 mem = gen_rtx_MEM (DFmode, addr); 15050 set_mem_alias_set (mem, rs6000_sr_alias_set); 15051 15052 emit_move_insn (gen_rtx_REG (DFmode, 15053 info->first_fp_reg_save + i), 15054 mem); 15055 } 15056 15057 /* If we saved cr, restore it here. Just those that were used. */ 15058 if (info->cr_save_p) 15059 { 15060 rtx r12_rtx = gen_rtx_REG (SImode, 12); 15061 int count = 0; 15062 15063 if (using_mfcr_multiple) 15064 { 15065 for (i = 0; i < 8; i++) 15066 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) 15067 count++; 15068 gcc_assert (count); 15069 } 15070 15071 if (using_mfcr_multiple && count > 1) 15072 { 15073 rtvec p; 15074 int ndx; 15075 15076 p = rtvec_alloc (count); 15077 15078 ndx = 0; 15079 for (i = 0; i < 8; i++) 15080 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) 15081 { 15082 rtvec r = rtvec_alloc (2); 15083 RTVEC_ELT (r, 0) = r12_rtx; 15084 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); 15085 RTVEC_ELT (p, ndx) = 15086 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), 15087 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR)); 15088 ndx++; 15089 } 15090 emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); 15091 gcc_assert (ndx == count); 15092 } 15093 else 15094 for (i = 0; i < 8; i++) 15095 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) 15096 { 15097 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, 15098 CR0_REGNO+i), 15099 r12_rtx)); 15100 } 15101 } 15102 15103 /* If this is V.4, unwind the stack pointer after all of the loads 15104 have been done. We need to emit a block here so that sched 15105 doesn't decide to move the sp change before the register restores 15106 (which may not have any obvious dependency on the stack). This 15107 doesn't hurt performance, because there is no scheduling that can 15108 be done after this point. */ 15109 if (DEFAULT_ABI == ABI_V4 15110 || current_function_calls_eh_return) 15111 { 15112 if (frame_reg_rtx != sp_reg_rtx) 15113 rs6000_emit_stack_tie (); 15114 15115 if (use_backchain_to_restore_sp) 15116 { 15117 emit_move_insn (sp_reg_rtx, frame_reg_rtx); 15118 } 15119 else if (sp_offset != 0) 15120 { 15121 emit_insn (TARGET_32BIT 15122 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, 15123 GEN_INT (sp_offset)) 15124 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, 15125 GEN_INT (sp_offset))); 15126 } 15127 } 15128 15129 if (current_function_calls_eh_return) 15130 { 15131 rtx sa = EH_RETURN_STACKADJ_RTX; 15132 emit_insn (TARGET_32BIT 15133 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) 15134 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); 15135 } 15136 15137 if (!sibcall) 15138 { 15139 rtvec p; 15140 if (! restoring_FPRs_inline) 15141 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); 15142 else 15143 p = rtvec_alloc (2); 15144 15145 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); 15146 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, 15147 gen_rtx_REG (Pmode, 15148 LINK_REGISTER_REGNUM)); 15149 15150 /* If we have to restore more than two FP registers, branch to the 15151 restore function. It will return to our caller. */ 15152 if (! restoring_FPRs_inline) 15153 { 15154 int i; 15155 char rname[30]; 15156 const char *alloc_rname; 15157 15158 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, 15159 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); 15160 alloc_rname = ggc_strdup (rname); 15161 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, 15162 gen_rtx_SYMBOL_REF (Pmode, 15163 alloc_rname)); 15164 15165 for (i = 0; i < 64 - info->first_fp_reg_save; i++) 15166 { 15167 rtx addr, mem; 15168 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, 15169 GEN_INT (info->fp_save_offset + 8*i)); 15170 mem = gen_rtx_MEM (DFmode, addr); 15171 set_mem_alias_set (mem, rs6000_sr_alias_set); 15172 15173 RTVEC_ELT (p, i+3) = 15174 gen_rtx_SET (VOIDmode, 15175 gen_rtx_REG (DFmode, info->first_fp_reg_save + i), 15176 mem); 15177 } 15178 } 15179 15180 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); 15181 } 15182} 15183 15184/* Write function epilogue. */ 15185 15186static void 15187rs6000_output_function_epilogue (FILE *file, 15188 HOST_WIDE_INT size ATTRIBUTE_UNUSED) 15189{ 15190 if (! HAVE_epilogue) 15191 { 15192 rtx insn = get_last_insn (); 15193 /* If the last insn was a BARRIER, we don't have to write anything except 15194 the trace table. */ 15195 if (GET_CODE (insn) == NOTE) 15196 insn = prev_nonnote_insn (insn); 15197 if (insn == 0 || GET_CODE (insn) != BARRIER) 15198 { 15199 /* This is slightly ugly, but at least we don't have two 15200 copies of the epilogue-emitting code. */ 15201 start_sequence (); 15202 15203 /* A NOTE_INSN_DELETED is supposed to be at the start 15204 and end of the "toplevel" insn chain. */ 15205 emit_note (NOTE_INSN_DELETED); 15206 rs6000_emit_epilogue (FALSE); 15207 emit_note (NOTE_INSN_DELETED); 15208 15209 /* Expand INSN_ADDRESSES so final() doesn't crash. */ 15210 { 15211 rtx insn; 15212 unsigned addr = 0; 15213 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) 15214 { 15215 INSN_ADDRESSES_NEW (insn, addr); 15216 addr += 4; 15217 } 15218 } 15219 15220 if (TARGET_DEBUG_STACK) 15221 debug_rtx_list (get_insns (), 100); 15222 final (get_insns (), file, FALSE); 15223 end_sequence (); 15224 } 15225 } 15226 15227#if TARGET_MACHO 15228 macho_branch_islands (); 15229 /* Mach-O doesn't support labels at the end of objects, so if 15230 it looks like we might want one, insert a NOP. */ 15231 { 15232 rtx insn = get_last_insn (); 15233 while (insn 15234 && NOTE_P (insn) 15235 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL) 15236 insn = PREV_INSN (insn); 15237 if (insn 15238 && (LABEL_P (insn) 15239 || (NOTE_P (insn) 15240 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL))) 15241 fputs ("\tnop\n", file); 15242 } 15243#endif 15244 15245 /* Output a traceback table here. See /usr/include/sys/debug.h for info 15246 on its format. 15247 15248 We don't output a traceback table if -finhibit-size-directive was 15249 used. The documentation for -finhibit-size-directive reads 15250 ``don't output a @code{.size} assembler directive, or anything 15251 else that would cause trouble if the function is split in the 15252 middle, and the two halves are placed at locations far apart in 15253 memory.'' The traceback table has this property, since it 15254 includes the offset from the start of the function to the 15255 traceback table itself. 15256 15257 System V.4 Powerpc's (and the embedded ABI derived from it) use a 15258 different traceback table. */ 15259 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive 15260 && rs6000_traceback != traceback_none && !current_function_is_thunk) 15261 { 15262 const char *fname = NULL; 15263 const char *language_string = lang_hooks.name; 15264 int fixed_parms = 0, float_parms = 0, parm_info = 0; 15265 int i; 15266 int optional_tbtab; 15267 rs6000_stack_t *info = rs6000_stack_info (); 15268 15269 if (rs6000_traceback == traceback_full) 15270 optional_tbtab = 1; 15271 else if (rs6000_traceback == traceback_part) 15272 optional_tbtab = 0; 15273 else 15274 optional_tbtab = !optimize_size && !TARGET_ELF; 15275 15276 if (optional_tbtab) 15277 { 15278 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); 15279 while (*fname == '.') /* V.4 encodes . in the name */ 15280 fname++; 15281 15282 /* Need label immediately before tbtab, so we can compute 15283 its offset from the function start. */ 15284 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); 15285 ASM_OUTPUT_LABEL (file, fname); 15286 } 15287 15288 /* The .tbtab pseudo-op can only be used for the first eight 15289 expressions, since it can't handle the possibly variable 15290 length fields that follow. However, if you omit the optional 15291 fields, the assembler outputs zeros for all optional fields 15292 anyways, giving each variable length field is minimum length 15293 (as defined in sys/debug.h). Thus we can not use the .tbtab 15294 pseudo-op at all. */ 15295 15296 /* An all-zero word flags the start of the tbtab, for debuggers 15297 that have to find it by searching forward from the entry 15298 point or from the current pc. */ 15299 fputs ("\t.long 0\n", file); 15300 15301 /* Tbtab format type. Use format type 0. */ 15302 fputs ("\t.byte 0,", file); 15303 15304 /* Language type. Unfortunately, there does not seem to be any 15305 official way to discover the language being compiled, so we 15306 use language_string. 15307 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9. 15308 Java is 13. Objective-C is 14. */ 15309 if (! strcmp (language_string, "GNU C")) 15310 i = 0; 15311 else if (! strcmp (language_string, "GNU F77") 15312 || ! strcmp (language_string, "GNU F95")) 15313 i = 1; 15314 else if (! strcmp (language_string, "GNU Pascal")) 15315 i = 2; 15316 else if (! strcmp (language_string, "GNU Ada")) 15317 i = 3; 15318 else if (! strcmp (language_string, "GNU C++")) 15319 i = 9; 15320 else if (! strcmp (language_string, "GNU Java")) 15321 i = 13; 15322 else if (! strcmp (language_string, "GNU Objective-C")) 15323 i = 14; 15324 else 15325 gcc_unreachable (); 15326 fprintf (file, "%d,", i); 15327 15328 /* 8 single bit fields: global linkage (not set for C extern linkage, 15329 apparently a PL/I convention?), out-of-line epilogue/prologue, offset 15330 from start of procedure stored in tbtab, internal function, function 15331 has controlled storage, function has no toc, function uses fp, 15332 function logs/aborts fp operations. */ 15333 /* Assume that fp operations are used if any fp reg must be saved. */ 15334 fprintf (file, "%d,", 15335 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1)); 15336 15337 /* 6 bitfields: function is interrupt handler, name present in 15338 proc table, function calls alloca, on condition directives 15339 (controls stack walks, 3 bits), saves condition reg, saves 15340 link reg. */ 15341 /* The `function calls alloca' bit seems to be set whenever reg 31 is 15342 set up as a frame pointer, even when there is no alloca call. */ 15343 fprintf (file, "%d,", 15344 ((optional_tbtab << 6) 15345 | ((optional_tbtab & frame_pointer_needed) << 5) 15346 | (info->cr_save_p << 1) 15347 | (info->lr_save_p))); 15348 15349 /* 3 bitfields: saves backchain, fixup code, number of fpr saved 15350 (6 bits). */ 15351 fprintf (file, "%d,", 15352 (info->push_p << 7) | (64 - info->first_fp_reg_save)); 15353 15354 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ 15355 fprintf (file, "%d,", (32 - first_reg_to_save ())); 15356 15357 if (optional_tbtab) 15358 { 15359 /* Compute the parameter info from the function decl argument 15360 list. */ 15361 tree decl; 15362 int next_parm_info_bit = 31; 15363 15364 for (decl = DECL_ARGUMENTS (current_function_decl); 15365 decl; decl = TREE_CHAIN (decl)) 15366 { 15367 rtx parameter = DECL_INCOMING_RTL (decl); 15368 enum machine_mode mode = GET_MODE (parameter); 15369 15370 if (GET_CODE (parameter) == REG) 15371 { 15372 if (GET_MODE_CLASS (mode) == MODE_FLOAT) 15373 { 15374 int bits; 15375 15376 float_parms++; 15377 15378 switch (mode) 15379 { 15380 case SFmode: 15381 bits = 0x2; 15382 break; 15383 15384 case DFmode: 15385 case TFmode: 15386 bits = 0x3; 15387 break; 15388 15389 default: 15390 gcc_unreachable (); 15391 } 15392 15393 /* If only one bit will fit, don't or in this entry. */ 15394 if (next_parm_info_bit > 0) 15395 parm_info |= (bits << (next_parm_info_bit - 1)); 15396 next_parm_info_bit -= 2; 15397 } 15398 else 15399 { 15400 fixed_parms += ((GET_MODE_SIZE (mode) 15401 + (UNITS_PER_WORD - 1)) 15402 / UNITS_PER_WORD); 15403 next_parm_info_bit -= 1; 15404 } 15405 } 15406 } 15407 } 15408 15409 /* Number of fixed point parameters. */ 15410 /* This is actually the number of words of fixed point parameters; thus 15411 an 8 byte struct counts as 2; and thus the maximum value is 8. */ 15412 fprintf (file, "%d,", fixed_parms); 15413 15414 /* 2 bitfields: number of floating point parameters (7 bits), parameters 15415 all on stack. */ 15416 /* This is actually the number of fp registers that hold parameters; 15417 and thus the maximum value is 13. */ 15418 /* Set parameters on stack bit if parameters are not in their original 15419 registers, regardless of whether they are on the stack? Xlc 15420 seems to set the bit when not optimizing. */ 15421 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); 15422 15423 if (! optional_tbtab) 15424 return; 15425 15426 /* Optional fields follow. Some are variable length. */ 15427 15428 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, 15429 11 double float. */ 15430 /* There is an entry for each parameter in a register, in the order that 15431 they occur in the parameter list. Any intervening arguments on the 15432 stack are ignored. If the list overflows a long (max possible length 15433 34 bits) then completely leave off all elements that don't fit. */ 15434 /* Only emit this long if there was at least one parameter. */ 15435 if (fixed_parms || float_parms) 15436 fprintf (file, "\t.long %d\n", parm_info); 15437 15438 /* Offset from start of code to tb table. */ 15439 fputs ("\t.long ", file); 15440 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); 15441 if (TARGET_AIX) 15442 RS6000_OUTPUT_BASENAME (file, fname); 15443 else 15444 assemble_name (file, fname); 15445 putc ('-', file); 15446 rs6000_output_function_entry (file, fname); 15447 putc ('\n', file); 15448 15449 /* Interrupt handler mask. */ 15450 /* Omit this long, since we never set the interrupt handler bit 15451 above. */ 15452 15453 /* Number of CTL (controlled storage) anchors. */ 15454 /* Omit this long, since the has_ctl bit is never set above. */ 15455 15456 /* Displacement into stack of each CTL anchor. */ 15457 /* Omit this list of longs, because there are no CTL anchors. */ 15458 15459 /* Length of function name. */ 15460 if (*fname == '*') 15461 ++fname; 15462 fprintf (file, "\t.short %d\n", (int) strlen (fname)); 15463 15464 /* Function name. */ 15465 assemble_string (fname, strlen (fname)); 15466 15467 /* Register for alloca automatic storage; this is always reg 31. 15468 Only emit this if the alloca bit was set above. */ 15469 if (frame_pointer_needed) 15470 fputs ("\t.byte 31\n", file); 15471 15472 fputs ("\t.align 2\n", file); 15473 } 15474} 15475 15476/* A C compound statement that outputs the assembler code for a thunk 15477 function, used to implement C++ virtual function calls with 15478 multiple inheritance. The thunk acts as a wrapper around a virtual 15479 function, adjusting the implicit object parameter before handing 15480 control off to the real function. 15481 15482 First, emit code to add the integer DELTA to the location that 15483 contains the incoming first argument. Assume that this argument 15484 contains a pointer, and is the one used to pass the `this' pointer 15485 in C++. This is the incoming argument *before* the function 15486 prologue, e.g. `%o0' on a sparc. The addition must preserve the 15487 values of all other incoming arguments. 15488 15489 After the addition, emit code to jump to FUNCTION, which is a 15490 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does 15491 not touch the return address. Hence returning from FUNCTION will 15492 return to whoever called the current `thunk'. 15493 15494 The effect must be as if FUNCTION had been called directly with the 15495 adjusted first argument. This macro is responsible for emitting 15496 all of the code for a thunk function; output_function_prologue() 15497 and output_function_epilogue() are not invoked. 15498 15499 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already 15500 been extracted from it.) It might possibly be useful on some 15501 targets, but probably not. 15502 15503 If you do not define this macro, the target-independent code in the 15504 C++ frontend will generate a less efficient heavyweight thunk that 15505 calls FUNCTION instead of jumping to it. The generic approach does 15506 not support varargs. */ 15507 15508static void 15509rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, 15510 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, 15511 tree function) 15512{ 15513 rtx this, insn, funexp; 15514 15515 reload_completed = 1; 15516 epilogue_completed = 1; 15517 no_new_pseudos = 1; 15518 reset_block_changes (); 15519 15520 /* Mark the end of the (empty) prologue. */ 15521 emit_note (NOTE_INSN_PROLOGUE_END); 15522 15523 /* Find the "this" pointer. If the function returns a structure, 15524 the structure return pointer is in r3. */ 15525 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) 15526 this = gen_rtx_REG (Pmode, 4); 15527 else 15528 this = gen_rtx_REG (Pmode, 3); 15529 15530 /* Apply the constant offset, if required. */ 15531 if (delta) 15532 { 15533 rtx delta_rtx = GEN_INT (delta); 15534 emit_insn (TARGET_32BIT 15535 ? gen_addsi3 (this, this, delta_rtx) 15536 : gen_adddi3 (this, this, delta_rtx)); 15537 } 15538 15539 /* Apply the offset from the vtable, if required. */ 15540 if (vcall_offset) 15541 { 15542 rtx vcall_offset_rtx = GEN_INT (vcall_offset); 15543 rtx tmp = gen_rtx_REG (Pmode, 12); 15544 15545 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this)); 15546 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000) 15547 { 15548 emit_insn (TARGET_32BIT 15549 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx) 15550 : gen_adddi3 (tmp, tmp, vcall_offset_rtx)); 15551 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); 15552 } 15553 else 15554 { 15555 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx); 15556 15557 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc)); 15558 } 15559 emit_insn (TARGET_32BIT 15560 ? gen_addsi3 (this, this, tmp) 15561 : gen_adddi3 (this, this, tmp)); 15562 } 15563 15564 /* Generate a tail call to the target function. */ 15565 if (!TREE_USED (function)) 15566 { 15567 assemble_external (function); 15568 TREE_USED (function) = 1; 15569 } 15570 funexp = XEXP (DECL_RTL (function), 0); 15571 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); 15572 15573#if TARGET_MACHO 15574 if (MACHOPIC_INDIRECT) 15575 funexp = machopic_indirect_call_target (funexp); 15576#endif 15577 15578 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must 15579 generate sibcall RTL explicitly. */ 15580 insn = emit_call_insn ( 15581 gen_rtx_PARALLEL (VOIDmode, 15582 gen_rtvec (4, 15583 gen_rtx_CALL (VOIDmode, 15584 funexp, const0_rtx), 15585 gen_rtx_USE (VOIDmode, const0_rtx), 15586 gen_rtx_USE (VOIDmode, 15587 gen_rtx_REG (SImode, 15588 LINK_REGISTER_REGNUM)), 15589 gen_rtx_RETURN (VOIDmode)))); 15590 SIBLING_CALL_P (insn) = 1; 15591 emit_barrier (); 15592 15593 /* Run just enough of rest_of_compilation to get the insns emitted. 15594 There's not really enough bulk here to make other passes such as 15595 instruction scheduling worth while. Note that use_thunk calls 15596 assemble_start_function and assemble_end_function. */ 15597 insn = get_insns (); 15598 insn_locators_initialize (); 15599 shorten_branches (insn); 15600 final_start_function (insn, file, 1); 15601 final (insn, file, 1); 15602 final_end_function (); 15603 15604 reload_completed = 0; 15605 epilogue_completed = 0; 15606 no_new_pseudos = 0; 15607} 15608 15609/* A quick summary of the various types of 'constant-pool tables' 15610 under PowerPC: 15611 15612 Target Flags Name One table per 15613 AIX (none) AIX TOC object file 15614 AIX -mfull-toc AIX TOC object file 15615 AIX -mminimal-toc AIX minimal TOC translation unit 15616 SVR4/EABI (none) SVR4 SDATA object file 15617 SVR4/EABI -fpic SVR4 pic object file 15618 SVR4/EABI -fPIC SVR4 PIC translation unit 15619 SVR4/EABI -mrelocatable EABI TOC function 15620 SVR4/EABI -maix AIX TOC object file 15621 SVR4/EABI -maix -mminimal-toc 15622 AIX minimal TOC translation unit 15623 15624 Name Reg. Set by entries contains: 15625 made by addrs? fp? sum? 15626 15627 AIX TOC 2 crt0 as Y option option 15628 AIX minimal TOC 30 prolog gcc Y Y option 15629 SVR4 SDATA 13 crt0 gcc N Y N 15630 SVR4 pic 30 prolog ld Y not yet N 15631 SVR4 PIC 30 prolog gcc Y option option 15632 EABI TOC 30 prolog gcc Y option option 15633 15634*/ 15635 15636/* Hash functions for the hash table. */ 15637 15638static unsigned 15639rs6000_hash_constant (rtx k) 15640{ 15641 enum rtx_code code = GET_CODE (k); 15642 enum machine_mode mode = GET_MODE (k); 15643 unsigned result = (code << 3) ^ mode; 15644 const char *format; 15645 int flen, fidx; 15646 15647 format = GET_RTX_FORMAT (code); 15648 flen = strlen (format); 15649 fidx = 0; 15650 15651 switch (code) 15652 { 15653 case LABEL_REF: 15654 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0)); 15655 15656 case CONST_DOUBLE: 15657 if (mode != VOIDmode) 15658 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result; 15659 flen = 2; 15660 break; 15661 15662 case CODE_LABEL: 15663 fidx = 3; 15664 break; 15665 15666 default: 15667 break; 15668 } 15669 15670 for (; fidx < flen; fidx++) 15671 switch (format[fidx]) 15672 { 15673 case 's': 15674 { 15675 unsigned i, len; 15676 const char *str = XSTR (k, fidx); 15677 len = strlen (str); 15678 result = result * 613 + len; 15679 for (i = 0; i < len; i++) 15680 result = result * 613 + (unsigned) str[i]; 15681 break; 15682 } 15683 case 'u': 15684 case 'e': 15685 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); 15686 break; 15687 case 'i': 15688 case 'n': 15689 result = result * 613 + (unsigned) XINT (k, fidx); 15690 break; 15691 case 'w': 15692 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) 15693 result = result * 613 + (unsigned) XWINT (k, fidx); 15694 else 15695 { 15696 size_t i; 15697 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++) 15698 result = result * 613 + (unsigned) (XWINT (k, fidx) 15699 >> CHAR_BIT * i); 15700 } 15701 break; 15702 case '0': 15703 break; 15704 default: 15705 gcc_unreachable (); 15706 } 15707 15708 return result; 15709} 15710 15711static unsigned 15712toc_hash_function (const void *hash_entry) 15713{ 15714 const struct toc_hash_struct *thc = 15715 (const struct toc_hash_struct *) hash_entry; 15716 return rs6000_hash_constant (thc->key) ^ thc->key_mode; 15717} 15718 15719/* Compare H1 and H2 for equivalence. */ 15720 15721static int 15722toc_hash_eq (const void *h1, const void *h2) 15723{ 15724 rtx r1 = ((const struct toc_hash_struct *) h1)->key; 15725 rtx r2 = ((const struct toc_hash_struct *) h2)->key; 15726 15727 if (((const struct toc_hash_struct *) h1)->key_mode 15728 != ((const struct toc_hash_struct *) h2)->key_mode) 15729 return 0; 15730 15731 return rtx_equal_p (r1, r2); 15732} 15733 15734/* These are the names given by the C++ front-end to vtables, and 15735 vtable-like objects. Ideally, this logic should not be here; 15736 instead, there should be some programmatic way of inquiring as 15737 to whether or not an object is a vtable. */ 15738 15739#define VTABLE_NAME_P(NAME) \ 15740 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \ 15741 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ 15742 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ 15743 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \ 15744 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) 15745 15746void 15747rs6000_output_symbol_ref (FILE *file, rtx x) 15748{ 15749 /* Currently C++ toc references to vtables can be emitted before it 15750 is decided whether the vtable is public or private. If this is 15751 the case, then the linker will eventually complain that there is 15752 a reference to an unknown section. Thus, for vtables only, 15753 we emit the TOC reference to reference the symbol and not the 15754 section. */ 15755 const char *name = XSTR (x, 0); 15756 15757 if (VTABLE_NAME_P (name)) 15758 { 15759 RS6000_OUTPUT_BASENAME (file, name); 15760 } 15761 else 15762 assemble_name (file, name); 15763} 15764 15765/* Output a TOC entry. We derive the entry name from what is being 15766 written. */ 15767 15768void 15769output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode) 15770{ 15771 char buf[256]; 15772 const char *name = buf; 15773 const char *real_name; 15774 rtx base = x; 15775 HOST_WIDE_INT offset = 0; 15776 15777 gcc_assert (!TARGET_NO_TOC); 15778 15779 /* When the linker won't eliminate them, don't output duplicate 15780 TOC entries (this happens on AIX if there is any kind of TOC, 15781 and on SVR4 under -fPIC or -mrelocatable). Don't do this for 15782 CODE_LABELs. */ 15783 if (TARGET_TOC && GET_CODE (x) != LABEL_REF) 15784 { 15785 struct toc_hash_struct *h; 15786 void * * found; 15787 15788 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS 15789 time because GGC is not initialized at that point. */ 15790 if (toc_hash_table == NULL) 15791 toc_hash_table = htab_create_ggc (1021, toc_hash_function, 15792 toc_hash_eq, NULL); 15793 15794 h = ggc_alloc (sizeof (*h)); 15795 h->key = x; 15796 h->key_mode = mode; 15797 h->labelno = labelno; 15798 15799 found = htab_find_slot (toc_hash_table, h, 1); 15800 if (*found == NULL) 15801 *found = h; 15802 else /* This is indeed a duplicate. 15803 Set this label equal to that label. */ 15804 { 15805 fputs ("\t.set ", file); 15806 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); 15807 fprintf (file, "%d,", labelno); 15808 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); 15809 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) 15810 found)->labelno)); 15811 return; 15812 } 15813 } 15814 15815 /* If we're going to put a double constant in the TOC, make sure it's 15816 aligned properly when strict alignment is on. */ 15817 if (GET_CODE (x) == CONST_DOUBLE 15818 && STRICT_ALIGNMENT 15819 && GET_MODE_BITSIZE (mode) >= 64 15820 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { 15821 ASM_OUTPUT_ALIGN (file, 3); 15822 } 15823 15824 (*targetm.asm_out.internal_label) (file, "LC", labelno); 15825 15826 /* Handle FP constants specially. Note that if we have a minimal 15827 TOC, things we put here aren't actually in the TOC, so we can allow 15828 FP constants. */ 15829 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode) 15830 { 15831 REAL_VALUE_TYPE rv; 15832 long k[4]; 15833 15834 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 15835 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); 15836 15837 if (TARGET_64BIT) 15838 { 15839 if (TARGET_MINIMAL_TOC) 15840 fputs (DOUBLE_INT_ASM_OP, file); 15841 else 15842 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", 15843 k[0] & 0xffffffff, k[1] & 0xffffffff, 15844 k[2] & 0xffffffff, k[3] & 0xffffffff); 15845 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n", 15846 k[0] & 0xffffffff, k[1] & 0xffffffff, 15847 k[2] & 0xffffffff, k[3] & 0xffffffff); 15848 return; 15849 } 15850 else 15851 { 15852 if (TARGET_MINIMAL_TOC) 15853 fputs ("\t.long ", file); 15854 else 15855 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", 15856 k[0] & 0xffffffff, k[1] & 0xffffffff, 15857 k[2] & 0xffffffff, k[3] & 0xffffffff); 15858 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n", 15859 k[0] & 0xffffffff, k[1] & 0xffffffff, 15860 k[2] & 0xffffffff, k[3] & 0xffffffff); 15861 return; 15862 } 15863 } 15864 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) 15865 { 15866 REAL_VALUE_TYPE rv; 15867 long k[2]; 15868 15869 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 15870 REAL_VALUE_TO_TARGET_DOUBLE (rv, k); 15871 15872 if (TARGET_64BIT) 15873 { 15874 if (TARGET_MINIMAL_TOC) 15875 fputs (DOUBLE_INT_ASM_OP, file); 15876 else 15877 fprintf (file, "\t.tc FD_%lx_%lx[TC],", 15878 k[0] & 0xffffffff, k[1] & 0xffffffff); 15879 fprintf (file, "0x%lx%08lx\n", 15880 k[0] & 0xffffffff, k[1] & 0xffffffff); 15881 return; 15882 } 15883 else 15884 { 15885 if (TARGET_MINIMAL_TOC) 15886 fputs ("\t.long ", file); 15887 else 15888 fprintf (file, "\t.tc FD_%lx_%lx[TC],", 15889 k[0] & 0xffffffff, k[1] & 0xffffffff); 15890 fprintf (file, "0x%lx,0x%lx\n", 15891 k[0] & 0xffffffff, k[1] & 0xffffffff); 15892 return; 15893 } 15894 } 15895 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) 15896 { 15897 REAL_VALUE_TYPE rv; 15898 long l; 15899 15900 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 15901 REAL_VALUE_TO_TARGET_SINGLE (rv, l); 15902 15903 if (TARGET_64BIT) 15904 { 15905 if (TARGET_MINIMAL_TOC) 15906 fputs (DOUBLE_INT_ASM_OP, file); 15907 else 15908 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); 15909 fprintf (file, "0x%lx00000000\n", l & 0xffffffff); 15910 return; 15911 } 15912 else 15913 { 15914 if (TARGET_MINIMAL_TOC) 15915 fputs ("\t.long ", file); 15916 else 15917 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); 15918 fprintf (file, "0x%lx\n", l & 0xffffffff); 15919 return; 15920 } 15921 } 15922 else if (GET_MODE (x) == VOIDmode 15923 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) 15924 { 15925 unsigned HOST_WIDE_INT low; 15926 HOST_WIDE_INT high; 15927 15928 if (GET_CODE (x) == CONST_DOUBLE) 15929 { 15930 low = CONST_DOUBLE_LOW (x); 15931 high = CONST_DOUBLE_HIGH (x); 15932 } 15933 else 15934#if HOST_BITS_PER_WIDE_INT == 32 15935 { 15936 low = INTVAL (x); 15937 high = (low & 0x80000000) ? ~0 : 0; 15938 } 15939#else 15940 { 15941 low = INTVAL (x) & 0xffffffff; 15942 high = (HOST_WIDE_INT) INTVAL (x) >> 32; 15943 } 15944#endif 15945 15946 /* TOC entries are always Pmode-sized, but since this 15947 is a bigendian machine then if we're putting smaller 15948 integer constants in the TOC we have to pad them. 15949 (This is still a win over putting the constants in 15950 a separate constant pool, because then we'd have 15951 to have both a TOC entry _and_ the actual constant.) 15952 15953 For a 32-bit target, CONST_INT values are loaded and shifted 15954 entirely within `low' and can be stored in one TOC entry. */ 15955 15956 /* It would be easy to make this work, but it doesn't now. */ 15957 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode)); 15958 15959 if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) 15960 { 15961#if HOST_BITS_PER_WIDE_INT == 32 15962 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), 15963 POINTER_SIZE, &low, &high, 0); 15964#else 15965 low |= high << 32; 15966 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode); 15967 high = (HOST_WIDE_INT) low >> 32; 15968 low &= 0xffffffff; 15969#endif 15970 } 15971 15972 if (TARGET_64BIT) 15973 { 15974 if (TARGET_MINIMAL_TOC) 15975 fputs (DOUBLE_INT_ASM_OP, file); 15976 else 15977 fprintf (file, "\t.tc ID_%lx_%lx[TC],", 15978 (long) high & 0xffffffff, (long) low & 0xffffffff); 15979 fprintf (file, "0x%lx%08lx\n", 15980 (long) high & 0xffffffff, (long) low & 0xffffffff); 15981 return; 15982 } 15983 else 15984 { 15985 if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) 15986 { 15987 if (TARGET_MINIMAL_TOC) 15988 fputs ("\t.long ", file); 15989 else 15990 fprintf (file, "\t.tc ID_%lx_%lx[TC],", 15991 (long) high & 0xffffffff, (long) low & 0xffffffff); 15992 fprintf (file, "0x%lx,0x%lx\n", 15993 (long) high & 0xffffffff, (long) low & 0xffffffff); 15994 } 15995 else 15996 { 15997 if (TARGET_MINIMAL_TOC) 15998 fputs ("\t.long ", file); 15999 else 16000 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff); 16001 fprintf (file, "0x%lx\n", (long) low & 0xffffffff); 16002 } 16003 return; 16004 } 16005 } 16006 16007 if (GET_CODE (x) == CONST) 16008 { 16009 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS); 16010 16011 base = XEXP (XEXP (x, 0), 0); 16012 offset = INTVAL (XEXP (XEXP (x, 0), 1)); 16013 } 16014 16015 switch (GET_CODE (base)) 16016 { 16017 case SYMBOL_REF: 16018 name = XSTR (base, 0); 16019 break; 16020 16021 case LABEL_REF: 16022 ASM_GENERATE_INTERNAL_LABEL (buf, "L", 16023 CODE_LABEL_NUMBER (XEXP (base, 0))); 16024 break; 16025 16026 case CODE_LABEL: 16027 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); 16028 break; 16029 16030 default: 16031 gcc_unreachable (); 16032 } 16033 16034 real_name = (*targetm.strip_name_encoding) (name); 16035 if (TARGET_MINIMAL_TOC) 16036 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); 16037 else 16038 { 16039 fprintf (file, "\t.tc %s", real_name); 16040 16041 if (offset < 0) 16042 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset); 16043 else if (offset) 16044 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset); 16045 16046 fputs ("[TC],", file); 16047 } 16048 16049 /* Currently C++ toc references to vtables can be emitted before it 16050 is decided whether the vtable is public or private. If this is 16051 the case, then the linker will eventually complain that there is 16052 a TOC reference to an unknown section. Thus, for vtables only, 16053 we emit the TOC reference to reference the symbol and not the 16054 section. */ 16055 if (VTABLE_NAME_P (name)) 16056 { 16057 RS6000_OUTPUT_BASENAME (file, name); 16058 if (offset < 0) 16059 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset); 16060 else if (offset > 0) 16061 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset); 16062 } 16063 else 16064 output_addr_const (file, x); 16065 putc ('\n', file); 16066} 16067 16068/* Output an assembler pseudo-op to write an ASCII string of N characters 16069 starting at P to FILE. 16070 16071 On the RS/6000, we have to do this using the .byte operation and 16072 write out special characters outside the quoted string. 16073 Also, the assembler is broken; very long strings are truncated, 16074 so we must artificially break them up early. */ 16075 16076void 16077output_ascii (FILE *file, const char *p, int n) 16078{ 16079 char c; 16080 int i, count_string; 16081 const char *for_string = "\t.byte \""; 16082 const char *for_decimal = "\t.byte "; 16083 const char *to_close = NULL; 16084 16085 count_string = 0; 16086 for (i = 0; i < n; i++) 16087 { 16088 c = *p++; 16089 if (c >= ' ' && c < 0177) 16090 { 16091 if (for_string) 16092 fputs (for_string, file); 16093 putc (c, file); 16094 16095 /* Write two quotes to get one. */ 16096 if (c == '"') 16097 { 16098 putc (c, file); 16099 ++count_string; 16100 } 16101 16102 for_string = NULL; 16103 for_decimal = "\"\n\t.byte "; 16104 to_close = "\"\n"; 16105 ++count_string; 16106 16107 if (count_string >= 512) 16108 { 16109 fputs (to_close, file); 16110 16111 for_string = "\t.byte \""; 16112 for_decimal = "\t.byte "; 16113 to_close = NULL; 16114 count_string = 0; 16115 } 16116 } 16117 else 16118 { 16119 if (for_decimal) 16120 fputs (for_decimal, file); 16121 fprintf (file, "%d", c); 16122 16123 for_string = "\n\t.byte \""; 16124 for_decimal = ", "; 16125 to_close = "\n"; 16126 count_string = 0; 16127 } 16128 } 16129 16130 /* Now close the string if we have written one. Then end the line. */ 16131 if (to_close) 16132 fputs (to_close, file); 16133} 16134 16135/* Generate a unique section name for FILENAME for a section type 16136 represented by SECTION_DESC. Output goes into BUF. 16137 16138 SECTION_DESC can be any string, as long as it is different for each 16139 possible section type. 16140 16141 We name the section in the same manner as xlc. The name begins with an 16142 underscore followed by the filename (after stripping any leading directory 16143 names) with the last period replaced by the string SECTION_DESC. If 16144 FILENAME does not contain a period, SECTION_DESC is appended to the end of 16145 the name. */ 16146 16147void 16148rs6000_gen_section_name (char **buf, const char *filename, 16149 const char *section_desc) 16150{ 16151 const char *q, *after_last_slash, *last_period = 0; 16152 char *p; 16153 int len; 16154 16155 after_last_slash = filename; 16156 for (q = filename; *q; q++) 16157 { 16158 if (*q == '/') 16159 after_last_slash = q + 1; 16160 else if (*q == '.') 16161 last_period = q; 16162 } 16163 16164 len = strlen (after_last_slash) + strlen (section_desc) + 2; 16165 *buf = (char *) xmalloc (len); 16166 16167 p = *buf; 16168 *p++ = '_'; 16169 16170 for (q = after_last_slash; *q; q++) 16171 { 16172 if (q == last_period) 16173 { 16174 strcpy (p, section_desc); 16175 p += strlen (section_desc); 16176 break; 16177 } 16178 16179 else if (ISALNUM (*q)) 16180 *p++ = *q; 16181 } 16182 16183 if (last_period == 0) 16184 strcpy (p, section_desc); 16185 else 16186 *p = '\0'; 16187} 16188 16189/* Emit profile function. */ 16190 16191void 16192output_profile_hook (int labelno ATTRIBUTE_UNUSED) 16193{ 16194 /* Non-standard profiling for kernels, which just saves LR then calls 16195 _mcount without worrying about arg saves. The idea is to change 16196 the function prologue as little as possible as it isn't easy to 16197 account for arg save/restore code added just for _mcount. */ 16198 if (TARGET_PROFILE_KERNEL) 16199 return; 16200 16201 if (DEFAULT_ABI == ABI_AIX) 16202 { 16203#ifndef NO_PROFILE_COUNTERS 16204# define NO_PROFILE_COUNTERS 0 16205#endif 16206 if (NO_PROFILE_COUNTERS) 16207 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0); 16208 else 16209 { 16210 char buf[30]; 16211 const char *label_name; 16212 rtx fun; 16213 16214 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); 16215 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf)); 16216 fun = gen_rtx_SYMBOL_REF (Pmode, label_name); 16217 16218 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, 16219 fun, Pmode); 16220 } 16221 } 16222 else if (DEFAULT_ABI == ABI_DARWIN) 16223 { 16224 const char *mcount_name = RS6000_MCOUNT; 16225 int caller_addr_regno = LINK_REGISTER_REGNUM; 16226 16227 /* Be conservative and always set this, at least for now. */ 16228 current_function_uses_pic_offset_table = 1; 16229 16230#if TARGET_MACHO 16231 /* For PIC code, set up a stub and collect the caller's address 16232 from r0, which is where the prologue puts it. */ 16233 if (MACHOPIC_INDIRECT 16234 && current_function_uses_pic_offset_table) 16235 caller_addr_regno = 0; 16236#endif 16237 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), 16238 0, VOIDmode, 1, 16239 gen_rtx_REG (Pmode, caller_addr_regno), Pmode); 16240 } 16241} 16242 16243/* Write function profiler code. */ 16244 16245void 16246output_function_profiler (FILE *file, int labelno) 16247{ 16248 char buf[100]; 16249 16250 switch (DEFAULT_ABI) 16251 { 16252 default: 16253 gcc_unreachable (); 16254 16255 case ABI_V4: 16256 if (!TARGET_32BIT) 16257 { 16258 warning (0, "no profiling of 64-bit code for this ABI"); 16259 return; 16260 } 16261 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); 16262 fprintf (file, "\tmflr %s\n", reg_names[0]); 16263 if (NO_PROFILE_COUNTERS) 16264 { 16265 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", 16266 reg_names[0], reg_names[1]); 16267 } 16268 else if (TARGET_SECURE_PLT && flag_pic) 16269 { 16270 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n", 16271 reg_names[0], reg_names[1]); 16272 asm_fprintf (file, "\tmflr %s\n", reg_names[12]); 16273 asm_fprintf (file, "\t{cau|addis} %s,%s,", 16274 reg_names[12], reg_names[12]); 16275 assemble_name (file, buf); 16276 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]); 16277 assemble_name (file, buf); 16278 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]); 16279 } 16280 else if (flag_pic == 1) 16281 { 16282 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); 16283 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", 16284 reg_names[0], reg_names[1]); 16285 asm_fprintf (file, "\tmflr %s\n", reg_names[12]); 16286 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); 16287 assemble_name (file, buf); 16288 asm_fprintf (file, "@got(%s)\n", reg_names[12]); 16289 } 16290 else if (flag_pic > 1) 16291 { 16292 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", 16293 reg_names[0], reg_names[1]); 16294 /* Now, we need to get the address of the label. */ 16295 fputs ("\tbcl 20,31,1f\n\t.long ", file); 16296 assemble_name (file, buf); 16297 fputs ("-.\n1:", file); 16298 asm_fprintf (file, "\tmflr %s\n", reg_names[11]); 16299 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", 16300 reg_names[0], reg_names[11]); 16301 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", 16302 reg_names[0], reg_names[0], reg_names[11]); 16303 } 16304 else 16305 { 16306 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); 16307 assemble_name (file, buf); 16308 fputs ("@ha\n", file); 16309 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", 16310 reg_names[0], reg_names[1]); 16311 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); 16312 assemble_name (file, buf); 16313 asm_fprintf (file, "@l(%s)\n", reg_names[12]); 16314 } 16315 16316 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */ 16317 fprintf (file, "\tbl %s%s\n", 16318 RS6000_MCOUNT, flag_pic ? "@plt" : ""); 16319 break; 16320 16321 case ABI_AIX: 16322 case ABI_DARWIN: 16323 if (!TARGET_PROFILE_KERNEL) 16324 { 16325 /* Don't do anything, done in output_profile_hook (). */ 16326 } 16327 else 16328 { 16329 gcc_assert (!TARGET_32BIT); 16330 16331 asm_fprintf (file, "\tmflr %s\n", reg_names[0]); 16332 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]); 16333 16334 if (cfun->static_chain_decl != NULL) 16335 { 16336 asm_fprintf (file, "\tstd %s,24(%s)\n", 16337 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); 16338 fprintf (file, "\tbl %s\n", RS6000_MCOUNT); 16339 asm_fprintf (file, "\tld %s,24(%s)\n", 16340 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); 16341 } 16342 else 16343 fprintf (file, "\tbl %s\n", RS6000_MCOUNT); 16344 } 16345 break; 16346 } 16347} 16348 16349 16350/* Power4 load update and store update instructions are cracked into a 16351 load or store and an integer insn which are executed in the same cycle. 16352 Branches have their own dispatch slot which does not count against the 16353 GCC issue rate, but it changes the program flow so there are no other 16354 instructions to issue in this cycle. */ 16355 16356static int 16357rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED, 16358 int verbose ATTRIBUTE_UNUSED, 16359 rtx insn, int more) 16360{ 16361 if (GET_CODE (PATTERN (insn)) == USE 16362 || GET_CODE (PATTERN (insn)) == CLOBBER) 16363 return more; 16364 16365 if (rs6000_sched_groups) 16366 { 16367 if (is_microcoded_insn (insn)) 16368 return 0; 16369 else if (is_cracked_insn (insn)) 16370 return more > 2 ? more - 2 : 0; 16371 } 16372 16373 return more - 1; 16374} 16375 16376/* Adjust the cost of a scheduling dependency. Return the new cost of 16377 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ 16378 16379static int 16380rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) 16381{ 16382 if (! recog_memoized (insn)) 16383 return 0; 16384 16385 if (REG_NOTE_KIND (link) != 0) 16386 return 0; 16387 16388 if (REG_NOTE_KIND (link) == 0) 16389 { 16390 /* Data dependency; DEP_INSN writes a register that INSN reads 16391 some cycles later. */ 16392 16393 /* Separate a load from a narrower, dependent store. */ 16394 if (rs6000_sched_groups 16395 && GET_CODE (PATTERN (insn)) == SET 16396 && GET_CODE (PATTERN (dep_insn)) == SET 16397 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM 16398 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM 16399 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1))) 16400 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0))))) 16401 return cost + 14; 16402 16403 switch (get_attr_type (insn)) 16404 { 16405 case TYPE_JMPREG: 16406 /* Tell the first scheduling pass about the latency between 16407 a mtctr and bctr (and mtlr and br/blr). The first 16408 scheduling pass will not know about this latency since 16409 the mtctr instruction, which has the latency associated 16410 to it, will be generated by reload. */ 16411 return TARGET_POWER ? 5 : 4; 16412 case TYPE_BRANCH: 16413 /* Leave some extra cycles between a compare and its 16414 dependent branch, to inhibit expensive mispredicts. */ 16415 if ((rs6000_cpu_attr == CPU_PPC603 16416 || rs6000_cpu_attr == CPU_PPC604 16417 || rs6000_cpu_attr == CPU_PPC604E 16418 || rs6000_cpu_attr == CPU_PPC620 16419 || rs6000_cpu_attr == CPU_PPC630 16420 || rs6000_cpu_attr == CPU_PPC750 16421 || rs6000_cpu_attr == CPU_PPC7400 16422 || rs6000_cpu_attr == CPU_PPC7450 16423 || rs6000_cpu_attr == CPU_POWER4 16424 || rs6000_cpu_attr == CPU_POWER5) 16425 && recog_memoized (dep_insn) 16426 && (INSN_CODE (dep_insn) >= 0) 16427 && (get_attr_type (dep_insn) == TYPE_CMP 16428 || get_attr_type (dep_insn) == TYPE_COMPARE 16429 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE 16430 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE 16431 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE 16432 || get_attr_type (dep_insn) == TYPE_FPCOMPARE 16433 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL 16434 || get_attr_type (dep_insn) == TYPE_DELAYED_CR)) 16435 return cost + 2; 16436 default: 16437 break; 16438 } 16439 /* Fall out to return default cost. */ 16440 } 16441 16442 return cost; 16443} 16444 16445/* The function returns a true if INSN is microcoded. 16446 Return false otherwise. */ 16447 16448static bool 16449is_microcoded_insn (rtx insn) 16450{ 16451 if (!insn || !INSN_P (insn) 16452 || GET_CODE (PATTERN (insn)) == USE 16453 || GET_CODE (PATTERN (insn)) == CLOBBER) 16454 return false; 16455 16456 if (rs6000_sched_groups) 16457 { 16458 enum attr_type type = get_attr_type (insn); 16459 if (type == TYPE_LOAD_EXT_U 16460 || type == TYPE_LOAD_EXT_UX 16461 || type == TYPE_LOAD_UX 16462 || type == TYPE_STORE_UX 16463 || type == TYPE_MFCR) 16464 return true; 16465 } 16466 16467 return false; 16468} 16469 16470/* The function returns a nonzero value if INSN can be scheduled only 16471 as the first insn in a dispatch group ("dispatch-slot restricted"). 16472 In this case, the returned value indicates how many dispatch slots 16473 the insn occupies (at the beginning of the group). 16474 Return 0 otherwise. */ 16475 16476static int 16477is_dispatch_slot_restricted (rtx insn) 16478{ 16479 enum attr_type type; 16480 16481 if (!rs6000_sched_groups) 16482 return 0; 16483 16484 if (!insn 16485 || insn == NULL_RTX 16486 || GET_CODE (insn) == NOTE 16487 || GET_CODE (PATTERN (insn)) == USE 16488 || GET_CODE (PATTERN (insn)) == CLOBBER) 16489 return 0; 16490 16491 type = get_attr_type (insn); 16492 16493 switch (type) 16494 { 16495 case TYPE_MFCR: 16496 case TYPE_MFCRF: 16497 case TYPE_MTCR: 16498 case TYPE_DELAYED_CR: 16499 case TYPE_CR_LOGICAL: 16500 case TYPE_MTJMPR: 16501 case TYPE_MFJMPR: 16502 return 1; 16503 case TYPE_IDIV: 16504 case TYPE_LDIV: 16505 return 2; 16506 case TYPE_LOAD_L: 16507 case TYPE_STORE_C: 16508 case TYPE_ISYNC: 16509 case TYPE_SYNC: 16510 return 4; 16511 default: 16512 if (rs6000_cpu == PROCESSOR_POWER5 16513 && is_cracked_insn (insn)) 16514 return 2; 16515 return 0; 16516 } 16517} 16518 16519/* The function returns true if INSN is cracked into 2 instructions 16520 by the processor (and therefore occupies 2 issue slots). */ 16521 16522static bool 16523is_cracked_insn (rtx insn) 16524{ 16525 if (!insn || !INSN_P (insn) 16526 || GET_CODE (PATTERN (insn)) == USE 16527 || GET_CODE (PATTERN (insn)) == CLOBBER) 16528 return false; 16529 16530 if (rs6000_sched_groups) 16531 { 16532 enum attr_type type = get_attr_type (insn); 16533 if (type == TYPE_LOAD_U || type == TYPE_STORE_U 16534 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U 16535 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX 16536 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR 16537 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE 16538 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE 16539 || type == TYPE_IDIV || type == TYPE_LDIV 16540 || type == TYPE_INSERT_WORD) 16541 return true; 16542 } 16543 16544 return false; 16545} 16546 16547/* The function returns true if INSN can be issued only from 16548 the branch slot. */ 16549 16550static bool 16551is_branch_slot_insn (rtx insn) 16552{ 16553 if (!insn || !INSN_P (insn) 16554 || GET_CODE (PATTERN (insn)) == USE 16555 || GET_CODE (PATTERN (insn)) == CLOBBER) 16556 return false; 16557 16558 if (rs6000_sched_groups) 16559 { 16560 enum attr_type type = get_attr_type (insn); 16561 if (type == TYPE_BRANCH || type == TYPE_JMPREG) 16562 return true; 16563 return false; 16564 } 16565 16566 return false; 16567} 16568 16569/* A C statement (sans semicolon) to update the integer scheduling 16570 priority INSN_PRIORITY (INSN). Increase the priority to execute the 16571 INSN earlier, reduce the priority to execute INSN later. Do not 16572 define this macro if you do not need to adjust the scheduling 16573 priorities of insns. */ 16574 16575static int 16576rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority) 16577{ 16578 /* On machines (like the 750) which have asymmetric integer units, 16579 where one integer unit can do multiply and divides and the other 16580 can't, reduce the priority of multiply/divide so it is scheduled 16581 before other integer operations. */ 16582 16583#if 0 16584 if (! INSN_P (insn)) 16585 return priority; 16586 16587 if (GET_CODE (PATTERN (insn)) == USE) 16588 return priority; 16589 16590 switch (rs6000_cpu_attr) { 16591 case CPU_PPC750: 16592 switch (get_attr_type (insn)) 16593 { 16594 default: 16595 break; 16596 16597 case TYPE_IMUL: 16598 case TYPE_IDIV: 16599 fprintf (stderr, "priority was %#x (%d) before adjustment\n", 16600 priority, priority); 16601 if (priority >= 0 && priority < 0x01000000) 16602 priority >>= 3; 16603 break; 16604 } 16605 } 16606#endif 16607 16608 if (is_dispatch_slot_restricted (insn) 16609 && reload_completed 16610 && current_sched_info->sched_max_insns_priority 16611 && rs6000_sched_restricted_insns_priority) 16612 { 16613 16614 /* Prioritize insns that can be dispatched only in the first 16615 dispatch slot. */ 16616 if (rs6000_sched_restricted_insns_priority == 1) 16617 /* Attach highest priority to insn. This means that in 16618 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations 16619 precede 'priority' (critical path) considerations. */ 16620 return current_sched_info->sched_max_insns_priority; 16621 else if (rs6000_sched_restricted_insns_priority == 2) 16622 /* Increase priority of insn by a minimal amount. This means that in 16623 haifa-sched.c:ready_sort(), only 'priority' (critical path) 16624 considerations precede dispatch-slot restriction considerations. */ 16625 return (priority + 1); 16626 } 16627 16628 return priority; 16629} 16630 16631/* Return how many instructions the machine can issue per cycle. */ 16632 16633static int 16634rs6000_issue_rate (void) 16635{ 16636 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */ 16637 if (!reload_completed) 16638 return 1; 16639 16640 switch (rs6000_cpu_attr) { 16641 case CPU_RIOS1: /* ? */ 16642 case CPU_RS64A: 16643 case CPU_PPC601: /* ? */ 16644 case CPU_PPC7450: 16645 return 3; 16646 case CPU_PPC440: 16647 case CPU_PPC603: 16648 case CPU_PPC750: 16649 case CPU_PPC7400: 16650 case CPU_PPC8540: 16651 return 2; 16652 case CPU_RIOS2: 16653 case CPU_PPC604: 16654 case CPU_PPC604E: 16655 case CPU_PPC620: 16656 case CPU_PPC630: 16657 return 4; 16658 case CPU_POWER4: 16659 case CPU_POWER5: 16660 return 5; 16661 default: 16662 return 1; 16663 } 16664} 16665 16666/* Return how many instructions to look ahead for better insn 16667 scheduling. */ 16668 16669static int 16670rs6000_use_sched_lookahead (void) 16671{ 16672 if (rs6000_cpu_attr == CPU_PPC8540) 16673 return 4; 16674 return 0; 16675} 16676 16677/* Determine is PAT refers to memory. */ 16678 16679static bool 16680is_mem_ref (rtx pat) 16681{ 16682 const char * fmt; 16683 int i, j; 16684 bool ret = false; 16685 16686 if (GET_CODE (pat) == MEM) 16687 return true; 16688 16689 /* Recursively process the pattern. */ 16690 fmt = GET_RTX_FORMAT (GET_CODE (pat)); 16691 16692 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--) 16693 { 16694 if (fmt[i] == 'e') 16695 ret |= is_mem_ref (XEXP (pat, i)); 16696 else if (fmt[i] == 'E') 16697 for (j = XVECLEN (pat, i) - 1; j >= 0; j--) 16698 ret |= is_mem_ref (XVECEXP (pat, i, j)); 16699 } 16700 16701 return ret; 16702} 16703 16704/* Determine if PAT is a PATTERN of a load insn. */ 16705 16706static bool 16707is_load_insn1 (rtx pat) 16708{ 16709 if (!pat || pat == NULL_RTX) 16710 return false; 16711 16712 if (GET_CODE (pat) == SET) 16713 return is_mem_ref (SET_SRC (pat)); 16714 16715 if (GET_CODE (pat) == PARALLEL) 16716 { 16717 int i; 16718 16719 for (i = 0; i < XVECLEN (pat, 0); i++) 16720 if (is_load_insn1 (XVECEXP (pat, 0, i))) 16721 return true; 16722 } 16723 16724 return false; 16725} 16726 16727/* Determine if INSN loads from memory. */ 16728 16729static bool 16730is_load_insn (rtx insn) 16731{ 16732 if (!insn || !INSN_P (insn)) 16733 return false; 16734 16735 if (GET_CODE (insn) == CALL_INSN) 16736 return false; 16737 16738 return is_load_insn1 (PATTERN (insn)); 16739} 16740 16741/* Determine if PAT is a PATTERN of a store insn. */ 16742 16743static bool 16744is_store_insn1 (rtx pat) 16745{ 16746 if (!pat || pat == NULL_RTX) 16747 return false; 16748 16749 if (GET_CODE (pat) == SET) 16750 return is_mem_ref (SET_DEST (pat)); 16751 16752 if (GET_CODE (pat) == PARALLEL) 16753 { 16754 int i; 16755 16756 for (i = 0; i < XVECLEN (pat, 0); i++) 16757 if (is_store_insn1 (XVECEXP (pat, 0, i))) 16758 return true; 16759 } 16760 16761 return false; 16762} 16763 16764/* Determine if INSN stores to memory. */ 16765 16766static bool 16767is_store_insn (rtx insn) 16768{ 16769 if (!insn || !INSN_P (insn)) 16770 return false; 16771 16772 return is_store_insn1 (PATTERN (insn)); 16773} 16774 16775/* Returns whether the dependence between INSN and NEXT is considered 16776 costly by the given target. */ 16777 16778static bool 16779rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, 16780 int distance) 16781{ 16782 /* If the flag is not enabled - no dependence is considered costly; 16783 allow all dependent insns in the same group. 16784 This is the most aggressive option. */ 16785 if (rs6000_sched_costly_dep == no_dep_costly) 16786 return false; 16787 16788 /* If the flag is set to 1 - a dependence is always considered costly; 16789 do not allow dependent instructions in the same group. 16790 This is the most conservative option. */ 16791 if (rs6000_sched_costly_dep == all_deps_costly) 16792 return true; 16793 16794 if (rs6000_sched_costly_dep == store_to_load_dep_costly 16795 && is_load_insn (next) 16796 && is_store_insn (insn)) 16797 /* Prevent load after store in the same group. */ 16798 return true; 16799 16800 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly 16801 && is_load_insn (next) 16802 && is_store_insn (insn) 16803 && (!link || (int) REG_NOTE_KIND (link) == 0)) 16804 /* Prevent load after store in the same group if it is a true 16805 dependence. */ 16806 return true; 16807 16808 /* The flag is set to X; dependences with latency >= X are considered costly, 16809 and will not be scheduled in the same group. */ 16810 if (rs6000_sched_costly_dep <= max_dep_latency 16811 && ((cost - distance) >= (int)rs6000_sched_costly_dep)) 16812 return true; 16813 16814 return false; 16815} 16816 16817/* Return the next insn after INSN that is found before TAIL is reached, 16818 skipping any "non-active" insns - insns that will not actually occupy 16819 an issue slot. Return NULL_RTX if such an insn is not found. */ 16820 16821static rtx 16822get_next_active_insn (rtx insn, rtx tail) 16823{ 16824 if (insn == NULL_RTX || insn == tail) 16825 return NULL_RTX; 16826 16827 while (1) 16828 { 16829 insn = NEXT_INSN (insn); 16830 if (insn == NULL_RTX || insn == tail) 16831 return NULL_RTX; 16832 16833 if (CALL_P (insn) 16834 || JUMP_P (insn) 16835 || (NONJUMP_INSN_P (insn) 16836 && GET_CODE (PATTERN (insn)) != USE 16837 && GET_CODE (PATTERN (insn)) != CLOBBER 16838 && INSN_CODE (insn) != CODE_FOR_stack_tie)) 16839 break; 16840 } 16841 return insn; 16842} 16843 16844/* Return whether the presence of INSN causes a dispatch group termination 16845 of group WHICH_GROUP. 16846 16847 If WHICH_GROUP == current_group, this function will return true if INSN 16848 causes the termination of the current group (i.e, the dispatch group to 16849 which INSN belongs). This means that INSN will be the last insn in the 16850 group it belongs to. 16851 16852 If WHICH_GROUP == previous_group, this function will return true if INSN 16853 causes the termination of the previous group (i.e, the dispatch group that 16854 precedes the group to which INSN belongs). This means that INSN will be 16855 the first insn in the group it belongs to). */ 16856 16857static bool 16858insn_terminates_group_p (rtx insn, enum group_termination which_group) 16859{ 16860 enum attr_type type; 16861 16862 if (! insn) 16863 return false; 16864 16865 type = get_attr_type (insn); 16866 16867 if (is_microcoded_insn (insn)) 16868 return true; 16869 16870 if (which_group == current_group) 16871 { 16872 if (is_branch_slot_insn (insn)) 16873 return true; 16874 return false; 16875 } 16876 else if (which_group == previous_group) 16877 { 16878 if (is_dispatch_slot_restricted (insn)) 16879 return true; 16880 return false; 16881 } 16882 16883 return false; 16884} 16885 16886/* Return true if it is recommended to keep NEXT_INSN "far" (in a separate 16887 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */ 16888 16889static bool 16890is_costly_group (rtx *group_insns, rtx next_insn) 16891{ 16892 int i; 16893 rtx link; 16894 int cost; 16895 int issue_rate = rs6000_issue_rate (); 16896 16897 for (i = 0; i < issue_rate; i++) 16898 { 16899 rtx insn = group_insns[i]; 16900 if (!insn) 16901 continue; 16902 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1)) 16903 { 16904 rtx next = XEXP (link, 0); 16905 if (next == next_insn) 16906 { 16907 cost = insn_cost (insn, link, next_insn); 16908 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0)) 16909 return true; 16910 } 16911 } 16912 } 16913 16914 return false; 16915} 16916 16917/* Utility of the function redefine_groups. 16918 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS 16919 in the same dispatch group. If so, insert nops before NEXT_INSN, in order 16920 to keep it "far" (in a separate group) from GROUP_INSNS, following 16921 one of the following schemes, depending on the value of the flag 16922 -minsert_sched_nops = X: 16923 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed 16924 in order to force NEXT_INSN into a separate group. 16925 (2) X < sched_finish_regroup_exact: insert exactly X nops. 16926 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop 16927 insertion (has a group just ended, how many vacant issue slots remain in the 16928 last group, and how many dispatch groups were encountered so far). */ 16929 16930static int 16931force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, 16932 rtx next_insn, bool *group_end, int can_issue_more, 16933 int *group_count) 16934{ 16935 rtx nop; 16936 bool force; 16937 int issue_rate = rs6000_issue_rate (); 16938 bool end = *group_end; 16939 int i; 16940 16941 if (next_insn == NULL_RTX) 16942 return can_issue_more; 16943 16944 if (rs6000_sched_insert_nops > sched_finish_regroup_exact) 16945 return can_issue_more; 16946 16947 force = is_costly_group (group_insns, next_insn); 16948 if (!force) 16949 return can_issue_more; 16950 16951 if (sched_verbose > 6) 16952 fprintf (dump,"force: group count = %d, can_issue_more = %d\n", 16953 *group_count ,can_issue_more); 16954 16955 if (rs6000_sched_insert_nops == sched_finish_regroup_exact) 16956 { 16957 if (*group_end) 16958 can_issue_more = 0; 16959 16960 /* Since only a branch can be issued in the last issue_slot, it is 16961 sufficient to insert 'can_issue_more - 1' nops if next_insn is not 16962 a branch. If next_insn is a branch, we insert 'can_issue_more' nops; 16963 in this case the last nop will start a new group and the branch 16964 will be forced to the new group. */ 16965 if (can_issue_more && !is_branch_slot_insn (next_insn)) 16966 can_issue_more--; 16967 16968 while (can_issue_more > 0) 16969 { 16970 nop = gen_nop (); 16971 emit_insn_before (nop, next_insn); 16972 can_issue_more--; 16973 } 16974 16975 *group_end = true; 16976 return 0; 16977 } 16978 16979 if (rs6000_sched_insert_nops < sched_finish_regroup_exact) 16980 { 16981 int n_nops = rs6000_sched_insert_nops; 16982 16983 /* Nops can't be issued from the branch slot, so the effective 16984 issue_rate for nops is 'issue_rate - 1'. */ 16985 if (can_issue_more == 0) 16986 can_issue_more = issue_rate; 16987 can_issue_more--; 16988 if (can_issue_more == 0) 16989 { 16990 can_issue_more = issue_rate - 1; 16991 (*group_count)++; 16992 end = true; 16993 for (i = 0; i < issue_rate; i++) 16994 { 16995 group_insns[i] = 0; 16996 } 16997 } 16998 16999 while (n_nops > 0) 17000 { 17001 nop = gen_nop (); 17002 emit_insn_before (nop, next_insn); 17003 if (can_issue_more == issue_rate - 1) /* new group begins */ 17004 end = false; 17005 can_issue_more--; 17006 if (can_issue_more == 0) 17007 { 17008 can_issue_more = issue_rate - 1; 17009 (*group_count)++; 17010 end = true; 17011 for (i = 0; i < issue_rate; i++) 17012 { 17013 group_insns[i] = 0; 17014 } 17015 } 17016 n_nops--; 17017 } 17018 17019 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */ 17020 can_issue_more++; 17021 17022 /* Is next_insn going to start a new group? */ 17023 *group_end 17024 = (end 17025 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) 17026 || (can_issue_more <= 2 && is_cracked_insn (next_insn)) 17027 || (can_issue_more < issue_rate && 17028 insn_terminates_group_p (next_insn, previous_group))); 17029 if (*group_end && end) 17030 (*group_count)--; 17031 17032 if (sched_verbose > 6) 17033 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n", 17034 *group_count, can_issue_more); 17035 return can_issue_more; 17036 } 17037 17038 return can_issue_more; 17039} 17040 17041/* This function tries to synch the dispatch groups that the compiler "sees" 17042 with the dispatch groups that the processor dispatcher is expected to 17043 form in practice. It tries to achieve this synchronization by forcing the 17044 estimated processor grouping on the compiler (as opposed to the function 17045 'pad_goups' which tries to force the scheduler's grouping on the processor). 17046 17047 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and 17048 examines the (estimated) dispatch groups that will be formed by the processor 17049 dispatcher. It marks these group boundaries to reflect the estimated 17050 processor grouping, overriding the grouping that the scheduler had marked. 17051 Depending on the value of the flag '-minsert-sched-nops' this function can 17052 force certain insns into separate groups or force a certain distance between 17053 them by inserting nops, for example, if there exists a "costly dependence" 17054 between the insns. 17055 17056 The function estimates the group boundaries that the processor will form as 17057 follows: It keeps track of how many vacant issue slots are available after 17058 each insn. A subsequent insn will start a new group if one of the following 17059 4 cases applies: 17060 - no more vacant issue slots remain in the current dispatch group. 17061 - only the last issue slot, which is the branch slot, is vacant, but the next 17062 insn is not a branch. 17063 - only the last 2 or less issue slots, including the branch slot, are vacant, 17064 which means that a cracked insn (which occupies two issue slots) can't be 17065 issued in this group. 17066 - less than 'issue_rate' slots are vacant, and the next insn always needs to 17067 start a new group. */ 17068 17069static int 17070redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) 17071{ 17072 rtx insn, next_insn; 17073 int issue_rate; 17074 int can_issue_more; 17075 int slot, i; 17076 bool group_end; 17077 int group_count = 0; 17078 rtx *group_insns; 17079 17080 /* Initialize. */ 17081 issue_rate = rs6000_issue_rate (); 17082 group_insns = alloca (issue_rate * sizeof (rtx)); 17083 for (i = 0; i < issue_rate; i++) 17084 { 17085 group_insns[i] = 0; 17086 } 17087 can_issue_more = issue_rate; 17088 slot = 0; 17089 insn = get_next_active_insn (prev_head_insn, tail); 17090 group_end = false; 17091 17092 while (insn != NULL_RTX) 17093 { 17094 slot = (issue_rate - can_issue_more); 17095 group_insns[slot] = insn; 17096 can_issue_more = 17097 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); 17098 if (insn_terminates_group_p (insn, current_group)) 17099 can_issue_more = 0; 17100 17101 next_insn = get_next_active_insn (insn, tail); 17102 if (next_insn == NULL_RTX) 17103 return group_count + 1; 17104 17105 /* Is next_insn going to start a new group? */ 17106 group_end 17107 = (can_issue_more == 0 17108 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) 17109 || (can_issue_more <= 2 && is_cracked_insn (next_insn)) 17110 || (can_issue_more < issue_rate && 17111 insn_terminates_group_p (next_insn, previous_group))); 17112 17113 can_issue_more = force_new_group (sched_verbose, dump, group_insns, 17114 next_insn, &group_end, can_issue_more, 17115 &group_count); 17116 17117 if (group_end) 17118 { 17119 group_count++; 17120 can_issue_more = 0; 17121 for (i = 0; i < issue_rate; i++) 17122 { 17123 group_insns[i] = 0; 17124 } 17125 } 17126 17127 if (GET_MODE (next_insn) == TImode && can_issue_more) 17128 PUT_MODE (next_insn, VOIDmode); 17129 else if (!can_issue_more && GET_MODE (next_insn) != TImode) 17130 PUT_MODE (next_insn, TImode); 17131 17132 insn = next_insn; 17133 if (can_issue_more == 0) 17134 can_issue_more = issue_rate; 17135 } /* while */ 17136 17137 return group_count; 17138} 17139 17140/* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the 17141 dispatch group boundaries that the scheduler had marked. Pad with nops 17142 any dispatch groups which have vacant issue slots, in order to force the 17143 scheduler's grouping on the processor dispatcher. The function 17144 returns the number of dispatch groups found. */ 17145 17146static int 17147pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) 17148{ 17149 rtx insn, next_insn; 17150 rtx nop; 17151 int issue_rate; 17152 int can_issue_more; 17153 int group_end; 17154 int group_count = 0; 17155 17156 /* Initialize issue_rate. */ 17157 issue_rate = rs6000_issue_rate (); 17158 can_issue_more = issue_rate; 17159 17160 insn = get_next_active_insn (prev_head_insn, tail); 17161 next_insn = get_next_active_insn (insn, tail); 17162 17163 while (insn != NULL_RTX) 17164 { 17165 can_issue_more = 17166 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); 17167 17168 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode); 17169 17170 if (next_insn == NULL_RTX) 17171 break; 17172 17173 if (group_end) 17174 { 17175 /* If the scheduler had marked group termination at this location 17176 (between insn and next_indn), and neither insn nor next_insn will 17177 force group termination, pad the group with nops to force group 17178 termination. */ 17179 if (can_issue_more 17180 && (rs6000_sched_insert_nops == sched_finish_pad_groups) 17181 && !insn_terminates_group_p (insn, current_group) 17182 && !insn_terminates_group_p (next_insn, previous_group)) 17183 { 17184 if (!is_branch_slot_insn (next_insn)) 17185 can_issue_more--; 17186 17187 while (can_issue_more) 17188 { 17189 nop = gen_nop (); 17190 emit_insn_before (nop, next_insn); 17191 can_issue_more--; 17192 } 17193 } 17194 17195 can_issue_more = issue_rate; 17196 group_count++; 17197 } 17198 17199 insn = next_insn; 17200 next_insn = get_next_active_insn (insn, tail); 17201 } 17202 17203 return group_count; 17204} 17205 17206/* The following function is called at the end of scheduling BB. 17207 After reload, it inserts nops at insn group bundling. */ 17208 17209static void 17210rs6000_sched_finish (FILE *dump, int sched_verbose) 17211{ 17212 int n_groups; 17213 17214 if (sched_verbose) 17215 fprintf (dump, "=== Finishing schedule.\n"); 17216 17217 if (reload_completed && rs6000_sched_groups) 17218 { 17219 if (rs6000_sched_insert_nops == sched_finish_none) 17220 return; 17221 17222 if (rs6000_sched_insert_nops == sched_finish_pad_groups) 17223 n_groups = pad_groups (dump, sched_verbose, 17224 current_sched_info->prev_head, 17225 current_sched_info->next_tail); 17226 else 17227 n_groups = redefine_groups (dump, sched_verbose, 17228 current_sched_info->prev_head, 17229 current_sched_info->next_tail); 17230 17231 if (sched_verbose >= 6) 17232 { 17233 fprintf (dump, "ngroups = %d\n", n_groups); 17234 print_rtl (dump, current_sched_info->prev_head); 17235 fprintf (dump, "Done finish_sched\n"); 17236 } 17237 } 17238} 17239 17240/* Length in units of the trampoline for entering a nested function. */ 17241 17242int 17243rs6000_trampoline_size (void) 17244{ 17245 int ret = 0; 17246 17247 switch (DEFAULT_ABI) 17248 { 17249 default: 17250 gcc_unreachable (); 17251 17252 case ABI_AIX: 17253 ret = (TARGET_32BIT) ? 12 : 24; 17254 break; 17255 17256 case ABI_DARWIN: 17257 case ABI_V4: 17258 ret = (TARGET_32BIT) ? 40 : 48; 17259 break; 17260 } 17261 17262 return ret; 17263} 17264 17265/* Emit RTL insns to initialize the variable parts of a trampoline. 17266 FNADDR is an RTX for the address of the function's pure code. 17267 CXT is an RTX for the static chain value for the function. */ 17268 17269void 17270rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt) 17271{ 17272 enum machine_mode pmode = Pmode; 17273 int regsize = (TARGET_32BIT) ? 4 : 8; 17274 rtx ctx_reg = force_reg (pmode, cxt); 17275 17276 switch (DEFAULT_ABI) 17277 { 17278 default: 17279 gcc_unreachable (); 17280 17281/* Macros to shorten the code expansions below. */ 17282#define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) 17283#define MEM_PLUS(addr,offset) \ 17284 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) 17285 17286 /* Under AIX, just build the 3 word function descriptor */ 17287 case ABI_AIX: 17288 { 17289 rtx fn_reg = gen_reg_rtx (pmode); 17290 rtx toc_reg = gen_reg_rtx (pmode); 17291 emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); 17292 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); 17293 emit_move_insn (MEM_DEREF (addr), fn_reg); 17294 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); 17295 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); 17296 } 17297 break; 17298 17299 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */ 17300 case ABI_DARWIN: 17301 case ABI_V4: 17302 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), 17303 FALSE, VOIDmode, 4, 17304 addr, pmode, 17305 GEN_INT (rs6000_trampoline_size ()), SImode, 17306 fnaddr, pmode, 17307 ctx_reg, pmode); 17308#ifdef TRANSFER_FROM_TRAMPOLINE 17309 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"), 17310 LCT_NORMAL, VOIDmode, 1, addr, Pmode); 17311#endif 17312 break; 17313 } 17314 17315 return; 17316} 17317 17318 17319/* Table of valid machine attributes. */ 17320 17321const struct attribute_spec rs6000_attribute_table[] = 17322{ 17323 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ 17324 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute }, 17325 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, 17326 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, 17327#ifdef SUBTARGET_ATTRIBUTE_TABLE 17328 SUBTARGET_ATTRIBUTE_TABLE, 17329#endif 17330 { NULL, 0, 0, false, false, false, NULL } 17331}; 17332 17333/* Handle the "altivec" attribute. The attribute may have 17334 arguments as follows: 17335 17336 __attribute__((altivec(vector__))) 17337 __attribute__((altivec(pixel__))) (always followed by 'unsigned short') 17338 __attribute__((altivec(bool__))) (always followed by 'unsigned') 17339 17340 and may appear more than once (e.g., 'vector bool char') in a 17341 given declaration. */ 17342 17343static tree 17344rs6000_handle_altivec_attribute (tree *node, 17345 tree name ATTRIBUTE_UNUSED, 17346 tree args, 17347 int flags ATTRIBUTE_UNUSED, 17348 bool *no_add_attrs) 17349{ 17350 tree type = *node, result = NULL_TREE; 17351 enum machine_mode mode; 17352 int unsigned_p; 17353 char altivec_type 17354 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args) 17355 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE) 17356 ? *IDENTIFIER_POINTER (TREE_VALUE (args)) 17357 : '?'); 17358 17359 while (POINTER_TYPE_P (type) 17360 || TREE_CODE (type) == FUNCTION_TYPE 17361 || TREE_CODE (type) == METHOD_TYPE 17362 || TREE_CODE (type) == ARRAY_TYPE) 17363 type = TREE_TYPE (type); 17364 17365 mode = TYPE_MODE (type); 17366 17367 /* Check for invalid AltiVec type qualifiers. */ 17368 if (type == long_unsigned_type_node || type == long_integer_type_node) 17369 { 17370 if (TARGET_64BIT) 17371 error ("use of %<long%> in AltiVec types is invalid for 64-bit code"); 17372 else if (rs6000_warn_altivec_long) 17373 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>"); 17374 } 17375 else if (type == long_long_unsigned_type_node 17376 || type == long_long_integer_type_node) 17377 error ("use of %<long long%> in AltiVec types is invalid"); 17378 else if (type == double_type_node) 17379 error ("use of %<double%> in AltiVec types is invalid"); 17380 else if (type == long_double_type_node) 17381 error ("use of %<long double%> in AltiVec types is invalid"); 17382 else if (type == boolean_type_node) 17383 error ("use of boolean types in AltiVec types is invalid"); 17384 else if (TREE_CODE (type) == COMPLEX_TYPE) 17385 error ("use of %<complex%> in AltiVec types is invalid"); 17386 17387 switch (altivec_type) 17388 { 17389 case 'v': 17390 unsigned_p = TYPE_UNSIGNED (type); 17391 switch (mode) 17392 { 17393 case SImode: 17394 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node); 17395 break; 17396 case HImode: 17397 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node); 17398 break; 17399 case QImode: 17400 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node); 17401 break; 17402 case SFmode: result = V4SF_type_node; break; 17403 /* If the user says 'vector int bool', we may be handed the 'bool' 17404 attribute _before_ the 'vector' attribute, and so select the 17405 proper type in the 'b' case below. */ 17406 case V4SImode: case V8HImode: case V16QImode: case V4SFmode: 17407 result = type; 17408 default: break; 17409 } 17410 break; 17411 case 'b': 17412 switch (mode) 17413 { 17414 case SImode: case V4SImode: result = bool_V4SI_type_node; break; 17415 case HImode: case V8HImode: result = bool_V8HI_type_node; break; 17416 case QImode: case V16QImode: result = bool_V16QI_type_node; 17417 default: break; 17418 } 17419 break; 17420 case 'p': 17421 switch (mode) 17422 { 17423 case V8HImode: result = pixel_V8HI_type_node; 17424 default: break; 17425 } 17426 default: break; 17427 } 17428 17429 if (result && result != type && TYPE_READONLY (type)) 17430 result = build_qualified_type (result, TYPE_QUAL_CONST); 17431 17432 *no_add_attrs = true; /* No need to hang on to the attribute. */ 17433 17434 if (result) 17435 *node = reconstruct_complex_type (*node, result); 17436 17437 return NULL_TREE; 17438} 17439 17440/* AltiVec defines four built-in scalar types that serve as vector 17441 elements; we must teach the compiler how to mangle them. */ 17442 17443static const char * 17444rs6000_mangle_fundamental_type (tree type) 17445{ 17446 if (type == bool_char_type_node) return "U6__boolc"; 17447 if (type == bool_short_type_node) return "U6__bools"; 17448 if (type == pixel_type_node) return "u7__pixel"; 17449 if (type == bool_int_type_node) return "U6__booli"; 17450 17451 /* Mangle IBM extended float long double as `g' (__float128) on 17452 powerpc*-linux where long-double-64 previously was the default. */ 17453 if (TYPE_MAIN_VARIANT (type) == long_double_type_node 17454 && TARGET_ELF 17455 && TARGET_LONG_DOUBLE_128 17456 && !TARGET_IEEEQUAD) 17457 return "g"; 17458 17459 /* For all other types, use normal C++ mangling. */ 17460 return NULL; 17461} 17462 17463/* Handle a "longcall" or "shortcall" attribute; arguments as in 17464 struct attribute_spec.handler. */ 17465 17466static tree 17467rs6000_handle_longcall_attribute (tree *node, tree name, 17468 tree args ATTRIBUTE_UNUSED, 17469 int flags ATTRIBUTE_UNUSED, 17470 bool *no_add_attrs) 17471{ 17472 if (TREE_CODE (*node) != FUNCTION_TYPE 17473 && TREE_CODE (*node) != FIELD_DECL 17474 && TREE_CODE (*node) != TYPE_DECL) 17475 { 17476 warning (OPT_Wattributes, "%qs attribute only applies to functions", 17477 IDENTIFIER_POINTER (name)); 17478 *no_add_attrs = true; 17479 } 17480 17481 return NULL_TREE; 17482} 17483 17484/* Set longcall attributes on all functions declared when 17485 rs6000_default_long_calls is true. */ 17486static void 17487rs6000_set_default_type_attributes (tree type) 17488{ 17489 if (rs6000_default_long_calls 17490 && (TREE_CODE (type) == FUNCTION_TYPE 17491 || TREE_CODE (type) == METHOD_TYPE)) 17492 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"), 17493 NULL_TREE, 17494 TYPE_ATTRIBUTES (type)); 17495} 17496 17497/* Return a reference suitable for calling a function with the 17498 longcall attribute. */ 17499 17500rtx 17501rs6000_longcall_ref (rtx call_ref) 17502{ 17503 const char *call_name; 17504 tree node; 17505 17506 if (GET_CODE (call_ref) != SYMBOL_REF) 17507 return call_ref; 17508 17509 /* System V adds '.' to the internal name, so skip them. */ 17510 call_name = XSTR (call_ref, 0); 17511 if (*call_name == '.') 17512 { 17513 while (*call_name == '.') 17514 call_name++; 17515 17516 node = get_identifier (call_name); 17517 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); 17518 } 17519 17520 return force_reg (Pmode, call_ref); 17521} 17522 17523#ifdef USING_ELFOS_H 17524 17525/* A C statement or statements to switch to the appropriate section 17526 for output of RTX in mode MODE. You can assume that RTX is some 17527 kind of constant in RTL. The argument MODE is redundant except in 17528 the case of a `const_int' rtx. Select the section by calling 17529 `text_section' or one of the alternatives for other sections. 17530 17531 Do not define this macro if you put all constants in the read-only 17532 data section. */ 17533 17534static void 17535rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x, 17536 unsigned HOST_WIDE_INT align) 17537{ 17538 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) 17539 toc_section (); 17540 else 17541 default_elf_select_rtx_section (mode, x, align); 17542} 17543 17544/* A C statement or statements to switch to the appropriate 17545 section for output of DECL. DECL is either a `VAR_DECL' node 17546 or a constant of some sort. RELOC indicates whether forming 17547 the initial value of DECL requires link-time relocations. */ 17548 17549static void 17550rs6000_elf_select_section (tree decl, int reloc, 17551 unsigned HOST_WIDE_INT align) 17552{ 17553 /* Pretend that we're always building for a shared library when 17554 ABI_AIX, because otherwise we end up with dynamic relocations 17555 in read-only sections. This happens for function pointers, 17556 references to vtables in typeinfo, and probably other cases. */ 17557 default_elf_select_section_1 (decl, reloc, align, 17558 flag_pic || DEFAULT_ABI == ABI_AIX); 17559} 17560 17561/* A C statement to build up a unique section name, expressed as a 17562 STRING_CST node, and assign it to DECL_SECTION_NAME (decl). 17563 RELOC indicates whether the initial value of EXP requires 17564 link-time relocations. If you do not define this macro, GCC will use 17565 the symbol name prefixed by `.' as the section name. Note - this 17566 macro can now be called for uninitialized data items as well as 17567 initialized data and functions. */ 17568 17569static void 17570rs6000_elf_unique_section (tree decl, int reloc) 17571{ 17572 /* As above, pretend that we're always building for a shared library 17573 when ABI_AIX, to avoid dynamic relocations in read-only sections. */ 17574 default_unique_section_1 (decl, reloc, 17575 flag_pic || DEFAULT_ABI == ABI_AIX); 17576} 17577 17578/* For a SYMBOL_REF, set generic flags and then perform some 17579 target-specific processing. 17580 17581 When the AIX ABI is requested on a non-AIX system, replace the 17582 function name with the real name (with a leading .) rather than the 17583 function descriptor name. This saves a lot of overriding code to 17584 read the prefixes. */ 17585 17586static void 17587rs6000_elf_encode_section_info (tree decl, rtx rtl, int first) 17588{ 17589 default_encode_section_info (decl, rtl, first); 17590 17591 if (first 17592 && TREE_CODE (decl) == FUNCTION_DECL 17593 && !TARGET_AIX 17594 && DEFAULT_ABI == ABI_AIX) 17595 { 17596 rtx sym_ref = XEXP (rtl, 0); 17597 size_t len = strlen (XSTR (sym_ref, 0)); 17598 char *str = alloca (len + 2); 17599 str[0] = '.'; 17600 memcpy (str + 1, XSTR (sym_ref, 0), len + 1); 17601 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); 17602 } 17603} 17604 17605static bool 17606rs6000_elf_in_small_data_p (tree decl) 17607{ 17608 if (rs6000_sdata == SDATA_NONE) 17609 return false; 17610 17611 /* We want to merge strings, so we never consider them small data. */ 17612 if (TREE_CODE (decl) == STRING_CST) 17613 return false; 17614 17615 /* Functions are never in the small data area. */ 17616 if (TREE_CODE (decl) == FUNCTION_DECL) 17617 return false; 17618 17619 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl)) 17620 { 17621 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); 17622 if (strcmp (section, ".sdata") == 0 17623 || strcmp (section, ".sdata2") == 0 17624 || strcmp (section, ".sbss") == 0 17625 || strcmp (section, ".sbss2") == 0 17626 || strcmp (section, ".PPC.EMB.sdata0") == 0 17627 || strcmp (section, ".PPC.EMB.sbss0") == 0) 17628 return true; 17629 } 17630 else 17631 { 17632 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl)); 17633 17634 if (size > 0 17635 && (unsigned HOST_WIDE_INT) size <= g_switch_value 17636 /* If it's not public, and we're not going to reference it there, 17637 there's no need to put it in the small data section. */ 17638 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))) 17639 return true; 17640 } 17641 17642 return false; 17643} 17644 17645#endif /* USING_ELFOS_H */ 17646 17647 17648/* Return a REG that occurs in ADDR with coefficient 1. 17649 ADDR can be effectively incremented by incrementing REG. 17650 17651 r0 is special and we must not select it as an address 17652 register by this routine since our caller will try to 17653 increment the returned register via an "la" instruction. */ 17654 17655rtx 17656find_addr_reg (rtx addr) 17657{ 17658 while (GET_CODE (addr) == PLUS) 17659 { 17660 if (GET_CODE (XEXP (addr, 0)) == REG 17661 && REGNO (XEXP (addr, 0)) != 0) 17662 addr = XEXP (addr, 0); 17663 else if (GET_CODE (XEXP (addr, 1)) == REG 17664 && REGNO (XEXP (addr, 1)) != 0) 17665 addr = XEXP (addr, 1); 17666 else if (CONSTANT_P (XEXP (addr, 0))) 17667 addr = XEXP (addr, 1); 17668 else if (CONSTANT_P (XEXP (addr, 1))) 17669 addr = XEXP (addr, 0); 17670 else 17671 gcc_unreachable (); 17672 } 17673 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0); 17674 return addr; 17675} 17676 17677void 17678rs6000_fatal_bad_address (rtx op) 17679{ 17680 fatal_insn ("bad address", op); 17681} 17682 17683#if TARGET_MACHO 17684 17685static tree branch_island_list = 0; 17686 17687/* Remember to generate a branch island for far calls to the given 17688 function. */ 17689 17690static void 17691add_compiler_branch_island (tree label_name, tree function_name, 17692 int line_number) 17693{ 17694 tree branch_island = build_tree_list (function_name, label_name); 17695 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number); 17696 TREE_CHAIN (branch_island) = branch_island_list; 17697 branch_island_list = branch_island; 17698} 17699 17700#define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND) 17701#define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND) 17702#define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \ 17703 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND)) 17704 17705/* Generate far-jump branch islands for everything on the 17706 branch_island_list. Invoked immediately after the last instruction 17707 of the epilogue has been emitted; the branch-islands must be 17708 appended to, and contiguous with, the function body. Mach-O stubs 17709 are generated in machopic_output_stub(). */ 17710 17711static void 17712macho_branch_islands (void) 17713{ 17714 char tmp_buf[512]; 17715 tree branch_island; 17716 17717 for (branch_island = branch_island_list; 17718 branch_island; 17719 branch_island = TREE_CHAIN (branch_island)) 17720 { 17721 const char *label = 17722 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island)); 17723 const char *name = 17724 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island)); 17725 char name_buf[512]; 17726 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */ 17727 if (name[0] == '*' || name[0] == '&') 17728 strcpy (name_buf, name+1); 17729 else 17730 { 17731 name_buf[0] = '_'; 17732 strcpy (name_buf+1, name); 17733 } 17734 strcpy (tmp_buf, "\n"); 17735 strcat (tmp_buf, label); 17736#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) 17737 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) 17738 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island)); 17739#endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ 17740 if (flag_pic) 17741 { 17742 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,"); 17743 strcat (tmp_buf, label); 17744 strcat (tmp_buf, "_pic\n"); 17745 strcat (tmp_buf, label); 17746 strcat (tmp_buf, "_pic:\n\tmflr r11\n"); 17747 17748 strcat (tmp_buf, "\taddis r11,r11,ha16("); 17749 strcat (tmp_buf, name_buf); 17750 strcat (tmp_buf, " - "); 17751 strcat (tmp_buf, label); 17752 strcat (tmp_buf, "_pic)\n"); 17753 17754 strcat (tmp_buf, "\tmtlr r0\n"); 17755 17756 strcat (tmp_buf, "\taddi r12,r11,lo16("); 17757 strcat (tmp_buf, name_buf); 17758 strcat (tmp_buf, " - "); 17759 strcat (tmp_buf, label); 17760 strcat (tmp_buf, "_pic)\n"); 17761 17762 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n"); 17763 } 17764 else 17765 { 17766 strcat (tmp_buf, ":\nlis r12,hi16("); 17767 strcat (tmp_buf, name_buf); 17768 strcat (tmp_buf, ")\n\tori r12,r12,lo16("); 17769 strcat (tmp_buf, name_buf); 17770 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); 17771 } 17772 output_asm_insn (tmp_buf, 0); 17773#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) 17774 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) 17775 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island)); 17776#endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ 17777 } 17778 17779 branch_island_list = 0; 17780} 17781 17782/* NO_PREVIOUS_DEF checks in the link list whether the function name is 17783 already there or not. */ 17784 17785static int 17786no_previous_def (tree function_name) 17787{ 17788 tree branch_island; 17789 for (branch_island = branch_island_list; 17790 branch_island; 17791 branch_island = TREE_CHAIN (branch_island)) 17792 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) 17793 return 0; 17794 return 1; 17795} 17796 17797/* GET_PREV_LABEL gets the label name from the previous definition of 17798 the function. */ 17799 17800static tree 17801get_prev_label (tree function_name) 17802{ 17803 tree branch_island; 17804 for (branch_island = branch_island_list; 17805 branch_island; 17806 branch_island = TREE_CHAIN (branch_island)) 17807 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) 17808 return BRANCH_ISLAND_LABEL_NAME (branch_island); 17809 return 0; 17810} 17811 17812/* INSN is either a function call or a millicode call. It may have an 17813 unconditional jump in its delay slot. 17814 17815 CALL_DEST is the routine we are calling. */ 17816 17817char * 17818output_call (rtx insn, rtx *operands, int dest_operand_number, 17819 int cookie_operand_number) 17820{ 17821 static char buf[256]; 17822 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF 17823 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG)) 17824 { 17825 tree labelname; 17826 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0)); 17827 17828 if (no_previous_def (funname)) 17829 { 17830 int line_number = 0; 17831 rtx label_rtx = gen_label_rtx (); 17832 char *label_buf, temp_buf[256]; 17833 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", 17834 CODE_LABEL_NUMBER (label_rtx)); 17835 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; 17836 labelname = get_identifier (label_buf); 17837 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); 17838 if (insn) 17839 line_number = NOTE_LINE_NUMBER (insn); 17840 add_compiler_branch_island (labelname, funname, line_number); 17841 } 17842 else 17843 labelname = get_prev_label (funname); 17844 17845 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl' 17846 instruction will reach 'foo', otherwise link as 'bl L42'". 17847 "L42" should be a 'branch island', that will do a far jump to 17848 'foo'. Branch islands are generated in 17849 macho_branch_islands(). */ 17850 sprintf (buf, "jbsr %%z%d,%.246s", 17851 dest_operand_number, IDENTIFIER_POINTER (labelname)); 17852 } 17853 else 17854 sprintf (buf, "bl %%z%d", dest_operand_number); 17855 return buf; 17856} 17857 17858/* Generate PIC and indirect symbol stubs. */ 17859 17860void 17861machopic_output_stub (FILE *file, const char *symb, const char *stub) 17862{ 17863 unsigned int length; 17864 char *symbol_name, *lazy_ptr_name; 17865 char *local_label_0; 17866 static int label = 0; 17867 17868 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ 17869 symb = (*targetm.strip_name_encoding) (symb); 17870 17871 17872 length = strlen (symb); 17873 symbol_name = alloca (length + 32); 17874 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); 17875 17876 lazy_ptr_name = alloca (length + 32); 17877 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); 17878 17879 if (flag_pic == 2) 17880 machopic_picsymbol_stub1_section (); 17881 else 17882 machopic_symbol_stub1_section (); 17883 17884 if (flag_pic == 2) 17885 { 17886 fprintf (file, "\t.align 5\n"); 17887 17888 fprintf (file, "%s:\n", stub); 17889 fprintf (file, "\t.indirect_symbol %s\n", symbol_name); 17890 17891 label++; 17892 local_label_0 = alloca (sizeof ("\"L00000000000$spb\"")); 17893 sprintf (local_label_0, "\"L%011d$spb\"", label); 17894 17895 fprintf (file, "\tmflr r0\n"); 17896 fprintf (file, "\tbcl 20,31,%s\n", local_label_0); 17897 fprintf (file, "%s:\n\tmflr r11\n", local_label_0); 17898 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", 17899 lazy_ptr_name, local_label_0); 17900 fprintf (file, "\tmtlr r0\n"); 17901 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n", 17902 (TARGET_64BIT ? "ldu" : "lwzu"), 17903 lazy_ptr_name, local_label_0); 17904 fprintf (file, "\tmtctr r12\n"); 17905 fprintf (file, "\tbctr\n"); 17906 } 17907 else 17908 { 17909 fprintf (file, "\t.align 4\n"); 17910 17911 fprintf (file, "%s:\n", stub); 17912 fprintf (file, "\t.indirect_symbol %s\n", symbol_name); 17913 17914 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name); 17915 fprintf (file, "\t%s r12,lo16(%s)(r11)\n", 17916 (TARGET_64BIT ? "ldu" : "lwzu"), 17917 lazy_ptr_name); 17918 fprintf (file, "\tmtctr r12\n"); 17919 fprintf (file, "\tbctr\n"); 17920 } 17921 17922 machopic_lazy_symbol_ptr_section (); 17923 fprintf (file, "%s:\n", lazy_ptr_name); 17924 fprintf (file, "\t.indirect_symbol %s\n", symbol_name); 17925 fprintf (file, "%sdyld_stub_binding_helper\n", 17926 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t")); 17927} 17928 17929/* Legitimize PIC addresses. If the address is already 17930 position-independent, we return ORIG. Newly generated 17931 position-independent addresses go into a reg. This is REG if non 17932 zero, otherwise we allocate register(s) as necessary. */ 17933 17934#define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000) 17935 17936rtx 17937rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, 17938 rtx reg) 17939{ 17940 rtx base, offset; 17941 17942 if (reg == NULL && ! reload_in_progress && ! reload_completed) 17943 reg = gen_reg_rtx (Pmode); 17944 17945 if (GET_CODE (orig) == CONST) 17946 { 17947 rtx reg_temp; 17948 17949 if (GET_CODE (XEXP (orig, 0)) == PLUS 17950 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) 17951 return orig; 17952 17953 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); 17954 17955 /* Use a different reg for the intermediate value, as 17956 it will be marked UNCHANGING. */ 17957 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode); 17958 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), 17959 Pmode, reg_temp); 17960 offset = 17961 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), 17962 Pmode, reg); 17963 17964 if (GET_CODE (offset) == CONST_INT) 17965 { 17966 if (SMALL_INT (offset)) 17967 return plus_constant (base, INTVAL (offset)); 17968 else if (! reload_in_progress && ! reload_completed) 17969 offset = force_reg (Pmode, offset); 17970 else 17971 { 17972 rtx mem = force_const_mem (Pmode, orig); 17973 return machopic_legitimize_pic_address (mem, Pmode, reg); 17974 } 17975 } 17976 return gen_rtx_PLUS (Pmode, base, offset); 17977 } 17978 17979 /* Fall back on generic machopic code. */ 17980 return machopic_legitimize_pic_address (orig, mode, reg); 17981} 17982 17983/* This is just a placeholder to make linking work without having to 17984 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is 17985 ever needed for Darwin (not too likely!) this would have to get a 17986 real definition. */ 17987 17988void 17989toc_section (void) 17990{ 17991} 17992 17993/* Output a .machine directive for the Darwin assembler, and call 17994 the generic start_file routine. */ 17995 17996static void 17997rs6000_darwin_file_start (void) 17998{ 17999 static const struct 18000 { 18001 const char *arg; 18002 const char *name; 18003 int if_set; 18004 } mapping[] = { 18005 { "ppc64", "ppc64", MASK_64BIT }, 18006 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 }, 18007 { "power4", "ppc970", 0 }, 18008 { "G5", "ppc970", 0 }, 18009 { "7450", "ppc7450", 0 }, 18010 { "7400", "ppc7400", MASK_ALTIVEC }, 18011 { "G4", "ppc7400", 0 }, 18012 { "750", "ppc750", 0 }, 18013 { "740", "ppc750", 0 }, 18014 { "G3", "ppc750", 0 }, 18015 { "604e", "ppc604e", 0 }, 18016 { "604", "ppc604", 0 }, 18017 { "603e", "ppc603", 0 }, 18018 { "603", "ppc603", 0 }, 18019 { "601", "ppc601", 0 }, 18020 { NULL, "ppc", 0 } }; 18021 const char *cpu_id = ""; 18022 size_t i; 18023 18024 rs6000_file_start (); 18025 18026 /* Determine the argument to -mcpu=. Default to G3 if not specified. */ 18027 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) 18028 if (rs6000_select[i].set_arch_p && rs6000_select[i].string 18029 && rs6000_select[i].string[0] != '\0') 18030 cpu_id = rs6000_select[i].string; 18031 18032 /* Look through the mapping array. Pick the first name that either 18033 matches the argument, has a bit set in IF_SET that is also set 18034 in the target flags, or has a NULL name. */ 18035 18036 i = 0; 18037 while (mapping[i].arg != NULL 18038 && strcmp (mapping[i].arg, cpu_id) != 0 18039 && (mapping[i].if_set & target_flags) == 0) 18040 i++; 18041 18042 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name); 18043} 18044 18045#endif /* TARGET_MACHO */ 18046 18047#if TARGET_ELF 18048static unsigned int 18049rs6000_elf_section_type_flags (tree decl, const char *name, int reloc) 18050{ 18051 return default_section_type_flags_1 (decl, name, reloc, 18052 flag_pic || DEFAULT_ABI == ABI_AIX); 18053} 18054 18055/* Record an element in the table of global constructors. SYMBOL is 18056 a SYMBOL_REF of the function to be called; PRIORITY is a number 18057 between 0 and MAX_INIT_PRIORITY. 18058 18059 This differs from default_named_section_asm_out_constructor in 18060 that we have special handling for -mrelocatable. */ 18061 18062static void 18063rs6000_elf_asm_out_constructor (rtx symbol, int priority) 18064{ 18065 const char *section = ".ctors"; 18066 char buf[16]; 18067 18068 if (priority != DEFAULT_INIT_PRIORITY) 18069 { 18070 sprintf (buf, ".ctors.%.5u", 18071 /* Invert the numbering so the linker puts us in the proper 18072 order; constructors are run from right to left, and the 18073 linker sorts in increasing order. */ 18074 MAX_INIT_PRIORITY - priority); 18075 section = buf; 18076 } 18077 18078 named_section_flags (section, SECTION_WRITE); 18079 assemble_align (POINTER_SIZE); 18080 18081 if (TARGET_RELOCATABLE) 18082 { 18083 fputs ("\t.long (", asm_out_file); 18084 output_addr_const (asm_out_file, symbol); 18085 fputs (")@fixup\n", asm_out_file); 18086 } 18087 else 18088 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); 18089} 18090 18091static void 18092rs6000_elf_asm_out_destructor (rtx symbol, int priority) 18093{ 18094 const char *section = ".dtors"; 18095 char buf[16]; 18096 18097 if (priority != DEFAULT_INIT_PRIORITY) 18098 { 18099 sprintf (buf, ".dtors.%.5u", 18100 /* Invert the numbering so the linker puts us in the proper 18101 order; constructors are run from right to left, and the 18102 linker sorts in increasing order. */ 18103 MAX_INIT_PRIORITY - priority); 18104 section = buf; 18105 } 18106 18107 named_section_flags (section, SECTION_WRITE); 18108 assemble_align (POINTER_SIZE); 18109 18110 if (TARGET_RELOCATABLE) 18111 { 18112 fputs ("\t.long (", asm_out_file); 18113 output_addr_const (asm_out_file, symbol); 18114 fputs (")@fixup\n", asm_out_file); 18115 } 18116 else 18117 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); 18118} 18119 18120void 18121rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl) 18122{ 18123 if (TARGET_64BIT) 18124 { 18125 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file); 18126 ASM_OUTPUT_LABEL (file, name); 18127 fputs (DOUBLE_INT_ASM_OP, file); 18128 rs6000_output_function_entry (file, name); 18129 fputs (",.TOC.@tocbase,0\n\t.previous\n", file); 18130 if (DOT_SYMBOLS) 18131 { 18132 fputs ("\t.size\t", file); 18133 assemble_name (file, name); 18134 fputs (",24\n\t.type\t.", file); 18135 assemble_name (file, name); 18136 fputs (",@function\n", file); 18137 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl)) 18138 { 18139 fputs ("\t.globl\t.", file); 18140 assemble_name (file, name); 18141 putc ('\n', file); 18142 } 18143 } 18144 else 18145 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); 18146 ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); 18147 rs6000_output_function_entry (file, name); 18148 fputs (":\n", file); 18149 return; 18150 } 18151 18152 if (TARGET_RELOCATABLE 18153 && !TARGET_SECURE_PLT 18154 && (get_pool_size () != 0 || current_function_profile) 18155 && uses_TOC ()) 18156 { 18157 char buf[256]; 18158 18159 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno); 18160 18161 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); 18162 fprintf (file, "\t.long "); 18163 assemble_name (file, buf); 18164 putc ('-', file); 18165 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); 18166 assemble_name (file, buf); 18167 putc ('\n', file); 18168 } 18169 18170 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); 18171 ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); 18172 18173 if (DEFAULT_ABI == ABI_AIX) 18174 { 18175 const char *desc_name, *orig_name; 18176 18177 orig_name = (*targetm.strip_name_encoding) (name); 18178 desc_name = orig_name; 18179 while (*desc_name == '.') 18180 desc_name++; 18181 18182 if (TREE_PUBLIC (decl)) 18183 fprintf (file, "\t.globl %s\n", desc_name); 18184 18185 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); 18186 fprintf (file, "%s:\n", desc_name); 18187 fprintf (file, "\t.long %s\n", orig_name); 18188 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file); 18189 if (DEFAULT_ABI == ABI_AIX) 18190 fputs ("\t.long 0\n", file); 18191 fprintf (file, "\t.previous\n"); 18192 } 18193 ASM_OUTPUT_LABEL (file, name); 18194} 18195 18196static void 18197rs6000_elf_end_indicate_exec_stack (void) 18198{ 18199 if (TARGET_32BIT) 18200 file_end_indicate_exec_stack (); 18201} 18202#endif 18203 18204#if TARGET_XCOFF 18205static void 18206rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name) 18207{ 18208 fputs (GLOBAL_ASM_OP, stream); 18209 RS6000_OUTPUT_BASENAME (stream, name); 18210 putc ('\n', stream); 18211} 18212 18213static void 18214rs6000_xcoff_asm_named_section (const char *name, unsigned int flags, 18215 tree decl ATTRIBUTE_UNUSED) 18216{ 18217 int smclass; 18218 static const char * const suffix[3] = { "PR", "RO", "RW" }; 18219 18220 if (flags & SECTION_CODE) 18221 smclass = 0; 18222 else if (flags & SECTION_WRITE) 18223 smclass = 2; 18224 else 18225 smclass = 1; 18226 18227 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n", 18228 (flags & SECTION_CODE) ? "." : "", 18229 name, suffix[smclass], flags & SECTION_ENTSIZE); 18230} 18231 18232static void 18233rs6000_xcoff_select_section (tree decl, int reloc, 18234 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) 18235{ 18236 if (decl_readonly_section_1 (decl, reloc, 1)) 18237 { 18238 if (TREE_PUBLIC (decl)) 18239 read_only_data_section (); 18240 else 18241 read_only_private_data_section (); 18242 } 18243 else 18244 { 18245 if (TREE_PUBLIC (decl)) 18246 data_section (); 18247 else 18248 private_data_section (); 18249 } 18250} 18251 18252static void 18253rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED) 18254{ 18255 const char *name; 18256 18257 /* Use select_section for private and uninitialized data. */ 18258 if (!TREE_PUBLIC (decl) 18259 || DECL_COMMON (decl) 18260 || DECL_INITIAL (decl) == NULL_TREE 18261 || DECL_INITIAL (decl) == error_mark_node 18262 || (flag_zero_initialized_in_bss 18263 && initializer_zerop (DECL_INITIAL (decl)))) 18264 return; 18265 18266 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); 18267 name = (*targetm.strip_name_encoding) (name); 18268 DECL_SECTION_NAME (decl) = build_string (strlen (name), name); 18269} 18270 18271/* Select section for constant in constant pool. 18272 18273 On RS/6000, all constants are in the private read-only data area. 18274 However, if this is being placed in the TOC it must be output as a 18275 toc entry. */ 18276 18277static void 18278rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x, 18279 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) 18280{ 18281 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) 18282 toc_section (); 18283 else 18284 read_only_private_data_section (); 18285} 18286 18287/* Remove any trailing [DS] or the like from the symbol name. */ 18288 18289static const char * 18290rs6000_xcoff_strip_name_encoding (const char *name) 18291{ 18292 size_t len; 18293 if (*name == '*') 18294 name++; 18295 len = strlen (name); 18296 if (name[len - 1] == ']') 18297 return ggc_alloc_string (name, len - 4); 18298 else 18299 return name; 18300} 18301 18302/* Section attributes. AIX is always PIC. */ 18303 18304static unsigned int 18305rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc) 18306{ 18307 unsigned int align; 18308 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1); 18309 18310 /* Align to at least UNIT size. */ 18311 if (flags & SECTION_CODE) 18312 align = MIN_UNITS_PER_WORD; 18313 else 18314 /* Increase alignment of large objects if not already stricter. */ 18315 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT), 18316 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD 18317 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD); 18318 18319 return flags | (exact_log2 (align) & SECTION_ENTSIZE); 18320} 18321 18322/* Output at beginning of assembler file. 18323 18324 Initialize the section names for the RS/6000 at this point. 18325 18326 Specify filename, including full path, to assembler. 18327 18328 We want to go into the TOC section so at least one .toc will be emitted. 18329 Also, in order to output proper .bs/.es pairs, we need at least one static 18330 [RW] section emitted. 18331 18332 Finally, declare mcount when profiling to make the assembler happy. */ 18333 18334static void 18335rs6000_xcoff_file_start (void) 18336{ 18337 rs6000_gen_section_name (&xcoff_bss_section_name, 18338 main_input_filename, ".bss_"); 18339 rs6000_gen_section_name (&xcoff_private_data_section_name, 18340 main_input_filename, ".rw_"); 18341 rs6000_gen_section_name (&xcoff_read_only_section_name, 18342 main_input_filename, ".ro_"); 18343 18344 fputs ("\t.file\t", asm_out_file); 18345 output_quoted_string (asm_out_file, main_input_filename); 18346 fputc ('\n', asm_out_file); 18347 if (write_symbols != NO_DEBUG) 18348 private_data_section (); 18349 text_section (); 18350 if (profile_flag) 18351 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT); 18352 rs6000_file_start (); 18353} 18354 18355/* Output at end of assembler file. 18356 On the RS/6000, referencing data should automatically pull in text. */ 18357 18358static void 18359rs6000_xcoff_file_end (void) 18360{ 18361 text_section (); 18362 fputs ("_section_.text:\n", asm_out_file); 18363 data_section (); 18364 fputs (TARGET_32BIT 18365 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n", 18366 asm_out_file); 18367} 18368#endif /* TARGET_XCOFF */ 18369 18370/* Compute a (partial) cost for rtx X. Return true if the complete 18371 cost has been computed, and false if subexpressions should be 18372 scanned. In either case, *TOTAL contains the cost result. */ 18373 18374static bool 18375rs6000_rtx_costs (rtx x, int code, int outer_code, int *total) 18376{ 18377 enum machine_mode mode = GET_MODE (x); 18378 18379 switch (code) 18380 { 18381 /* On the RS/6000, if it is valid in the insn, it is free. */ 18382 case CONST_INT: 18383 if (((outer_code == SET 18384 || outer_code == PLUS 18385 || outer_code == MINUS) 18386 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') 18387 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L'))) 18388 || (outer_code == AND 18389 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') 18390 || (CONST_OK_FOR_LETTER_P (INTVAL (x), 18391 mode == SImode ? 'L' : 'J')) 18392 || mask_operand (x, mode) 18393 || (mode == DImode 18394 && mask64_operand (x, DImode)))) 18395 || ((outer_code == IOR || outer_code == XOR) 18396 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') 18397 || (CONST_OK_FOR_LETTER_P (INTVAL (x), 18398 mode == SImode ? 'L' : 'J')))) 18399 || outer_code == ASHIFT 18400 || outer_code == ASHIFTRT 18401 || outer_code == LSHIFTRT 18402 || outer_code == ROTATE 18403 || outer_code == ROTATERT 18404 || outer_code == ZERO_EXTRACT 18405 || (outer_code == MULT 18406 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')) 18407 || ((outer_code == DIV || outer_code == UDIV 18408 || outer_code == MOD || outer_code == UMOD) 18409 && exact_log2 (INTVAL (x)) >= 0) 18410 || (outer_code == COMPARE 18411 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') 18412 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K'))) 18413 || (outer_code == EQ 18414 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') 18415 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') 18416 || (CONST_OK_FOR_LETTER_P (INTVAL (x), 18417 mode == SImode ? 'L' : 'J')))) 18418 || (outer_code == GTU 18419 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')) 18420 || (outer_code == LTU 18421 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P'))) 18422 { 18423 *total = 0; 18424 return true; 18425 } 18426 else if ((outer_code == PLUS 18427 && reg_or_add_cint_operand (x, VOIDmode)) 18428 || (outer_code == MINUS 18429 && reg_or_sub_cint_operand (x, VOIDmode)) 18430 || ((outer_code == SET 18431 || outer_code == IOR 18432 || outer_code == XOR) 18433 && (INTVAL (x) 18434 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0)) 18435 { 18436 *total = COSTS_N_INSNS (1); 18437 return true; 18438 } 18439 /* FALLTHRU */ 18440 18441 case CONST_DOUBLE: 18442 if (mode == DImode 18443 && ((outer_code == AND 18444 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') 18445 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L') 18446 || mask_operand (x, DImode) 18447 || mask64_operand (x, DImode))) 18448 || ((outer_code == IOR || outer_code == XOR) 18449 && CONST_DOUBLE_HIGH (x) == 0 18450 && (CONST_DOUBLE_LOW (x) 18451 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0))) 18452 { 18453 *total = 0; 18454 return true; 18455 } 18456 else if (mode == DImode 18457 && (outer_code == SET 18458 || outer_code == IOR 18459 || outer_code == XOR) 18460 && CONST_DOUBLE_HIGH (x) == 0) 18461 { 18462 *total = COSTS_N_INSNS (1); 18463 return true; 18464 } 18465 /* FALLTHRU */ 18466 18467 case CONST: 18468 case HIGH: 18469 case SYMBOL_REF: 18470 case MEM: 18471 /* When optimizing for size, MEM should be slightly more expensive 18472 than generating address, e.g., (plus (reg) (const)). 18473 L1 cache latency is about two instructions. */ 18474 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2); 18475 return true; 18476 18477 case LABEL_REF: 18478 *total = 0; 18479 return true; 18480 18481 case PLUS: 18482 if (mode == DFmode) 18483 { 18484 if (GET_CODE (XEXP (x, 0)) == MULT) 18485 { 18486 /* FNMA accounted in outer NEG. */ 18487 if (outer_code == NEG) 18488 *total = rs6000_cost->dmul - rs6000_cost->fp; 18489 else 18490 *total = rs6000_cost->dmul; 18491 } 18492 else 18493 *total = rs6000_cost->fp; 18494 } 18495 else if (mode == SFmode) 18496 { 18497 /* FNMA accounted in outer NEG. */ 18498 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT) 18499 *total = 0; 18500 else 18501 *total = rs6000_cost->fp; 18502 } 18503 else 18504 *total = COSTS_N_INSNS (1); 18505 return false; 18506 18507 case MINUS: 18508 if (mode == DFmode) 18509 { 18510 if (GET_CODE (XEXP (x, 0)) == MULT) 18511 { 18512 /* FNMA accounted in outer NEG. */ 18513 if (outer_code == NEG) 18514 *total = 0; 18515 else 18516 *total = rs6000_cost->dmul; 18517 } 18518 else 18519 *total = rs6000_cost->fp; 18520 } 18521 else if (mode == SFmode) 18522 { 18523 /* FNMA accounted in outer NEG. */ 18524 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT) 18525 *total = 0; 18526 else 18527 *total = rs6000_cost->fp; 18528 } 18529 else 18530 *total = COSTS_N_INSNS (1); 18531 return false; 18532 18533 case MULT: 18534 if (GET_CODE (XEXP (x, 1)) == CONST_INT 18535 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I')) 18536 { 18537 if (INTVAL (XEXP (x, 1)) >= -256 18538 && INTVAL (XEXP (x, 1)) <= 255) 18539 *total = rs6000_cost->mulsi_const9; 18540 else 18541 *total = rs6000_cost->mulsi_const; 18542 } 18543 /* FMA accounted in outer PLUS/MINUS. */ 18544 else if ((mode == DFmode || mode == SFmode) 18545 && (outer_code == PLUS || outer_code == MINUS)) 18546 *total = 0; 18547 else if (mode == DFmode) 18548 *total = rs6000_cost->dmul; 18549 else if (mode == SFmode) 18550 *total = rs6000_cost->fp; 18551 else if (mode == DImode) 18552 *total = rs6000_cost->muldi; 18553 else 18554 *total = rs6000_cost->mulsi; 18555 return false; 18556 18557 case DIV: 18558 case MOD: 18559 if (FLOAT_MODE_P (mode)) 18560 { 18561 *total = mode == DFmode ? rs6000_cost->ddiv 18562 : rs6000_cost->sdiv; 18563 return false; 18564 } 18565 /* FALLTHRU */ 18566 18567 case UDIV: 18568 case UMOD: 18569 if (GET_CODE (XEXP (x, 1)) == CONST_INT 18570 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) 18571 { 18572 if (code == DIV || code == MOD) 18573 /* Shift, addze */ 18574 *total = COSTS_N_INSNS (2); 18575 else 18576 /* Shift */ 18577 *total = COSTS_N_INSNS (1); 18578 } 18579 else 18580 { 18581 if (GET_MODE (XEXP (x, 1)) == DImode) 18582 *total = rs6000_cost->divdi; 18583 else 18584 *total = rs6000_cost->divsi; 18585 } 18586 /* Add in shift and subtract for MOD. */ 18587 if (code == MOD || code == UMOD) 18588 *total += COSTS_N_INSNS (2); 18589 return false; 18590 18591 case FFS: 18592 *total = COSTS_N_INSNS (4); 18593 return false; 18594 18595 case NOT: 18596 if (outer_code == AND || outer_code == IOR || outer_code == XOR) 18597 { 18598 *total = 0; 18599 return false; 18600 } 18601 /* FALLTHRU */ 18602 18603 case AND: 18604 case IOR: 18605 case XOR: 18606 case ZERO_EXTRACT: 18607 *total = COSTS_N_INSNS (1); 18608 return false; 18609 18610 case ASHIFT: 18611 case ASHIFTRT: 18612 case LSHIFTRT: 18613 case ROTATE: 18614 case ROTATERT: 18615 /* Handle mul_highpart. */ 18616 if (outer_code == TRUNCATE 18617 && GET_CODE (XEXP (x, 0)) == MULT) 18618 { 18619 if (mode == DImode) 18620 *total = rs6000_cost->muldi; 18621 else 18622 *total = rs6000_cost->mulsi; 18623 return true; 18624 } 18625 else if (outer_code == AND) 18626 *total = 0; 18627 else 18628 *total = COSTS_N_INSNS (1); 18629 return false; 18630 18631 case SIGN_EXTEND: 18632 case ZERO_EXTEND: 18633 if (GET_CODE (XEXP (x, 0)) == MEM) 18634 *total = 0; 18635 else 18636 *total = COSTS_N_INSNS (1); 18637 return false; 18638 18639 case COMPARE: 18640 case NEG: 18641 case ABS: 18642 if (!FLOAT_MODE_P (mode)) 18643 { 18644 *total = COSTS_N_INSNS (1); 18645 return false; 18646 } 18647 /* FALLTHRU */ 18648 18649 case FLOAT: 18650 case UNSIGNED_FLOAT: 18651 case FIX: 18652 case UNSIGNED_FIX: 18653 case FLOAT_TRUNCATE: 18654 *total = rs6000_cost->fp; 18655 return false; 18656 18657 case FLOAT_EXTEND: 18658 if (mode == DFmode) 18659 *total = 0; 18660 else 18661 *total = rs6000_cost->fp; 18662 return false; 18663 18664 case UNSPEC: 18665 switch (XINT (x, 1)) 18666 { 18667 case UNSPEC_FRSP: 18668 *total = rs6000_cost->fp; 18669 return true; 18670 18671 default: 18672 break; 18673 } 18674 break; 18675 18676 case CALL: 18677 case IF_THEN_ELSE: 18678 if (optimize_size) 18679 { 18680 *total = COSTS_N_INSNS (1); 18681 return true; 18682 } 18683 else if (FLOAT_MODE_P (mode) 18684 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS) 18685 { 18686 *total = rs6000_cost->fp; 18687 return false; 18688 } 18689 break; 18690 18691 case EQ: 18692 case GTU: 18693 case LTU: 18694 /* Carry bit requires mode == Pmode. 18695 NEG or PLUS already counted so only add one. */ 18696 if (mode == Pmode 18697 && (outer_code == NEG || outer_code == PLUS)) 18698 { 18699 *total = COSTS_N_INSNS (1); 18700 return true; 18701 } 18702 if (outer_code == SET) 18703 { 18704 if (XEXP (x, 1) == const0_rtx) 18705 { 18706 *total = COSTS_N_INSNS (2); 18707 return true; 18708 } 18709 else if (mode == Pmode) 18710 { 18711 *total = COSTS_N_INSNS (3); 18712 return false; 18713 } 18714 } 18715 /* FALLTHRU */ 18716 18717 case GT: 18718 case LT: 18719 case UNORDERED: 18720 if (outer_code == SET && (XEXP (x, 1) == const0_rtx)) 18721 { 18722 *total = COSTS_N_INSNS (2); 18723 return true; 18724 } 18725 /* CC COMPARE. */ 18726 if (outer_code == COMPARE) 18727 { 18728 *total = 0; 18729 return true; 18730 } 18731 break; 18732 18733 default: 18734 break; 18735 } 18736 18737 return false; 18738} 18739 18740/* A C expression returning the cost of moving data from a register of class 18741 CLASS1 to one of CLASS2. */ 18742 18743int 18744rs6000_register_move_cost (enum machine_mode mode, 18745 enum reg_class from, enum reg_class to) 18746{ 18747 /* Moves from/to GENERAL_REGS. */ 18748 if (reg_classes_intersect_p (to, GENERAL_REGS) 18749 || reg_classes_intersect_p (from, GENERAL_REGS)) 18750 { 18751 if (! reg_classes_intersect_p (to, GENERAL_REGS)) 18752 from = to; 18753 18754 if (from == FLOAT_REGS || from == ALTIVEC_REGS) 18755 return (rs6000_memory_move_cost (mode, from, 0) 18756 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0)); 18757 18758 /* It's more expensive to move CR_REGS than CR0_REGS because of the 18759 shift. */ 18760 else if (from == CR_REGS) 18761 return 4; 18762 18763 else 18764 /* A move will cost one instruction per GPR moved. */ 18765 return 2 * hard_regno_nregs[0][mode]; 18766 } 18767 18768 /* Moving between two similar registers is just one instruction. */ 18769 else if (reg_classes_intersect_p (to, from)) 18770 return mode == TFmode ? 4 : 2; 18771 18772 /* Everything else has to go through GENERAL_REGS. */ 18773 else 18774 return (rs6000_register_move_cost (mode, GENERAL_REGS, to) 18775 + rs6000_register_move_cost (mode, from, GENERAL_REGS)); 18776} 18777 18778/* A C expressions returning the cost of moving data of MODE from a register to 18779 or from memory. */ 18780 18781int 18782rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class, 18783 int in ATTRIBUTE_UNUSED) 18784{ 18785 if (reg_classes_intersect_p (class, GENERAL_REGS)) 18786 return 4 * hard_regno_nregs[0][mode]; 18787 else if (reg_classes_intersect_p (class, FLOAT_REGS)) 18788 return 4 * hard_regno_nregs[32][mode]; 18789 else if (reg_classes_intersect_p (class, ALTIVEC_REGS)) 18790 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode]; 18791 else 18792 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS); 18793} 18794 18795/* Newton-Raphson approximation of single-precision floating point divide n/d. 18796 Assumes no trapping math and finite arguments. */ 18797 18798void 18799rs6000_emit_swdivsf (rtx res, rtx n, rtx d) 18800{ 18801 rtx x0, e0, e1, y1, u0, v0, one; 18802 18803 x0 = gen_reg_rtx (SFmode); 18804 e0 = gen_reg_rtx (SFmode); 18805 e1 = gen_reg_rtx (SFmode); 18806 y1 = gen_reg_rtx (SFmode); 18807 u0 = gen_reg_rtx (SFmode); 18808 v0 = gen_reg_rtx (SFmode); 18809 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode)); 18810 18811 /* x0 = 1./d estimate */ 18812 emit_insn (gen_rtx_SET (VOIDmode, x0, 18813 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d), 18814 UNSPEC_FRES))); 18815 /* e0 = 1. - d * x0 */ 18816 emit_insn (gen_rtx_SET (VOIDmode, e0, 18817 gen_rtx_MINUS (SFmode, one, 18818 gen_rtx_MULT (SFmode, d, x0)))); 18819 /* e1 = e0 + e0 * e0 */ 18820 emit_insn (gen_rtx_SET (VOIDmode, e1, 18821 gen_rtx_PLUS (SFmode, 18822 gen_rtx_MULT (SFmode, e0, e0), e0))); 18823 /* y1 = x0 + e1 * x0 */ 18824 emit_insn (gen_rtx_SET (VOIDmode, y1, 18825 gen_rtx_PLUS (SFmode, 18826 gen_rtx_MULT (SFmode, e1, x0), x0))); 18827 /* u0 = n * y1 */ 18828 emit_insn (gen_rtx_SET (VOIDmode, u0, 18829 gen_rtx_MULT (SFmode, n, y1))); 18830 /* v0 = n - d * u0 */ 18831 emit_insn (gen_rtx_SET (VOIDmode, v0, 18832 gen_rtx_MINUS (SFmode, n, 18833 gen_rtx_MULT (SFmode, d, u0)))); 18834 /* res = u0 + v0 * y1 */ 18835 emit_insn (gen_rtx_SET (VOIDmode, res, 18836 gen_rtx_PLUS (SFmode, 18837 gen_rtx_MULT (SFmode, v0, y1), u0))); 18838} 18839 18840/* Newton-Raphson approximation of double-precision floating point divide n/d. 18841 Assumes no trapping math and finite arguments. */ 18842 18843void 18844rs6000_emit_swdivdf (rtx res, rtx n, rtx d) 18845{ 18846 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one; 18847 18848 x0 = gen_reg_rtx (DFmode); 18849 e0 = gen_reg_rtx (DFmode); 18850 e1 = gen_reg_rtx (DFmode); 18851 e2 = gen_reg_rtx (DFmode); 18852 y1 = gen_reg_rtx (DFmode); 18853 y2 = gen_reg_rtx (DFmode); 18854 y3 = gen_reg_rtx (DFmode); 18855 u0 = gen_reg_rtx (DFmode); 18856 v0 = gen_reg_rtx (DFmode); 18857 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode)); 18858 18859 /* x0 = 1./d estimate */ 18860 emit_insn (gen_rtx_SET (VOIDmode, x0, 18861 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d), 18862 UNSPEC_FRES))); 18863 /* e0 = 1. - d * x0 */ 18864 emit_insn (gen_rtx_SET (VOIDmode, e0, 18865 gen_rtx_MINUS (DFmode, one, 18866 gen_rtx_MULT (SFmode, d, x0)))); 18867 /* y1 = x0 + e0 * x0 */ 18868 emit_insn (gen_rtx_SET (VOIDmode, y1, 18869 gen_rtx_PLUS (DFmode, 18870 gen_rtx_MULT (DFmode, e0, x0), x0))); 18871 /* e1 = e0 * e0 */ 18872 emit_insn (gen_rtx_SET (VOIDmode, e1, 18873 gen_rtx_MULT (DFmode, e0, e0))); 18874 /* y2 = y1 + e1 * y1 */ 18875 emit_insn (gen_rtx_SET (VOIDmode, y2, 18876 gen_rtx_PLUS (DFmode, 18877 gen_rtx_MULT (DFmode, e1, y1), y1))); 18878 /* e2 = e1 * e1 */ 18879 emit_insn (gen_rtx_SET (VOIDmode, e2, 18880 gen_rtx_MULT (DFmode, e1, e1))); 18881 /* y3 = y2 + e2 * y2 */ 18882 emit_insn (gen_rtx_SET (VOIDmode, y3, 18883 gen_rtx_PLUS (DFmode, 18884 gen_rtx_MULT (DFmode, e2, y2), y2))); 18885 /* u0 = n * y3 */ 18886 emit_insn (gen_rtx_SET (VOIDmode, u0, 18887 gen_rtx_MULT (DFmode, n, y3))); 18888 /* v0 = n - d * u0 */ 18889 emit_insn (gen_rtx_SET (VOIDmode, v0, 18890 gen_rtx_MINUS (DFmode, n, 18891 gen_rtx_MULT (DFmode, d, u0)))); 18892 /* res = u0 + v0 * y3 */ 18893 emit_insn (gen_rtx_SET (VOIDmode, res, 18894 gen_rtx_PLUS (DFmode, 18895 gen_rtx_MULT (DFmode, v0, y3), u0))); 18896} 18897 18898/* Return an RTX representing where to find the function value of a 18899 function returning MODE. */ 18900static rtx 18901rs6000_complex_function_value (enum machine_mode mode) 18902{ 18903 unsigned int regno; 18904 rtx r1, r2; 18905 enum machine_mode inner = GET_MODE_INNER (mode); 18906 unsigned int inner_bytes = GET_MODE_SIZE (inner); 18907 18908 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS) 18909 regno = FP_ARG_RETURN; 18910 else 18911 { 18912 regno = GP_ARG_RETURN; 18913 18914 /* 32-bit is OK since it'll go in r3/r4. */ 18915 if (TARGET_32BIT && inner_bytes >= 4) 18916 return gen_rtx_REG (mode, regno); 18917 } 18918 18919 if (inner_bytes >= 8) 18920 return gen_rtx_REG (mode, regno); 18921 18922 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno), 18923 const0_rtx); 18924 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1), 18925 GEN_INT (inner_bytes)); 18926 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); 18927} 18928 18929/* Define how to find the value returned by a function. 18930 VALTYPE is the data type of the value (as a tree). 18931 If the precise function being called is known, FUNC is its FUNCTION_DECL; 18932 otherwise, FUNC is 0. 18933 18934 On the SPE, both FPs and vectors are returned in r3. 18935 18936 On RS/6000 an integer value is in r3 and a floating-point value is in 18937 fp1, unless -msoft-float. */ 18938 18939rtx 18940rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED) 18941{ 18942 enum machine_mode mode; 18943 unsigned int regno; 18944 18945 /* Special handling for structs in darwin64. */ 18946 if (rs6000_darwin64_abi 18947 && TYPE_MODE (valtype) == BLKmode 18948 && TREE_CODE (valtype) == RECORD_TYPE 18949 && int_size_in_bytes (valtype) > 0) 18950 { 18951 CUMULATIVE_ARGS valcum; 18952 rtx valret; 18953 18954 valcum.words = 0; 18955 valcum.fregno = FP_ARG_MIN_REG; 18956 valcum.vregno = ALTIVEC_ARG_MIN_REG; 18957 /* Do a trial code generation as if this were going to be passed as 18958 an argument; if any part goes in memory, we return NULL. */ 18959 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true); 18960 if (valret) 18961 return valret; 18962 /* Otherwise fall through to standard ABI rules. */ 18963 } 18964 18965 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode) 18966 { 18967 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ 18968 return gen_rtx_PARALLEL (DImode, 18969 gen_rtvec (2, 18970 gen_rtx_EXPR_LIST (VOIDmode, 18971 gen_rtx_REG (SImode, GP_ARG_RETURN), 18972 const0_rtx), 18973 gen_rtx_EXPR_LIST (VOIDmode, 18974 gen_rtx_REG (SImode, 18975 GP_ARG_RETURN + 1), 18976 GEN_INT (4)))); 18977 } 18978 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode) 18979 { 18980 return gen_rtx_PARALLEL (DCmode, 18981 gen_rtvec (4, 18982 gen_rtx_EXPR_LIST (VOIDmode, 18983 gen_rtx_REG (SImode, GP_ARG_RETURN), 18984 const0_rtx), 18985 gen_rtx_EXPR_LIST (VOIDmode, 18986 gen_rtx_REG (SImode, 18987 GP_ARG_RETURN + 1), 18988 GEN_INT (4)), 18989 gen_rtx_EXPR_LIST (VOIDmode, 18990 gen_rtx_REG (SImode, 18991 GP_ARG_RETURN + 2), 18992 GEN_INT (8)), 18993 gen_rtx_EXPR_LIST (VOIDmode, 18994 gen_rtx_REG (SImode, 18995 GP_ARG_RETURN + 3), 18996 GEN_INT (12)))); 18997 } 18998 if ((INTEGRAL_TYPE_P (valtype) 18999 && TYPE_PRECISION (valtype) < BITS_PER_WORD) 19000 || POINTER_TYPE_P (valtype)) 19001 mode = TARGET_32BIT ? SImode : DImode; 19002 else 19003 mode = TYPE_MODE (valtype); 19004 19005 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS) 19006 regno = FP_ARG_RETURN; 19007 else if (TREE_CODE (valtype) == COMPLEX_TYPE 19008 && targetm.calls.split_complex_arg) 19009 return rs6000_complex_function_value (mode); 19010 else if (TREE_CODE (valtype) == VECTOR_TYPE 19011 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI 19012 && ALTIVEC_VECTOR_MODE (mode)) 19013 regno = ALTIVEC_ARG_RETURN; 19014 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT 19015 && (mode == DFmode || mode == DCmode)) 19016 return spe_build_register_parallel (mode, GP_ARG_RETURN); 19017 else 19018 regno = GP_ARG_RETURN; 19019 19020 return gen_rtx_REG (mode, regno); 19021} 19022 19023/* Define how to find the value returned by a library function 19024 assuming the value has mode MODE. */ 19025rtx 19026rs6000_libcall_value (enum machine_mode mode) 19027{ 19028 unsigned int regno; 19029 19030 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode) 19031 { 19032 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ 19033 return gen_rtx_PARALLEL (DImode, 19034 gen_rtvec (2, 19035 gen_rtx_EXPR_LIST (VOIDmode, 19036 gen_rtx_REG (SImode, GP_ARG_RETURN), 19037 const0_rtx), 19038 gen_rtx_EXPR_LIST (VOIDmode, 19039 gen_rtx_REG (SImode, 19040 GP_ARG_RETURN + 1), 19041 GEN_INT (4)))); 19042 } 19043 19044 if (GET_MODE_CLASS (mode) == MODE_FLOAT 19045 && TARGET_HARD_FLOAT && TARGET_FPRS) 19046 regno = FP_ARG_RETURN; 19047 else if (ALTIVEC_VECTOR_MODE (mode) 19048 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) 19049 regno = ALTIVEC_ARG_RETURN; 19050 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg) 19051 return rs6000_complex_function_value (mode); 19052 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT 19053 && (mode == DFmode || mode == DCmode)) 19054 return spe_build_register_parallel (mode, GP_ARG_RETURN); 19055 else 19056 regno = GP_ARG_RETURN; 19057 19058 return gen_rtx_REG (mode, regno); 19059} 19060 19061/* Define the offset between two registers, FROM to be eliminated and its 19062 replacement TO, at the start of a routine. */ 19063HOST_WIDE_INT 19064rs6000_initial_elimination_offset (int from, int to) 19065{ 19066 rs6000_stack_t *info = rs6000_stack_info (); 19067 HOST_WIDE_INT offset; 19068 19069 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) 19070 offset = info->push_p ? 0 : -info->total_size; 19071 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) 19072 { 19073 offset = info->push_p ? 0 : -info->total_size; 19074 if (FRAME_GROWS_DOWNWARD) 19075 offset += info->fixed_size + info->vars_size + info->parm_size; 19076 } 19077 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) 19078 offset = FRAME_GROWS_DOWNWARD 19079 ? info->fixed_size + info->vars_size + info->parm_size 19080 : 0; 19081 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) 19082 offset = info->total_size; 19083 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) 19084 offset = info->push_p ? info->total_size : 0; 19085 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM) 19086 offset = 0; 19087 else 19088 gcc_unreachable (); 19089 19090 return offset; 19091} 19092 19093/* Return true if TYPE is a SPE or AltiVec opaque type. */ 19094 19095static bool 19096rs6000_is_opaque_type (tree type) 19097{ 19098 return (type == opaque_V2SI_type_node 19099 || type == opaque_V2SF_type_node 19100 || type == opaque_p_V2SI_type_node 19101 || type == opaque_V4SI_type_node); 19102} 19103 19104static rtx 19105rs6000_dwarf_register_span (rtx reg) 19106{ 19107 unsigned regno; 19108 19109 if (TARGET_SPE 19110 && (SPE_VECTOR_MODE (GET_MODE (reg)) 19111 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode))) 19112 ; 19113 else 19114 return NULL_RTX; 19115 19116 regno = REGNO (reg); 19117 19118 /* The duality of the SPE register size wreaks all kinds of havoc. 19119 This is a way of distinguishing r0 in 32-bits from r0 in 19120 64-bits. */ 19121 return 19122 gen_rtx_PARALLEL (VOIDmode, 19123 BYTES_BIG_ENDIAN 19124 ? gen_rtvec (2, 19125 gen_rtx_REG (SImode, regno + 1200), 19126 gen_rtx_REG (SImode, regno)) 19127 : gen_rtvec (2, 19128 gen_rtx_REG (SImode, regno), 19129 gen_rtx_REG (SImode, regno + 1200))); 19130} 19131 19132/* Map internal gcc register numbers to DWARF2 register numbers. */ 19133 19134unsigned int 19135rs6000_dbx_register_number (unsigned int regno) 19136{ 19137 if (regno <= 63 || write_symbols != DWARF2_DEBUG) 19138 return regno; 19139 if (regno == MQ_REGNO) 19140 return 100; 19141 if (regno == LINK_REGISTER_REGNUM) 19142 return 108; 19143 if (regno == COUNT_REGISTER_REGNUM) 19144 return 109; 19145 if (CR_REGNO_P (regno)) 19146 return regno - CR0_REGNO + 86; 19147 if (regno == XER_REGNO) 19148 return 101; 19149 if (ALTIVEC_REGNO_P (regno)) 19150 return regno - FIRST_ALTIVEC_REGNO + 1124; 19151 if (regno == VRSAVE_REGNO) 19152 return 356; 19153 if (regno == VSCR_REGNO) 19154 return 67; 19155 if (regno == SPE_ACC_REGNO) 19156 return 99; 19157 if (regno == SPEFSCR_REGNO) 19158 return 612; 19159 /* SPE high reg number. We get these values of regno from 19160 rs6000_dwarf_register_span. */ 19161 gcc_assert (regno >= 1200 && regno < 1232); 19162 return regno; 19163} 19164 19165/* target hook eh_return_filter_mode */ 19166static enum machine_mode 19167rs6000_eh_return_filter_mode (void) 19168{ 19169 return TARGET_32BIT ? SImode : word_mode; 19170} 19171 19172/* Target hook for vector_mode_supported_p. */ 19173static bool 19174rs6000_vector_mode_supported_p (enum machine_mode mode) 19175{ 19176 19177 if (TARGET_SPE && SPE_VECTOR_MODE (mode)) 19178 return true; 19179 19180 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode)) 19181 return true; 19182 19183 else 19184 return false; 19185} 19186 19187/* Target hook for invalid_arg_for_unprototyped_fn. */ 19188static const char * 19189invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val) 19190{ 19191 return (!rs6000_darwin64_abi 19192 && typelist == 0 19193 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE 19194 && (funcdecl == NULL_TREE 19195 || (TREE_CODE (funcdecl) == FUNCTION_DECL 19196 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD))) 19197 ? N_("AltiVec argument passed to unprototyped function") 19198 : NULL; 19199} 19200 19201/* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register 19202 setup by using __stack_chk_fail_local hidden function instead of 19203 calling __stack_chk_fail directly. Otherwise it is better to call 19204 __stack_chk_fail directly. */ 19205 19206static tree 19207rs6000_stack_protect_fail (void) 19208{ 19209 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic) 19210 ? default_hidden_stack_protect_fail () 19211 : default_external_stack_protect_fail (); 19212} 19213 19214#include "gt-rs6000.h" 19215