1/* Definitions of target machine for GNU compiler. MIPS version. 2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998 3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. 4 Contributed by A. Lichnewsky (lich@inria.inria.fr). 5 Changed by Michael Meissner (meissner@osf.org). 6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and 7 Brendan Eich (brendan@microunity.com). 8 9This file is part of GCC. 10 11GCC is free software; you can redistribute it and/or modify 12it under the terms of the GNU General Public License as published by 13the Free Software Foundation; either version 2, or (at your option) 14any later version. 15 16GCC is distributed in the hope that it will be useful, 17but WITHOUT ANY WARRANTY; without even the implied warranty of 18MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19GNU General Public License for more details. 20 21You should have received a copy of the GNU General Public License 22along with GCC; see the file COPYING. If not, write to 23the Free Software Foundation, 51 Franklin Street, Fifth Floor, 24Boston, MA 02110-1301, USA. */ 25 26 27/* MIPS external variables defined in mips.c. */ 28 29/* Which processor to schedule for. Since there is no difference between 30 a R2000 and R3000 in terms of the scheduler, we collapse them into 31 just an R3000. The elements of the enumeration must match exactly 32 the cpu attribute in the mips.md machine description. */ 33 34enum processor_type { 35 PROCESSOR_R3000, 36 PROCESSOR_4KC, 37 PROCESSOR_4KP, 38 PROCESSOR_5KC, 39 PROCESSOR_5KF, 40 PROCESSOR_20KC, 41 PROCESSOR_24K, 42 PROCESSOR_24KX, 43 PROCESSOR_M4K, 44 PROCESSOR_R3900, 45 PROCESSOR_R6000, 46 PROCESSOR_R4000, 47 PROCESSOR_R4100, 48 PROCESSOR_R4111, 49 PROCESSOR_R4120, 50 PROCESSOR_R4130, 51 PROCESSOR_R4300, 52 PROCESSOR_R4600, 53 PROCESSOR_R4650, 54 PROCESSOR_R5000, 55 PROCESSOR_R5400, 56 PROCESSOR_R5500, 57 PROCESSOR_R7000, 58 PROCESSOR_R8000, 59 PROCESSOR_R9000, 60 PROCESSOR_SB1, 61 PROCESSOR_SR71000, 62 PROCESSOR_MAX 63}; 64 65/* Costs of various operations on the different architectures. */ 66 67struct mips_rtx_cost_data 68{ 69 unsigned short fp_add; 70 unsigned short fp_mult_sf; 71 unsigned short fp_mult_df; 72 unsigned short fp_div_sf; 73 unsigned short fp_div_df; 74 unsigned short int_mult_si; 75 unsigned short int_mult_di; 76 unsigned short int_div_si; 77 unsigned short int_div_di; 78 unsigned short branch_cost; 79 unsigned short memory_latency; 80}; 81 82/* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32), 83 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended 84 to work on a 64 bit machine. */ 85 86#define ABI_32 0 87#define ABI_N32 1 88#define ABI_64 2 89#define ABI_EABI 3 90#define ABI_O64 4 91 92/* Information about one recognized processor. Defined here for the 93 benefit of TARGET_CPU_CPP_BUILTINS. */ 94struct mips_cpu_info { 95 /* The 'canonical' name of the processor as far as GCC is concerned. 96 It's typically a manufacturer's prefix followed by a numerical 97 designation. It should be lower case. */ 98 const char *name; 99 100 /* The internal processor number that most closely matches this 101 entry. Several processors can have the same value, if there's no 102 difference between them from GCC's point of view. */ 103 enum processor_type cpu; 104 105 /* The ISA level that the processor implements. */ 106 int isa; 107}; 108 109extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */ 110extern const char *current_function_file; /* filename current function is in */ 111extern int num_source_filenames; /* current .file # */ 112extern int mips_section_threshold; /* # bytes of data/sdata cutoff */ 113extern int sym_lineno; /* sgi next label # for each stmt */ 114extern int set_noreorder; /* # of nested .set noreorder's */ 115extern int set_nomacro; /* # of nested .set nomacro's */ 116extern int set_noat; /* # of nested .set noat's */ 117extern int set_volatile; /* # of nested .set volatile's */ 118extern int mips_branch_likely; /* emit 'l' after br (branch likely) */ 119extern int mips_dbx_regno[]; /* Map register # to debug register # */ 120extern GTY(()) rtx cmp_operands[2]; 121extern enum processor_type mips_arch; /* which cpu to codegen for */ 122extern enum processor_type mips_tune; /* which cpu to schedule for */ 123extern int mips_isa; /* architectural level */ 124extern int mips_abi; /* which ABI to use */ 125extern int mips16_hard_float; /* mips16 without -msoft-float */ 126extern const struct mips_cpu_info mips_cpu_info_table[]; 127extern const struct mips_cpu_info *mips_arch_info; 128extern const struct mips_cpu_info *mips_tune_info; 129extern const struct mips_rtx_cost_data *mips_cost; 130 131/* Macros to silence warnings about numbers being signed in traditional 132 C and unsigned in ISO C when compiled on 32-bit hosts. */ 133 134#define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */ 135#define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */ 136#define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */ 137 138 139/* Run-time compilation parameters selecting different hardware subsets. */ 140 141/* True if the call patterns should be split into a jalr followed by 142 an instruction to restore $gp. This is only ever true for SVR4 PIC, 143 in which $gp is call-clobbered. It is only safe to split the load 144 from the call when every use of $gp is explicit. */ 145 146#define TARGET_SPLIT_CALLS \ 147 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI) 148 149/* True if we can optimize sibling calls. For simplicity, we only 150 handle cases in which call_insn_operand will reject invalid 151 sibcall addresses. There are two cases in which this isn't true: 152 153 - TARGET_MIPS16. call_insn_operand accepts constant addresses 154 but there is no direct jump instruction. It isn't worth 155 using sibling calls in this case anyway; they would usually 156 be longer than normal calls. 157 158 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand 159 accepts global constants, but "jr $25" is the only allowed 160 sibcall. */ 161 162#define TARGET_SIBCALLS \ 163 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS)) 164 165/* True if .gpword or .gpdword should be used for switch tables. 166 167 Although GAS does understand .gpdword, the SGI linker mishandles 168 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64). 169 We therefore disable GP-relative switch tables for n64 on IRIX targets. */ 170#define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX)) 171 172/* Generate mips16 code */ 173#define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0) 174/* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64/mips64r2 */ 175#define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32) 176 177/* Generic ISA defines. */ 178#define ISA_MIPS1 (mips_isa == 1) 179#define ISA_MIPS2 (mips_isa == 2) 180#define ISA_MIPS3 (mips_isa == 3) 181#define ISA_MIPS4 (mips_isa == 4) 182#define ISA_MIPS32 (mips_isa == 32) 183#define ISA_MIPS32R2 (mips_isa == 33) 184#define ISA_MIPS64 (mips_isa == 64) 185#define ISA_MIPS64R2 (mips_isa == 65) 186 187/* Architecture target defines. */ 188#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) 189#define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) 190#define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) 191#define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130) 192#define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400) 193#define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500) 194#define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000) 195#define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000) 196#define TARGET_SB1 (mips_arch == PROCESSOR_SB1) 197#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000) 198 199/* Scheduling target defines. */ 200#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) 201#define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) 202#define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) 203#define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120) 204#define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130) 205#define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000) 206#define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400) 207#define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500) 208#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000) 209#define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000) 210#define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000) 211#define TUNE_SB1 (mips_tune == PROCESSOR_SB1) 212 213/* True if the pre-reload scheduler should try to create chains of 214 multiply-add or multiply-subtract instructions. For example, 215 suppose we have: 216 217 t1 = a * b 218 t2 = t1 + c * d 219 t3 = e * f 220 t4 = t3 - g * h 221 222 t1 will have a higher priority than t2 and t3 will have a higher 223 priority than t4. However, before reload, there is no dependence 224 between t1 and t3, and they can often have similar priorities. 225 The scheduler will then tend to prefer: 226 227 t1 = a * b 228 t3 = e * f 229 t2 = t1 + c * d 230 t4 = t3 - g * h 231 232 which stops us from making full use of macc/madd-style instructions. 233 This sort of situation occurs frequently in Fourier transforms and 234 in unrolled loops. 235 236 To counter this, the TUNE_MACC_CHAINS code will reorder the ready 237 queue so that chained multiply-add and multiply-subtract instructions 238 appear ahead of any other instruction that is likely to clobber lo. 239 In the example above, if t2 and t3 become ready at the same time, 240 the code ensures that t2 is scheduled first. 241 242 Multiply-accumulate instructions are a bigger win for some targets 243 than others, so this macro is defined on an opt-in basis. */ 244#define TUNE_MACC_CHAINS (TUNE_MIPS5500 \ 245 || TUNE_MIPS4120 \ 246 || TUNE_MIPS4130) 247 248#define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64) 249#define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64) 250 251/* IRIX specific stuff. */ 252#define TARGET_IRIX 0 253#define TARGET_IRIX6 0 254 255/* Define preprocessor macros for the -march and -mtune options. 256 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected 257 processor. If INFO's canonical name is "foo", define PREFIX to 258 be "foo", and define an additional macro PREFIX_FOO. */ 259#define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \ 260 do \ 261 { \ 262 char *macro, *p; \ 263 \ 264 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \ 265 for (p = macro; *p != 0; p++) \ 266 *p = TOUPPER (*p); \ 267 \ 268 builtin_define (macro); \ 269 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \ 270 free (macro); \ 271 } \ 272 while (0) 273 274/* Target CPU builtins. */ 275#define TARGET_CPU_CPP_BUILTINS() \ 276 do \ 277 { \ 278 /* Everyone but IRIX defines this to mips. */ \ 279 if (!TARGET_IRIX) \ 280 builtin_assert ("machine=mips"); \ 281 \ 282 builtin_assert ("cpu=mips"); \ 283 builtin_define ("__mips__"); \ 284 builtin_define ("_mips"); \ 285 \ 286 /* We do this here because __mips is defined below \ 287 and so we can't use builtin_define_std. */ \ 288 if (!flag_iso) \ 289 builtin_define ("mips"); \ 290 \ 291 if (TARGET_64BIT) \ 292 builtin_define ("__mips64"); \ 293 \ 294 if (!TARGET_IRIX) \ 295 { \ 296 /* Treat _R3000 and _R4000 like register-size \ 297 defines, which is how they've historically \ 298 been used. */ \ 299 if (TARGET_64BIT) \ 300 { \ 301 builtin_define_std ("R4000"); \ 302 builtin_define ("_R4000"); \ 303 } \ 304 else \ 305 { \ 306 builtin_define_std ("R3000"); \ 307 builtin_define ("_R3000"); \ 308 } \ 309 } \ 310 if (TARGET_FLOAT64) \ 311 builtin_define ("__mips_fpr=64"); \ 312 else \ 313 builtin_define ("__mips_fpr=32"); \ 314 \ 315 if (TARGET_MIPS16) \ 316 builtin_define ("__mips16"); \ 317 \ 318 if (TARGET_MIPS3D) \ 319 builtin_define ("__mips3d"); \ 320 \ 321 if (TARGET_DSP) \ 322 builtin_define ("__mips_dsp"); \ 323 \ 324 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \ 325 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \ 326 \ 327 if (ISA_MIPS1) \ 328 { \ 329 builtin_define ("__mips=1"); \ 330 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \ 331 } \ 332 else if (ISA_MIPS2) \ 333 { \ 334 builtin_define ("__mips=2"); \ 335 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \ 336 } \ 337 else if (ISA_MIPS3) \ 338 { \ 339 builtin_define ("__mips=3"); \ 340 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \ 341 } \ 342 else if (ISA_MIPS4) \ 343 { \ 344 builtin_define ("__mips=4"); \ 345 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \ 346 } \ 347 else if (ISA_MIPS32) \ 348 { \ 349 builtin_define ("__mips=32"); \ 350 builtin_define ("__mips_isa_rev=1"); \ 351 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \ 352 } \ 353 else if (ISA_MIPS32R2) \ 354 { \ 355 builtin_define ("__mips=32"); \ 356 builtin_define ("__mips_isa_rev=2"); \ 357 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \ 358 } \ 359 else if (ISA_MIPS64) \ 360 { \ 361 builtin_define ("__mips=64"); \ 362 builtin_define ("__mips_isa_rev=1"); \ 363 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ 364 } \ 365 else if (ISA_MIPS64R2) \ 366 { \ 367 builtin_define ("__mips=64"); \ 368 builtin_define ("__mips_isa_rev=2"); \ 369 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ 370 } \ 371 \ 372 if (TARGET_HARD_FLOAT) \ 373 builtin_define ("__mips_hard_float"); \ 374 else if (TARGET_SOFT_FLOAT) \ 375 builtin_define ("__mips_soft_float"); \ 376 \ 377 if (TARGET_SINGLE_FLOAT) \ 378 builtin_define ("__mips_single_float"); \ 379 \ 380 if (TARGET_PAIRED_SINGLE_FLOAT) \ 381 builtin_define ("__mips_paired_single_float"); \ 382 \ 383 if (TARGET_BIG_ENDIAN) \ 384 { \ 385 builtin_define_std ("MIPSEB"); \ 386 builtin_define ("_MIPSEB"); \ 387 } \ 388 else \ 389 { \ 390 builtin_define_std ("MIPSEL"); \ 391 builtin_define ("_MIPSEL"); \ 392 } \ 393 \ 394 /* Macros dependent on the C dialect. */ \ 395 if (preprocessing_asm_p ()) \ 396 { \ 397 builtin_define_std ("LANGUAGE_ASSEMBLY"); \ 398 builtin_define ("_LANGUAGE_ASSEMBLY"); \ 399 } \ 400 else if (c_dialect_cxx ()) \ 401 { \ 402 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \ 403 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \ 404 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \ 405 } \ 406 else \ 407 { \ 408 builtin_define_std ("LANGUAGE_C"); \ 409 builtin_define ("_LANGUAGE_C"); \ 410 } \ 411 if (c_dialect_objc ()) \ 412 { \ 413 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \ 414 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \ 415 /* Bizarre, but needed at least for Irix. */ \ 416 builtin_define_std ("LANGUAGE_C"); \ 417 builtin_define ("_LANGUAGE_C"); \ 418 } \ 419 \ 420 if (mips_abi == ABI_EABI) \ 421 builtin_define ("__mips_eabi"); \ 422 \ 423} while (0) 424 425/* Default target_flags if no switches are specified */ 426 427#ifndef TARGET_DEFAULT 428#define TARGET_DEFAULT 0 429#endif 430 431#ifndef TARGET_CPU_DEFAULT 432#define TARGET_CPU_DEFAULT 0 433#endif 434 435#ifndef TARGET_ENDIAN_DEFAULT 436#define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN 437#endif 438 439#ifndef TARGET_FP_EXCEPTIONS_DEFAULT 440#define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS 441#endif 442 443/* 'from-abi' makes a good default: you get whatever the ABI requires. */ 444#ifndef MIPS_ISA_DEFAULT 445#ifndef MIPS_CPU_STRING_DEFAULT 446#define MIPS_CPU_STRING_DEFAULT "from-abi" 447#endif 448#endif 449 450#ifdef IN_LIBGCC2 451#undef TARGET_64BIT 452/* Make this compile time constant for libgcc2 */ 453#ifdef __mips64 454#define TARGET_64BIT 1 455#else 456#define TARGET_64BIT 0 457#endif 458#endif /* IN_LIBGCC2 */ 459 460#ifndef MULTILIB_ENDIAN_DEFAULT 461#if TARGET_ENDIAN_DEFAULT == 0 462#define MULTILIB_ENDIAN_DEFAULT "EL" 463#else 464#define MULTILIB_ENDIAN_DEFAULT "EB" 465#endif 466#endif 467 468#ifndef MULTILIB_ISA_DEFAULT 469# if MIPS_ISA_DEFAULT == 1 470# define MULTILIB_ISA_DEFAULT "mips1" 471# else 472# if MIPS_ISA_DEFAULT == 2 473# define MULTILIB_ISA_DEFAULT "mips2" 474# else 475# if MIPS_ISA_DEFAULT == 3 476# define MULTILIB_ISA_DEFAULT "mips3" 477# else 478# if MIPS_ISA_DEFAULT == 4 479# define MULTILIB_ISA_DEFAULT "mips4" 480# else 481# if MIPS_ISA_DEFAULT == 32 482# define MULTILIB_ISA_DEFAULT "mips32" 483# else 484# if MIPS_ISA_DEFAULT == 33 485# define MULTILIB_ISA_DEFAULT "mips32r2" 486# else 487# if MIPS_ISA_DEFAULT == 64 488# define MULTILIB_ISA_DEFAULT "mips64" 489# else 490# if MIPS_ISA_DEFAULT == 65 491# define MULTILIB_ISA_DEFAULT "mips64r2" 492# else 493# define MULTILIB_ISA_DEFAULT "mips1" 494# endif 495# endif 496# endif 497# endif 498# endif 499# endif 500# endif 501# endif 502#endif 503 504#ifndef MULTILIB_DEFAULTS 505#define MULTILIB_DEFAULTS \ 506 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT } 507#endif 508 509/* We must pass -EL to the linker by default for little endian embedded 510 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the 511 linker will default to using big-endian output files. The OUTPUT_FORMAT 512 line must be in the linker script, otherwise -EB/-EL will not work. */ 513 514#ifndef ENDIAN_SPEC 515#if TARGET_ENDIAN_DEFAULT == 0 516#define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}" 517#else 518#define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}" 519#endif 520#endif 521 522/* Support for a compile-time default CPU, et cetera. The rules are: 523 --with-arch is ignored if -march is specified or a -mips is specified 524 (other than -mips16). 525 --with-tune is ignored if -mtune is specified. 526 --with-abi is ignored if -mabi is specified. 527 --with-float is ignored if -mhard-float or -msoft-float are 528 specified. 529 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are 530 specified. */ 531#define OPTION_DEFAULT_SPECS \ 532 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \ 533 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 534 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \ 535 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \ 536 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" } 537 538 539#define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \ 540 && ISA_HAS_COND_TRAP) 541 542#define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \ 543 && !TARGET_SR71K \ 544 && !TARGET_MIPS16) 545 546/* Generate three-operand multiply instructions for SImode. */ 547#define GENERATE_MULT3_SI ((TARGET_MIPS3900 \ 548 || TARGET_MIPS5400 \ 549 || TARGET_MIPS5500 \ 550 || TARGET_MIPS7000 \ 551 || TARGET_MIPS9000 \ 552 || TARGET_MAD \ 553 || ISA_MIPS32 \ 554 || ISA_MIPS32R2 \ 555 || ISA_MIPS64 \ 556 || ISA_MIPS64R2 \ 557 ) && !TARGET_MIPS16) 558 559/* Generate three-operand multiply instructions for DImode. */ 560#define GENERATE_MULT3_DI ((TARGET_MIPS3900) \ 561 && !TARGET_MIPS16) 562 563/* True if the ABI can only work with 64-bit integer registers. We 564 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but 565 otherwise floating-point registers must also be 64-bit. */ 566#define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64) 567 568/* Likewise for 32-bit regs. */ 569#define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32) 570 571/* True if symbols are 64 bits wide. At present, n64 is the only 572 ABI for which this is true. */ 573#define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32) 574 575/* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3). */ 576#define ISA_HAS_64BIT_REGS (ISA_MIPS3 \ 577 || ISA_MIPS4 \ 578 || ISA_MIPS64 \ 579 || ISA_MIPS64R2) 580 581/* ISA has branch likely instructions (e.g. mips2). */ 582/* Disable branchlikely for tx39 until compare rewrite. They haven't 583 been generated up to this point. */ 584#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1) 585 586/* ISA has the conditional move instructions introduced in mips4. */ 587#define ISA_HAS_CONDMOVE ((ISA_MIPS4 \ 588 || ISA_MIPS32 \ 589 || ISA_MIPS32R2 \ 590 || ISA_MIPS64 \ 591 || ISA_MIPS64R2 \ 592 ) && !TARGET_MIPS5500 \ 593 && !TARGET_MIPS16) 594 595/* ISA has the mips4 FP condition code instructions: FP-compare to CC, 596 branch on CC, and move (both FP and non-FP) on CC. */ 597#define ISA_HAS_8CC (ISA_MIPS4 \ 598 || ISA_MIPS32 \ 599 || ISA_MIPS32R2 \ 600 || ISA_MIPS64 \ 601 || ISA_MIPS64R2) 602 603/* This is a catch all for other mips4 instructions: indexed load, the 604 FP madd and msub instructions, and the FP recip and recip sqrt 605 instructions. */ 606#define ISA_HAS_FP4 ((ISA_MIPS4 \ 607 || ISA_MIPS64 \ 608 || ISA_MIPS64R2 \ 609 ) && !TARGET_MIPS16) 610 611/* ISA has conditional trap instructions. */ 612#define ISA_HAS_COND_TRAP (!ISA_MIPS1 \ 613 && !TARGET_MIPS16) 614 615/* ISA has integer multiply-accumulate instructions, madd and msub. */ 616#define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \ 617 || ISA_MIPS32R2 \ 618 || ISA_MIPS64 \ 619 || ISA_MIPS64R2 \ 620 ) && !TARGET_MIPS16) 621 622/* ISA has floating-point nmadd and nmsub instructions. */ 623#define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \ 624 || ISA_MIPS64 \ 625 || ISA_MIPS64R2 \ 626 ) && (!TARGET_MIPS5400 || TARGET_MAD) \ 627 && ! TARGET_MIPS16) 628 629/* ISA has count leading zeroes/ones instruction (not implemented). */ 630#define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \ 631 || ISA_MIPS32R2 \ 632 || ISA_MIPS64 \ 633 || ISA_MIPS64R2 \ 634 ) && !TARGET_MIPS16) 635 636/* ISA has double-word count leading zeroes/ones instruction (not 637 implemented). */ 638#define ISA_HAS_DCLZ_DCLO ((ISA_MIPS64 \ 639 || ISA_MIPS64R2 \ 640 ) && !TARGET_MIPS16) 641 642/* ISA has three operand multiply instructions that put 643 the high part in an accumulator: mulhi or mulhiu. */ 644#define ISA_HAS_MULHI (TARGET_MIPS5400 \ 645 || TARGET_MIPS5500 \ 646 || TARGET_SR71K \ 647 ) 648 649/* ISA has three operand multiply instructions that 650 negates the result and puts the result in an accumulator. */ 651#define ISA_HAS_MULS (TARGET_MIPS5400 \ 652 || TARGET_MIPS5500 \ 653 || TARGET_SR71K \ 654 ) 655 656/* ISA has three operand multiply instructions that subtracts the 657 result from a 4th operand and puts the result in an accumulator. */ 658#define ISA_HAS_MSAC (TARGET_MIPS5400 \ 659 || TARGET_MIPS5500 \ 660 || TARGET_SR71K \ 661 ) 662/* ISA has three operand multiply instructions that the result 663 from a 4th operand and puts the result in an accumulator. */ 664#define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \ 665 || (TARGET_MIPS4130 && !TARGET_MIPS16) \ 666 || TARGET_MIPS5400 \ 667 || TARGET_MIPS5500 \ 668 || TARGET_SR71K \ 669 ) 670 671/* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */ 672#define ISA_HAS_MACCHI (!TARGET_MIPS16 \ 673 && (TARGET_MIPS4120 \ 674 || TARGET_MIPS4130)) 675 676/* ISA has 32-bit rotate right instruction. */ 677#define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \ 678 && (ISA_MIPS32R2 \ 679 || ISA_MIPS64R2 \ 680 || TARGET_MIPS5400 \ 681 || TARGET_MIPS5500 \ 682 || TARGET_SR71K \ 683 )) 684 685/* ISA has 64-bit rotate right instruction. */ 686#define ISA_HAS_ROTR_DI (TARGET_64BIT \ 687 && !TARGET_MIPS16 \ 688 && (TARGET_MIPS5400 \ 689 || TARGET_MIPS5500 \ 690 || TARGET_SR71K \ 691 || ISA_MIPS64R2 \ 692 )) 693 694/* ISA has data prefetch instructions. This controls use of 'pref'. */ 695#define ISA_HAS_PREFETCH ((ISA_MIPS4 \ 696 || ISA_MIPS32 \ 697 || ISA_MIPS32R2 \ 698 || ISA_MIPS64 \ 699 || ISA_MIPS64R2 \ 700 ) && !TARGET_MIPS16) 701 702/* ISA has data indexed prefetch instructions. This controls use of 703 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. 704 (prefx is a cop1x instruction, so can only be used if FP is 705 enabled.) */ 706#define ISA_HAS_PREFETCHX ((ISA_MIPS4 \ 707 || ISA_MIPS64 \ 708 || ISA_MIPS64R2 \ 709 ) && !TARGET_MIPS16) 710 711/* True if trunc.w.s and trunc.w.d are real (not synthetic) 712 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d 713 also requires TARGET_DOUBLE_FLOAT. */ 714#define ISA_HAS_TRUNC_W (!ISA_MIPS1) 715 716/* ISA includes the MIPS32/64 rev2 seb and seh instructions. */ 717#define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \ 718 && (ISA_MIPS32R2 \ 719 || ISA_MIPS64R2 \ 720 )) 721 722/* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */ 723#define ISA_HAS_EXT_INS (!TARGET_MIPS16 \ 724 && (ISA_MIPS32R2 \ 725 || ISA_MIPS64R2 \ 726 )) 727 728/* True if the result of a load is not available to the next instruction. 729 A nop will then be needed between instructions like "lw $4,..." 730 and "addiu $4,$4,1". */ 731#define ISA_HAS_LOAD_DELAY (mips_isa == 1 \ 732 && !TARGET_MIPS3900 \ 733 && !TARGET_MIPS16) 734 735/* Likewise mtc1 and mfc1. */ 736#define ISA_HAS_XFER_DELAY (mips_isa <= 3) 737 738/* Likewise floating-point comparisons. */ 739#define ISA_HAS_FCMP_DELAY (mips_isa <= 3) 740 741/* True if mflo and mfhi can be immediately followed by instructions 742 which write to the HI and LO registers. 743 744 According to MIPS specifications, MIPS ISAs I, II, and III need 745 (at least) two instructions between the reads of HI/LO and 746 instructions which write them, and later ISAs do not. Contradicting 747 the MIPS specifications, some MIPS IV processor user manuals (e.g. 748 the UM for the NEC Vr5000) document needing the instructions between 749 HI/LO reads and writes, as well. Therefore, we declare only MIPS32, 750 MIPS64 and later ISAs to have the interlocks, plus any specific 751 earlier-ISA CPUs for which CPU documentation declares that the 752 instructions are really interlocked. */ 753#define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \ 754 || ISA_MIPS32R2 \ 755 || ISA_MIPS64 \ 756 || ISA_MIPS64R2 \ 757 || TARGET_MIPS5500) 758 759/* Add -G xx support. */ 760 761#undef SWITCH_TAKES_ARG 762#define SWITCH_TAKES_ARG(CHAR) \ 763 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G') 764 765#define OVERRIDE_OPTIONS override_options () 766 767#define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage () 768 769/* Show we can debug even without a frame pointer. */ 770#define CAN_DEBUG_WITHOUT_FP 771 772/* Tell collect what flags to pass to nm. */ 773#ifndef NM_FLAGS 774#define NM_FLAGS "-Bn" 775#endif 776 777 778#ifndef MIPS_ABI_DEFAULT 779#define MIPS_ABI_DEFAULT ABI_32 780#endif 781 782/* Use the most portable ABI flag for the ASM specs. */ 783 784#if MIPS_ABI_DEFAULT == ABI_32 785#define MULTILIB_ABI_DEFAULT "mabi=32" 786#endif 787 788#if MIPS_ABI_DEFAULT == ABI_O64 789#define MULTILIB_ABI_DEFAULT "mabi=o64" 790#endif 791 792#if MIPS_ABI_DEFAULT == ABI_N32 793#define MULTILIB_ABI_DEFAULT "mabi=n32" 794#endif 795 796#if MIPS_ABI_DEFAULT == ABI_64 797#define MULTILIB_ABI_DEFAULT "mabi=64" 798#endif 799 800#if MIPS_ABI_DEFAULT == ABI_EABI 801#define MULTILIB_ABI_DEFAULT "mabi=eabi" 802#endif 803 804/* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options 805 to the assembler. It may be overridden by subtargets. */ 806#ifndef SUBTARGET_ASM_OPTIMIZING_SPEC 807#define SUBTARGET_ASM_OPTIMIZING_SPEC "\ 808%{noasmopt:-O0} \ 809%{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}" 810#endif 811 812/* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to 813 the assembler. It may be overridden by subtargets. 814 815 Beginning with gas 2.13, -mdebug must be passed to correctly handle 816 COFF debugging info. */ 817 818#ifndef SUBTARGET_ASM_DEBUGGING_SPEC 819#define SUBTARGET_ASM_DEBUGGING_SPEC "\ 820%{g} %{g0} %{g1} %{g2} %{g3} \ 821%{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \ 822%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \ 823%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \ 824%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \ 825%{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}" 826#endif 827 828/* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be 829 overridden by subtargets. */ 830 831#ifndef SUBTARGET_ASM_SPEC 832#define SUBTARGET_ASM_SPEC "" 833#endif 834 835#undef ASM_SPEC 836#define ASM_SPEC "\ 837%{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \ 838%{mips32} %{mips32r2} %{mips64} %{mips64r2} \ 839%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \ 840%{mips3d:-mips3d} \ 841%{mdsp} \ 842%{mfix-vr4120} %{mfix-vr4130} \ 843%(subtarget_asm_optimizing_spec) \ 844%(subtarget_asm_debugging_spec) \ 845%{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \ 846%{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \ 847%{msym32} %{mno-sym32} \ 848%{mtune=*} %{v} \ 849%(subtarget_asm_spec)" 850 851/* Extra switches sometimes passed to the linker. */ 852/* ??? The bestGnum will never be passed to the linker, because the gcc driver 853 will interpret it as a -b option. */ 854 855#ifndef LINK_SPEC 856#define LINK_SPEC "\ 857%(endian_spec) \ 858%{G*} %{mips1} %{mips2} %{mips3} %{mips4} \ 859%{mips32} %{mips32r2} %{mips64} %{mips64r2} \ 860%{bestGnum} %{shared} %{non_shared}" 861#endif /* LINK_SPEC defined */ 862 863 864/* Specs for the compiler proper */ 865 866/* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be 867 overridden by subtargets. */ 868#ifndef SUBTARGET_CC1_SPEC 869#define SUBTARGET_CC1_SPEC "" 870#endif 871 872/* CC1_SPEC is the set of arguments to pass to the compiler proper. */ 873 874#ifndef CC1_SPEC 875#define CC1_SPEC "\ 876%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \ 877%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \ 878%{save-temps: } \ 879%(subtarget_cc1_spec)" 880#endif 881 882/* Preprocessor specs. */ 883 884/* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be 885 overridden by subtargets. */ 886#ifndef SUBTARGET_CPP_SPEC 887#define SUBTARGET_CPP_SPEC "" 888#endif 889 890#define CPP_SPEC "%(subtarget_cpp_spec)" 891 892/* This macro defines names of additional specifications to put in the specs 893 that can be used in various specifications like CC1_SPEC. Its definition 894 is an initializer with a subgrouping for each command option. 895 896 Each subgrouping contains a string constant, that defines the 897 specification name, and a string constant that used by the GCC driver 898 program. 899 900 Do not define this macro if it does not need to do anything. */ 901 902#define EXTRA_SPECS \ 903 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \ 904 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 905 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \ 906 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \ 907 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ 908 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \ 909 { "endian_spec", ENDIAN_SPEC }, \ 910 SUBTARGET_EXTRA_SPECS 911 912#ifndef SUBTARGET_EXTRA_SPECS 913#define SUBTARGET_EXTRA_SPECS 914#endif 915 916#define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */ 917#define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */ 918#define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */ 919 920#ifndef PREFERRED_DEBUGGING_TYPE 921#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 922#endif 923 924#define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4) 925 926/* By default, turn on GDB extensions. */ 927#define DEFAULT_GDB_EXTENSIONS 1 928 929/* Local compiler-generated symbols must have a prefix that the assembler 930 understands. By default, this is $, although some targets (e.g., 931 NetBSD-ELF) need to override this. */ 932 933#ifndef LOCAL_LABEL_PREFIX 934#define LOCAL_LABEL_PREFIX "$" 935#endif 936 937/* By default on the mips, external symbols do not have an underscore 938 prepended, but some targets (e.g., NetBSD) require this. */ 939 940#ifndef USER_LABEL_PREFIX 941#define USER_LABEL_PREFIX "" 942#endif 943 944/* On Sun 4, this limit is 2048. We use 1500 to be safe, 945 since the length can run past this up to a continuation point. */ 946#undef DBX_CONTIN_LENGTH 947#define DBX_CONTIN_LENGTH 1500 948 949/* How to renumber registers for dbx and gdb. */ 950#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ] 951 952/* The mapping from gcc register number to DWARF 2 CFA column number. */ 953#define DWARF_FRAME_REGNUM(REG) (REG) 954 955/* The DWARF 2 CFA column which tracks the return address. */ 956#define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31) 957 958/* The DWARF 2 CFA column which tracks the return address from a 959 signal handler context. */ 960#define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1) 961 962/* Before the prologue, RA lives in r31. */ 963#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31) 964 965/* Describe how we implement __builtin_eh_return. */ 966#define EH_RETURN_DATA_REGNO(N) \ 967 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM) 968 969#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3) 970 971/* Offsets recorded in opcodes are a multiple of this alignment factor. 972 The default for this in 64-bit mode is 8, which causes problems with 973 SFmode register saves. */ 974#define DWARF_CIE_DATA_ALIGNMENT -4 975 976/* Correct the offset of automatic variables and arguments. Note that 977 the MIPS debug format wants all automatic variables and arguments 978 to be in terms of the virtual frame pointer (stack pointer before 979 any adjustment in the function), while the MIPS 3.0 linker wants 980 the frame pointer to be the stack pointer after the initial 981 adjustment. */ 982 983#define DEBUGGER_AUTO_OFFSET(X) \ 984 mips_debugger_offset (X, (HOST_WIDE_INT) 0) 985#define DEBUGGER_ARG_OFFSET(OFFSET, X) \ 986 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET) 987 988/* Target machine storage layout */ 989 990#define BITS_BIG_ENDIAN 0 991#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 992#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 993 994/* Define this to set the endianness to use in libgcc2.c, which can 995 not depend on target_flags. */ 996#if !defined(MIPSEL) && !defined(__MIPSEL__) 997#define LIBGCC2_WORDS_BIG_ENDIAN 1 998#else 999#define LIBGCC2_WORDS_BIG_ENDIAN 0 1000#endif 1001 1002#define MAX_BITS_PER_WORD 64 1003 1004/* Width of a word, in units (bytes). */ 1005#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 1006#ifndef IN_LIBGCC2 1007#define MIN_UNITS_PER_WORD 4 1008#endif 1009 1010/* For MIPS, width of a floating point register. */ 1011#define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4) 1012 1013/* If register $f0 holds a floating-point value, $f(0 + FP_INC) is 1014 the next available register. */ 1015#define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2) 1016 1017/* The largest size of value that can be held in floating-point 1018 registers and moved with a single instruction. */ 1019#define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG) 1020 1021/* The largest size of value that can be held in floating-point 1022 registers. */ 1023#define UNITS_PER_FPVALUE \ 1024 (TARGET_SOFT_FLOAT ? 0 \ 1025 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \ 1026 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT) 1027 1028/* The number of bytes in a double. */ 1029#define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT) 1030 1031#define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD) 1032 1033/* Set the sizes of the core types. */ 1034#define SHORT_TYPE_SIZE 16 1035#define INT_TYPE_SIZE 32 1036#define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32) 1037#define LONG_LONG_TYPE_SIZE 64 1038 1039#define FLOAT_TYPE_SIZE 32 1040#define DOUBLE_TYPE_SIZE 64 1041#define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64) 1042 1043/* long double is not a fixed mode, but the idea is that, if we 1044 support long double, we also want a 128-bit integer type. */ 1045#define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE 1046 1047#ifdef IN_LIBGCC2 1048#if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \ 1049 || (defined _ABI64 && _MIPS_SIM == _ABI64) 1050# define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 1051# else 1052# define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 1053# endif 1054#endif 1055 1056/* Width in bits of a pointer. */ 1057#ifndef POINTER_SIZE 1058#define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32) 1059#endif 1060 1061/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 1062#define PARM_BOUNDARY BITS_PER_WORD 1063 1064/* Allocation boundary (in *bits*) for the code of a function. */ 1065#define FUNCTION_BOUNDARY 32 1066 1067/* Alignment of field after `int : 0' in a structure. */ 1068#define EMPTY_FIELD_BOUNDARY 32 1069 1070/* Every structure's size must be a multiple of this. */ 1071/* 8 is observed right on a DECstation and on riscos 4.02. */ 1072#define STRUCTURE_SIZE_BOUNDARY 8 1073 1074/* There is no point aligning anything to a rounder boundary than this. */ 1075#define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE 1076 1077/* All accesses must be aligned. */ 1078#define STRICT_ALIGNMENT 1 1079 1080/* Define this if you wish to imitate the way many other C compilers 1081 handle alignment of bitfields and the structures that contain 1082 them. 1083 1084 The behavior is that the type written for a bit-field (`int', 1085 `short', or other integer type) imposes an alignment for the 1086 entire structure, as if the structure really did contain an 1087 ordinary field of that type. In addition, the bit-field is placed 1088 within the structure so that it would fit within such a field, 1089 not crossing a boundary for it. 1090 1091 Thus, on most machines, a bit-field whose type is written as `int' 1092 would not cross a four-byte boundary, and would force four-byte 1093 alignment for the whole structure. (The alignment used may not 1094 be four bytes; it is controlled by the other alignment 1095 parameters.) 1096 1097 If the macro is defined, its definition should be a C expression; 1098 a nonzero value for the expression enables this behavior. */ 1099 1100#define PCC_BITFIELD_TYPE_MATTERS 1 1101 1102/* If defined, a C expression to compute the alignment given to a 1103 constant that is being placed in memory. CONSTANT is the constant 1104 and ALIGN is the alignment that the object would ordinarily have. 1105 The value of this macro is used instead of that alignment to align 1106 the object. 1107 1108 If this macro is not defined, then ALIGN is used. 1109 1110 The typical use of this macro is to increase alignment for string 1111 constants to be word aligned so that `strcpy' calls that copy 1112 constants can be done inline. */ 1113 1114#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 1115 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ 1116 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 1117 1118/* If defined, a C expression to compute the alignment for a static 1119 variable. TYPE is the data type, and ALIGN is the alignment that 1120 the object would ordinarily have. The value of this macro is used 1121 instead of that alignment to align the object. 1122 1123 If this macro is not defined, then ALIGN is used. 1124 1125 One use of this macro is to increase alignment of medium-size 1126 data to make it all fit in fewer cache lines. Another is to 1127 cause character arrays to be word-aligned so that `strcpy' calls 1128 that copy constants to character arrays can be done inline. */ 1129 1130#undef DATA_ALIGNMENT 1131#define DATA_ALIGNMENT(TYPE, ALIGN) \ 1132 ((((ALIGN) < BITS_PER_WORD) \ 1133 && (TREE_CODE (TYPE) == ARRAY_TYPE \ 1134 || TREE_CODE (TYPE) == UNION_TYPE \ 1135 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 1136 1137 1138#define PAD_VARARGS_DOWN \ 1139 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) 1140 1141/* Define if operations between registers always perform the operation 1142 on the full register even if a narrower mode is specified. */ 1143#define WORD_REGISTER_OPERATIONS 1144 1145/* When in 64 bit mode, move insns will sign extend SImode and CCmode 1146 moves. All other references are zero extended. */ 1147#define LOAD_EXTEND_OP(MODE) \ 1148 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \ 1149 ? SIGN_EXTEND : ZERO_EXTEND) 1150 1151/* Define this macro if it is advisable to hold scalars in registers 1152 in a wider mode than that declared by the program. In such cases, 1153 the value is constrained to be within the bounds of the declared 1154 type, but kept valid in the wider mode. The signedness of the 1155 extension may differ from that of the type. */ 1156 1157#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1158 if (GET_MODE_CLASS (MODE) == MODE_INT \ 1159 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 1160 { \ 1161 if ((MODE) == SImode) \ 1162 (UNSIGNEDP) = 0; \ 1163 (MODE) = Pmode; \ 1164 } 1165 1166/* Define if loading short immediate values into registers sign extends. */ 1167#define SHORT_IMMEDIATES_SIGN_EXTEND 1168 1169/* The [d]clz instructions have the natural values at 0. */ 1170 1171#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1172 ((VALUE) = GET_MODE_BITSIZE (MODE), true) 1173 1174/* Standard register usage. */ 1175 1176/* Number of hardware registers. We have: 1177 1178 - 32 integer registers 1179 - 32 floating point registers 1180 - 8 condition code registers 1181 - 2 accumulator registers (hi and lo) 1182 - 32 registers each for coprocessors 0, 2 and 3 1183 - 3 fake registers: 1184 - ARG_POINTER_REGNUM 1185 - FRAME_POINTER_REGNUM 1186 - FAKE_CALL_REGNO (see the comment above load_callsi for details) 1187 - 3 dummy entries that were used at various times in the past. 1188 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE 1189 - 6 DSP control registers */ 1190 1191#define FIRST_PSEUDO_REGISTER 188 1192 1193/* By default, fix the kernel registers ($26 and $27), the global 1194 pointer ($28) and the stack pointer ($29). This can change 1195 depending on the command-line options. 1196 1197 Regarding coprocessor registers: without evidence to the contrary, 1198 it's best to assume that each coprocessor register has a unique 1199 use. This can be overridden, in, e.g., override_options() or 1200 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate 1201 for a particular target. */ 1202 1203#define FIXED_REGISTERS \ 1204{ \ 1205 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1206 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \ 1207 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1208 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1209 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \ 1210 /* COP0 registers */ \ 1211 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1212 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1213 /* COP2 registers */ \ 1214 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1215 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1216 /* COP3 registers */ \ 1217 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1218 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1219 /* 6 DSP accumulator registers & 6 control registers */ \ 1220 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \ 1221} 1222 1223 1224/* Set up this array for o32 by default. 1225 1226 Note that we don't mark $31 as a call-clobbered register. The idea is 1227 that it's really the call instructions themselves which clobber $31. 1228 We don't care what the called function does with it afterwards. 1229 1230 This approach makes it easier to implement sibcalls. Unlike normal 1231 calls, sibcalls don't clobber $31, so the register reaches the 1232 called function in tact. EPILOGUE_USES says that $31 is useful 1233 to the called function. */ 1234 1235#define CALL_USED_REGISTERS \ 1236{ \ 1237 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1238 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \ 1239 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1240 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1241 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1242 /* COP0 registers */ \ 1243 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1244 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1245 /* COP2 registers */ \ 1246 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1247 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1248 /* COP3 registers */ \ 1249 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1250 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1251 /* 6 DSP accumulator registers & 6 control registers */ \ 1252 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ 1253} 1254 1255 1256/* Define this since $28, though fixed, is call-saved in many ABIs. */ 1257 1258#define CALL_REALLY_USED_REGISTERS \ 1259{ /* General registers. */ \ 1260 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1261 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \ 1262 /* Floating-point registers. */ \ 1263 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1264 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1265 /* Others. */ \ 1266 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1267 /* COP0 registers */ \ 1268 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1269 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1270 /* COP2 registers */ \ 1271 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1272 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1273 /* COP3 registers */ \ 1274 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1275 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1276 /* 6 DSP accumulator registers & 6 control registers */ \ 1277 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \ 1278} 1279 1280/* Internal macros to classify a register number as to whether it's a 1281 general purpose register, a floating point register, a 1282 multiply/divide register, or a status register. */ 1283 1284#define GP_REG_FIRST 0 1285#define GP_REG_LAST 31 1286#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) 1287#define GP_DBX_FIRST 0 1288 1289#define FP_REG_FIRST 32 1290#define FP_REG_LAST 63 1291#define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) 1292#define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32) 1293 1294#define MD_REG_FIRST 64 1295#define MD_REG_LAST 65 1296#define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1) 1297#define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM) 1298 1299#define ST_REG_FIRST 67 1300#define ST_REG_LAST 74 1301#define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1) 1302 1303 1304/* FIXME: renumber. */ 1305#define COP0_REG_FIRST 80 1306#define COP0_REG_LAST 111 1307#define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1) 1308 1309#define COP2_REG_FIRST 112 1310#define COP2_REG_LAST 143 1311#define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1) 1312 1313#define COP3_REG_FIRST 144 1314#define COP3_REG_LAST 175 1315#define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1) 1316/* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */ 1317#define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1) 1318 1319#define DSP_ACC_REG_FIRST 176 1320#define DSP_ACC_REG_LAST 181 1321#define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1) 1322 1323#define AT_REGNUM (GP_REG_FIRST + 1) 1324#define HI_REGNUM (MD_REG_FIRST + 0) 1325#define LO_REGNUM (MD_REG_FIRST + 1) 1326#define AC1HI_REGNUM (DSP_ACC_REG_FIRST + 0) 1327#define AC1LO_REGNUM (DSP_ACC_REG_FIRST + 1) 1328#define AC2HI_REGNUM (DSP_ACC_REG_FIRST + 2) 1329#define AC2LO_REGNUM (DSP_ACC_REG_FIRST + 3) 1330#define AC3HI_REGNUM (DSP_ACC_REG_FIRST + 4) 1331#define AC3LO_REGNUM (DSP_ACC_REG_FIRST + 5) 1332 1333/* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC. 1334 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG 1335 should be used instead. */ 1336#define FPSW_REGNUM ST_REG_FIRST 1337 1338#define GP_REG_P(REGNO) \ 1339 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) 1340#define M16_REG_P(REGNO) \ 1341 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17) 1342#define FP_REG_P(REGNO) \ 1343 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) 1344#define MD_REG_P(REGNO) \ 1345 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM) 1346#define ST_REG_P(REGNO) \ 1347 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM) 1348#define COP0_REG_P(REGNO) \ 1349 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM) 1350#define COP2_REG_P(REGNO) \ 1351 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM) 1352#define COP3_REG_P(REGNO) \ 1353 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM) 1354#define ALL_COP_REG_P(REGNO) \ 1355 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM) 1356/* Test if REGNO is one of the 6 new DSP accumulators. */ 1357#define DSP_ACC_REG_P(REGNO) \ 1358 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM) 1359/* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */ 1360#define ACC_REG_P(REGNO) \ 1361 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO)) 1362/* Test if REGNO is HI or the first register of 3 new DSP accumulator pairs. */ 1363#define ACC_HI_REG_P(REGNO) \ 1364 ((REGNO) == HI_REGNUM || (REGNO) == AC1HI_REGNUM || (REGNO) == AC2HI_REGNUM \ 1365 || (REGNO) == AC3HI_REGNUM) 1366 1367#define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) 1368 1369/* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used 1370 to initialize the mips16 gp pseudo register. */ 1371#define CONST_GP_P(X) \ 1372 (GET_CODE (X) == CONST \ 1373 && GET_CODE (XEXP (X, 0)) == UNSPEC \ 1374 && XINT (XEXP (X, 0), 1) == UNSPEC_GP) 1375 1376/* Return coprocessor number from register number. */ 1377 1378#define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \ 1379 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \ 1380 : COP3_REG_P (REGNO) ? '3' : '?') 1381 1382 1383#define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE) 1384 1385/* To make the code simpler, HARD_REGNO_MODE_OK just references an 1386 array built in override_options. Because machmodes.h is not yet 1387 included before this file is processed, the MODE bound can't be 1388 expressed here. */ 1389 1390extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER]; 1391 1392#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1393 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ] 1394 1395/* Value is 1 if it is a good idea to tie two pseudo registers 1396 when one has mode MODE1 and one has mode MODE2. 1397 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1398 for any hard reg, then this must be 0 for correct output. */ 1399#define MODES_TIEABLE_P(MODE1, MODE2) \ 1400 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \ 1401 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ 1402 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \ 1403 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)) 1404 1405/* Register to use for pushing function arguments. */ 1406#define STACK_POINTER_REGNUM (GP_REG_FIRST + 29) 1407 1408/* These two registers don't really exist: they get eliminated to either 1409 the stack or hard frame pointer. */ 1410#define ARG_POINTER_REGNUM 77 1411#define FRAME_POINTER_REGNUM 78 1412 1413/* $30 is not available on the mips16, so we use $17 as the frame 1414 pointer. */ 1415#define HARD_FRAME_POINTER_REGNUM \ 1416 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30) 1417 1418/* Value should be nonzero if functions must have frame pointers. 1419 Zero means the frame pointer need not be set up (and parms 1420 may be accessed via the stack pointer) in functions that seem suitable. 1421 This is computed in `reload', in reload1.c. */ 1422#define FRAME_POINTER_REQUIRED (current_function_calls_alloca) 1423 1424/* Register in which static-chain is passed to a function. */ 1425#define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2) 1426 1427/* Registers used as temporaries in prologue/epilogue code. If we're 1428 generating mips16 code, these registers must come from the core set 1429 of 8. The prologue register mustn't conflict with any incoming 1430 arguments, the static chain pointer, or the frame pointer. The 1431 epilogue temporary mustn't conflict with the return registers, the 1432 frame pointer, the EH stack adjustment, or the EH data registers. */ 1433 1434#define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3) 1435#define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8)) 1436 1437#define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM) 1438#define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM) 1439 1440/* Define this macro if it is as good or better to call a constant 1441 function address than to call an address kept in a register. */ 1442#define NO_FUNCTION_CSE 1 1443 1444/* The ABI-defined global pointer. Sometimes we use a different 1445 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */ 1446#define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28) 1447 1448/* We normally use $28 as the global pointer. However, when generating 1449 n32/64 PIC, it is better for leaf functions to use a call-clobbered 1450 register instead. They can then avoid saving and restoring $28 1451 and perhaps avoid using a frame at all. 1452 1453 When a leaf function uses something other than $28, mips_expand_prologue 1454 will modify pic_offset_table_rtx in place. Take the register number 1455 from there after reload. */ 1456#define PIC_OFFSET_TABLE_REGNUM \ 1457 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM) 1458 1459#define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25) 1460 1461/* Define the classes of registers for register constraints in the 1462 machine description. Also define ranges of constants. 1463 1464 One of the classes must always be named ALL_REGS and include all hard regs. 1465 If there is more than one class, another class must be named NO_REGS 1466 and contain no registers. 1467 1468 The name GENERAL_REGS must be the name of a class (or an alias for 1469 another name such as ALL_REGS). This is the class of registers 1470 that is allowed by "g" or "r" in a register constraint. 1471 Also, registers outside this class are allocated only when 1472 instructions express preferences for them. 1473 1474 The classes must be numbered in nondecreasing order; that is, 1475 a larger-numbered class must never be contained completely 1476 in a smaller-numbered class. 1477 1478 For any two classes, it is very desirable that there be another 1479 class that represents their union. */ 1480 1481enum reg_class 1482{ 1483 NO_REGS, /* no registers in set */ 1484 M16_NA_REGS, /* mips16 regs not used to pass args */ 1485 M16_REGS, /* mips16 directly accessible registers */ 1486 T_REG, /* mips16 T register ($24) */ 1487 M16_T_REGS, /* mips16 registers plus T register */ 1488 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */ 1489 V1_REG, /* Register $v1 ($3) used for TLS access. */ 1490 LEA_REGS, /* Every GPR except $25 */ 1491 GR_REGS, /* integer registers */ 1492 FP_REGS, /* floating point registers */ 1493 HI_REG, /* hi register */ 1494 LO_REG, /* lo register */ 1495 MD_REGS, /* multiply/divide registers (hi/lo) */ 1496 COP0_REGS, /* generic coprocessor classes */ 1497 COP2_REGS, 1498 COP3_REGS, 1499 HI_AND_GR_REGS, /* union classes */ 1500 LO_AND_GR_REGS, 1501 HI_AND_FP_REGS, 1502 COP0_AND_GR_REGS, 1503 COP2_AND_GR_REGS, 1504 COP3_AND_GR_REGS, 1505 ALL_COP_REGS, 1506 ALL_COP_AND_GR_REGS, 1507 ST_REGS, /* status registers (fp status) */ 1508 DSP_ACC_REGS, /* DSP accumulator registers */ 1509 ACC_REGS, /* Hi/Lo and DSP accumulator registers */ 1510 ALL_REGS, /* all registers */ 1511 LIM_REG_CLASSES /* max value + 1 */ 1512}; 1513 1514#define N_REG_CLASSES (int) LIM_REG_CLASSES 1515 1516#define GENERAL_REGS GR_REGS 1517 1518/* An initializer containing the names of the register classes as C 1519 string constants. These names are used in writing some of the 1520 debugging dumps. */ 1521 1522#define REG_CLASS_NAMES \ 1523{ \ 1524 "NO_REGS", \ 1525 "M16_NA_REGS", \ 1526 "M16_REGS", \ 1527 "T_REG", \ 1528 "M16_T_REGS", \ 1529 "PIC_FN_ADDR_REG", \ 1530 "V1_REG", \ 1531 "LEA_REGS", \ 1532 "GR_REGS", \ 1533 "FP_REGS", \ 1534 "HI_REG", \ 1535 "LO_REG", \ 1536 "MD_REGS", \ 1537 /* coprocessor registers */ \ 1538 "COP0_REGS", \ 1539 "COP2_REGS", \ 1540 "COP3_REGS", \ 1541 "HI_AND_GR_REGS", \ 1542 "LO_AND_GR_REGS", \ 1543 "HI_AND_FP_REGS", \ 1544 "COP0_AND_GR_REGS", \ 1545 "COP2_AND_GR_REGS", \ 1546 "COP3_AND_GR_REGS", \ 1547 "ALL_COP_REGS", \ 1548 "ALL_COP_AND_GR_REGS", \ 1549 "ST_REGS", \ 1550 "DSP_ACC_REGS", \ 1551 "ACC_REGS", \ 1552 "ALL_REGS" \ 1553} 1554 1555/* An initializer containing the contents of the register classes, 1556 as integers which are bit masks. The Nth integer specifies the 1557 contents of class N. The way the integer MASK is interpreted is 1558 that register R is in the class if `MASK & (1 << R)' is 1. 1559 1560 When the machine has more than 32 registers, an integer does not 1561 suffice. Then the integers are replaced by sub-initializers, 1562 braced groupings containing several integers. Each 1563 sub-initializer must be suitable as an initializer for the type 1564 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ 1565 1566#define REG_CLASS_CONTENTS \ 1567{ \ 1568 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \ 1569 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\ 1570 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \ 1571 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \ 1572 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \ 1573 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \ 1574 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \ 1575 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \ 1576 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \ 1577 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \ 1578 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \ 1579 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \ 1580 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \ 1581 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \ 1582 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \ 1583 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \ 1584 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \ 1585 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \ 1586 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \ 1587 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \ 1588 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \ 1589 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \ 1590 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \ 1591 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \ 1592 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \ 1593 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \ 1594 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \ 1595 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \ 1596} 1597 1598 1599/* A C expression whose value is a register class containing hard 1600 register REGNO. In general there is more that one such class; 1601 choose a class which is "minimal", meaning that no smaller class 1602 also contains the register. */ 1603 1604extern const enum reg_class mips_regno_to_class[]; 1605 1606#define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ] 1607 1608/* A macro whose definition is the name of the class to which a 1609 valid base register must belong. A base register is one used in 1610 an address which is the register value plus a displacement. */ 1611 1612#define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS) 1613 1614/* A macro whose definition is the name of the class to which a 1615 valid index register must belong. An index register is one used 1616 in an address where its value is either multiplied by a scale 1617 factor or added to another register (as well as added to a 1618 displacement). */ 1619 1620#define INDEX_REG_CLASS NO_REGS 1621 1622/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows 1623 registers explicitly used in the rtl to be used as spill registers 1624 but prevents the compiler from extending the lifetime of these 1625 registers. */ 1626 1627#define SMALL_REGISTER_CLASSES (TARGET_MIPS16) 1628 1629/* This macro is used later on in the file. */ 1630#define GR_REG_CLASS_P(CLASS) \ 1631 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \ 1632 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \ 1633 || (CLASS) == V1_REG \ 1634 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS) 1635 1636/* This macro is also used later on in the file. */ 1637#define COP_REG_CLASS_P(CLASS) \ 1638 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS) 1639 1640/* REG_ALLOC_ORDER is to order in which to allocate registers. This 1641 is the default value (allocate the registers in numeric order). We 1642 define it just so that we can override it for the mips16 target in 1643 ORDER_REGS_FOR_LOCAL_ALLOC. */ 1644 1645#define REG_ALLOC_ORDER \ 1646{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 1647 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 1648 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 1649 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ 1650 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ 1651 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \ 1652 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \ 1653 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \ 1654 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \ 1655 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \ 1656 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \ 1657 176,177,178,179,180,181,182,183,184,185,186,187 \ 1658} 1659 1660/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 1661 to be rearranged based on a particular function. On the mips16, we 1662 want to allocate $24 (T_REG) before other registers for 1663 instructions for which it is possible. */ 1664 1665#define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc () 1666 1667/* REGISTER AND CONSTANT CLASSES */ 1668 1669/* Get reg_class from a letter such as appears in the machine 1670 description. 1671 1672 DEFINED REGISTER CLASSES: 1673 1674 'd' General (aka integer) registers 1675 Normally this is GR_REGS, but in mips16 mode this is M16_REGS 1676 'y' General registers (in both mips16 and non mips16 mode) 1677 'e' Effective address registers (general registers except $25) 1678 't' mips16 temporary register ($24) 1679 'f' Floating point registers 1680 'h' Hi register 1681 'l' Lo register 1682 'v' $v1 only 1683 'x' Multiply/divide registers 1684 'z' FP Status register 1685 'B' Cop0 register 1686 'C' Cop2 register 1687 'D' Cop3 register 1688 'A' DSP accumulator registers 1689 'a' MD registers and DSP accumulator registers 1690 'b' All registers */ 1691 1692extern enum reg_class mips_char_to_class[256]; 1693 1694#define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)] 1695 1696/* True if VALUE is an unsigned 6-bit number. */ 1697 1698#define UIMM6_OPERAND(VALUE) \ 1699 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0) 1700 1701/* True if VALUE is a signed 10-bit number. */ 1702 1703#define IMM10_OPERAND(VALUE) \ 1704 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400) 1705 1706/* True if VALUE is a signed 16-bit number. */ 1707 1708#define SMALL_OPERAND(VALUE) \ 1709 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000) 1710 1711/* True if VALUE is an unsigned 16-bit number. */ 1712 1713#define SMALL_OPERAND_UNSIGNED(VALUE) \ 1714 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0) 1715 1716/* True if VALUE can be loaded into a register using LUI. */ 1717 1718#define LUI_OPERAND(VALUE) \ 1719 (((VALUE) | 0x7fff0000) == 0x7fff0000 \ 1720 || ((VALUE) | 0x7fff0000) + 0x10000 == 0) 1721 1722/* Return a value X with the low 16 bits clear, and such that 1723 VALUE - X is a signed 16-bit value. */ 1724 1725#define CONST_HIGH_PART(VALUE) \ 1726 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff) 1727 1728#define CONST_LOW_PART(VALUE) \ 1729 ((VALUE) - CONST_HIGH_PART (VALUE)) 1730 1731#define SMALL_INT(X) SMALL_OPERAND (INTVAL (X)) 1732#define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X)) 1733#define LUI_INT(X) LUI_OPERAND (INTVAL (X)) 1734 1735/* The letters I, J, K, L, M, N, O, and P in a register constraint 1736 string can be used to stand for particular ranges of immediate 1737 operands. This macro defines what the ranges are. C is the 1738 letter, and VALUE is a constant value. Return 1 if VALUE is 1739 in the range specified by C. */ 1740 1741/* For MIPS: 1742 1743 `I' is used for the range of constants an arithmetic insn can 1744 actually contain (16 bits signed integers). 1745 1746 `J' is used for the range which is just zero (i.e., $r0). 1747 1748 `K' is used for the range of constants a logical insn can actually 1749 contain (16 bit zero-extended integers). 1750 1751 `L' is used for the range of constants that be loaded with lui 1752 (i.e., the bottom 16 bits are zero). 1753 1754 `M' is used for the range of constants that take two words to load 1755 (i.e., not matched by `I', `K', and `L'). 1756 1757 `N' is used for negative 16 bit constants other than -65536. 1758 1759 `O' is a 15 bit signed integer. 1760 1761 `P' is used for positive 16 bit constants. */ 1762 1763#define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1764 ((C) == 'I' ? SMALL_OPERAND (VALUE) \ 1765 : (C) == 'J' ? ((VALUE) == 0) \ 1766 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \ 1767 : (C) == 'L' ? LUI_OPERAND (VALUE) \ 1768 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \ 1769 && !SMALL_OPERAND_UNSIGNED (VALUE) \ 1770 && !LUI_OPERAND (VALUE)) \ 1771 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \ 1772 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \ 1773 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \ 1774 : 0) 1775 1776/* Similar, but for floating constants, and defining letters G and H. 1777 Here VALUE is the CONST_DOUBLE rtx itself. */ 1778 1779/* For MIPS 1780 1781 'G' : Floating point 0 */ 1782 1783#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1784 ((C) == 'G' \ 1785 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) 1786 1787/* Letters in the range `Q' through `U' may be defined in a 1788 machine-dependent fashion to stand for arbitrary operand types. 1789 The machine description macro `EXTRA_CONSTRAINT' is passed the 1790 operand as its first argument and the constraint letter as its 1791 second operand. 1792 1793 `Q' is for signed 16-bit constants. 1794 `R' is for single-instruction memory references. Note that this 1795 constraint has often been used in linux and glibc code. 1796 `S' is for legitimate constant call addresses. 1797 `T' is for constant move_operands that cannot be safely loaded into $25. 1798 `U' is for constant move_operands that can be safely loaded into $25. 1799 `W' is for memory references that are based on a member of BASE_REG_CLASS. 1800 This is true for all non-mips16 references (although it can sometimes 1801 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes 1802 stack and constant-pool references. 1803 `YG' is for 0 valued vector constants. 1804 `YA' is for unsigned 6-bit constants. 1805 `YB' is for signed 10-bit constants. */ 1806 1807#define EXTRA_CONSTRAINT_Y(OP,STR) \ 1808 (((STR)[1] == 'G') ? (GET_CODE (OP) == CONST_VECTOR \ 1809 && (OP) == CONST0_RTX (GET_MODE (OP))) \ 1810 : ((STR)[1] == 'A') ? (GET_CODE (OP) == CONST_INT \ 1811 && UIMM6_OPERAND (INTVAL (OP))) \ 1812 : ((STR)[1] == 'B') ? (GET_CODE (OP) == CONST_INT \ 1813 && IMM10_OPERAND (INTVAL (OP))) \ 1814 : FALSE) 1815 1816 1817#define EXTRA_CONSTRAINT_STR(OP,CODE,STR) \ 1818 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \ 1819 : ((CODE) == 'R') ? (MEM_P (OP) \ 1820 && mips_fetch_insns (OP) == 1) \ 1821 : ((CODE) == 'S') ? (CONSTANT_P (OP) \ 1822 && call_insn_operand (OP, VOIDmode)) \ 1823 : ((CODE) == 'T') ? (CONSTANT_P (OP) \ 1824 && move_operand (OP, VOIDmode) \ 1825 && mips_dangerous_for_la25_p (OP)) \ 1826 : ((CODE) == 'U') ? (CONSTANT_P (OP) \ 1827 && move_operand (OP, VOIDmode) \ 1828 && !mips_dangerous_for_la25_p (OP)) \ 1829 : ((CODE) == 'W') ? (MEM_P (OP) \ 1830 && memory_operand (OP, VOIDmode) \ 1831 && (!TARGET_MIPS16 \ 1832 || (!stack_operand (OP, VOIDmode) \ 1833 && !CONSTANT_P (XEXP (OP, 0))))) \ 1834 : ((CODE) == 'Y') ? EXTRA_CONSTRAINT_Y (OP, STR) \ 1835 : FALSE) 1836 1837/* Y is the only multi-letter constraint, and has length 2. */ 1838 1839#define CONSTRAINT_LEN(C,STR) \ 1840 (((C) == 'Y') ? 2 \ 1841 : DEFAULT_CONSTRAINT_LEN (C, STR)) 1842 1843/* Say which of the above are memory constraints. */ 1844#define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W') 1845 1846#define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1847 mips_preferred_reload_class (X, CLASS) 1848 1849/* Certain machines have the property that some registers cannot be 1850 copied to some other registers without using memory. Define this 1851 macro on those machines to be a C expression that is nonzero if 1852 objects of mode MODE in registers of CLASS1 can only be copied to 1853 registers of class CLASS2 by storing a register of CLASS1 into 1854 memory and loading that memory location into a register of CLASS2. 1855 1856 Do not define this macro if its value would always be zero. */ 1857#if 0 1858#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1859 ((!TARGET_DEBUG_H_MODE \ 1860 && GET_MODE_CLASS (MODE) == MODE_INT \ 1861 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \ 1862 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \ 1863 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \ 1864 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \ 1865 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS)))) 1866#endif 1867/* The HI and LO registers can only be reloaded via the general 1868 registers. Condition code registers can only be loaded to the 1869 general registers, and from the floating point registers. */ 1870 1871#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1872 mips_secondary_reload_class (CLASS, MODE, X, 1) 1873#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1874 mips_secondary_reload_class (CLASS, MODE, X, 0) 1875 1876/* Return the maximum number of consecutive registers 1877 needed to represent mode MODE in a register of class CLASS. */ 1878 1879#define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE) 1880 1881#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1882 mips_cannot_change_mode_class (FROM, TO, CLASS) 1883 1884/* Stack layout; function entry, exit and calling. */ 1885 1886#define STACK_GROWS_DOWNWARD 1887 1888/* The offset of the first local variable from the beginning of the frame. 1889 See compute_frame_size for details about the frame layout. 1890 1891 ??? If flag_profile_values is true, and we are generating 32-bit code, then 1892 we assume that we will need 16 bytes of argument space. This is because 1893 the value profiling code may emit calls to cmpdi2 in leaf functions. 1894 Without this hack, the local variables will start at sp+8 and the gp save 1895 area will be at sp+16, and thus they will overlap. compute_frame_size is 1896 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which 1897 will end up as 24 instead of 8. This won't be needed if profiling code is 1898 inserted before virtual register instantiation. */ 1899 1900#define STARTING_FRAME_OFFSET \ 1901 ((flag_profile_values && ! TARGET_64BIT \ 1902 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \ 1903 : current_function_outgoing_args_size) \ 1904 + (TARGET_ABICALLS && !TARGET_NEWABI \ 1905 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)) 1906 1907#define RETURN_ADDR_RTX mips_return_addr 1908 1909/* Since the mips16 ISA mode is encoded in the least-significant bit 1910 of the address, mask it off return addresses for purposes of 1911 finding exception handling regions. */ 1912 1913#define MASK_RETURN_ADDR GEN_INT (-2) 1914 1915 1916/* Similarly, don't use the least-significant bit to tell pointers to 1917 code from vtable index. */ 1918 1919#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 1920 1921/* The eliminations to $17 are only used for mips16 code. See the 1922 definition of HARD_FRAME_POINTER_REGNUM. */ 1923 1924#define ELIMINABLE_REGS \ 1925{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1926 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \ 1927 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \ 1928 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1929 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \ 1930 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}} 1931 1932/* We can always eliminate to the hard frame pointer. We can eliminate 1933 to the stack pointer unless a frame pointer is needed. 1934 1935 In mips16 mode, we need a frame pointer for a large frame; otherwise, 1936 reload may be unable to compute the address of a local variable, 1937 since there is no way to add a large constant to the stack pointer 1938 without using a temporary register. */ 1939#define CAN_ELIMINATE(FROM, TO) \ 1940 ((TO) == HARD_FRAME_POINTER_REGNUM \ 1941 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \ 1942 && (!TARGET_MIPS16 \ 1943 || compute_frame_size (get_frame_size ()) < 32768))) 1944 1945#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1946 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO)) 1947 1948/* Allocate stack space for arguments at the beginning of each function. */ 1949#define ACCUMULATE_OUTGOING_ARGS 1 1950 1951/* The argument pointer always points to the first argument. */ 1952#define FIRST_PARM_OFFSET(FNDECL) 0 1953 1954/* o32 and o64 reserve stack space for all argument registers. */ 1955#define REG_PARM_STACK_SPACE(FNDECL) \ 1956 (TARGET_OLDABI \ 1957 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \ 1958 : 0) 1959 1960/* Define this if it is the responsibility of the caller to 1961 allocate the area reserved for arguments passed in registers. 1962 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect 1963 of this macro is to determine whether the space is included in 1964 `current_function_outgoing_args_size'. */ 1965#define OUTGOING_REG_PARM_STACK_SPACE 1966 1967#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64) 1968 1969#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1970 1971/* Symbolic macros for the registers used to return integer and floating 1972 point values. */ 1973 1974#define GP_RETURN (GP_REG_FIRST + 2) 1975#define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0)) 1976 1977#define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8) 1978 1979/* Symbolic macros for the first/last argument registers. */ 1980 1981#define GP_ARG_FIRST (GP_REG_FIRST + 4) 1982#define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 1983#define FP_ARG_FIRST (FP_REG_FIRST + 12) 1984#define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 1985 1986#define LIBCALL_VALUE(MODE) \ 1987 mips_function_value (NULL_TREE, NULL, (MODE)) 1988 1989#define FUNCTION_VALUE(VALTYPE, FUNC) \ 1990 mips_function_value ((VALTYPE), (FUNC), VOIDmode) 1991 1992/* 1 if N is a possible register number for a function value. 1993 On the MIPS, R2 R3 and F0 F2 are the only register thus used. 1994 Currently, R2 and F0 are only implemented here (C has no complex type) */ 1995 1996#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \ 1997 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \ 1998 && (N) == FP_RETURN + 2)) 1999 2000/* 1 if N is a possible register number for function argument passing. 2001 We have no FP argument registers when soft-float. When FP registers 2002 are 32 bits, we can't directly reference the odd numbered ones. */ 2003 2004#define FUNCTION_ARG_REGNO_P(N) \ 2005 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \ 2006 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \ 2007 && !fixed_regs[N]) 2008 2009/* This structure has to cope with two different argument allocation 2010 schemes. Most MIPS ABIs view the arguments as a structure, of which 2011 the first N words go in registers and the rest go on the stack. If I 2012 < N, the Ith word might go in Ith integer argument register or in a 2013 floating-point register. For these ABIs, we only need to remember 2014 the offset of the current argument into the structure. 2015 2016 The EABI instead allocates the integer and floating-point arguments 2017 separately. The first N words of FP arguments go in FP registers, 2018 the rest go on the stack. Likewise, the first N words of the other 2019 arguments go in integer registers, and the rest go on the stack. We 2020 need to maintain three counts: the number of integer registers used, 2021 the number of floating-point registers used, and the number of words 2022 passed on the stack. 2023 2024 We could keep separate information for the two ABIs (a word count for 2025 the standard ABIs, and three separate counts for the EABI). But it 2026 seems simpler to view the standard ABIs as forms of EABI that do not 2027 allocate floating-point registers. 2028 2029 So for the standard ABIs, the first N words are allocated to integer 2030 registers, and function_arg decides on an argument-by-argument basis 2031 whether that argument should really go in an integer register, or in 2032 a floating-point one. */ 2033 2034typedef struct mips_args { 2035 /* Always true for varargs functions. Otherwise true if at least 2036 one argument has been passed in an integer register. */ 2037 int gp_reg_found; 2038 2039 /* The number of arguments seen so far. */ 2040 unsigned int arg_number; 2041 2042 /* The number of integer registers used so far. For all ABIs except 2043 EABI, this is the number of words that have been added to the 2044 argument structure, limited to MAX_ARGS_IN_REGISTERS. */ 2045 unsigned int num_gprs; 2046 2047 /* For EABI, the number of floating-point registers used so far. */ 2048 unsigned int num_fprs; 2049 2050 /* The number of words passed on the stack. */ 2051 unsigned int stack_words; 2052 2053 /* On the mips16, we need to keep track of which floating point 2054 arguments were passed in general registers, but would have been 2055 passed in the FP regs if this were a 32 bit function, so that we 2056 can move them to the FP regs if we wind up calling a 32 bit 2057 function. We record this information in fp_code, encoded in base 2058 four. A zero digit means no floating point argument, a one digit 2059 means an SFmode argument, and a two digit means a DFmode argument, 2060 and a three digit is not used. The low order digit is the first 2061 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by 2062 an SFmode argument. ??? A more sophisticated approach will be 2063 needed if MIPS_ABI != ABI_32. */ 2064 int fp_code; 2065 2066 /* True if the function has a prototype. */ 2067 int prototype; 2068} CUMULATIVE_ARGS; 2069 2070/* Initialize a variable CUM of type CUMULATIVE_ARGS 2071 for a call to a function whose data type is FNTYPE. 2072 For a library call, FNTYPE is 0. */ 2073 2074#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 2075 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \ 2076 2077/* Update the data in CUM to advance over an argument 2078 of mode MODE and data type TYPE. 2079 (TYPE is null for libcalls where that information may not be available.) */ 2080 2081#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 2082 function_arg_advance (&CUM, MODE, TYPE, NAMED) 2083 2084/* Determine where to put an argument to a function. 2085 Value is zero to push the argument on the stack, 2086 or a hard register in which to store the argument. 2087 2088 MODE is the argument's machine mode. 2089 TYPE is the data type of the argument (as a tree). 2090 This is null for libcalls where that information may 2091 not be available. 2092 CUM is a variable of type CUMULATIVE_ARGS which gives info about 2093 the preceding args and about the function being called. 2094 NAMED is nonzero if this argument is a named parameter 2095 (otherwise it is an extra parameter matching an ellipsis). */ 2096 2097#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 2098 function_arg( &CUM, MODE, TYPE, NAMED) 2099 2100#define FUNCTION_ARG_BOUNDARY function_arg_boundary 2101 2102#define FUNCTION_ARG_PADDING(MODE, TYPE) \ 2103 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward) 2104 2105#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 2106 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward) 2107 2108/* True if using EABI and varargs can be passed in floating-point 2109 registers. Under these conditions, we need a more complex form 2110 of va_list, which tracks GPR, FPR and stack arguments separately. */ 2111#define EABI_FLOAT_VARARGS_P \ 2112 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE) 2113 2114 2115/* Say that the epilogue uses the return address register. Note that 2116 in the case of sibcalls, the values "used by the epilogue" are 2117 considered live at the start of the called function. */ 2118#define EPILOGUE_USES(REGNO) ((REGNO) == 31) 2119 2120/* Treat LOC as a byte offset from the stack pointer and round it up 2121 to the next fully-aligned offset. */ 2122#define MIPS_STACK_ALIGN(LOC) \ 2123 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8) 2124 2125 2126/* Implement `va_start' for varargs and stdarg. */ 2127#define EXPAND_BUILTIN_VA_START(valist, nextarg) \ 2128 mips_va_start (valist, nextarg) 2129 2130/* Output assembler code to FILE to increment profiler label # LABELNO 2131 for profiling a function entry. */ 2132 2133#define FUNCTION_PROFILER(FILE, LABELNO) \ 2134{ \ 2135 if (TARGET_MIPS16) \ 2136 sorry ("mips16 function profiling"); \ 2137 fprintf (FILE, "\t.set\tnoat\n"); \ 2138 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \ 2139 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \ 2140 if (!TARGET_NEWABI) \ 2141 { \ 2142 fprintf (FILE, \ 2143 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \ 2144 TARGET_64BIT ? "dsubu" : "subu", \ 2145 reg_names[STACK_POINTER_REGNUM], \ 2146 reg_names[STACK_POINTER_REGNUM], \ 2147 Pmode == DImode ? 16 : 8); \ 2148 } \ 2149 fprintf (FILE, "\tjal\t_mcount\n"); \ 2150 fprintf (FILE, "\t.set\tat\n"); \ 2151} 2152 2153/* No mips port has ever used the profiler counter word, so don't emit it 2154 or the label for it. */ 2155 2156#define NO_PROFILE_COUNTERS 1 2157 2158/* Define this macro if the code for function profiling should come 2159 before the function prologue. Normally, the profiling code comes 2160 after. */ 2161 2162/* #define PROFILE_BEFORE_PROLOGUE */ 2163 2164/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 2165 the stack pointer does not matter. The value is tested only in 2166 functions that have frame pointers. 2167 No definition is equivalent to always zero. */ 2168 2169#define EXIT_IGNORE_STACK 1 2170 2171 2172/* A C statement to output, on the stream FILE, assembler code for a 2173 block of data that contains the constant parts of a trampoline. 2174 This code should not include a label--the label is taken care of 2175 automatically. */ 2176 2177#define TRAMPOLINE_TEMPLATE(STREAM) \ 2178{ \ 2179 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \ 2180 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \ 2181 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \ 2182 if (ptr_mode == DImode) \ 2183 { \ 2184 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \ 2185 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \ 2186 } \ 2187 else \ 2188 { \ 2189 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \ 2190 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \ 2191 } \ 2192 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \ 2193 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \ 2194 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \ 2195 if (ptr_mode == DImode) \ 2196 { \ 2197 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \ 2198 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \ 2199 } \ 2200 else \ 2201 { \ 2202 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \ 2203 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \ 2204 } \ 2205} 2206 2207/* A C expression for the size in bytes of the trampoline, as an 2208 integer. */ 2209 2210#define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2) 2211 2212/* Alignment required for trampolines, in bits. */ 2213 2214#define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode) 2215 2216/* INITIALIZE_TRAMPOLINE calls this library function to flush 2217 program and data caches. */ 2218 2219#ifndef CACHE_FLUSH_FUNC 2220#define CACHE_FLUSH_FUNC "_flush_cache" 2221#endif 2222 2223/* A C statement to initialize the variable parts of a trampoline. 2224 ADDR is an RTX for the address of the trampoline; FNADDR is an 2225 RTX for the address of the nested function; STATIC_CHAIN is an 2226 RTX for the static chain value that should be passed to the 2227 function when it is called. */ 2228 2229#define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \ 2230{ \ 2231 rtx func_addr, chain_addr; \ 2232 \ 2233 func_addr = plus_constant (ADDR, 32); \ 2234 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \ 2235 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \ 2236 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \ 2237 \ 2238 /* Flush both caches. We need to flush the data cache in case \ 2239 the system has a write-back cache. */ \ 2240 /* ??? Should check the return value for errors. */ \ 2241 if (mips_cache_flush_func && mips_cache_flush_func[0]) \ 2242 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \ 2243 0, VOIDmode, 3, ADDR, Pmode, \ 2244 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\ 2245 GEN_INT (3), TYPE_MODE (integer_type_node)); \ 2246} 2247 2248/* Addressing modes, and classification of registers for them. */ 2249 2250#define REGNO_OK_FOR_INDEX_P(REGNO) 0 2251#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 2252 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1) 2253 2254/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 2255 and check its validity for a certain class. 2256 We have two alternate definitions for each of them. 2257 The usual definition accepts all pseudo regs; the other rejects them all. 2258 The symbol REG_OK_STRICT causes the latter definition to be used. 2259 2260 Most source files want to accept pseudo regs in the hope that 2261 they will get allocated to the class that the insn wants them to be in. 2262 Some source files that are used after register allocation 2263 need to be strict. */ 2264 2265#ifndef REG_OK_STRICT 2266#define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2267 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0) 2268#else 2269#define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2270 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1) 2271#endif 2272 2273#define REG_OK_FOR_INDEX_P(X) 0 2274 2275 2276/* Maximum number of registers that can appear in a valid memory address. */ 2277 2278#define MAX_REGS_PER_ADDRESS 1 2279 2280#ifdef REG_OK_STRICT 2281#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 2282{ \ 2283 if (mips_legitimate_address_p (MODE, X, 1)) \ 2284 goto ADDR; \ 2285} 2286#else 2287#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 2288{ \ 2289 if (mips_legitimate_address_p (MODE, X, 0)) \ 2290 goto ADDR; \ 2291} 2292#endif 2293 2294/* Check for constness inline but use mips_legitimate_address_p 2295 to check whether a constant really is an address. */ 2296 2297#define CONSTANT_ADDRESS_P(X) \ 2298 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0)) 2299 2300#define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0) 2301 2302#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 2303 do { \ 2304 if (mips_legitimize_address (&(X), MODE)) \ 2305 goto WIN; \ 2306 } while (0) 2307 2308 2309/* A C statement or compound statement with a conditional `goto 2310 LABEL;' executed if memory address X (an RTX) can have different 2311 meanings depending on the machine mode of the memory reference it 2312 is used for. 2313 2314 Autoincrement and autodecrement addresses typically have 2315 mode-dependent effects because the amount of the increment or 2316 decrement is the size of the operand being addressed. Some 2317 machines have other mode-dependent addresses. Many RISC machines 2318 have no mode-dependent addresses. 2319 2320 You may assume that ADDR is a valid address for the machine. */ 2321 2322#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {} 2323 2324/* This handles the magic '..CURRENT_FUNCTION' symbol, which means 2325 'the start of the function that this code is output in'. */ 2326 2327#define ASM_OUTPUT_LABELREF(FILE,NAME) \ 2328 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \ 2329 asm_fprintf ((FILE), "%U%s", \ 2330 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \ 2331 else \ 2332 asm_fprintf ((FILE), "%U%s", (NAME)) 2333 2334/* Flag to mark a function decl symbol that requires a long call. */ 2335#define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0) 2336#define SYMBOL_REF_LONG_CALL_P(X) \ 2337 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0) 2338 2339/* Specify the machine mode that this machine uses 2340 for the index in the tablejump instruction. 2341 ??? Using HImode in mips16 mode can cause overflow. */ 2342#define CASE_VECTOR_MODE \ 2343 (TARGET_MIPS16 ? HImode : ptr_mode) 2344 2345/* Define as C expression which evaluates to nonzero if the tablejump 2346 instruction expects the table to contain offsets from the address of the 2347 table. 2348 Do not define this if the table should contain absolute addresses. */ 2349#define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16) 2350 2351/* Define this as 1 if `char' should by default be signed; else as 0. */ 2352#ifndef DEFAULT_SIGNED_CHAR 2353#define DEFAULT_SIGNED_CHAR 1 2354#endif 2355 2356/* Max number of bytes we can move from memory to memory 2357 in one reasonably fast instruction. */ 2358#define MOVE_MAX (TARGET_64BIT ? 8 : 4) 2359#define MAX_MOVE_MAX 8 2360 2361/* Define this macro as a C expression which is nonzero if 2362 accessing less than a word of memory (i.e. a `char' or a 2363 `short') is no faster than accessing a word of memory, i.e., if 2364 such access require more than one instruction or if there is no 2365 difference in cost between byte and (aligned) word loads. 2366 2367 On RISC machines, it tends to generate better code to define 2368 this as 1, since it avoids making a QI or HI mode register. */ 2369#define SLOW_BYTE_ACCESS 1 2370 2371/* Define this to be nonzero if shift instructions ignore all but the low-order 2372 few bits. */ 2373#define SHIFT_COUNT_TRUNCATED 1 2374 2375/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2376 is done just by pretending it is already truncated. */ 2377#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \ 2378 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1) 2379 2380 2381/* Specify the machine mode that pointers have. 2382 After generation of rtl, the compiler makes no further distinction 2383 between pointers and any other objects of this machine mode. */ 2384 2385#ifndef Pmode 2386#define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode) 2387#endif 2388 2389/* Give call MEMs SImode since it is the "most permissive" mode 2390 for both 32-bit and 64-bit targets. */ 2391 2392#define FUNCTION_MODE SImode 2393 2394 2395/* The cost of loading values from the constant pool. It should be 2396 larger than the cost of any constant we want to synthesize in-line. */ 2397 2398#define CONSTANT_POOL_COST COSTS_N_INSNS (8) 2399 2400/* A C expression for the cost of moving data from a register in 2401 class FROM to one in class TO. The classes are expressed using 2402 the enumeration values such as `GENERAL_REGS'. A value of 2 is 2403 the default; other values are interpreted relative to that. 2404 2405 It is not required that the cost always equal 2 when FROM is the 2406 same as TO; on some machines it is expensive to move between 2407 registers if they are not general registers. 2408 2409 If reload sees an insn consisting of a single `set' between two 2410 hard registers, and if `REGISTER_MOVE_COST' applied to their 2411 classes returns a value of 2, reload does not check to ensure 2412 that the constraints of the insn are met. Setting a cost of 2413 other than 2 will allow reload to verify that the constraints are 2414 met. You should do this if the `movM' pattern's constraints do 2415 not allow such copying. */ 2416 2417#define REGISTER_MOVE_COST(MODE, FROM, TO) \ 2418 mips_register_move_cost (MODE, FROM, TO) 2419 2420#define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \ 2421 (mips_cost->memory_latency \ 2422 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P))) 2423 2424/* Define if copies to/from condition code registers should be avoided. 2425 2426 This is needed for the MIPS because reload_outcc is not complete; 2427 it needs to handle cases where the source is a general or another 2428 condition code register. */ 2429#define AVOID_CCMODE_COPIES 2430 2431/* A C expression for the cost of a branch instruction. A value of 2432 1 is the default; other values are interpreted relative to that. */ 2433 2434#define BRANCH_COST mips_cost->branch_cost 2435#define LOGICAL_OP_NON_SHORT_CIRCUIT 0 2436 2437/* If defined, modifies the length assigned to instruction INSN as a 2438 function of the context in which it is used. LENGTH is an lvalue 2439 that contains the initially computed length of the insn and should 2440 be updated with the correct length of the insn. */ 2441#define ADJUST_INSN_LENGTH(INSN, LENGTH) \ 2442 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH))) 2443 2444/* Control the assembler format that we output. */ 2445 2446/* Output to assembler file text saying following lines 2447 may contain character constants, extra white space, comments, etc. */ 2448 2449#ifndef ASM_APP_ON 2450#define ASM_APP_ON " #APP\n" 2451#endif 2452 2453/* Output to assembler file text saying following lines 2454 no longer contain unusual constructs. */ 2455 2456#ifndef ASM_APP_OFF 2457#define ASM_APP_OFF " #NO_APP\n" 2458#endif 2459 2460#define REGISTER_NAMES \ 2461{ "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \ 2462 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ 2463 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ 2464 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \ 2465 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \ 2466 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ 2467 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \ 2468 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \ 2469 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \ 2470 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \ 2471 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \ 2472 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \ 2473 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \ 2474 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \ 2475 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \ 2476 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \ 2477 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \ 2478 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \ 2479 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \ 2480 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \ 2481 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \ 2482 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \ 2483 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \ 2484 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" } 2485 2486/* List the "software" names for each register. Also list the numerical 2487 names for $fp and $sp. */ 2488 2489#define ADDITIONAL_REGISTER_NAMES \ 2490{ \ 2491 { "$29", 29 + GP_REG_FIRST }, \ 2492 { "$30", 30 + GP_REG_FIRST }, \ 2493 { "at", 1 + GP_REG_FIRST }, \ 2494 { "v0", 2 + GP_REG_FIRST }, \ 2495 { "v1", 3 + GP_REG_FIRST }, \ 2496 { "a0", 4 + GP_REG_FIRST }, \ 2497 { "a1", 5 + GP_REG_FIRST }, \ 2498 { "a2", 6 + GP_REG_FIRST }, \ 2499 { "a3", 7 + GP_REG_FIRST }, \ 2500 { "t0", 8 + GP_REG_FIRST }, \ 2501 { "t1", 9 + GP_REG_FIRST }, \ 2502 { "t2", 10 + GP_REG_FIRST }, \ 2503 { "t3", 11 + GP_REG_FIRST }, \ 2504 { "t4", 12 + GP_REG_FIRST }, \ 2505 { "t5", 13 + GP_REG_FIRST }, \ 2506 { "t6", 14 + GP_REG_FIRST }, \ 2507 { "t7", 15 + GP_REG_FIRST }, \ 2508 { "s0", 16 + GP_REG_FIRST }, \ 2509 { "s1", 17 + GP_REG_FIRST }, \ 2510 { "s2", 18 + GP_REG_FIRST }, \ 2511 { "s3", 19 + GP_REG_FIRST }, \ 2512 { "s4", 20 + GP_REG_FIRST }, \ 2513 { "s5", 21 + GP_REG_FIRST }, \ 2514 { "s6", 22 + GP_REG_FIRST }, \ 2515 { "s7", 23 + GP_REG_FIRST }, \ 2516 { "t8", 24 + GP_REG_FIRST }, \ 2517 { "t9", 25 + GP_REG_FIRST }, \ 2518 { "k0", 26 + GP_REG_FIRST }, \ 2519 { "k1", 27 + GP_REG_FIRST }, \ 2520 { "gp", 28 + GP_REG_FIRST }, \ 2521 { "sp", 29 + GP_REG_FIRST }, \ 2522 { "fp", 30 + GP_REG_FIRST }, \ 2523 { "ra", 31 + GP_REG_FIRST }, \ 2524 ALL_COP_ADDITIONAL_REGISTER_NAMES \ 2525} 2526 2527/* This is meant to be redefined in the host dependent files. It is a 2528 set of alternative names and regnums for mips coprocessors. */ 2529 2530#define ALL_COP_ADDITIONAL_REGISTER_NAMES 2531 2532/* A C compound statement to output to stdio stream STREAM the 2533 assembler syntax for an instruction operand X. X is an RTL 2534 expression. 2535 2536 CODE is a value that can be used to specify one of several ways 2537 of printing the operand. It is used when identical operands 2538 must be printed differently depending on the context. CODE 2539 comes from the `%' specification that was used to request 2540 printing of the operand. If the specification was just `%DIGIT' 2541 then CODE is 0; if the specification was `%LTR DIGIT' then CODE 2542 is the ASCII code for LTR. 2543 2544 If X is a register, this macro should print the register's name. 2545 The names can be found in an array `reg_names' whose type is 2546 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. 2547 2548 When the machine description has a specification `%PUNCT' (a `%' 2549 followed by a punctuation character), this macro is called with 2550 a null pointer for X and the punctuation character for CODE. 2551 2552 See mips.c for the MIPS specific codes. */ 2553 2554#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2555 2556/* A C expression which evaluates to true if CODE is a valid 2557 punctuation character for use in the `PRINT_OPERAND' macro. If 2558 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no 2559 punctuation characters (except for the standard one, `%') are 2560 used in this way. */ 2561 2562#define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE] 2563 2564/* A C compound statement to output to stdio stream STREAM the 2565 assembler syntax for an instruction operand that is a memory 2566 reference whose address is ADDR. ADDR is an RTL expression. */ 2567 2568#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 2569 2570 2571/* A C statement, to be executed after all slot-filler instructions 2572 have been output. If necessary, call `dbr_sequence_length' to 2573 determine the number of slots filled in a sequence (zero if not 2574 currently outputting a sequence), to decide how many no-ops to 2575 output, or whatever. 2576 2577 Don't define this macro if it has nothing to do, but it is 2578 helpful in reading assembly output if the extent of the delay 2579 sequence is made explicit (e.g. with white space). 2580 2581 Note that output routines for instructions with delay slots must 2582 be prepared to deal with not being output as part of a sequence 2583 (i.e. when the scheduling pass is not run, or when no slot 2584 fillers could be found.) The variable `final_sequence' is null 2585 when not processing a sequence, otherwise it contains the 2586 `sequence' rtx being output. */ 2587 2588#define DBR_OUTPUT_SEQEND(STREAM) \ 2589do \ 2590 { \ 2591 if (set_nomacro > 0 && --set_nomacro == 0) \ 2592 fputs ("\t.set\tmacro\n", STREAM); \ 2593 \ 2594 if (set_noreorder > 0 && --set_noreorder == 0) \ 2595 fputs ("\t.set\treorder\n", STREAM); \ 2596 \ 2597 fputs ("\n", STREAM); \ 2598 } \ 2599while (0) 2600 2601 2602/* How to tell the debugger about changes of source files. */ 2603#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \ 2604 mips_output_filename (STREAM, NAME) 2605 2606/* mips-tfile does not understand .stabd directives. */ 2607#define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \ 2608 dbxout_begin_stabn_sline (LINE); \ 2609 dbxout_stab_value_internal_label ("LM", &COUNTER); \ 2610} while (0) 2611 2612/* Use .loc directives for SDB line numbers. */ 2613#define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \ 2614 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE) 2615 2616/* The MIPS implementation uses some labels for its own purpose. The 2617 following lists what labels are created, and are all formed by the 2618 pattern $L[a-z].*. The machine independent portion of GCC creates 2619 labels matching: $L[A-Z][0-9]+ and $L[0-9]+. 2620 2621 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt. 2622 $Lb[0-9]+ Begin blocks for MIPS debug support 2623 $Lc[0-9]+ Label for use in s<xx> operation. 2624 $Le[0-9]+ End blocks for MIPS debug support */ 2625 2626#undef ASM_DECLARE_OBJECT_NAME 2627#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ 2628 mips_declare_object (STREAM, NAME, "", ":\n", 0) 2629 2630/* Globalizing directive for a label. */ 2631#define GLOBAL_ASM_OP "\t.globl\t" 2632 2633/* This says how to define a global common symbol. */ 2634 2635#define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common 2636 2637/* This says how to define a local common symbol (i.e., not visible to 2638 linker). */ 2639 2640#ifndef ASM_OUTPUT_ALIGNED_LOCAL 2641#define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \ 2642 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false) 2643#endif 2644 2645/* This says how to output an external. It would be possible not to 2646 output anything and let undefined symbol become external. However 2647 the assembler uses length information on externals to allocate in 2648 data/sdata bss/sbss, thereby saving exec time. */ 2649 2650#define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \ 2651 mips_output_external(STREAM,DECL,NAME) 2652 2653/* This is how to declare a function name. The actual work of 2654 emitting the label is moved to function_prologue, so that we can 2655 get the line number correctly emitted before the .ent directive, 2656 and after any .file directives. Define as empty so that the function 2657 is not declared before the .ent directive elsewhere. */ 2658 2659#undef ASM_DECLARE_FUNCTION_NAME 2660#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) 2661 2662#ifndef FUNCTION_NAME_ALREADY_DECLARED 2663#define FUNCTION_NAME_ALREADY_DECLARED 0 2664#endif 2665 2666/* This is how to store into the string LABEL 2667 the symbol_ref name of an internal numbered label where 2668 PREFIX is the class of label and NUM is the number within the class. 2669 This is suitable for output with `assemble_name'. */ 2670 2671#undef ASM_GENERATE_INTERNAL_LABEL 2672#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 2673 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) 2674 2675/* This is how to output an element of a case-vector that is absolute. */ 2676 2677#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 2678 fprintf (STREAM, "\t%s\t%sL%d\n", \ 2679 ptr_mode == DImode ? ".dword" : ".word", \ 2680 LOCAL_LABEL_PREFIX, \ 2681 VALUE) 2682 2683/* This is how to output an element of a case-vector. We can make the 2684 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word 2685 is supported. */ 2686 2687#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 2688do { \ 2689 if (TARGET_MIPS16) \ 2690 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \ 2691 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \ 2692 else if (TARGET_GPWORD) \ 2693 fprintf (STREAM, "\t%s\t%sL%d\n", \ 2694 ptr_mode == DImode ? ".gpdword" : ".gpword", \ 2695 LOCAL_LABEL_PREFIX, VALUE); \ 2696 else \ 2697 fprintf (STREAM, "\t%s\t%sL%d\n", \ 2698 ptr_mode == DImode ? ".dword" : ".word", \ 2699 LOCAL_LABEL_PREFIX, VALUE); \ 2700} while (0) 2701 2702/* When generating MIPS16 code, we want the jump table to be in the text 2703 section so that we can load its address using a PC-relative addition. */ 2704#define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16 2705 2706/* This is how to output an assembler line 2707 that says to advance the location counter 2708 to a multiple of 2**LOG bytes. */ 2709 2710#define ASM_OUTPUT_ALIGN(STREAM,LOG) \ 2711 fprintf (STREAM, "\t.align\t%d\n", (LOG)) 2712 2713/* This is how to output an assembler line to advance the location 2714 counter by SIZE bytes. */ 2715 2716#undef ASM_OUTPUT_SKIP 2717#define ASM_OUTPUT_SKIP(STREAM,SIZE) \ 2718 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 2719 2720/* This is how to output a string. */ 2721#undef ASM_OUTPUT_ASCII 2722#define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \ 2723 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t") 2724 2725/* Output #ident as a in the read-only data section. */ 2726#undef ASM_OUTPUT_IDENT 2727#define ASM_OUTPUT_IDENT(FILE, STRING) \ 2728{ \ 2729 const char *p = STRING; \ 2730 int size = strlen (p) + 1; \ 2731 readonly_data_section (); \ 2732 assemble_string (p, size); \ 2733} 2734 2735/* Default to -G 8 */ 2736#ifndef MIPS_DEFAULT_GVALUE 2737#define MIPS_DEFAULT_GVALUE 8 2738#endif 2739 2740/* Define the strings to put out for each section in the object file. */ 2741#define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ 2742#define DATA_SECTION_ASM_OP "\t.data" /* large data */ 2743#define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */ 2744 2745#undef READONLY_DATA_SECTION_ASM_OP 2746#define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */ 2747 2748#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ 2749do \ 2750 { \ 2751 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \ 2752 TARGET_64BIT ? "dsubu" : "subu", \ 2753 reg_names[STACK_POINTER_REGNUM], \ 2754 reg_names[STACK_POINTER_REGNUM], \ 2755 TARGET_64BIT ? "sd" : "sw", \ 2756 reg_names[REGNO], \ 2757 reg_names[STACK_POINTER_REGNUM]); \ 2758 } \ 2759while (0) 2760 2761#define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ 2762do \ 2763 { \ 2764 if (! set_noreorder) \ 2765 fprintf (STREAM, "\t.set\tnoreorder\n"); \ 2766 \ 2767 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \ 2768 TARGET_64BIT ? "ld" : "lw", \ 2769 reg_names[REGNO], \ 2770 reg_names[STACK_POINTER_REGNUM], \ 2771 TARGET_64BIT ? "daddu" : "addu", \ 2772 reg_names[STACK_POINTER_REGNUM], \ 2773 reg_names[STACK_POINTER_REGNUM]); \ 2774 \ 2775 if (! set_noreorder) \ 2776 fprintf (STREAM, "\t.set\treorder\n"); \ 2777 } \ 2778while (0) 2779 2780/* How to start an assembler comment. 2781 The leading space is important (the mips native assembler requires it). */ 2782#ifndef ASM_COMMENT_START 2783#define ASM_COMMENT_START " #" 2784#endif 2785 2786/* Default definitions for size_t and ptrdiff_t. We must override the 2787 definitions from ../svr4.h on mips-*-linux-gnu. */ 2788 2789#undef SIZE_TYPE 2790#define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") 2791 2792#undef PTRDIFF_TYPE 2793#define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int") 2794 2795#ifndef __mips16 2796/* Since the bits of the _init and _fini function is spread across 2797 many object files, each potentially with its own GP, we must assume 2798 we need to load our GP. We don't preserve $gp or $ra, since each 2799 init/fini chunk is supposed to initialize $gp, and crti/crtn 2800 already take care of preserving $ra and, when appropriate, $gp. */ 2801#if (defined _ABIO32 && _MIPS_SIM == _ABIO32) 2802#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2803 asm (SECTION_OP "\n\ 2804 .set noreorder\n\ 2805 bal 1f\n\ 2806 nop\n\ 28071: .cpload $31\n\ 2808 .set reorder\n\ 2809 jal " USER_LABEL_PREFIX #FUNC "\n\ 2810 " TEXT_SECTION_ASM_OP); 2811#endif /* Switch to #elif when we're no longer limited by K&R C. */ 2812#if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \ 2813 || (defined _ABI64 && _MIPS_SIM == _ABI64) 2814#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2815 asm (SECTION_OP "\n\ 2816 .set noreorder\n\ 2817 bal 1f\n\ 2818 nop\n\ 28191: .set reorder\n\ 2820 .cpsetup $31, $2, 1b\n\ 2821 jal " USER_LABEL_PREFIX #FUNC "\n\ 2822 " TEXT_SECTION_ASM_OP); 2823#endif 2824#endif 2825 2826#ifndef HAVE_AS_TLS 2827#define HAVE_AS_TLS 0 2828#endif 2829