1/* Definitions of target machine for GNU compiler, 2 for m68k (including m68010) NetBSD platforms using the 3 ELF object format. 4 Copyright (C) 2002, 2003, 2004 Free Software Foundation, Inc. 5 Contributed by Wasabi Systems. Inc. 6 7 This file is derived from <m68k/m68kv4.h>, <m68k/m68kelf.h>, 8 and <m68k/linux.h>. 9 10This file is part of GCC. 11 12GCC is free software; you can redistribute it and/or modify 13it under the terms of the GNU General Public License as published by 14the Free Software Foundation; either version 2, or (at your option) 15any later version. 16 17GCC is distributed in the hope that it will be useful, 18but WITHOUT ANY WARRANTY; without even the implied warranty of 19MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20GNU General Public License for more details. 21 22You should have received a copy of the GNU General Public License 23along with GCC; see the file COPYING. If not, write to 24the Free Software Foundation, 51 Franklin Street, Fifth Floor, 25Boston, MA 02110-1301, USA. */ 26 27#define TARGET_OS_CPP_BUILTINS() \ 28 do \ 29 { \ 30 NETBSD_OS_CPP_BUILTINS_ELF(); \ 31 builtin_define ("__m68k__"); \ 32 builtin_define ("__SVR4_ABI__"); \ 33 builtin_define ("__motorola__"); \ 34 } \ 35 while (0) 36 37/* Default target comes from config.gcc */ 38#undef TARGET_DEFAULT 39#define TARGET_DEFAULT TARGET_CPU_DEFAULT 40 41 42/* Don't try using XFmode on the 68010. */ 43#undef LONG_DOUBLE_TYPE_SIZE 44#define LONG_DOUBLE_TYPE_SIZE \ 45 ((TARGET_68020 || TARGET_68040 || TARGET_68040_ONLY || \ 46 TARGET_68060) ? 80 : 64) 47 48#ifdef __mc68010__ 49#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 50#else 51#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80 52#endif 53 54#define EXTRA_SPECS \ 55 { "cpp_cpu_default_spec", CPP_CPU_DEFAULT_SPEC }, \ 56 { "cpp_cpu_spec", CPP_CPU_SPEC }, \ 57 { "cpp_fpu_spec", CPP_FPU_SPEC }, \ 58 { "asm_default_spec", ASM_DEFAULT_SPEC }, \ 59 { "netbsd_cpp_spec", NETBSD_CPP_SPEC }, \ 60 { "netbsd_entry_point", NETBSD_ENTRY_POINT }, 61 62 63#define CPP_CPU_SPEC \ 64 "%{m68010:-D__mc68010__} \ 65 %{m68020:-D__mc68020__} \ 66 %{m68030:-D__mc68030__} \ 67 %{m68040:-D__mc68040__} \ 68 %(cpp_cpu_default_spec)" 69 70 71#undef TARGET_VERSION 72#if TARGET_DEFAULT & MASK_68020 73#define TARGET_VERSION fprintf (stderr, " (NetBSD/m68k ELF)"); 74#define CPP_CPU_DEFAULT_SPEC "%{!m680*:-D__mc68020__}" 75#define ASM_DEFAULT_SPEC "%{!m680*:-m68020}" 76#else 77#define TARGET_VERSION fprintf (stderr, " (NetBSD/68010 ELF)"); 78#define CPP_CPU_DEFAULT_SPEC "%{!m680*:-D__mc68010__}" 79#define ASM_DEFAULT_SPEC "%{!m680*:-m68010}" 80#endif 81 82 83#if TARGET_DEFAULT & MASK_68881 84#define CPP_FPU_SPEC "%{!msoft-float:-D__HAVE_68881__ -D__HAVE_FPU__}" 85#else 86#define CPP_FPU_SPEC "%{m68881:-D__HAVE_68881__ -D__HAVE_FPU__}" 87#endif 88 89 90/* Provide a CPP_SPEC appropriate for NetBSD m68k targets. Currently we 91 deal with the GCC option '-posix', as well as an indication as to 92 whether or not use of the FPU is allowed. */ 93 94#undef CPP_SPEC 95#define CPP_SPEC \ 96 "%(netbsd_cpp_spec) %(cpp_cpu_spec) %(cpp_fpu_spec)" 97 98 99/* Provide an ASM_SPEC appropriate for NetBSD m68k ELF targets. We pass 100 on some CPU options, as well as PIC code generation options. */ 101 102#undef ASM_SPEC 103#define ASM_SPEC \ 104 "%(asm_default_spec) \ 105 %{m68010} %{m68020} %{m68030} %{m68040} %{m68060} \ 106 %{fpic|fpie:-k} %{fPIC|fPIE:-k -K}" 107 108#define AS_NEEDS_DASH_FOR_PIPED_INPUT 109 110/* Provide a LINK_SPEC appropriate for a NetBSD/m68k ELF target. */ 111 112#undef LINK_SPEC 113#define LINK_SPEC NETBSD_LINK_SPEC_ELF 114 115#define NETBSD_ENTRY_POINT "_start" 116 117/* Output assembler code to FILE to increment profiler label # LABELNO 118 for profiling a function only. */ 119 120#undef FUNCTION_PROFILER 121#define FUNCTION_PROFILER(FILE, LABELNO) \ 122do \ 123 { \ 124 asm_fprintf (FILE, "\tlea (%LLP%d,%Rpc),%Ra1\n", (LABELNO)); \ 125 if (flag_pic) \ 126 fprintf (FILE, "\tbsr.l __mcount@PLTPC\n"); \ 127 else \ 128 fprintf (FILE, "\tjbsr __mcount\n"); \ 129 } \ 130while (0) 131 132 133/* Make gcc agree with <machine/ansi.h> */ 134 135#undef SIZE_TYPE 136#define SIZE_TYPE "unsigned int" 137 138#undef PTRDIFF_TYPE 139#define PTRDIFF_TYPE "int" 140 141 142/* XXX 143 Here is a bunch of stuff lifted from m68kelf.h. We don't use that 144 file directly, because it has a lot of baggage we don't want. */ 145 146 147/* The prefix for register names. Note that REGISTER_NAMES 148 is supposed to include this prefix. Also note that this is NOT an 149 fprintf format string, it is a literal string. */ 150 151#undef REGISTER_PREFIX 152#define REGISTER_PREFIX "%" 153 154 155/* The prefix for local (compiler generated) lables. 156 These labels will not appear in the symbol table. */ 157 158#undef LOCAL_LABEL_PREFIX 159#define LOCAL_LABEL_PREFIX "." 160 161 162/* The prefix to add to user-visible assembler symbols. */ 163 164#undef USER_LABEL_PREFIX 165#define USER_LABEL_PREFIX "" 166 167 168/* The prefix for immediate operands. */ 169 170#undef IMMEDIATE_PREFIX 171#define IMMEDIATE_PREFIX "#" 172 173 174#undef ASM_COMMENT_START 175#define ASM_COMMENT_START "|" 176 177 178/* Currently, JUMP_TABLES_IN_TEXT_SECTION must be defined in order to 179 keep switch tables in the text section. */ 180 181#undef JUMP_TABLES_IN_TEXT_SECTION 182#define JUMP_TABLES_IN_TEXT_SECTION 1 183 184 185/* Use the default action for outputting the case label. */ 186#undef ASM_OUTPUT_CASE_LABEL 187#define ASM_RETURN_CASE_JUMP \ 188 do { \ 189 if (TARGET_COLDFIRE) \ 190 { \ 191 if (ADDRESS_REG_P (operands[0])) \ 192 return "jmp %%pc@(2,%0:l)"; \ 193 else \ 194 return "ext%.l %0\n\tjmp %%pc@(2,%0:l)"; \ 195 } \ 196 else \ 197 return "jmp %%pc@(2,%0:w)"; \ 198 } while (0) 199 200 201/* This is how to output an assembler line that says to advance the 202 location counter to a multiple of 2**LOG bytes. */ 203 204#undef ASM_OUTPUT_ALIGN 205#define ASM_OUTPUT_ALIGN(FILE,LOG) \ 206do \ 207 { \ 208 if ((LOG) > 0) \ 209 fprintf ((FILE), "%s%u\n", ALIGN_ASM_OP, 1 << (LOG)); \ 210 } \ 211while (0) 212 213 214/* If defined, a C expression whose value is a string containing the 215 assembler operation to identify the following data as uninitialized global 216 data. */ 217 218#define BSS_SECTION_ASM_OP ".section\t.bss" 219 220 221/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a 222 separate, explicit argument. If you define this macro, it is used 223 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in 224 handling the required alignment of the variable. The alignment is 225 specified as the number of bits. 226 227 Try to use function `asm_output_aligned_bss' defined in file 228 `varasm.c' when defining this macro. */ 229 230#undef ASM_OUTPUT_ALIGNED_BSS 231#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 232 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) 233 234 235#undef ASM_OUTPUT_COMMON 236#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 237( fputs (".comm ", (FILE)), \ 238 assemble_name ((FILE), (NAME)), \ 239 fprintf ((FILE), ",%u\n", (int)(SIZE))) 240 241#undef ASM_OUTPUT_LOCAL 242#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 243( fputs (".lcomm ", (FILE)), \ 244 assemble_name ((FILE), (NAME)), \ 245 fprintf ((FILE), ",%u\n", (int)(SIZE))) 246 247 248/* XXX 249 This is the end of the chunk lifted from m68kelf.h */ 250 251 252/* XXX 253 The following chunk is more or less lifted from m68kv4.h. 254 We'd like to just #include that file, but it has not yet 255 been converted to the new include style. 256 257 Should there be a m68kv4-abi.h ?? */ 258 259 260/* Register in which address to store a structure value is passed to a 261 function. The default in m68k.h is a1. For m68k/SVR4 it is a0. */ 262 263#undef M68K_STRUCT_VALUE_REGNUM 264#define M68K_STRUCT_VALUE_REGNUM 8 265 266 267/* Register in which static-chain is passed to a function. The 268 default isn m68k.h is a0, but that is already the struct value 269 regnum. Make it a1 instead. */ 270 271#undef STATIC_CHAIN_REGNUM 272#define STATIC_CHAIN_REGNUM 9 273 274 275/* Now to renumber registers for dbx and gdb. 276 We use the Sun-3 convention, which is: 277 floating point registers have numbers 18 to 25, not 278 16 to 23 as they do in the compiler. */ 279 280#undef DBX_REGISTER_NUMBER 281#define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2) 282 283 284/* 1 if N is a possible register number for a function value. For 285 m68k/SVR4 allow d0, a0, or fp0 as return registers, for integral, 286 pointer, or floating types, respectively. Reject fp0 if not using 287 a 68881 coprocessor. */ 288 289#undef FUNCTION_VALUE_REGNO_P 290#define FUNCTION_VALUE_REGNO_P(N) \ 291 ((N) == 0 || (N) == 8 || (TARGET_68881 && (N) == 16)) 292 293 294/* Define this to be true when FUNCTION_VALUE_REGNO_P is true for 295 more than one register. */ 296 297#undef NEEDS_UNTYPED_CALL 298#define NEEDS_UNTYPED_CALL 1 299 300 301/* Define how to generate (in the callee) the output value of a 302 function and how to find (in the caller) the value returned by a 303 function. VALTYPE is the data type of the value (as a tree). If 304 the precise function being called is known, FUNC is its 305 FUNCTION_DECL; otherwise, FUNC is 0. For m68k/SVR4 generate the 306 result in d0, a0, or fp0 as appropriate. */ 307 308#undef FUNCTION_VALUE 309#define FUNCTION_VALUE(VALTYPE, FUNC) \ 310 (TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_68881 \ 311 ? gen_rtx_REG (TYPE_MODE (VALTYPE), 16) \ 312 : (POINTER_TYPE_P (VALTYPE) \ 313 ? gen_rtx_REG (TYPE_MODE (VALTYPE), 8) \ 314 : gen_rtx_REG (TYPE_MODE (VALTYPE), 0))) 315 316 317/* For compatibility with the large body of existing code which does 318 not always properly declare external functions returning pointer 319 types, the m68k/SVR4 convention is to copy the value returned for 320 pointer functions from a0 to d0 in the function epilogue, so that 321 callers that have neglected to properly declare the callee can 322 still find the correct return value. */ 323 324extern int current_function_returns_pointer; 325#define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) \ 326do \ 327 { \ 328 if (current_function_returns_pointer \ 329 && ! find_equiv_reg (0, get_last_insn (), 0, 0, 0, 8, Pmode)) \ 330 asm_fprintf (FILE, "\tmove.l %Ra0,%Rd0\n"); \ 331 } \ 332while (0) 333 334 335/* Define how to find the value returned by a library function 336 assuming the value has mode MODE. 337 For m68k/SVR4 look for integer values in d0, pointer values in d0 338 (returned in both d0 and a0), and floating values in fp0. */ 339 340#undef LIBCALL_VALUE 341#define LIBCALL_VALUE(MODE) \ 342 ((((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode) \ 343 && TARGET_68881) \ 344 ? gen_rtx_REG (MODE, 16) \ 345 : gen_rtx_REG (MODE, 0)) 346 347 348/* Boundary (in *bits*) on which stack pointer should be aligned. 349 The m68k/SVR4 convention is to keep the stack pointer longword aligned. */ 350 351#undef STACK_BOUNDARY 352#define STACK_BOUNDARY 32 353 354 355/* Alignment of field after `int : 0' in a structure. 356 For m68k/SVR4, this is the next longword boundary. */ 357 358#undef EMPTY_FIELD_BOUNDARY 359#define EMPTY_FIELD_BOUNDARY 32 360 361 362/* No data type wants to be aligned rounder than this. 363 For m68k/SVR4, some types (doubles for example) are aligned on 8 byte 364 boundaries */ 365 366#undef BIGGEST_ALIGNMENT 367#define BIGGEST_ALIGNMENT 64 368 369 370/* For m68k SVR4, structures are returned using the reentrant 371 technique. */ 372 373#undef PCC_STATIC_STRUCT_RETURN 374 375 376/* The svr4 ABI for the m68k says that records and unions are returned 377 in memory. */ 378 379#undef DEFAULT_PCC_STRUCT_RETURN 380#define DEFAULT_PCC_STRUCT_RETURN 1 381 382/* Output assembler code for a block containing the constant parts 383 of a trampoline, leaving space for the variable parts. */ 384 385/* On m68k svr4, the trampoline is different from the generic version 386 in that we use a1 as the static call chain. */ 387 388#undef TRAMPOLINE_TEMPLATE 389#define TRAMPOLINE_TEMPLATE(FILE) \ 390{ \ 391 assemble_aligned_integer (2, GEN_INT (0x227a)); \ 392 assemble_aligned_integer (2, GEN_INT (8)); \ 393 assemble_aligned_integer (2, GEN_INT (0x2f3a)); \ 394 assemble_aligned_integer (2, GEN_INT (8)); \ 395 assemble_aligned_integer (2, GEN_INT (0x4e75)); \ 396 assemble_aligned_integer (4, const0_rtx); \ 397 assemble_aligned_integer (4, const0_rtx); \ 398} 399 400/* Redefine since we are using a different trampoline */ 401#undef TRAMPOLINE_SIZE 402#define TRAMPOLINE_SIZE 18 403 404/* Emit RTL insns to initialize the variable parts of a trampoline. 405 FNADDR is an RTX for the address of the function's pure code. 406 CXT is an RTX for the static chain value for the function. */ 407 408#undef INITIALIZE_TRAMPOLINE 409#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 410{ \ 411 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 10)), CXT); \ 412 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 14)), FNADDR); \ 413} 414 415 416/* XXX 417 This is the end of the chunk lifted from m68kv4.h */ 418