1/* Definitions of target machine for GCC for IA-32. 2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. 4 5This file is part of GCC. 6 7GCC is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 2, or (at your option) 10any later version. 11 12GCC is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with GCC; see the file COPYING. If not, write to 19the Free Software Foundation, 51 Franklin Street, Fifth Floor, 20Boston, MA 02110-1301, USA. */ 21 22/* The purpose of this file is to define the characteristics of the i386, 23 independent of assembler syntax or operating system. 24 25 Three other files build on this one to describe a specific assembler syntax: 26 bsd386.h, att386.h, and sun386.h. 27 28 The actual tm.h file for a particular system should include 29 this file, and then the file for the appropriate assembler syntax. 30 31 Many macros that specify assembler syntax are omitted entirely from 32 this file because they really belong in the files for particular 33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 35 that start with ASM_ or end in ASM_OP. */ 36 37/* Define the specific costs for a given cpu */ 38 39struct processor_costs { 40 const int add; /* cost of an add instruction */ 41 const int lea; /* cost of a lea instruction */ 42 const int shift_var; /* variable shift costs */ 43 const int shift_const; /* constant shift costs */ 44 const int mult_init[5]; /* cost of starting a multiply 45 in QImode, HImode, SImode, DImode, TImode*/ 46 const int mult_bit; /* cost of multiply per each bit set */ 47 const int divide[5]; /* cost of a divide/mod 48 in QImode, HImode, SImode, DImode, TImode*/ 49 int movsx; /* The cost of movsx operation. */ 50 int movzx; /* The cost of movzx operation. */ 51 const int large_insn; /* insns larger than this cost more */ 52 const int move_ratio; /* The threshold of number of scalar 53 memory-to-memory move insns. */ 54 const int movzbl_load; /* cost of loading using movzbl */ 55 const int int_load[3]; /* cost of loading integer registers 56 in QImode, HImode and SImode relative 57 to reg-reg move (2). */ 58 const int int_store[3]; /* cost of storing integer register 59 in QImode, HImode and SImode */ 60 const int fp_move; /* cost of reg,reg fld/fst */ 61 const int fp_load[3]; /* cost of loading FP register 62 in SFmode, DFmode and XFmode */ 63 const int fp_store[3]; /* cost of storing FP register 64 in SFmode, DFmode and XFmode */ 65 const int mmx_move; /* cost of moving MMX register. */ 66 const int mmx_load[2]; /* cost of loading MMX register 67 in SImode and DImode */ 68 const int mmx_store[2]; /* cost of storing MMX register 69 in SImode and DImode */ 70 const int sse_move; /* cost of moving SSE register. */ 71 const int sse_load[3]; /* cost of loading SSE register 72 in SImode, DImode and TImode*/ 73 const int sse_store[3]; /* cost of storing SSE register 74 in SImode, DImode and TImode*/ 75 const int mmxsse_to_integer; /* cost of moving mmxsse register to 76 integer and vice versa. */ 77 const int prefetch_block; /* bytes moved to cache for prefetch. */ 78 const int simultaneous_prefetches; /* number of parallel prefetch 79 operations. */ 80 const int branch_cost; /* Default value for BRANCH_COST. */ 81 const int fadd; /* cost of FADD and FSUB instructions. */ 82 const int fmul; /* cost of FMUL instruction. */ 83 const int fdiv; /* cost of FDIV instruction. */ 84 const int fabs; /* cost of FABS instruction. */ 85 const int fchs; /* cost of FCHS instruction. */ 86 const int fsqrt; /* cost of FSQRT instruction. */ 87}; 88 89extern const struct processor_costs *ix86_cost; 90 91/* Macros used in the machine description to test the flags. */ 92 93/* configure can arrange to make this 2, to force a 486. */ 94 95#ifndef TARGET_CPU_DEFAULT 96#ifdef TARGET_64BIT_DEFAULT 97#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_k8 98#else 99#define TARGET_CPU_DEFAULT 0 100#endif 101#endif 102 103#ifndef TARGET_FPMATH_DEFAULT 104#define TARGET_FPMATH_DEFAULT \ 105 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) 106#endif 107 108#define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS 109 110/* 64bit Sledgehammer mode. For libgcc2 we make sure this is a 111 compile-time constant. */ 112#ifdef IN_LIBGCC2 113#undef TARGET_64BIT 114#ifdef __x86_64__ 115#define TARGET_64BIT 1 116#else 117#define TARGET_64BIT 0 118#endif 119#else 120#ifndef TARGET_BI_ARCH 121#undef TARGET_64BIT 122#if TARGET_64BIT_DEFAULT 123#define TARGET_64BIT 1 124#else 125#define TARGET_64BIT 0 126#endif 127#endif 128#endif 129 130#define HAS_LONG_COND_BRANCH 1 131#define HAS_LONG_UNCOND_BRANCH 1 132 133#define TARGET_386 (ix86_tune == PROCESSOR_I386) 134#define TARGET_486 (ix86_tune == PROCESSOR_I486) 135#define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) 136#define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) 137#define TARGET_K6 (ix86_tune == PROCESSOR_K6) 138#define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) 139#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) 140#define TARGET_K8 (ix86_tune == PROCESSOR_K8) 141#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) 142#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) 143 144#define TUNEMASK (1 << ix86_tune) 145extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and; 146extern const int x86_use_bit_test, x86_cmove, x86_fisttp, x86_deep_branch; 147extern const int x86_branch_hints, x86_unroll_strlen; 148extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx; 149extern const int x86_use_himode_fiop, x86_use_simode_fiop; 150extern const int x86_use_mov0, x86_use_cltd, x86_read_modify_write; 151extern const int x86_read_modify, x86_split_long_moves; 152extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix; 153extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs; 154extern const int x86_promote_hi_regs, x86_integer_DFmode_moves; 155extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8; 156extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall; 157extern const int x86_accumulate_outgoing_args, x86_prologue_using_move; 158extern const int x86_epilogue_using_move, x86_decompose_lea; 159extern const int x86_arch_always_fancy_math_387, x86_shift1; 160extern const int x86_sse_partial_reg_dependency, x86_sse_split_regs; 161extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor; 162extern const int x86_use_ffreep; 163extern const int x86_inter_unit_moves, x86_schedule; 164extern const int x86_use_bt; 165extern const int x86_cmpxchg, x86_xadd; 166extern int x86_prefetch_sse; 167 168#define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK) 169#define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK) 170#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK) 171#define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK) 172#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK) 173/* For sane SSE instruction set generation we need fcomi instruction. It is 174 safe to enable all CMOVE instructions. */ 175#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE) 176#define TARGET_FISTTP (((x86_fisttp & (1 << ix86_arch)) || TARGET_SSE3) \ 177 && TARGET_80387) 178#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK) 179#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK) 180#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK) 181#define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT) 182#define TARGET_MOVX (x86_movx & TUNEMASK) 183#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK) 184#define TARGET_USE_HIMODE_FIOP (x86_use_himode_fiop & TUNEMASK) 185#define TARGET_USE_SIMODE_FIOP (x86_use_simode_fiop & TUNEMASK) 186#define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK) 187#define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK) 188#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK) 189#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK) 190#define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK) 191#define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK) 192#define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK) 193#define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK) 194#define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK) 195#define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK) 196#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK) 197#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK) 198#define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK) 199#define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK) 200#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK) 201#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK) 202#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK) 203#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK) 204#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ 205 (x86_sse_partial_reg_dependency & TUNEMASK) 206#define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK) 207#define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK) 208#define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK) 209#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK) 210#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK) 211#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK) 212#define TARGET_DECOMPOSE_LEA (x86_decompose_lea & TUNEMASK) 213#define TARGET_PREFETCH_SSE (x86_prefetch_sse) 214#define TARGET_SHIFT1 (x86_shift1 & TUNEMASK) 215#define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK) 216#define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK) 217#define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK) 218#define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK) 219#define TARGET_SCHEDULE (x86_schedule & TUNEMASK) 220#define TARGET_USE_BT (x86_use_bt & TUNEMASK) 221 222#define ASSEMBLER_DIALECT (ix86_asm_dialect) 223 224#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 225#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ 226 && (ix86_fpmath & FPMATH_387)) 227 228#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) 229#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN) 230 231#define TARGET_CMPXCHG (x86_cmpxchg & (1 << ix86_arch)) 232#define TARGET_XADD (x86_xadd & (1 << ix86_arch)) 233 234#ifndef TARGET_64BIT_DEFAULT 235#define TARGET_64BIT_DEFAULT 0 236#endif 237#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 238#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 239#endif 240 241/* Once GDB has been enhanced to deal with functions without frame 242 pointers, we can change this to allow for elimination of 243 the frame pointer in leaf functions. */ 244#define TARGET_DEFAULT 0 245 246/* This is not really a target flag, but is done this way so that 247 it's analogous to similar code for Mach-O on PowerPC. darwin.h 248 redefines this to 1. */ 249#define TARGET_MACHO 0 250 251/* Subtargets may reset this to 1 in order to enable 96-bit long double 252 with the rounding mode forced to 53 bits. */ 253#define TARGET_96_ROUND_53_LONG_DOUBLE 0 254 255/* Sometimes certain combinations of command options do not make 256 sense on a particular target machine. You can define a macro 257 `OVERRIDE_OPTIONS' to take account of this. This macro, if 258 defined, is executed once just after all the command options have 259 been parsed. 260 261 Don't use this macro to turn on various extra optimizations for 262 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 263 264#define OVERRIDE_OPTIONS override_options () 265 266/* Define this to change the optimizations performed by default. */ 267#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 268 optimization_options ((LEVEL), (SIZE)) 269 270/* Support for configure-time defaults of some command line options. */ 271#define OPTION_DEFAULT_SPECS \ 272 {"arch", "%{!march=*:-march=%(VALUE)}"}, \ 273 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 274 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" } 275 276/* Specs for the compiler proper */ 277 278#ifndef CC1_CPU_SPEC 279#define CC1_CPU_SPEC "\ 280%{!mtune*: \ 281%{m386:mtune=i386 \ 282%n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \ 283%{m486:-mtune=i486 \ 284%n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \ 285%{mpentium:-mtune=pentium \ 286%n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \ 287%{mpentiumpro:-mtune=pentiumpro \ 288%n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \ 289%{mcpu=*:-mtune=%* \ 290%n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \ 291%<mcpu=* \ 292%{mintel-syntax:-masm=intel \ 293%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ 294%{mno-intel-syntax:-masm=att \ 295%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" 296#endif 297 298/* Target CPU builtins. */ 299#define TARGET_CPU_CPP_BUILTINS() \ 300 do \ 301 { \ 302 size_t arch_len = strlen (ix86_arch_string); \ 303 size_t tune_len = strlen (ix86_tune_string); \ 304 int last_arch_char = ix86_arch_string[arch_len - 1]; \ 305 int last_tune_char = ix86_tune_string[tune_len - 1]; \ 306 \ 307 if (TARGET_64BIT) \ 308 { \ 309 builtin_assert ("cpu=x86_64"); \ 310 builtin_assert ("machine=x86_64"); \ 311 builtin_define ("__amd64"); \ 312 builtin_define ("__amd64__"); \ 313 builtin_define ("__x86_64"); \ 314 builtin_define ("__x86_64__"); \ 315 } \ 316 else \ 317 { \ 318 builtin_assert ("cpu=i386"); \ 319 builtin_assert ("machine=i386"); \ 320 builtin_define_std ("i386"); \ 321 } \ 322 \ 323 /* Built-ins based on -mtune= (or -march= if no \ 324 -mtune= given). */ \ 325 if (TARGET_386) \ 326 builtin_define ("__tune_i386__"); \ 327 else if (TARGET_486) \ 328 builtin_define ("__tune_i486__"); \ 329 else if (TARGET_PENTIUM) \ 330 { \ 331 builtin_define ("__tune_i586__"); \ 332 builtin_define ("__tune_pentium__"); \ 333 if (last_tune_char == 'x') \ 334 builtin_define ("__tune_pentium_mmx__"); \ 335 } \ 336 else if (TARGET_PENTIUMPRO) \ 337 { \ 338 builtin_define ("__tune_i686__"); \ 339 builtin_define ("__tune_pentiumpro__"); \ 340 switch (last_tune_char) \ 341 { \ 342 case '3': \ 343 builtin_define ("__tune_pentium3__"); \ 344 /* FALLTHRU */ \ 345 case '2': \ 346 builtin_define ("__tune_pentium2__"); \ 347 break; \ 348 } \ 349 } \ 350 else if (TARGET_K6) \ 351 { \ 352 builtin_define ("__tune_k6__"); \ 353 if (last_tune_char == '2') \ 354 builtin_define ("__tune_k6_2__"); \ 355 else if (last_tune_char == '3') \ 356 builtin_define ("__tune_k6_3__"); \ 357 } \ 358 else if (TARGET_ATHLON) \ 359 { \ 360 builtin_define ("__tune_athlon__"); \ 361 /* Only plain "athlon" lacks SSE. */ \ 362 if (last_tune_char != 'n') \ 363 builtin_define ("__tune_athlon_sse__"); \ 364 } \ 365 else if (TARGET_K8) \ 366 builtin_define ("__tune_k8__"); \ 367 else if (TARGET_PENTIUM4) \ 368 builtin_define ("__tune_pentium4__"); \ 369 else if (TARGET_NOCONA) \ 370 builtin_define ("__tune_nocona__"); \ 371 \ 372 if (TARGET_MMX) \ 373 builtin_define ("__MMX__"); \ 374 if (TARGET_3DNOW) \ 375 builtin_define ("__3dNOW__"); \ 376 if (TARGET_3DNOW_A) \ 377 builtin_define ("__3dNOW_A__"); \ 378 if (TARGET_SSE) \ 379 builtin_define ("__SSE__"); \ 380 if (TARGET_SSE2) \ 381 builtin_define ("__SSE2__"); \ 382 if (TARGET_SSE3) \ 383 builtin_define ("__SSE3__"); \ 384 if (TARGET_SSE_MATH && TARGET_SSE) \ 385 builtin_define ("__SSE_MATH__"); \ 386 if (TARGET_SSE_MATH && TARGET_SSE2) \ 387 builtin_define ("__SSE2_MATH__"); \ 388 \ 389 /* Built-ins based on -march=. */ \ 390 if (ix86_arch == PROCESSOR_I486) \ 391 { \ 392 builtin_define ("__i486"); \ 393 builtin_define ("__i486__"); \ 394 } \ 395 else if (ix86_arch == PROCESSOR_PENTIUM) \ 396 { \ 397 builtin_define ("__i586"); \ 398 builtin_define ("__i586__"); \ 399 builtin_define ("__pentium"); \ 400 builtin_define ("__pentium__"); \ 401 if (last_arch_char == 'x') \ 402 builtin_define ("__pentium_mmx__"); \ 403 } \ 404 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \ 405 { \ 406 builtin_define ("__i686"); \ 407 builtin_define ("__i686__"); \ 408 builtin_define ("__pentiumpro"); \ 409 builtin_define ("__pentiumpro__"); \ 410 } \ 411 else if (ix86_arch == PROCESSOR_K6) \ 412 { \ 413 \ 414 builtin_define ("__k6"); \ 415 builtin_define ("__k6__"); \ 416 if (last_arch_char == '2') \ 417 builtin_define ("__k6_2__"); \ 418 else if (last_arch_char == '3') \ 419 builtin_define ("__k6_3__"); \ 420 } \ 421 else if (ix86_arch == PROCESSOR_ATHLON) \ 422 { \ 423 builtin_define ("__athlon"); \ 424 builtin_define ("__athlon__"); \ 425 /* Only plain "athlon" lacks SSE. */ \ 426 if (last_arch_char != 'n') \ 427 builtin_define ("__athlon_sse__"); \ 428 } \ 429 else if (ix86_arch == PROCESSOR_K8) \ 430 { \ 431 builtin_define ("__k8"); \ 432 builtin_define ("__k8__"); \ 433 } \ 434 else if (ix86_arch == PROCESSOR_PENTIUM4) \ 435 { \ 436 builtin_define ("__pentium4"); \ 437 builtin_define ("__pentium4__"); \ 438 } \ 439 else if (ix86_arch == PROCESSOR_NOCONA) \ 440 { \ 441 builtin_define ("__nocona"); \ 442 builtin_define ("__nocona__"); \ 443 } \ 444 } \ 445 while (0) 446 447#define TARGET_CPU_DEFAULT_i386 0 448#define TARGET_CPU_DEFAULT_i486 1 449#define TARGET_CPU_DEFAULT_pentium 2 450#define TARGET_CPU_DEFAULT_pentium_mmx 3 451#define TARGET_CPU_DEFAULT_pentiumpro 4 452#define TARGET_CPU_DEFAULT_pentium2 5 453#define TARGET_CPU_DEFAULT_pentium3 6 454#define TARGET_CPU_DEFAULT_pentium4 7 455#define TARGET_CPU_DEFAULT_k6 8 456#define TARGET_CPU_DEFAULT_k6_2 9 457#define TARGET_CPU_DEFAULT_k6_3 10 458#define TARGET_CPU_DEFAULT_athlon 11 459#define TARGET_CPU_DEFAULT_athlon_sse 12 460#define TARGET_CPU_DEFAULT_k8 13 461#define TARGET_CPU_DEFAULT_pentium_m 14 462#define TARGET_CPU_DEFAULT_prescott 15 463#define TARGET_CPU_DEFAULT_nocona 16 464 465#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ 466 "pentiumpro", "pentium2", "pentium3", \ 467 "pentium4", "k6", "k6-2", "k6-3",\ 468 "athlon", "athlon-4", "k8", \ 469 "pentium-m", "prescott", "nocona"} 470 471#ifndef CC1_SPEC 472#define CC1_SPEC "%(cc1_cpu) " 473#endif 474 475/* This macro defines names of additional specifications to put in the 476 specs that can be used in various specifications like CC1_SPEC. Its 477 definition is an initializer with a subgrouping for each command option. 478 479 Each subgrouping contains a string constant, that defines the 480 specification name, and a string constant that used by the GCC driver 481 program. 482 483 Do not define this macro if it does not need to do anything. */ 484 485#ifndef SUBTARGET_EXTRA_SPECS 486#define SUBTARGET_EXTRA_SPECS 487#endif 488 489#define EXTRA_SPECS \ 490 { "cc1_cpu", CC1_CPU_SPEC }, \ 491 SUBTARGET_EXTRA_SPECS 492 493/* target machine storage layout */ 494 495#define LONG_DOUBLE_TYPE_SIZE 80 496 497/* Set the value of FLT_EVAL_METHOD in float.h. When using only the 498 FPU, assume that the fpcw is set to extended precision; when using 499 only SSE, rounding is correct; when using both SSE and the FPU, 500 the rounding precision is indeterminate, since either may be chosen 501 apparently at random. */ 502#define TARGET_FLT_EVAL_METHOD \ 503 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) 504 505#define SHORT_TYPE_SIZE 16 506#define INT_TYPE_SIZE 32 507#define FLOAT_TYPE_SIZE 32 508#define LONG_TYPE_SIZE BITS_PER_WORD 509#define DOUBLE_TYPE_SIZE 64 510#define LONG_LONG_TYPE_SIZE 64 511 512#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT 513#define MAX_BITS_PER_WORD 64 514#else 515#define MAX_BITS_PER_WORD 32 516#endif 517 518/* Define this if most significant byte of a word is the lowest numbered. */ 519/* That is true on the 80386. */ 520 521#define BITS_BIG_ENDIAN 0 522 523/* Define this if most significant byte of a word is the lowest numbered. */ 524/* That is not true on the 80386. */ 525#define BYTES_BIG_ENDIAN 0 526 527/* Define this if most significant word of a multiword number is the lowest 528 numbered. */ 529/* Not true for 80386 */ 530#define WORDS_BIG_ENDIAN 0 531 532/* Width of a word, in units (bytes). */ 533#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 534#ifdef IN_LIBGCC2 535#define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 536#else 537#define MIN_UNITS_PER_WORD 4 538#endif 539 540/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 541#define PARM_BOUNDARY BITS_PER_WORD 542 543/* Boundary (in *bits*) on which stack pointer should be aligned. */ 544#define STACK_BOUNDARY BITS_PER_WORD 545 546/* Boundary (in *bits*) on which the stack pointer prefers to be 547 aligned; the compiler cannot rely on having this alignment. */ 548#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 549 550/* As of July 2001, many runtimes to not align the stack properly when 551 entering main. This causes expand_main_function to forcibly align 552 the stack, which results in aligned frames for functions called from 553 main, though it does nothing for the alignment of main itself. */ 554#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ 555 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) 556 557/* Minimum allocation boundary for the code of a function. */ 558#define FUNCTION_BOUNDARY 8 559 560/* C++ stores the virtual bit in the lowest bit of function pointers. */ 561#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 562 563/* Alignment of field after `int : 0' in a structure. */ 564 565#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 566 567/* Minimum size in bits of the largest boundary to which any 568 and all fundamental data types supported by the hardware 569 might need to be aligned. No data type wants to be aligned 570 rounder than this. 571 572 Pentium+ prefers DFmode values to be aligned to 64 bit boundary 573 and Pentium Pro XFmode values at 128 bit boundaries. */ 574 575#define BIGGEST_ALIGNMENT 128 576 577/* Decide whether a variable of mode MODE should be 128 bit aligned. */ 578#define ALIGN_MODE_128(MODE) \ 579 ((MODE) == XFmode || (MODE) == TFmode || SSE_REG_MODE_P (MODE)) 580 581/* The published ABIs say that doubles should be aligned on word 582 boundaries, so lower the alignment for structure fields unless 583 -malign-double is set. */ 584 585/* ??? Blah -- this macro is used directly by libobjc. Since it 586 supports no vector modes, cut out the complexity and fall back 587 on BIGGEST_FIELD_ALIGNMENT. */ 588#ifdef IN_TARGET_LIBS 589#ifdef __x86_64__ 590#define BIGGEST_FIELD_ALIGNMENT 128 591#else 592#define BIGGEST_FIELD_ALIGNMENT 32 593#endif 594#else 595#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ 596 x86_field_alignment (FIELD, COMPUTED) 597#endif 598 599/* If defined, a C expression to compute the alignment given to a 600 constant that is being placed in memory. EXP is the constant 601 and ALIGN is the alignment that the object would ordinarily have. 602 The value of this macro is used instead of that alignment to align 603 the object. 604 605 If this macro is not defined, then ALIGN is used. 606 607 The typical use of this macro is to increase alignment for string 608 constants to be word aligned so that `strcpy' calls that copy 609 constants can be done inline. */ 610 611#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 612 613/* If defined, a C expression to compute the alignment for a static 614 variable. TYPE is the data type, and ALIGN is the alignment that 615 the object would ordinarily have. The value of this macro is used 616 instead of that alignment to align the object. 617 618 If this macro is not defined, then ALIGN is used. 619 620 One use of this macro is to increase alignment of medium-size 621 data to make it all fit in fewer cache lines. Another is to 622 cause character arrays to be word-aligned so that `strcpy' calls 623 that copy constants to character arrays can be done inline. */ 624 625#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) 626 627/* If defined, a C expression to compute the alignment for a local 628 variable. TYPE is the data type, and ALIGN is the alignment that 629 the object would ordinarily have. The value of this macro is used 630 instead of that alignment to align the object. 631 632 If this macro is not defined, then ALIGN is used. 633 634 One use of this macro is to increase alignment of medium-size 635 data to make it all fit in fewer cache lines. */ 636 637#define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN)) 638 639/* If defined, a C expression that gives the alignment boundary, in 640 bits, of an argument with the specified mode and type. If it is 641 not defined, `PARM_BOUNDARY' is used for all arguments. */ 642 643#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 644 ix86_function_arg_boundary ((MODE), (TYPE)) 645 646/* Set this nonzero if move instructions will actually fail to work 647 when given unaligned data. */ 648#define STRICT_ALIGNMENT 0 649 650/* If bit field type is int, don't let it cross an int, 651 and give entire struct the alignment of an int. */ 652/* Required on the 386 since it doesn't have bit-field insns. */ 653#define PCC_BITFIELD_TYPE_MATTERS 1 654 655/* Standard register usage. */ 656 657/* This processor has special stack-like registers. See reg-stack.c 658 for details. */ 659 660#define STACK_REGS 661#define IS_STACK_MODE(MODE) \ 662 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode) \ 663 664/* Number of actual hardware registers. 665 The hardware registers are assigned numbers for the compiler 666 from 0 to just below FIRST_PSEUDO_REGISTER. 667 All registers that the compiler knows about must be given numbers, 668 even those that are not normally considered general registers. 669 670 In the 80386 we give the 8 general purpose registers the numbers 0-7. 671 We number the floating point registers 8-15. 672 Note that registers 0-7 can be accessed as a short or int, 673 while only 0-3 may be used with byte `mov' instructions. 674 675 Reg 16 does not correspond to any hardware register, but instead 676 appears in the RTL as an argument pointer prior to reload, and is 677 eliminated during reloading in favor of either the stack or frame 678 pointer. */ 679 680#define FIRST_PSEUDO_REGISTER 53 681 682/* Number of hardware registers that go into the DWARF-2 unwind info. 683 If not defined, equals FIRST_PSEUDO_REGISTER. */ 684 685#define DWARF_FRAME_REGISTERS 17 686 687/* 1 for registers that have pervasive standard uses 688 and are not available for the register allocator. 689 On the 80386, the stack pointer is such, as is the arg pointer. 690 691 The value is zero if the register is not fixed on either 32 or 692 64 bit targets, one if the register if fixed on both 32 and 64 693 bit targets, two if it is only fixed on 32bit targets and three 694 if its only fixed on 64bit targets. 695 Proper values are computed in the CONDITIONAL_REGISTER_USAGE. 696 */ 697#define FIXED_REGISTERS \ 698/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 699{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 700/*arg,flags,fpsr,dir,frame*/ \ 701 1, 1, 1, 1, 1, \ 702/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 703 0, 0, 0, 0, 0, 0, 0, 0, \ 704/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 705 0, 0, 0, 0, 0, 0, 0, 0, \ 706/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 707 2, 2, 2, 2, 2, 2, 2, 2, \ 708/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 709 2, 2, 2, 2, 2, 2, 2, 2} 710 711 712/* 1 for registers not available across function calls. 713 These must include the FIXED_REGISTERS and also any 714 registers that can be used without being saved. 715 The latter must include the registers where values are returned 716 and the register where structure-value addresses are passed. 717 Aside from that, you can include as many other registers as you like. 718 719 The value is zero if the register is not call used on either 32 or 720 64 bit targets, one if the register if call used on both 32 and 64 721 bit targets, two if it is only call used on 32bit targets and three 722 if its only call used on 64bit targets. 723 Proper values are computed in the CONDITIONAL_REGISTER_USAGE. 724*/ 725#define CALL_USED_REGISTERS \ 726/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 727{ 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 728/*arg,flags,fpsr,dir,frame*/ \ 729 1, 1, 1, 1, 1, \ 730/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 731 1, 1, 1, 1, 1, 1, 1, 1, \ 732/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 733 1, 1, 1, 1, 1, 1, 1, 1, \ 734/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 735 1, 1, 1, 1, 2, 2, 2, 2, \ 736/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 737 1, 1, 1, 1, 1, 1, 1, 1} \ 738 739/* Order in which to allocate registers. Each register must be 740 listed once, even those in FIXED_REGISTERS. List frame pointer 741 late and fixed registers last. Note that, in general, we prefer 742 registers listed in CALL_USED_REGISTERS, keeping the others 743 available for storage of persistent values. 744 745 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, 746 so this is just empty initializer for array. */ 747 748#define REG_ALLOC_ORDER \ 749{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 750 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 751 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 752 48, 49, 50, 51, 52 } 753 754/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 755 to be rearranged based on a particular function. When using sse math, 756 we want to allocate SSE before x87 registers and vice vera. */ 757 758#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () 759 760 761/* Macro to conditionally modify fixed_regs/call_used_regs. */ 762#define CONDITIONAL_REGISTER_USAGE \ 763do { \ 764 int i; \ 765 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 766 { \ 767 if (fixed_regs[i] > 1) \ 768 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \ 769 if (call_used_regs[i] > 1) \ 770 call_used_regs[i] = (call_used_regs[i] \ 771 == (TARGET_64BIT ? 3 : 2)); \ 772 } \ 773 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 774 { \ 775 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 776 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 777 } \ 778 if (! TARGET_MMX) \ 779 { \ 780 int i; \ 781 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 782 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ 783 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ 784 } \ 785 if (! TARGET_SSE) \ 786 { \ 787 int i; \ 788 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 789 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ 790 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ 791 } \ 792 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ 793 { \ 794 int i; \ 795 HARD_REG_SET x; \ 796 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ 797 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 798 if (TEST_HARD_REG_BIT (x, i)) \ 799 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ 800 } \ 801 if (! TARGET_64BIT) \ 802 { \ 803 int i; \ 804 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \ 805 reg_names[i] = ""; \ 806 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \ 807 reg_names[i] = ""; \ 808 } \ 809 } while (0) 810 811/* Return number of consecutive hard regs needed starting at reg REGNO 812 to hold something of mode MODE. 813 This is ordinarily the length in words of a value of mode MODE 814 but can be less for certain modes in special long registers. 815 816 Actually there are no two word move instructions for consecutive 817 registers. And only registers 0-3 may have mov byte instructions 818 applied to them. 819 */ 820 821#define HARD_REGNO_NREGS(REGNO, MODE) \ 822 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 823 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 824 : ((MODE) == XFmode \ 825 ? (TARGET_64BIT ? 2 : 3) \ 826 : (MODE) == XCmode \ 827 ? (TARGET_64BIT ? 4 : 6) \ 828 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 829 830#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ 831 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \ 832 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 833 ? 0 \ 834 : ((MODE) == XFmode || (MODE) == XCmode)) \ 835 : 0) 836 837#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) 838 839#define VALID_SSE2_REG_MODE(MODE) \ 840 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ 841 || (MODE) == V2DImode || (MODE) == DFmode) 842 843#define VALID_SSE_REG_MODE(MODE) \ 844 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 845 || (MODE) == SFmode || (MODE) == TFmode) 846 847#define VALID_MMX_REG_MODE_3DNOW(MODE) \ 848 ((MODE) == V2SFmode || (MODE) == SFmode) 849 850#define VALID_MMX_REG_MODE(MODE) \ 851 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \ 852 || (MODE) == V2SImode || (MODE) == SImode) 853 854/* ??? No autovectorization into MMX or 3DNOW until we can reliably 855 place emms and femms instructions. */ 856#define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD) 857 858#define VALID_FP_MODE_P(MODE) \ 859 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ 860 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ 861 862#define VALID_INT_MODE_P(MODE) \ 863 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 864 || (MODE) == DImode \ 865 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 866 || (MODE) == CDImode \ 867 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ 868 || (MODE) == TFmode || (MODE) == TCmode))) 869 870/* Return true for modes passed in SSE registers. */ 871#define SSE_REG_MODE_P(MODE) \ 872 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \ 873 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \ 874 || (MODE) == V4SFmode || (MODE) == V4SImode) 875 876/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 877 878#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 879 ix86_hard_regno_mode_ok ((REGNO), (MODE)) 880 881/* Value is 1 if it is a good idea to tie two pseudo registers 882 when one has mode MODE1 and one has mode MODE2. 883 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 884 for any hard reg, then this must be 0 for correct output. */ 885 886#define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) 887 888/* It is possible to write patterns to move flags; but until someone 889 does it, */ 890#define AVOID_CCMODE_COPIES 891 892/* Specify the modes required to caller save a given hard regno. 893 We do this on i386 to prevent flags from being saved at all. 894 895 Kill any attempts to combine saving of modes. */ 896 897#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 898 (CC_REGNO_P (REGNO) ? VOIDmode \ 899 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 900 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\ 901 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ 902 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ 903 : (MODE)) 904/* Specify the registers used for certain standard purposes. 905 The values of these macros are register numbers. */ 906 907/* on the 386 the pc register is %eip, and is not usable as a general 908 register. The ordinary mov instructions won't work */ 909/* #define PC_REGNUM */ 910 911/* Register to use for pushing function arguments. */ 912#define STACK_POINTER_REGNUM 7 913 914/* Base register for access to local variables of the function. */ 915#define HARD_FRAME_POINTER_REGNUM 6 916 917/* Base register for access to local variables of the function. */ 918#define FRAME_POINTER_REGNUM 20 919 920/* First floating point reg */ 921#define FIRST_FLOAT_REG 8 922 923/* First & last stack-like regs */ 924#define FIRST_STACK_REG FIRST_FLOAT_REG 925#define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 926 927#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 928#define LAST_SSE_REG (FIRST_SSE_REG + 7) 929 930#define FIRST_MMX_REG (LAST_SSE_REG + 1) 931#define LAST_MMX_REG (FIRST_MMX_REG + 7) 932 933#define FIRST_REX_INT_REG (LAST_MMX_REG + 1) 934#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 935 936#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) 937#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 938 939/* Value should be nonzero if functions must have frame pointers. 940 Zero means the frame pointer need not be set up (and parms 941 may be accessed via the stack pointer) in functions that seem suitable. 942 This is computed in `reload', in reload1.c. */ 943#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () 944 945/* Override this in other tm.h files to cope with various OS lossage 946 requiring a frame pointer. */ 947#ifndef SUBTARGET_FRAME_POINTER_REQUIRED 948#define SUBTARGET_FRAME_POINTER_REQUIRED 0 949#endif 950 951/* Make sure we can access arbitrary call frames. */ 952#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 953 954/* Base register for access to arguments of the function. */ 955#define ARG_POINTER_REGNUM 16 956 957/* Register in which static-chain is passed to a function. 958 We do use ECX as static chain register for 32 bit ABI. On the 959 64bit ABI, ECX is an argument register, so we use R10 instead. */ 960#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2) 961 962/* Register to hold the addressing base for position independent 963 code access to data items. We don't use PIC pointer for 64bit 964 mode. Define the regnum to dummy value to prevent gcc from 965 pessimizing code dealing with EBX. 966 967 To avoid clobbering a call-saved register unnecessarily, we renumber 968 the pic register when possible. The change is visible after the 969 prologue has been emitted. */ 970 971#define REAL_PIC_OFFSET_TABLE_REGNUM 3 972 973#define PIC_OFFSET_TABLE_REGNUM \ 974 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \ 975 || !flag_pic ? INVALID_REGNUM \ 976 : reload_completed ? REGNO (pic_offset_table_rtx) \ 977 : REAL_PIC_OFFSET_TABLE_REGNUM) 978 979#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" 980 981/* A C expression which can inhibit the returning of certain function 982 values in registers, based on the type of value. A nonzero value 983 says to return the function value in memory, just as large 984 structures are always returned. Here TYPE will be a C expression 985 of type `tree', representing the data type of the value. 986 987 Note that values of mode `BLKmode' must be explicitly handled by 988 this macro. Also, the option `-fpcc-struct-return' takes effect 989 regardless of this macro. On most systems, it is possible to 990 leave the macro undefined; this causes a default definition to be 991 used, whose value is the constant 1 for `BLKmode' values, and 0 992 otherwise. 993 994 Do not use this macro to indicate that structures and unions 995 should always be returned in memory. You should instead use 996 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ 997 998#define RETURN_IN_MEMORY(TYPE) \ 999 ix86_return_in_memory (TYPE) 1000 1001/* This is overridden by <cygwin.h>. */ 1002#define MS_AGGREGATE_RETURN 0 1003 1004/* This is overridden by <netware.h>. */ 1005#define KEEP_AGGREGATE_RETURN_POINTER 0 1006 1007/* Define the classes of registers for register constraints in the 1008 machine description. Also define ranges of constants. 1009 1010 One of the classes must always be named ALL_REGS and include all hard regs. 1011 If there is more than one class, another class must be named NO_REGS 1012 and contain no registers. 1013 1014 The name GENERAL_REGS must be the name of a class (or an alias for 1015 another name such as ALL_REGS). This is the class of registers 1016 that is allowed by "g" or "r" in a register constraint. 1017 Also, registers outside this class are allocated only when 1018 instructions express preferences for them. 1019 1020 The classes must be numbered in nondecreasing order; that is, 1021 a larger-numbered class must never be contained completely 1022 in a smaller-numbered class. 1023 1024 For any two classes, it is very desirable that there be another 1025 class that represents their union. 1026 1027 It might seem that class BREG is unnecessary, since no useful 386 1028 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1029 and the "b" register constraint is useful in asms for syscalls. 1030 1031 The flags and fpsr registers are in no class. */ 1032 1033enum reg_class 1034{ 1035 NO_REGS, 1036 AREG, DREG, CREG, BREG, SIREG, DIREG, 1037 AD_REGS, /* %eax/%edx for DImode */ 1038 Q_REGS, /* %eax %ebx %ecx %edx */ 1039 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1040 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1041 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1042 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ 1043 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1044 FLOAT_REGS, 1045 SSE_REGS, 1046 MMX_REGS, 1047 FP_TOP_SSE_REGS, 1048 FP_SECOND_SSE_REGS, 1049 FLOAT_SSE_REGS, 1050 FLOAT_INT_REGS, 1051 INT_SSE_REGS, 1052 FLOAT_INT_SSE_REGS, 1053 ALL_REGS, LIM_REG_CLASSES 1054}; 1055 1056#define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1057 1058#define INTEGER_CLASS_P(CLASS) \ 1059 reg_class_subset_p ((CLASS), GENERAL_REGS) 1060#define FLOAT_CLASS_P(CLASS) \ 1061 reg_class_subset_p ((CLASS), FLOAT_REGS) 1062#define SSE_CLASS_P(CLASS) \ 1063 ((CLASS) == SSE_REGS) 1064#define MMX_CLASS_P(CLASS) \ 1065 ((CLASS) == MMX_REGS) 1066#define MAYBE_INTEGER_CLASS_P(CLASS) \ 1067 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1068#define MAYBE_FLOAT_CLASS_P(CLASS) \ 1069 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1070#define MAYBE_SSE_CLASS_P(CLASS) \ 1071 reg_classes_intersect_p (SSE_REGS, (CLASS)) 1072#define MAYBE_MMX_CLASS_P(CLASS) \ 1073 reg_classes_intersect_p (MMX_REGS, (CLASS)) 1074 1075#define Q_CLASS_P(CLASS) \ 1076 reg_class_subset_p ((CLASS), Q_REGS) 1077 1078/* Give names of register classes as strings for dump file. */ 1079 1080#define REG_CLASS_NAMES \ 1081{ "NO_REGS", \ 1082 "AREG", "DREG", "CREG", "BREG", \ 1083 "SIREG", "DIREG", \ 1084 "AD_REGS", \ 1085 "Q_REGS", "NON_Q_REGS", \ 1086 "INDEX_REGS", \ 1087 "LEGACY_REGS", \ 1088 "GENERAL_REGS", \ 1089 "FP_TOP_REG", "FP_SECOND_REG", \ 1090 "FLOAT_REGS", \ 1091 "SSE_REGS", \ 1092 "MMX_REGS", \ 1093 "FP_TOP_SSE_REGS", \ 1094 "FP_SECOND_SSE_REGS", \ 1095 "FLOAT_SSE_REGS", \ 1096 "FLOAT_INT_REGS", \ 1097 "INT_SSE_REGS", \ 1098 "FLOAT_INT_SSE_REGS", \ 1099 "ALL_REGS" } 1100 1101/* Define which registers fit in which classes. 1102 This is an initializer for a vector of HARD_REG_SET 1103 of length N_REG_CLASSES. */ 1104 1105#define REG_CLASS_CONTENTS \ 1106{ { 0x00, 0x0 }, \ 1107 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1108 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1109 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1110 { 0x03, 0x0 }, /* AD_REGS */ \ 1111 { 0x0f, 0x0 }, /* Q_REGS */ \ 1112 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1113 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1114 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1115 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1116 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ 1117 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ 1118{ 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ 1119{ 0xe0000000, 0x1f }, /* MMX_REGS */ \ 1120{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ 1121{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ 1122{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ 1123 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ 1124{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ 1125{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ 1126{ 0xffffffff,0x1fffff } \ 1127} 1128 1129/* The same information, inverted: 1130 Return the class number of the smallest class containing 1131 reg number REGNO. This could be a conditional expression 1132 or could index an array. */ 1133 1134#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1135 1136/* When defined, the compiler allows registers explicitly used in the 1137 rtl to be used as spill registers but prevents the compiler from 1138 extending the lifetime of these registers. */ 1139 1140#define SMALL_REGISTER_CLASSES 1 1141 1142#define QI_REG_P(X) \ 1143 (REG_P (X) && REGNO (X) < 4) 1144 1145#define GENERAL_REGNO_P(N) \ 1146 ((N) < 8 || REX_INT_REGNO_P (N)) 1147 1148#define GENERAL_REG_P(X) \ 1149 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1150 1151#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) 1152 1153#define NON_QI_REG_P(X) \ 1154 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) 1155 1156#define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG) 1157#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1158 1159#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 1160#define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG) 1161#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1162#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) 1163 1164#define SSE_REGNO_P(N) \ 1165 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \ 1166 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)) 1167 1168#define REX_SSE_REGNO_P(N) \ 1169 ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG) 1170 1171#define SSE_REGNO(N) \ 1172 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) 1173#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) 1174 1175#define SSE_FLOAT_MODE_P(MODE) \ 1176 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1177 1178#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG) 1179#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) 1180 1181#define STACK_REG_P(XOP) \ 1182 (REG_P (XOP) && \ 1183 REGNO (XOP) >= FIRST_STACK_REG && \ 1184 REGNO (XOP) <= LAST_STACK_REG) 1185 1186#define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP)) 1187 1188#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) 1189 1190#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1191#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1192 1193/* The class value for index registers, and the one for base regs. */ 1194 1195#define INDEX_REG_CLASS INDEX_REGS 1196#define BASE_REG_CLASS GENERAL_REGS 1197 1198/* Unused letters: 1199 B TU W 1200 h jk vw z 1201*/ 1202 1203/* Get reg_class from a letter such as appears in the machine description. */ 1204 1205#define REG_CLASS_FROM_LETTER(C) \ 1206 ((C) == 'r' ? GENERAL_REGS : \ 1207 (C) == 'R' ? LEGACY_REGS : \ 1208 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \ 1209 (C) == 'Q' ? Q_REGS : \ 1210 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1211 ? FLOAT_REGS \ 1212 : NO_REGS) : \ 1213 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1214 ? FP_TOP_REG \ 1215 : NO_REGS) : \ 1216 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1217 ? FP_SECOND_REG \ 1218 : NO_REGS) : \ 1219 (C) == 'a' ? AREG : \ 1220 (C) == 'b' ? BREG : \ 1221 (C) == 'c' ? CREG : \ 1222 (C) == 'd' ? DREG : \ 1223 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \ 1224 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \ 1225 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \ 1226 (C) == 'A' ? AD_REGS : \ 1227 (C) == 'D' ? DIREG : \ 1228 (C) == 'S' ? SIREG : \ 1229 (C) == 'l' ? INDEX_REGS : \ 1230 NO_REGS) 1231 1232/* The letters I, J, K, L, M, N, and O in a register constraint string 1233 can be used to stand for particular ranges of immediate operands. 1234 This macro defines what the ranges are. 1235 C is the letter, and VALUE is a constant value. 1236 Return 1 if VALUE is in the range specified by C. 1237 1238 I is for non-DImode shifts. 1239 J is for DImode shifts. 1240 K is for signed imm8 operands. 1241 L is for andsi as zero-extending move. 1242 M is for shifts that can be executed by the "lea" opcode. 1243 N is for immediate operands for out/in instructions (0-255) 1244 O is for TImode shifts. 1245 */ 1246 1247#define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1248 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \ 1249 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \ 1250 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \ 1251 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \ 1252 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \ 1253 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \ 1254 : (C) == 'O' ? (VALUE) >= 0 && (VALUE) <= 127 \ 1255 : 0) 1256 1257/* Similar, but for floating constants, and defining letters G and H. 1258 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if 1259 TARGET_387 isn't set, because the stack register converter may need to 1260 load 0.0 into the function value register. */ 1261 1262#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1263 ((C) == 'G' ? standard_80387_constant_p (VALUE) \ 1264 : 0) 1265 1266/* A C expression that defines the optional machine-dependent 1267 constraint letters that can be used to segregate specific types of 1268 operands, usually memory references, for the target machine. Any 1269 letter that is not elsewhere defined and not matched by 1270 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not 1271 be defined. 1272 1273 If it is required for a particular target machine, it should 1274 return 1 if VALUE corresponds to the operand type represented by 1275 the constraint letter C. If C is not defined as an extra 1276 constraint, the value returned should be 0 regardless of VALUE. */ 1277 1278#define EXTRA_CONSTRAINT(VALUE, D) \ 1279 ((D) == 'e' ? x86_64_immediate_operand (VALUE, VOIDmode) \ 1280 : (D) == 'Z' ? x86_64_zext_immediate_operand (VALUE, VOIDmode) \ 1281 : (D) == 'C' ? standard_sse_constant_p (VALUE) \ 1282 : 0) 1283 1284/* Place additional restrictions on the register class to use when it 1285 is necessary to be able to hold a value of mode MODE in a reload 1286 register for which class CLASS would ordinarily be used. */ 1287 1288#define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1289 ((MODE) == QImode && !TARGET_64BIT \ 1290 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ 1291 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ 1292 ? Q_REGS : (CLASS)) 1293 1294/* Given an rtx X being reloaded into a reg required to be 1295 in class CLASS, return the class of reg to actually use. 1296 In general this is just CLASS; but on some machines 1297 in some cases it is preferable to use a more restrictive class. 1298 On the 80386 series, we prevent floating constants from being 1299 reloaded into floating registers (since no move-insn can do that) 1300 and we ensure that QImodes aren't reloaded into the esi or edi reg. */ 1301 1302/* Put float CONST_DOUBLE in the constant pool instead of fp regs. 1303 QImode must go into class Q_REGS. 1304 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and 1305 movdf to do mem-to-mem moves through integer regs. */ 1306 1307#define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1308 ix86_preferred_reload_class ((X), (CLASS)) 1309 1310/* If we are copying between general and FP registers, we need a memory 1311 location. The same is true for SSE and MMX registers. */ 1312#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1313 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1314 1315/* QImode spills from non-QI registers need a scratch. This does not 1316 happen often -- the only example so far requires an uninitialized 1317 pseudo. */ 1318 1319#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ 1320 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \ 1321 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \ 1322 ? Q_REGS : NO_REGS) 1323 1324/* Return the maximum number of consecutive registers 1325 needed to represent mode MODE in a register of class CLASS. */ 1326/* On the 80386, this is the size of MODE in words, 1327 except in the FP regs, where a single reg is always enough. */ 1328#define CLASS_MAX_NREGS(CLASS, MODE) \ 1329 (!MAYBE_INTEGER_CLASS_P (CLASS) \ 1330 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1331 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \ 1332 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1333 1334/* A C expression whose value is nonzero if pseudos that have been 1335 assigned to registers of class CLASS would likely be spilled 1336 because registers of CLASS are needed for spill registers. 1337 1338 The default value of this macro returns 1 if CLASS has exactly one 1339 register and zero otherwise. On most machines, this default 1340 should be used. Only define this macro to some other expression 1341 if pseudo allocated by `local-alloc.c' end up in memory because 1342 their hard registers were needed for spill registers. If this 1343 macro returns nonzero for those classes, those pseudos will only 1344 be allocated by `global.c', which knows how to reallocate the 1345 pseudo to another register. If there would not be another 1346 register available for reallocation, you should not change the 1347 definition of this macro since the only effect of such a 1348 definition would be to slow down register allocation. */ 1349 1350#define CLASS_LIKELY_SPILLED_P(CLASS) \ 1351 (((CLASS) == AREG) \ 1352 || ((CLASS) == DREG) \ 1353 || ((CLASS) == CREG) \ 1354 || ((CLASS) == BREG) \ 1355 || ((CLASS) == AD_REGS) \ 1356 || ((CLASS) == SIREG) \ 1357 || ((CLASS) == DIREG) \ 1358 || ((CLASS) == FP_TOP_REG) \ 1359 || ((CLASS) == FP_SECOND_REG)) 1360 1361/* Return a class of registers that cannot change FROM mode to TO mode. */ 1362 1363#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1364 ix86_cannot_change_mode_class (FROM, TO, CLASS) 1365 1366/* Stack layout; function entry, exit and calling. */ 1367 1368/* Define this if pushing a word on the stack 1369 makes the stack pointer a smaller address. */ 1370#define STACK_GROWS_DOWNWARD 1371 1372/* Define this to nonzero if the nominal address of the stack frame 1373 is at the high-address end of the local variables; 1374 that is, each additional local variable allocated 1375 goes at a more negative offset in the frame. */ 1376#define FRAME_GROWS_DOWNWARD 1 1377 1378/* Offset within stack frame to start allocating local variables at. 1379 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1380 first local allocated. Otherwise, it is the offset to the BEGINNING 1381 of the first local allocated. */ 1382#define STARTING_FRAME_OFFSET 0 1383 1384/* If we generate an insn to push BYTES bytes, 1385 this says how many the stack pointer really advances by. 1386 On 386, we have pushw instruction that decrements by exactly 2 no 1387 matter what the position was, there is no pushb. 1388 But as CIE data alignment factor on this arch is -4, we need to make 1389 sure all stack pointer adjustments are in multiple of 4. 1390 1391 For 64bit ABI we round up to 8 bytes. 1392 */ 1393 1394#define PUSH_ROUNDING(BYTES) \ 1395 (TARGET_64BIT \ 1396 ? (((BYTES) + 7) & (-8)) \ 1397 : (((BYTES) + 3) & (-4))) 1398 1399/* If defined, the maximum amount of space required for outgoing arguments will 1400 be computed and placed into the variable 1401 `current_function_outgoing_args_size'. No space will be pushed onto the 1402 stack for each call; instead, the function prologue should increase the stack 1403 frame size by this amount. */ 1404 1405#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS 1406 1407/* If defined, a C expression whose value is nonzero when we want to use PUSH 1408 instructions to pass outgoing arguments. */ 1409 1410#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1411 1412/* We want the stack and args grow in opposite directions, even if 1413 PUSH_ARGS is 0. */ 1414#define PUSH_ARGS_REVERSED 1 1415 1416/* Offset of first parameter from the argument pointer register value. */ 1417#define FIRST_PARM_OFFSET(FNDECL) 0 1418 1419/* Define this macro if functions should assume that stack space has been 1420 allocated for arguments even when their values are passed in registers. 1421 1422 The value of this macro is the size, in bytes, of the area reserved for 1423 arguments passed in registers for the function represented by FNDECL. 1424 1425 This space can be allocated by the caller, or be a part of the 1426 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1427 which. */ 1428#define REG_PARM_STACK_SPACE(FNDECL) 0 1429 1430/* Value is the number of bytes of arguments automatically 1431 popped when returning from a subroutine call. 1432 FUNDECL is the declaration node of the function (as a tree), 1433 FUNTYPE is the data type of the function (as a tree), 1434 or for a library call it is an identifier node for the subroutine name. 1435 SIZE is the number of bytes of arguments passed on the stack. 1436 1437 On the 80386, the RTD insn may be used to pop them if the number 1438 of args is fixed, but if the number is variable then the caller 1439 must pop them all. RTD can't be used for library calls now 1440 because the library is compiled with the Unix compiler. 1441 Use of RTD is a selectable option, since it is incompatible with 1442 standard Unix calling sequences. If the option is not selected, 1443 the caller must always pop the args. 1444 1445 The attribute stdcall is equivalent to RTD on a per module basis. */ 1446 1447#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ 1448 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) 1449 1450#define FUNCTION_VALUE_REGNO_P(N) \ 1451 ix86_function_value_regno_p (N) 1452 1453/* Define how to find the value returned by a library function 1454 assuming the value has mode MODE. */ 1455 1456#define LIBCALL_VALUE(MODE) \ 1457 ix86_libcall_value (MODE) 1458 1459/* Define the size of the result block used for communication between 1460 untyped_call and untyped_return. The block contains a DImode value 1461 followed by the block used by fnsave and frstor. */ 1462 1463#define APPLY_RESULT_SIZE (8+108) 1464 1465/* 1 if N is a possible register number for function argument passing. */ 1466#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1467 1468/* Define a data type for recording info about an argument list 1469 during the scan of that argument list. This data type should 1470 hold all necessary information about the function itself 1471 and about the args processed so far, enough to enable macros 1472 such as FUNCTION_ARG to determine where the next arg should go. */ 1473 1474typedef struct ix86_args { 1475 int words; /* # words passed so far */ 1476 int nregs; /* # registers available for passing */ 1477 int regno; /* next available register number */ 1478 int fastcall; /* fastcall calling convention is used */ 1479 int sse_words; /* # sse words passed so far */ 1480 int sse_nregs; /* # sse registers available for passing */ 1481 int warn_sse; /* True when we want to warn about SSE ABI. */ 1482 int warn_mmx; /* True when we want to warn about MMX ABI. */ 1483 int sse_regno; /* next available sse register number */ 1484 int mmx_words; /* # mmx words passed so far */ 1485 int mmx_nregs; /* # mmx registers available for passing */ 1486 int mmx_regno; /* next available mmx register number */ 1487 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1488 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should 1489 be passed in SSE registers. Otherwise 0. */ 1490} CUMULATIVE_ARGS; 1491 1492/* Initialize a variable CUM of type CUMULATIVE_ARGS 1493 for a call to a function whose data type is FNTYPE. 1494 For a library call, FNTYPE is 0. */ 1495 1496#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1497 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1498 1499/* Update the data in CUM to advance over an argument 1500 of mode MODE and data type TYPE. 1501 (TYPE is null for libcalls where that information may not be available.) */ 1502 1503#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1504 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1505 1506/* Define where to put the arguments to a function. 1507 Value is zero to push the argument on the stack, 1508 or a hard register in which to store the argument. 1509 1510 MODE is the argument's machine mode. 1511 TYPE is the data type of the argument (as a tree). 1512 This is null for libcalls where that information may 1513 not be available. 1514 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1515 the preceding args and about the function being called. 1516 NAMED is nonzero if this argument is a named parameter 1517 (otherwise it is an extra parameter matching an ellipsis). */ 1518 1519#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1520 function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1521 1522/* Implement `va_start' for varargs and stdarg. */ 1523#define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \ 1524 ix86_va_start (VALIST, NEXTARG) 1525 1526#define TARGET_ASM_FILE_END ix86_file_end 1527#define NEED_INDICATE_EXEC_STACK 0 1528 1529/* Output assembler code to FILE to increment profiler label # LABELNO 1530 for profiling a function entry. */ 1531 1532#define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) 1533 1534#define MCOUNT_NAME "_mcount" 1535 1536#define PROFILE_COUNT_REGISTER "edx" 1537 1538/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1539 the stack pointer does not matter. The value is tested only in 1540 functions that have frame pointers. 1541 No definition is equivalent to always zero. */ 1542/* Note on the 386 it might be more efficient not to define this since 1543 we have to restore it ourselves from the frame pointer, in order to 1544 use pop */ 1545 1546#define EXIT_IGNORE_STACK 1 1547 1548/* Output assembler code for a block containing the constant parts 1549 of a trampoline, leaving space for the variable parts. */ 1550 1551/* On the 386, the trampoline contains two instructions: 1552 mov #STATIC,ecx 1553 jmp FUNCTION 1554 The trampoline is generated entirely at runtime. The operand of JMP 1555 is the address of FUNCTION relative to the instruction following the 1556 JMP (which is 5 bytes long). */ 1557 1558/* Length in units of the trampoline for entering a nested function. */ 1559 1560#define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) 1561 1562/* Emit RTL insns to initialize the variable parts of a trampoline. 1563 FNADDR is an RTX for the address of the function's pure code. 1564 CXT is an RTX for the static chain value for the function. */ 1565 1566#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1567 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) 1568 1569/* Definitions for register eliminations. 1570 1571 This is an array of structures. Each structure initializes one pair 1572 of eliminable registers. The "from" register number is given first, 1573 followed by "to". Eliminations of the same "from" register are listed 1574 in order of preference. 1575 1576 There are two registers that can always be eliminated on the i386. 1577 The frame pointer and the arg pointer can be replaced by either the 1578 hard frame pointer or to the stack pointer, depending upon the 1579 circumstances. The hard frame pointer is not used before reload and 1580 so it is not eligible for elimination. */ 1581 1582#define ELIMINABLE_REGS \ 1583{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1584 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1585 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1586 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1587 1588/* Given FROM and TO register numbers, say whether this elimination is 1589 allowed. Frame pointer elimination is automatically handled. 1590 1591 All other eliminations are valid. */ 1592 1593#define CAN_ELIMINATE(FROM, TO) \ 1594 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) 1595 1596/* Define the offset between two registers, one to be eliminated, and the other 1597 its replacement, at the start of a routine. */ 1598 1599#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1600 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1601 1602/* Addressing modes, and classification of registers for them. */ 1603 1604/* Macros to check register numbers against specific register classes. */ 1605 1606/* These assume that REGNO is a hard or pseudo reg number. 1607 They give nonzero only if REGNO is a hard reg of the suitable class 1608 or a pseudo reg currently allocated to a suitable hard reg. 1609 Since they use reg_renumber, they are safe only once reg_renumber 1610 has been allocated, which happens in local-alloc.c. */ 1611 1612#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1613 ((REGNO) < STACK_POINTER_REGNUM \ 1614 || (REGNO >= FIRST_REX_INT_REG \ 1615 && (REGNO) <= LAST_REX_INT_REG) \ 1616 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1617 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1618 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM) 1619 1620#define REGNO_OK_FOR_BASE_P(REGNO) \ 1621 ((REGNO) <= STACK_POINTER_REGNUM \ 1622 || (REGNO) == ARG_POINTER_REGNUM \ 1623 || (REGNO) == FRAME_POINTER_REGNUM \ 1624 || (REGNO >= FIRST_REX_INT_REG \ 1625 && (REGNO) <= LAST_REX_INT_REG) \ 1626 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1627 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1628 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM) 1629 1630#define REGNO_OK_FOR_SIREG_P(REGNO) \ 1631 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4) 1632#define REGNO_OK_FOR_DIREG_P(REGNO) \ 1633 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5) 1634 1635/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1636 and check its validity for a certain class. 1637 We have two alternate definitions for each of them. 1638 The usual definition accepts all pseudo regs; the other rejects 1639 them unless they have been allocated suitable hard regs. 1640 The symbol REG_OK_STRICT causes the latter definition to be used. 1641 1642 Most source files want to accept pseudo regs in the hope that 1643 they will get allocated to the class that the insn wants them to be in. 1644 Source files for reload pass need to be strict. 1645 After reload, it makes no difference, since pseudo regs have 1646 been eliminated by then. */ 1647 1648 1649/* Non strict versions, pseudos are ok. */ 1650#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1651 (REGNO (X) < STACK_POINTER_REGNUM \ 1652 || (REGNO (X) >= FIRST_REX_INT_REG \ 1653 && REGNO (X) <= LAST_REX_INT_REG) \ 1654 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1655 1656#define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1657 (REGNO (X) <= STACK_POINTER_REGNUM \ 1658 || REGNO (X) == ARG_POINTER_REGNUM \ 1659 || REGNO (X) == FRAME_POINTER_REGNUM \ 1660 || (REGNO (X) >= FIRST_REX_INT_REG \ 1661 && REGNO (X) <= LAST_REX_INT_REG) \ 1662 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1663 1664/* Strict versions, hard registers only */ 1665#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1666#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1667 1668#ifndef REG_OK_STRICT 1669#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1670#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1671 1672#else 1673#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1674#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1675#endif 1676 1677/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1678 that is a valid memory address for an instruction. 1679 The MODE argument is the machine mode for the MEM expression 1680 that wants to use this address. 1681 1682 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, 1683 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1684 1685 See legitimize_pic_address in i386.c for details as to what 1686 constitutes a legitimate address when -fpic is used. */ 1687 1688#define MAX_REGS_PER_ADDRESS 2 1689 1690#define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1691 1692/* Nonzero if the constant value X is a legitimate general operand. 1693 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1694 1695#define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) 1696 1697#ifdef REG_OK_STRICT 1698#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1699do { \ 1700 if (legitimate_address_p ((MODE), (X), 1)) \ 1701 goto ADDR; \ 1702} while (0) 1703 1704#else 1705#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1706do { \ 1707 if (legitimate_address_p ((MODE), (X), 0)) \ 1708 goto ADDR; \ 1709} while (0) 1710 1711#endif 1712 1713/* If defined, a C expression to determine the base term of address X. 1714 This macro is used in only one place: `find_base_term' in alias.c. 1715 1716 It is always safe for this macro to not be defined. It exists so 1717 that alias analysis can understand machine-dependent addresses. 1718 1719 The typical use of this macro is to handle addresses containing 1720 a label_ref or symbol_ref within an UNSPEC. */ 1721 1722#define FIND_BASE_TERM(X) ix86_find_base_term (X) 1723 1724/* Try machine-dependent ways of modifying an illegitimate address 1725 to be legitimate. If we find one, return the new, valid address. 1726 This macro is used in only one place: `memory_address' in explow.c. 1727 1728 OLDX is the address as it was before break_out_memory_refs was called. 1729 In some cases it is useful to look at this to decide what needs to be done. 1730 1731 MODE and WIN are passed so that this macro can use 1732 GO_IF_LEGITIMATE_ADDRESS. 1733 1734 It is always safe for this macro to do nothing. It exists to recognize 1735 opportunities to optimize the output. 1736 1737 For the 80386, we handle X+REG by loading X into a register R and 1738 using R+REG. R will go in a general reg and indexing will be used. 1739 However, if REG is a broken-out memory address or multiplication, 1740 nothing needs to be done because REG can certainly go in a general reg. 1741 1742 When -fpic is used, special handling is needed for symbolic references. 1743 See comments by legitimize_pic_address in i386.c for details. */ 1744 1745#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 1746do { \ 1747 (X) = legitimize_address ((X), (OLDX), (MODE)); \ 1748 if (memory_address_p ((MODE), (X))) \ 1749 goto WIN; \ 1750} while (0) 1751 1752#define REWRITE_ADDRESS(X) rewrite_address (X) 1753 1754/* Nonzero if the constant value X is a legitimate general operand 1755 when generating PIC code. It is given that flag_pic is on and 1756 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1757 1758#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1759 1760#define SYMBOLIC_CONST(X) \ 1761 (GET_CODE (X) == SYMBOL_REF \ 1762 || GET_CODE (X) == LABEL_REF \ 1763 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 1764 1765/* Go to LABEL if ADDR (a legitimate address expression) 1766 has an effect that depends on the machine mode it is used for. 1767 On the 80386, only postdecrement and postincrement address depend thus 1768 (the amount of decrement or increment being the length of the operand). */ 1769#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 1770do { \ 1771 if (GET_CODE (ADDR) == POST_INC \ 1772 || GET_CODE (ADDR) == POST_DEC) \ 1773 goto LABEL; \ 1774} while (0) 1775 1776/* Max number of args passed in registers. If this is more than 3, we will 1777 have problems with ebx (register #4), since it is a caller save register and 1778 is also used as the pic register in ELF. So for now, don't allow more than 1779 3 registers to be passed in registers. */ 1780 1781#define REGPARM_MAX (TARGET_64BIT ? 6 : 3) 1782 1783#define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0)) 1784 1785#define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) 1786 1787 1788/* Specify the machine mode that this machine uses 1789 for the index in the tablejump instruction. */ 1790#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode) 1791 1792/* Define this as 1 if `char' should by default be signed; else as 0. */ 1793#define DEFAULT_SIGNED_CHAR 1 1794 1795/* Number of bytes moved into a data cache for a single prefetch operation. */ 1796#define PREFETCH_BLOCK ix86_cost->prefetch_block 1797 1798/* Number of prefetch operations that can be done in parallel. */ 1799#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches 1800 1801/* Max number of bytes we can move from memory to memory 1802 in one reasonably fast instruction. */ 1803#define MOVE_MAX 16 1804 1805/* MOVE_MAX_PIECES is the number of bytes at a time which we can 1806 move efficiently, as opposed to MOVE_MAX which is the maximum 1807 number of bytes we can move with a single instruction. */ 1808#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) 1809 1810/* If a memory-to-memory move would take MOVE_RATIO or more simple 1811 move-instruction pairs, we will do a movmem or libcall instead. 1812 Increasing the value will always make code faster, but eventually 1813 incurs high cost in increased code size. 1814 1815 If you don't define this, a reasonable default is used. */ 1816 1817#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) 1818 1819/* If a clear memory operation would take CLEAR_RATIO or more simple 1820 move-instruction sequences, we will do a clrmem or libcall instead. */ 1821 1822#define CLEAR_RATIO (optimize_size ? 2 \ 1823 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio) 1824 1825/* Define if shifts truncate the shift count 1826 which implies one can omit a sign-extension or zero-extension 1827 of a shift count. */ 1828/* On i386, shifts do truncate the count. But bit opcodes don't. */ 1829 1830/* #define SHIFT_COUNT_TRUNCATED */ 1831 1832/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1833 is done just by pretending it is already truncated. */ 1834#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1835 1836/* A macro to update M and UNSIGNEDP when an object whose type is 1837 TYPE and which has the specified mode and signedness is to be 1838 stored in a register. This macro is only called when TYPE is a 1839 scalar type. 1840 1841 On i386 it is sometimes useful to promote HImode and QImode 1842 quantities to SImode. The choice depends on target type. */ 1843 1844#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1845do { \ 1846 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 1847 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 1848 (MODE) = SImode; \ 1849} while (0) 1850 1851/* Specify the machine mode that pointers have. 1852 After generation of rtl, the compiler makes no further distinction 1853 between pointers and any other objects of this machine mode. */ 1854#define Pmode (TARGET_64BIT ? DImode : SImode) 1855 1856/* A function address in a call instruction 1857 is a byte address (for indexing purposes) 1858 so give the MEM rtx a byte's mode. */ 1859#define FUNCTION_MODE QImode 1860 1861/* A C expression for the cost of moving data from a register in class FROM to 1862 one in class TO. The classes are expressed using the enumeration values 1863 such as `GENERAL_REGS'. A value of 2 is the default; other values are 1864 interpreted relative to that. 1865 1866 It is not required that the cost always equal 2 when FROM is the same as TO; 1867 on some machines it is expensive to move between registers if they are not 1868 general registers. */ 1869 1870#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 1871 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) 1872 1873/* A C expression for the cost of moving data of mode M between a 1874 register and memory. A value of 2 is the default; this cost is 1875 relative to those in `REGISTER_MOVE_COST'. 1876 1877 If moving between registers and memory is more expensive than 1878 between two registers, you should define this macro to express the 1879 relative cost. */ 1880 1881#define MEMORY_MOVE_COST(MODE, CLASS, IN) \ 1882 ix86_memory_move_cost ((MODE), (CLASS), (IN)) 1883 1884/* A C expression for the cost of a branch instruction. A value of 1 1885 is the default; other values are interpreted relative to that. */ 1886 1887#define BRANCH_COST ix86_branch_cost 1888 1889/* Define this macro as a C expression which is nonzero if accessing 1890 less than a word of memory (i.e. a `char' or a `short') is no 1891 faster than accessing a word of memory, i.e., if such access 1892 require more than one instruction or if there is no difference in 1893 cost between byte and (aligned) word loads. 1894 1895 When this macro is not defined, the compiler will access a field by 1896 finding the smallest containing object; when it is defined, a 1897 fullword load will be used if alignment permits. Unless bytes 1898 accesses are faster than word accesses, using word accesses is 1899 preferable since it may eliminate subsequent memory access if 1900 subsequent accesses occur to other fields in the same word of the 1901 structure, but to different bytes. */ 1902 1903#define SLOW_BYTE_ACCESS 0 1904 1905/* Nonzero if access to memory by shorts is slow and undesirable. */ 1906#define SLOW_SHORT_ACCESS 0 1907 1908/* Define this macro to be the value 1 if unaligned accesses have a 1909 cost many times greater than aligned accesses, for example if they 1910 are emulated in a trap handler. 1911 1912 When this macro is nonzero, the compiler will act as if 1913 `STRICT_ALIGNMENT' were nonzero when generating code for block 1914 moves. This can cause significantly more instructions to be 1915 produced. Therefore, do not set this macro nonzero if unaligned 1916 accesses only add a cycle or two to the time for a memory access. 1917 1918 If the value of this macro is always zero, it need not be defined. */ 1919 1920/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 1921 1922/* Define this macro if it is as good or better to call a constant 1923 function address than to call an address kept in a register. 1924 1925 Desirable on the 386 because a CALL with a constant address is 1926 faster than one with a register address. */ 1927 1928#define NO_FUNCTION_CSE 1929 1930/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1931 return the mode to be used for the comparison. 1932 1933 For floating-point equality comparisons, CCFPEQmode should be used. 1934 VOIDmode should be used in all other cases. 1935 1936 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 1937 possible, to allow for more combinations. */ 1938 1939#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 1940 1941/* Return nonzero if MODE implies a floating point inequality can be 1942 reversed. */ 1943 1944#define REVERSIBLE_CC_MODE(MODE) 1 1945 1946/* A C expression whose value is reversed condition code of the CODE for 1947 comparison done in CC_MODE mode. */ 1948#define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) 1949 1950 1951/* Control the assembler format that we output, to the extent 1952 this does not vary between assemblers. */ 1953 1954/* How to refer to registers in assembler output. 1955 This sequence is indexed by compiler's hard-register-number (see above). */ 1956 1957/* In order to refer to the first 8 regs as 32 bit regs, prefix an "e". 1958 For non floating point regs, the following are the HImode names. 1959 1960 For float regs, the stack top is sometimes referred to as "%st(0)" 1961 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */ 1962 1963#define HI_REGISTER_NAMES \ 1964{"ax","dx","cx","bx","si","di","bp","sp", \ 1965 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ 1966 "argp", "flags", "fpsr", "dirflag", "frame", \ 1967 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 1968 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \ 1969 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 1970 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} 1971 1972#define REGISTER_NAMES HI_REGISTER_NAMES 1973 1974/* Table of additional register names to use in user input. */ 1975 1976#define ADDITIONAL_REGISTER_NAMES \ 1977{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 1978 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 1979 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 1980 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 1981 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 1982 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } } 1983 1984/* Note we are omitting these since currently I don't know how 1985to get gcc to use these, since they want the same but different 1986number as al, and ax. 1987*/ 1988 1989#define QI_REGISTER_NAMES \ 1990{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 1991 1992/* These parallel the array above, and can be used to access bits 8:15 1993 of regs 0 through 3. */ 1994 1995#define QI_HIGH_REGISTER_NAMES \ 1996{"ah", "dh", "ch", "bh", } 1997 1998/* How to renumber registers for dbx and gdb. */ 1999 2000#define DBX_REGISTER_NUMBER(N) \ 2001 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 2002 2003extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 2004extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 2005extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 2006 2007/* Before the prologue, RA is at 0(%esp). */ 2008#define INCOMING_RETURN_ADDR_RTX \ 2009 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 2010 2011/* After the prologue, RA is at -4(AP) in the current frame. */ 2012#define RETURN_ADDR_RTX(COUNT, FRAME) \ 2013 ((COUNT) == 0 \ 2014 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ 2015 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) 2016 2017/* PC is dbx register 8; let's use that column for RA. */ 2018#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 2019 2020/* Before the prologue, the top of the frame is at 4(%esp). */ 2021#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 2022 2023/* Describe how we implement __builtin_eh_return. */ 2024#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 2025#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 2026 2027 2028/* Select a format to encode pointers in exception handling data. CODE 2029 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 2030 true if the symbol may be affected by dynamic relocations. 2031 2032 ??? All x86 object file formats are capable of representing this. 2033 After all, the relocation needed is the same as for the call insn. 2034 Whether or not a particular assembler allows us to enter such, I 2035 guess we'll have to see. */ 2036#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 2037 asm_preferred_eh_data_format ((CODE), (GLOBAL)) 2038 2039/* This is how to output an insn to push a register on the stack. 2040 It need not be very fast code. */ 2041 2042#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 2043do { \ 2044 if (TARGET_64BIT) \ 2045 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ 2046 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2047 else \ 2048 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2049} while (0) 2050 2051/* This is how to output an insn to pop a register from the stack. 2052 It need not be very fast code. */ 2053 2054#define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 2055do { \ 2056 if (TARGET_64BIT) \ 2057 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ 2058 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2059 else \ 2060 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2061} while (0) 2062 2063/* This is how to output an element of a case-vector that is absolute. */ 2064 2065#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2066 ix86_output_addr_vec_elt ((FILE), (VALUE)) 2067 2068/* This is how to output an element of a case-vector that is relative. */ 2069 2070#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2071 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 2072 2073/* Under some conditions we need jump tables in the text section, because 2074 the assembler cannot handle label differences between sections. */ 2075 2076#define JUMP_TABLES_IN_TEXT_SECTION \ 2077 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA) 2078 2079/* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2080 and switch back. For x86 we do this only to save a few bytes that 2081 would otherwise be unused in the text section. */ 2082#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2083 asm (SECTION_OP "\n\t" \ 2084 "call " USER_LABEL_PREFIX #FUNC "\n" \ 2085 TEXT_SECTION_ASM_OP); 2086 2087/* Print operand X (an rtx) in assembler syntax to file FILE. 2088 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2089 Effect of various CODE letters is described in i386.c near 2090 print_operand function. */ 2091 2092#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2093 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&') 2094 2095#define PRINT_OPERAND(FILE, X, CODE) \ 2096 print_operand ((FILE), (X), (CODE)) 2097 2098#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2099 print_operand_address ((FILE), (ADDR)) 2100 2101#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ 2102do { \ 2103 if (! output_addr_const_extra (FILE, (X))) \ 2104 goto FAIL; \ 2105} while (0); 2106 2107/* a letter which is not needed by the normal asm syntax, which 2108 we can use for operand syntax in the extended asm */ 2109 2110#define ASM_OPERAND_LETTER '#' 2111#define RET return "" 2112#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx)) 2113 2114/* Which processor to schedule for. The cpu attribute defines a list that 2115 mirrors this list, so changes to i386.md must be made at the same time. */ 2116 2117enum processor_type 2118{ 2119 PROCESSOR_I386, /* 80386 */ 2120 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 2121 PROCESSOR_PENTIUM, 2122 PROCESSOR_PENTIUMPRO, 2123 PROCESSOR_K6, 2124 PROCESSOR_ATHLON, 2125 PROCESSOR_PENTIUM4, 2126 PROCESSOR_K8, 2127 PROCESSOR_NOCONA, 2128 PROCESSOR_max 2129}; 2130 2131extern enum processor_type ix86_tune; 2132extern enum processor_type ix86_arch; 2133 2134enum fpmath_unit 2135{ 2136 FPMATH_387 = 1, 2137 FPMATH_SSE = 2 2138}; 2139 2140extern enum fpmath_unit ix86_fpmath; 2141 2142enum tls_dialect 2143{ 2144 TLS_DIALECT_GNU, 2145 TLS_DIALECT_SUN 2146}; 2147 2148extern enum tls_dialect ix86_tls_dialect; 2149 2150enum cmodel { 2151 CM_32, /* The traditional 32-bit ABI. */ 2152 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ 2153 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ 2154 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ 2155 CM_LARGE, /* No assumptions. */ 2156 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */ 2157 CM_MEDIUM_PIC /* Assumes code+got/plt fits in a 31 bit region. */ 2158}; 2159 2160extern enum cmodel ix86_cmodel; 2161 2162/* Size of the RED_ZONE area. */ 2163#define RED_ZONE_SIZE 128 2164/* Reserved area of the red zone for temporaries. */ 2165#define RED_ZONE_RESERVE 8 2166 2167enum asm_dialect { 2168 ASM_ATT, 2169 ASM_INTEL 2170}; 2171 2172extern enum asm_dialect ix86_asm_dialect; 2173extern unsigned int ix86_preferred_stack_boundary; 2174extern int ix86_branch_cost, ix86_section_threshold; 2175 2176/* Smallest class containing REGNO. */ 2177extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; 2178 2179extern rtx ix86_compare_op0; /* operand 0 for comparisons */ 2180extern rtx ix86_compare_op1; /* operand 1 for comparisons */ 2181extern rtx ix86_compare_emitted; 2182 2183/* To properly truncate FP values into integers, we need to set i387 control 2184 word. We can't emit proper mode switching code before reload, as spills 2185 generated by reload may truncate values incorrectly, but we still can avoid 2186 redundant computation of new control word by the mode switching pass. 2187 The fldcw instructions are still emitted redundantly, but this is probably 2188 not going to be noticeable problem, as most CPUs do have fast path for 2189 the sequence. 2190 2191 The machinery is to emit simple truncation instructions and split them 2192 before reload to instructions having USEs of two memory locations that 2193 are filled by this code to old and new control word. 2194 2195 Post-reload pass may be later used to eliminate the redundant fildcw if 2196 needed. */ 2197 2198enum ix86_entity 2199{ 2200 I387_TRUNC = 0, 2201 I387_FLOOR, 2202 I387_CEIL, 2203 I387_MASK_PM, 2204 MAX_386_ENTITIES 2205}; 2206 2207enum ix86_stack_slot 2208{ 2209 SLOT_VIRTUAL = 0, 2210 SLOT_TEMP, 2211 SLOT_CW_STORED, 2212 SLOT_CW_TRUNC, 2213 SLOT_CW_FLOOR, 2214 SLOT_CW_CEIL, 2215 SLOT_CW_MASK_PM, 2216 MAX_386_STACK_LOCALS 2217}; 2218 2219/* Define this macro if the port needs extra instructions inserted 2220 for mode switching in an optimizing compilation. */ 2221 2222#define OPTIMIZE_MODE_SWITCHING(ENTITY) \ 2223 ix86_optimize_mode_switching[(ENTITY)] 2224 2225/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 2226 initializer for an array of integers. Each initializer element N 2227 refers to an entity that needs mode switching, and specifies the 2228 number of different modes that might need to be set for this 2229 entity. The position of the initializer in the initializer - 2230 starting counting at zero - determines the integer that is used to 2231 refer to the mode-switched entity in question. */ 2232 2233#define NUM_MODES_FOR_MODE_SWITCHING \ 2234 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } 2235 2236/* ENTITY is an integer specifying a mode-switched entity. If 2237 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to 2238 return an integer value not larger than the corresponding element 2239 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY 2240 must be switched into prior to the execution of INSN. */ 2241 2242#define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I)) 2243 2244/* This macro specifies the order in which modes for ENTITY are 2245 processed. 0 is the highest priority. */ 2246 2247#define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) 2248 2249/* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE 2250 is the set of hard registers live at the point where the insn(s) 2251 are to be inserted. */ 2252 2253#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 2254 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \ 2255 ? emit_i387_cw_initialization (MODE), 0 \ 2256 : 0) 2257 2258 2259/* Avoid renaming of stack registers, as doing so in combination with 2260 scheduling just increases amount of live registers at time and in 2261 the turn amount of fxch instructions needed. 2262 2263 ??? Maybe Pentium chips benefits from renaming, someone can try.... */ 2264 2265#define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 2266 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG) 2267 2268 2269#define DLL_IMPORT_EXPORT_PREFIX '#' 2270 2271#define FASTCALL_PREFIX '@' 2272 2273struct machine_function GTY(()) 2274{ 2275 struct stack_local_entry *stack_locals; 2276 const char *some_ld_name; 2277 rtx force_align_arg_pointer; 2278 int save_varrargs_registers; 2279 int accesses_prev_frame; 2280 int optimize_mode_switching[MAX_386_ENTITIES]; 2281 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to 2282 determine the style used. */ 2283 int use_fast_prologue_epilogue; 2284 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed 2285 for. */ 2286 int use_fast_prologue_epilogue_nregs; 2287}; 2288 2289#define ix86_stack_locals (cfun->machine->stack_locals) 2290#define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers) 2291#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) 2292 2293/* Control behavior of x86_file_start. */ 2294#define X86_FILE_START_VERSION_DIRECTIVE false 2295#define X86_FILE_START_FLTUSED false 2296 2297/* Flag to mark data that is in the large address area. */ 2298#define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) 2299#define SYMBOL_REF_FAR_ADDR_P(X) \ 2300 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) 2301/* 2302Local variables: 2303version-control: t 2304End: 2305*/ 2306