1/* CPU family header for sh64. 2 3THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5Copyright 1996-2010 Free Software Foundation, Inc. 6 7This file is part of the GNU simulators. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22 23*/ 24 25#ifndef CPU_SH64_H 26#define CPU_SH64_H 27 28/* Maximum number of instructions that are fetched at a time. 29 This is for LIW type instructions sets (e.g. m32r). */ 30#define MAX_LIW_INSNS 1 31 32/* Maximum number of instructions that can be executed in parallel. */ 33#define MAX_PARALLEL_INSNS 1 34 35/* The size of an "int" needed to hold an instruction word. 36 This is usually 32 bits, but some architectures needs 64 bits. */ 37typedef CGEN_INSN_INT CGEN_INSN_WORD; 38 39#include "cgen-engine.h" 40 41/* CPU state information. */ 42typedef struct { 43 /* Hardware elements. */ 44 struct { 45 /* Program counter */ 46 UDI h_pc; 47#define GET_H_PC() CPU (h_pc) 48#define SET_H_PC(x) \ 49do { \ 50{\ 51CPU (h_ism) = ANDDI ((x), 1);\ 52CPU (h_pc) = ANDDI ((x), INVDI (1));\ 53}\ 54;} while (0) 55 /* General purpose integer registers */ 56 DI h_gr[64]; 57#define GET_H_GR(index) ((((index) == (63))) ? (MAKEDI (0, 0)) : (CPU (h_gr[index]))) 58#define SET_H_GR(index, x) \ 59do { \ 60if ((((index)) != (63))) {\ 61CPU (h_gr[(index)]) = (x);\ 62} else {\ 63((void) 0); /*nop*/\ 64}\ 65;} while (0) 66 /* Control registers */ 67 DI h_cr[64]; 68#define GET_H_CR(index) ((((index) == (0))) ? (ZEXTSIDI (CPU (h_sr))) : (CPU (h_cr[index]))) 69#define SET_H_CR(index, x) \ 70do { \ 71if ((((index)) == (0))) {\ 72CPU (h_sr) = (x);\ 73} else {\ 74CPU (h_cr[(index)]) = (x);\ 75}\ 76;} while (0) 77 /* Status register */ 78 SI h_sr; 79#define GET_H_SR() CPU (h_sr) 80#define SET_H_SR(x) (CPU (h_sr) = (x)) 81 /* Floating point status and control register */ 82 SI h_fpscr; 83#define GET_H_FPSCR() CPU (h_fpscr) 84#define SET_H_FPSCR(x) (CPU (h_fpscr) = (x)) 85 /* Single precision floating point registers */ 86 SF h_fr[64]; 87#define GET_H_FR(a1) CPU (h_fr)[a1] 88#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x)) 89 /* Single/Double precision floating point registers */ 90 DF h_fsd[16]; 91#define GET_H_FSD(index) ((GET_H_PRBIT ()) ? (GET_H_DRC (index)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, CPU (h_fr[index])))) 92#define SET_H_FSD(index, x) \ 93do { \ 94if (GET_H_PRBIT ()) {\ 95SET_H_DRC ((index), (x));\ 96} else {\ 97SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, (x)));\ 98}\ 99;} while (0) 100 /* floating point registers for fmov */ 101 DF h_fmov[16]; 102#define GET_H_FMOV(index) ((NOTBI (GET_H_SZBIT ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, GET_H_FRC (index))) : (((((((index) & (1))) == (1))) ? (GET_H_XD (((index) & ((~ (1)))))) : (GET_H_DR (index))))) 103#define SET_H_FMOV(index, x) \ 104do { \ 105if (NOTBI (GET_H_SZBIT ())) {\ 106SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, (x)));\ 107} else {\ 108if ((((((index)) & (1))) == (1))) {\ 109SET_H_XD ((((index)) & ((~ (1)))), (x));\ 110} else {\ 111SET_H_DR ((index), (x));\ 112}\ 113}\ 114;} while (0) 115 /* Branch target registers */ 116 DI h_tr[8]; 117#define GET_H_TR(a1) CPU (h_tr)[a1] 118#define SET_H_TR(a1, x) (CPU (h_tr)[a1] = (x)) 119 /* Current instruction set mode */ 120 BI h_ism; 121#define GET_H_ISM() CPU (h_ism) 122#define SET_H_ISM(x) \ 123do { \ 124cgen_rtx_error (current_cpu, "cannot set ism directly");\ 125;} while (0) 126 } hardware; 127#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) 128} SH64_CPU_DATA; 129 130/* Virtual regs. */ 131 132#define GET_H_GRC(index) ANDDI (CPU (h_gr[index]), ZEXTSIDI (0xffffffff)) 133#define SET_H_GRC(index, x) \ 134do { \ 135CPU (h_gr[(index)]) = EXTSIDI ((x));\ 136;} while (0) 137#define GET_H_FRBIT() ANDSI (SRLSI (CPU (h_fpscr), 21), 1) 138#define SET_H_FRBIT(x) \ 139do { \ 140CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (21))))), SLLSI ((x), 21));\ 141;} while (0) 142#define GET_H_SZBIT() ANDSI (SRLSI (CPU (h_fpscr), 20), 1) 143#define SET_H_SZBIT(x) \ 144do { \ 145CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (20))))), SLLSI ((x), 20));\ 146;} while (0) 147#define GET_H_PRBIT() ANDSI (SRLSI (CPU (h_fpscr), 19), 1) 148#define SET_H_PRBIT(x) \ 149do { \ 150CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (19))))), SLLSI ((x), 19));\ 151;} while (0) 152#define GET_H_SBIT() ANDSI (SRLSI (CPU (h_sr), 1), 1) 153#define SET_H_SBIT(x) \ 154do { \ 155CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (2))), SLLSI ((x), 1));\ 156;} while (0) 157#define GET_H_MBIT() ANDSI (SRLSI (CPU (h_sr), 9), 1) 158#define SET_H_MBIT(x) \ 159do { \ 160CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (9))))), SLLSI ((x), 9));\ 161;} while (0) 162#define GET_H_QBIT() ANDSI (SRLSI (CPU (h_sr), 8), 1) 163#define SET_H_QBIT(x) \ 164do { \ 165CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (8))))), SLLSI ((x), 8));\ 166;} while (0) 167#define GET_H_FP(index) CPU (h_fr[index]) 168#define SET_H_FP(index, x) \ 169do { \ 170CPU (h_fr[(index)]) = (x);\ 171;} while (0) 172#define GET_H_FV(index) CPU (h_fr[index]) 173#define SET_H_FV(index, x) \ 174do { \ 175CPU (h_fr[(index)]) = (x);\ 176;} while (0) 177#define GET_H_FMTX(index) CPU (h_fr[index]) 178#define SET_H_FMTX(index, x) \ 179do { \ 180CPU (h_fr[(index)]) = (x);\ 181;} while (0) 182#define GET_H_DR(index) SUBWORDDIDF (ORDI (SLLDI (ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[index]))), 32), ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[((index) + (1))]))))) 183#define SET_H_DR(index, x) \ 184do { \ 185{\ 186CPU (h_fr[(index)]) = SUBWORDSISF (SUBWORDDFSI ((x), 0));\ 187CPU (h_fr[(((index)) + (1))]) = SUBWORDSISF (SUBWORDDFSI ((x), 1));\ 188}\ 189;} while (0) 190#define GET_H_ENDIAN() sh64_endian (current_cpu) 191#define SET_H_ENDIAN(x) \ 192do { \ 193cgen_rtx_error (current_cpu, "cannot alter target byte order mid-program");\ 194;} while (0) 195#define GET_H_FRC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))]) 196#define SET_H_FRC(index, x) \ 197do { \ 198CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\ 199;} while (0) 200#define GET_H_DRC(index) GET_H_DR (((((16) * (GET_H_FRBIT ()))) + (index))) 201#define SET_H_DRC(index, x) \ 202do { \ 203SET_H_DR (((((16) * (GET_H_FRBIT ()))) + ((index))), (x));\ 204;} while (0) 205#define GET_H_XF(index) CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + (index))]) 206#define SET_H_XF(index, x) \ 207do { \ 208CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index)))]) = (x);\ 209;} while (0) 210#define GET_H_XD(index) GET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + (index))) 211#define SET_H_XD(index, x) \ 212do { \ 213SET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index))), (x));\ 214;} while (0) 215#define GET_H_FVC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))]) 216#define SET_H_FVC(index, x) \ 217do { \ 218CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\ 219;} while (0) 220#define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1) 221#define SET_H_GBR(x) \ 222do { \ 223CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\ 224;} while (0) 225#define GET_H_VBR() SUBWORDDISI (CPU (h_gr[((UINT) 20)]), 1) 226#define SET_H_VBR(x) \ 227do { \ 228CPU (h_gr[((UINT) 20)]) = EXTSIDI ((x));\ 229;} while (0) 230#define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UINT) 18)]), 1) 231#define SET_H_PR(x) \ 232do { \ 233CPU (h_gr[((UINT) 18)]) = EXTSIDI ((x));\ 234;} while (0) 235#define GET_H_MACL() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1) 236#define SET_H_MACL(x) \ 237do { \ 238CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)), 32), ZEXTSIDI ((x)));\ 239;} while (0) 240#define GET_H_MACH() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0) 241#define SET_H_MACH(x) \ 242do { \ 243CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI ((x)), 32), ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)));\ 244;} while (0) 245#define GET_H_TBIT() ANDBI (CPU (h_gr[((UINT) 19)]), 1) 246#define SET_H_TBIT(x) \ 247do { \ 248CPU (h_gr[((UINT) 19)]) = ORDI (ANDDI (CPU (h_gr[((UINT) 19)]), INVDI (1)), ZEXTBIDI ((x)));\ 249;} while (0) 250 251/* Cover fns for register access. */ 252UDI sh64_h_pc_get (SIM_CPU *); 253void sh64_h_pc_set (SIM_CPU *, UDI); 254DI sh64_h_gr_get (SIM_CPU *, UINT); 255void sh64_h_gr_set (SIM_CPU *, UINT, DI); 256SI sh64_h_grc_get (SIM_CPU *, UINT); 257void sh64_h_grc_set (SIM_CPU *, UINT, SI); 258DI sh64_h_cr_get (SIM_CPU *, UINT); 259void sh64_h_cr_set (SIM_CPU *, UINT, DI); 260SI sh64_h_sr_get (SIM_CPU *); 261void sh64_h_sr_set (SIM_CPU *, SI); 262SI sh64_h_fpscr_get (SIM_CPU *); 263void sh64_h_fpscr_set (SIM_CPU *, SI); 264BI sh64_h_frbit_get (SIM_CPU *); 265void sh64_h_frbit_set (SIM_CPU *, BI); 266BI sh64_h_szbit_get (SIM_CPU *); 267void sh64_h_szbit_set (SIM_CPU *, BI); 268BI sh64_h_prbit_get (SIM_CPU *); 269void sh64_h_prbit_set (SIM_CPU *, BI); 270BI sh64_h_sbit_get (SIM_CPU *); 271void sh64_h_sbit_set (SIM_CPU *, BI); 272BI sh64_h_mbit_get (SIM_CPU *); 273void sh64_h_mbit_set (SIM_CPU *, BI); 274BI sh64_h_qbit_get (SIM_CPU *); 275void sh64_h_qbit_set (SIM_CPU *, BI); 276SF sh64_h_fr_get (SIM_CPU *, UINT); 277void sh64_h_fr_set (SIM_CPU *, UINT, SF); 278SF sh64_h_fp_get (SIM_CPU *, UINT); 279void sh64_h_fp_set (SIM_CPU *, UINT, SF); 280SF sh64_h_fv_get (SIM_CPU *, UINT); 281void sh64_h_fv_set (SIM_CPU *, UINT, SF); 282SF sh64_h_fmtx_get (SIM_CPU *, UINT); 283void sh64_h_fmtx_set (SIM_CPU *, UINT, SF); 284DF sh64_h_dr_get (SIM_CPU *, UINT); 285void sh64_h_dr_set (SIM_CPU *, UINT, DF); 286DF sh64_h_fsd_get (SIM_CPU *, UINT); 287void sh64_h_fsd_set (SIM_CPU *, UINT, DF); 288DF sh64_h_fmov_get (SIM_CPU *, UINT); 289void sh64_h_fmov_set (SIM_CPU *, UINT, DF); 290DI sh64_h_tr_get (SIM_CPU *, UINT); 291void sh64_h_tr_set (SIM_CPU *, UINT, DI); 292BI sh64_h_endian_get (SIM_CPU *); 293void sh64_h_endian_set (SIM_CPU *, BI); 294BI sh64_h_ism_get (SIM_CPU *); 295void sh64_h_ism_set (SIM_CPU *, BI); 296SF sh64_h_frc_get (SIM_CPU *, UINT); 297void sh64_h_frc_set (SIM_CPU *, UINT, SF); 298DF sh64_h_drc_get (SIM_CPU *, UINT); 299void sh64_h_drc_set (SIM_CPU *, UINT, DF); 300SF sh64_h_xf_get (SIM_CPU *, UINT); 301void sh64_h_xf_set (SIM_CPU *, UINT, SF); 302DF sh64_h_xd_get (SIM_CPU *, UINT); 303void sh64_h_xd_set (SIM_CPU *, UINT, DF); 304SF sh64_h_fvc_get (SIM_CPU *, UINT); 305void sh64_h_fvc_set (SIM_CPU *, UINT, SF); 306SI sh64_h_gbr_get (SIM_CPU *); 307void sh64_h_gbr_set (SIM_CPU *, SI); 308SI sh64_h_vbr_get (SIM_CPU *); 309void sh64_h_vbr_set (SIM_CPU *, SI); 310SI sh64_h_pr_get (SIM_CPU *); 311void sh64_h_pr_set (SIM_CPU *, SI); 312SI sh64_h_macl_get (SIM_CPU *); 313void sh64_h_macl_set (SIM_CPU *, SI); 314SI sh64_h_mach_get (SIM_CPU *); 315void sh64_h_mach_set (SIM_CPU *, SI); 316BI sh64_h_tbit_get (SIM_CPU *); 317void sh64_h_tbit_set (SIM_CPU *, BI); 318 319/* These must be hand-written. */ 320extern CPUREG_FETCH_FN sh64_fetch_register; 321extern CPUREG_STORE_FN sh64_store_register; 322 323typedef struct { 324 int empty; 325} MODEL_SH4_DATA; 326 327typedef struct { 328 int empty; 329} MODEL_SH5_DATA; 330 331typedef struct { 332 int empty; 333} MODEL_SH5_MEDIA_DATA; 334 335/* Collection of various things for the trace handler to use. */ 336 337typedef struct trace_record { 338 IADDR pc; 339 /* FIXME:wip */ 340} TRACE_RECORD; 341 342#endif /* CPU_SH64_H */ 343