1/* CPU family header for iq2000bf. 2 3THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5Copyright 1996-2010 Free Software Foundation, Inc. 6 7This file is part of the GNU simulators. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22 23*/ 24 25#ifndef CPU_IQ2000BF_H 26#define CPU_IQ2000BF_H 27 28/* Maximum number of instructions that are fetched at a time. 29 This is for LIW type instructions sets (e.g. m32r). */ 30#define MAX_LIW_INSNS 1 31 32/* Maximum number of instructions that can be executed in parallel. */ 33#define MAX_PARALLEL_INSNS 1 34 35/* The size of an "int" needed to hold an instruction word. 36 This is usually 32 bits, but some architectures needs 64 bits. */ 37typedef CGEN_INSN_INT CGEN_INSN_WORD; 38 39#include "cgen-engine.h" 40 41/* CPU state information. */ 42typedef struct { 43 /* Hardware elements. */ 44 struct { 45 /* program counter */ 46 USI h_pc; 47#define GET_H_PC() get_h_pc (current_cpu) 48#define SET_H_PC(x) \ 49do { \ 50set_h_pc (current_cpu, (x));\ 51;} while (0) 52 /* General purpose registers */ 53 SI h_gr[32]; 54#define GET_H_GR(index) (((index) == (0))) ? (0) : (CPU (h_gr[index])) 55#define SET_H_GR(index, x) \ 56do { \ 57if ((((index)) == (0))) {\ 58((void) 0); /*nop*/\ 59}\ 60 else {\ 61CPU (h_gr[(index)]) = (x);\ 62}\ 63;} while (0) 64 } hardware; 65#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) 66} IQ2000BF_CPU_DATA; 67 68/* Cover fns for register access. */ 69USI iq2000bf_h_pc_get (SIM_CPU *); 70void iq2000bf_h_pc_set (SIM_CPU *, USI); 71SI iq2000bf_h_gr_get (SIM_CPU *, UINT); 72void iq2000bf_h_gr_set (SIM_CPU *, UINT, SI); 73 74/* These must be hand-written. */ 75extern CPUREG_FETCH_FN iq2000bf_fetch_register; 76extern CPUREG_STORE_FN iq2000bf_store_register; 77 78typedef struct { 79 int empty; 80} MODEL_IQ2000_DATA; 81 82/* Instruction argument buffer. */ 83 84union sem_fields { 85 struct { /* no operands */ 86 int empty; 87 } sfmt_empty; 88 struct { /* */ 89 IADDR i_jmptarg; 90 } sfmt_j; 91 struct { /* */ 92 IADDR i_offset; 93 UINT f_rs; 94 UINT f_rt; 95 } sfmt_bbi; 96 struct { /* */ 97 UINT f_imm; 98 UINT f_rs; 99 UINT f_rt; 100 } sfmt_addi; 101 struct { /* */ 102 UINT f_mask; 103 UINT f_rd; 104 UINT f_rs; 105 UINT f_rt; 106 } sfmt_mrgb; 107 struct { /* */ 108 UINT f_maskl; 109 UINT f_rd; 110 UINT f_rs; 111 UINT f_rt; 112 UINT f_shamt; 113 } sfmt_ram; 114#if WITH_SCACHE_PBB 115 /* Writeback handler. */ 116 struct { 117 /* Pointer to argbuf entry for insn whose results need writing back. */ 118 const struct argbuf *abuf; 119 } write; 120 /* x-before handler */ 121 struct { 122 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/ 123 int first_p; 124 } before; 125 /* x-after handler */ 126 struct { 127 int empty; 128 } after; 129 /* This entry is used to terminate each pbb. */ 130 struct { 131 /* Number of insns in pbb. */ 132 int insn_count; 133 /* Next pbb to execute. */ 134 SCACHE *next; 135 SCACHE *branch_target; 136 } chain; 137#endif 138}; 139 140/* The ARGBUF struct. */ 141struct argbuf { 142 /* These are the baseclass definitions. */ 143 IADDR addr; 144 const IDESC *idesc; 145 char trace_p; 146 char profile_p; 147 /* ??? Temporary hack for skip insns. */ 148 char skip_count; 149 char unused; 150 /* cpu specific data follows */ 151 union sem semantic; 152 int written; 153 union sem_fields fields; 154}; 155 156/* A cached insn. 157 158 ??? SCACHE used to contain more than just argbuf. We could delete the 159 type entirely and always just use ARGBUF, but for future concerns and as 160 a level of abstraction it is left in. */ 161 162struct scache { 163 struct argbuf argbuf; 164}; 165 166/* Macros to simplify extraction, reading and semantic code. 167 These define and assign the local vars that contain the insn's fields. */ 168 169#define EXTRACT_IFMT_EMPTY_VARS \ 170 unsigned int length; 171#define EXTRACT_IFMT_EMPTY_CODE \ 172 length = 0; \ 173 174#define EXTRACT_IFMT_ADD_VARS \ 175 UINT f_opcode; \ 176 UINT f_rs; \ 177 UINT f_rt; \ 178 UINT f_rd; \ 179 UINT f_shamt; \ 180 UINT f_func; \ 181 unsigned int length; 182#define EXTRACT_IFMT_ADD_CODE \ 183 length = 4; \ 184 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 185 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 186 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 187 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ 188 f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ 189 f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ 190 191#define EXTRACT_IFMT_ADDI_VARS \ 192 UINT f_opcode; \ 193 UINT f_rs; \ 194 UINT f_rt; \ 195 UINT f_imm; \ 196 unsigned int length; 197#define EXTRACT_IFMT_ADDI_CODE \ 198 length = 4; \ 199 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 200 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 201 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 202 f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ 203 204#define EXTRACT_IFMT_RAM_VARS \ 205 UINT f_opcode; \ 206 UINT f_rs; \ 207 UINT f_rt; \ 208 UINT f_rd; \ 209 UINT f_shamt; \ 210 UINT f_5; \ 211 UINT f_maskl; \ 212 unsigned int length; 213#define EXTRACT_IFMT_RAM_CODE \ 214 length = 4; \ 215 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 216 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 217 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 218 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ 219 f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ 220 f_5 = EXTRACT_LSB0_UINT (insn, 32, 5, 1); \ 221 f_maskl = EXTRACT_LSB0_UINT (insn, 32, 4, 5); \ 222 223#define EXTRACT_IFMT_SLL_VARS \ 224 UINT f_opcode; \ 225 UINT f_rs; \ 226 UINT f_rt; \ 227 UINT f_rd; \ 228 UINT f_shamt; \ 229 UINT f_func; \ 230 unsigned int length; 231#define EXTRACT_IFMT_SLL_CODE \ 232 length = 4; \ 233 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 234 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 235 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 236 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ 237 f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ 238 f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ 239 240#define EXTRACT_IFMT_SLMV_VARS \ 241 UINT f_opcode; \ 242 UINT f_rs; \ 243 UINT f_rt; \ 244 UINT f_rd; \ 245 UINT f_shamt; \ 246 UINT f_func; \ 247 unsigned int length; 248#define EXTRACT_IFMT_SLMV_CODE \ 249 length = 4; \ 250 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 251 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 252 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 253 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ 254 f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ 255 f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ 256 257#define EXTRACT_IFMT_SLTI_VARS \ 258 UINT f_opcode; \ 259 UINT f_rs; \ 260 UINT f_rt; \ 261 UINT f_imm; \ 262 unsigned int length; 263#define EXTRACT_IFMT_SLTI_CODE \ 264 length = 4; \ 265 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 266 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 267 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 268 f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ 269 270#define EXTRACT_IFMT_BBI_VARS \ 271 UINT f_opcode; \ 272 UINT f_rs; \ 273 UINT f_rt; \ 274 SI f_offset; \ 275 unsigned int length; 276#define EXTRACT_IFMT_BBI_CODE \ 277 length = 4; \ 278 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 279 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 280 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 281 f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \ 282 283#define EXTRACT_IFMT_BBV_VARS \ 284 UINT f_opcode; \ 285 UINT f_rs; \ 286 UINT f_rt; \ 287 SI f_offset; \ 288 unsigned int length; 289#define EXTRACT_IFMT_BBV_CODE \ 290 length = 4; \ 291 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 292 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 293 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 294 f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \ 295 296#define EXTRACT_IFMT_BGEZ_VARS \ 297 UINT f_opcode; \ 298 UINT f_rs; \ 299 UINT f_rt; \ 300 SI f_offset; \ 301 unsigned int length; 302#define EXTRACT_IFMT_BGEZ_CODE \ 303 length = 4; \ 304 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 305 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 306 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 307 f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \ 308 309#define EXTRACT_IFMT_JALR_VARS \ 310 UINT f_opcode; \ 311 UINT f_rs; \ 312 UINT f_rt; \ 313 UINT f_rd; \ 314 UINT f_shamt; \ 315 UINT f_func; \ 316 unsigned int length; 317#define EXTRACT_IFMT_JALR_CODE \ 318 length = 4; \ 319 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 320 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 321 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 322 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ 323 f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ 324 f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ 325 326#define EXTRACT_IFMT_JR_VARS \ 327 UINT f_opcode; \ 328 UINT f_rs; \ 329 UINT f_rt; \ 330 UINT f_rd; \ 331 UINT f_shamt; \ 332 UINT f_func; \ 333 unsigned int length; 334#define EXTRACT_IFMT_JR_CODE \ 335 length = 4; \ 336 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 337 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 338 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 339 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ 340 f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ 341 f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ 342 343#define EXTRACT_IFMT_LB_VARS \ 344 UINT f_opcode; \ 345 UINT f_rs; \ 346 UINT f_rt; \ 347 UINT f_imm; \ 348 unsigned int length; 349#define EXTRACT_IFMT_LB_CODE \ 350 length = 4; \ 351 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 352 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 353 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 354 f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ 355 356#define EXTRACT_IFMT_LUI_VARS \ 357 UINT f_opcode; \ 358 UINT f_rs; \ 359 UINT f_rt; \ 360 UINT f_imm; \ 361 unsigned int length; 362#define EXTRACT_IFMT_LUI_CODE \ 363 length = 4; \ 364 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 365 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 366 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 367 f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ 368 369#define EXTRACT_IFMT_BREAK_VARS \ 370 UINT f_opcode; \ 371 UINT f_rs; \ 372 UINT f_rt; \ 373 UINT f_rd; \ 374 UINT f_shamt; \ 375 UINT f_func; \ 376 unsigned int length; 377#define EXTRACT_IFMT_BREAK_CODE \ 378 length = 4; \ 379 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 380 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 381 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 382 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ 383 f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ 384 f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ 385 386#define EXTRACT_IFMT_SYSCALL_VARS \ 387 UINT f_opcode; \ 388 UINT f_excode; \ 389 UINT f_func; \ 390 unsigned int length; 391#define EXTRACT_IFMT_SYSCALL_CODE \ 392 length = 4; \ 393 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 394 f_excode = EXTRACT_LSB0_UINT (insn, 32, 25, 20); \ 395 f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ 396 397#define EXTRACT_IFMT_ANDOUI_VARS \ 398 UINT f_opcode; \ 399 UINT f_rs; \ 400 UINT f_rt; \ 401 UINT f_imm; \ 402 unsigned int length; 403#define EXTRACT_IFMT_ANDOUI_CODE \ 404 length = 4; \ 405 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 406 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 407 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 408 f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ 409 410#define EXTRACT_IFMT_MRGB_VARS \ 411 UINT f_opcode; \ 412 UINT f_rs; \ 413 UINT f_rt; \ 414 UINT f_rd; \ 415 UINT f_10; \ 416 UINT f_mask; \ 417 UINT f_func; \ 418 unsigned int length; 419#define EXTRACT_IFMT_MRGB_CODE \ 420 length = 4; \ 421 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 422 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 423 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 424 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ 425 f_10 = EXTRACT_LSB0_UINT (insn, 32, 10, 1); \ 426 f_mask = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \ 427 f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ 428 429#define EXTRACT_IFMT_BC0F_VARS \ 430 UINT f_opcode; \ 431 UINT f_rs; \ 432 UINT f_rt; \ 433 SI f_offset; \ 434 unsigned int length; 435#define EXTRACT_IFMT_BC0F_CODE \ 436 length = 4; \ 437 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 438 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 439 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 440 f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \ 441 442#define EXTRACT_IFMT_CFC0_VARS \ 443 UINT f_opcode; \ 444 UINT f_rs; \ 445 UINT f_rt; \ 446 UINT f_rd; \ 447 UINT f_10_11; \ 448 unsigned int length; 449#define EXTRACT_IFMT_CFC0_CODE \ 450 length = 4; \ 451 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 452 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 453 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 454 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ 455 f_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \ 456 457#define EXTRACT_IFMT_CHKHDR_VARS \ 458 UINT f_opcode; \ 459 UINT f_rs; \ 460 UINT f_rt; \ 461 UINT f_rd; \ 462 UINT f_shamt; \ 463 UINT f_func; \ 464 unsigned int length; 465#define EXTRACT_IFMT_CHKHDR_CODE \ 466 length = 4; \ 467 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 468 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 469 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 470 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ 471 f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ 472 f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ 473 474#define EXTRACT_IFMT_LULCK_VARS \ 475 UINT f_opcode; \ 476 UINT f_rs; \ 477 UINT f_rt; \ 478 UINT f_rd; \ 479 UINT f_shamt; \ 480 UINT f_func; \ 481 unsigned int length; 482#define EXTRACT_IFMT_LULCK_CODE \ 483 length = 4; \ 484 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 485 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 486 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 487 f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ 488 f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ 489 f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ 490 491#define EXTRACT_IFMT_PKRLR1_VARS \ 492 UINT f_opcode; \ 493 UINT f_rs; \ 494 UINT f_rt; \ 495 UINT f_count; \ 496 UINT f_index; \ 497 unsigned int length; 498#define EXTRACT_IFMT_PKRLR1_CODE \ 499 length = 4; \ 500 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 501 f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ 502 f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ 503 f_count = EXTRACT_LSB0_UINT (insn, 32, 15, 7); \ 504 f_index = EXTRACT_LSB0_UINT (insn, 32, 8, 9); \ 505 506#define EXTRACT_IFMT_RFE_VARS \ 507 UINT f_opcode; \ 508 UINT f_25; \ 509 UINT f_24_19; \ 510 UINT f_func; \ 511 unsigned int length; 512#define EXTRACT_IFMT_RFE_CODE \ 513 length = 4; \ 514 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 515 f_25 = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \ 516 f_24_19 = EXTRACT_LSB0_UINT (insn, 32, 24, 19); \ 517 f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ 518 519#define EXTRACT_IFMT_J_VARS \ 520 UINT f_opcode; \ 521 UINT f_rsrvd; \ 522 USI f_jtarg; \ 523 unsigned int length; 524#define EXTRACT_IFMT_J_CODE \ 525 length = 4; \ 526 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ 527 f_rsrvd = EXTRACT_LSB0_UINT (insn, 32, 25, 10); \ 528 f_jtarg = ((((pc) & (0xf0000000))) | (((EXTRACT_LSB0_UINT (insn, 32, 15, 16)) << (2)))); \ 529 530/* Collection of various things for the trace handler to use. */ 531 532typedef struct trace_record { 533 IADDR pc; 534 /* FIXME:wip */ 535} TRACE_RECORD; 536 537#endif /* CPU_IQ2000BF_H */ 538