1 2SIS - Sparc Instruction Simulator README file (v2.0, 05-02-1996) 3------------------------------------------------------------------- 4 51. Introduction 6 7The SIS is a SPARC V7 architecture simulator. It consist of two parts, 8the simulator core and a user defined memory module. The simulator 9core executes the instructions while the memory module emulates memory 10and peripherals. 11 122. Usage 13 14The simulator is started as follows: 15 16sis [-uart1 uart_device1] [-uart2 uart_device2] 17 [-nfp] [-freq frequency] [-c batch_file] [files] 18 19The default uart devices for SIS are /dev/ptypc and /dev/ptypd. The 20-uart[1,2] switch can be used to connect the uarts to other devices. 21Use 'tip /dev/ttypc' to connect a terminal emulator to the uarts. 22The '-nfp' will disable the simulated FPU, so each FPU instruction will 23generate a FPU disabled trap. The '-freq' switch can be used to define 24which "frequency" the simulator runs at. This is used by the 'perf' 25command to calculated the MIPS figure for a particular configuration. 26The give frequency must be an integer indicating the frequency in MHz. 27 28The -c option indicates that sis commands should be read from 'batch_file' 29at startup. 30 31Files to be loaded must be in one of the supported formats (see INSTALLATION), 32and will be loaded into the simulated memory. The file formats are 33automatically recognised. 34 35The script 'startsim' will start the simulator in one xterm window and 36open a terminal emulator (tip) connected to the UART A in a second 37xterm window. Below is description of commands that are recognized by 38the simulator. The command-line is parsed using GNU readline. A command 39history of 64 commands is maintained. Use the up/down arrows to recall 40previous commands. For more details, see the readline documentation. 41 42batch <file> 43 44Execute a batch file of SIS commands. 45 46+bp <address> 47 48Adds an breakpoint at address <address>. 49 50bp 51 52Prints all breakpoints 53 54-bp <num> 55 56Deletes breakpoint <num>. Use 'bp' to see which number is assigned to the 57breakpoints. 58 59cont [inst_count] 60 61Continue execution at present position, optionally for [inst_count] 62instructions. 63 64dis [addr] [count] 65 66Disassemble [count] instructions at address [addr]. Default values for 67count is 16 and addr is the present address. 68 69echo <string> 70 71Print <string> to the simulator window. 72 73float 74 75Prints the FPU registers 76 77go <address> [inst_count] 78 79The go command will set pc to <address> and npc to <address> + 4, and start 80execution. No other initialisation will be done. If inst_count is given, 81execution will stop after the specified number of instructions. 82 83help 84 85Print a small help menu for the SIS commands. 86 87hist [trace_length] 88 89Enable the instruction trace buffer. The 'trace_length' last executed 90instructions will be placed in the trace buffer. A 'hist' command without 91a trace_length will display the trace buffer. Specifying a zero trace 92length will disable the trace buffer. 93 94load <file_name> 95 96Loads a file into simulator memory. 97 98mem [addr] [count] 99 100Display memory at [addr] for [count] bytes. Same default values as above. 101 102quit 103 104Exits the simulator. 105 106perf [reset] 107 108The 'perf' command will display various execution statistics. A 'perf reset' 109command will reset the statistics. This can be used if statistics shall 110be calculated only over a part of the program. The 'run' and 'reset' 111command also resets the statistic information. 112 113reg [reg_name] [value] 114 115Prints and sets the IU regiters. 'reg' without parameters prints the IU 116registers. 'reg [reg_name] [value]' sets the corresponding register to 117[value]. Valid register names are psr, tbr, wim, y, g1-g7, o0-o7 and 118l0-l7. 119 120reset 121 122Performs a power-on reset. This command is equal to 'run 0'. 123 124run [inst_count] 125 126Resets the simulator and starts execution from address 0. If an instruction 127count is given (inst_count), the simulator will stop after the specified 128number of instructions. The event queue is emptied but any set breakpoints 129remain. 130 131step 132 133Equal to 'trace 1' 134 135tra [inst_count] 136 137Starts the simulator at the present position and prints each instruction 138it executes. If an instruction count is given (inst_count), the simulator 139will stop after the specified number of instructions. 140 141Typing a 'Ctrl-C' will interrupt a running simulator. 142 143Short forms of the commands are allowed, e.g 'c' 'co' or 'con' are all 144interpreted as 'cont'. 145 146 1473. Simulator core 148 149The SIS emulates the behavior of the 90C601E and 90C602E sparc IU and 150FPU from Matra MHS. These are roughly equivalent to the Cypress C601 151and C602. The simulator is cycle true, i.e a simulator time is 152maintained and inremented according the IU and FPU instruction timing. 153The parallel execution between the IU and FPU is modelled, as well as 154stalls due to operand dependencies (FPU). The core interacts with the 155user-defined memory modules through a number of functions. The memory 156module must provide the following functions: 157 158int memory_read(asi,addr,data,ws) 159int asi; 160unsigned int addr; 161unsigned int *data; 162int *ws; 163 164int memory_write(asi,addr,data,sz,ws) 165int asi; 166unsigned int addr; 167unsigned int *data; 168int sz; 169int *ws; 170 171int sis_memory_read(addr, data, length) 172unsigned int addr; 173char *data; 174unsigned int length; 175 176int sis_memory_write(addr, data, length) 177unsigned int addr; 178char *data; 179unsigned int length; 180 181int init_sim() 182 183int reset() 184 185int error_mode(pc) 186unsigned int pc; 187 188memory_read() is used by the simulator to fetch instructions and 189operands. The address space identifier (asi) and address is passed as 190parameters. The read data should be assigned to the data pointer 191(*data) and the number of waitstate to *ws. 'memory_read' should return 1920 on success and 1 on failure. A failure will cause a data or 193instruction fetch trap. memory_read() always reads one 32-bit word. 194 195sis_memory_read() is used by the simulator to display and disassemble 196memory contants. The function should copy 'length' bytes of the simulated 197memory starting at 'addr' to '*data'. 198The sis_memory_read() should return 1 on success and 0 on failure. 199Failure should only be indicated if access to unimplemented memory is attempted. 200 201memory_write() is used to write to memory. In addition to the asi 202and address parameters, the size of the written data is given by 'sz'. 203The pointer *data points to the data to be written. The 'sz' is coded 204as follows: 205 206 sz access type 207 0 byte 208 1 halfword 209 2 word 210 3 double-word 211 212If a double word is written, the most significant word is in data[0] and 213the least significant in data[1]. 214 215sis_memory_write() is used by the simulator during loading of programs. 216The function should copy 'length' bytes from *data to the simulated 217memory starting at 'addr'. sis_memory_write() should return 1 on 218success and 0 on failure. Failure should only be indicated if access 219to unimplemented memory is attempted. See erc32.c for more details 220on how to define the memory emulation functions. 221 222The 'init_sim' is called once when the simulator is started. This function 223should be used to perform initialisations of user defined memory or 224peripherals that only have to be done once, such as opening files etc. 225 226The 'reset' is called every time the simulator is reset, i.e. when a 227'run' command is given. This function should be used to simulate a power 228on reset of memory and peripherals. 229 230error_mode() is called by the simulator when the IU goes into error mode, 231typically if a trap is caused when traps are disabled. The memory module 232can then take actions, such as issue a reset. 233 234sys_reset() can be called by the memory module to reset the simulator. A 235reset will empty the event queue and perform a power-on reset. 236 2374. Events and interrupts 238 239The simulator supports an event queue and the generation of processor 240interrupts. The following functions are available to the user-defined 241memory module: 242 243event(cfunc,arg,delta) 244void (*cfunc)(); 245int arg; 246unsigned int delta; 247 248set_int(level,callback,arg) 249int level; 250void (*callback)(); 251int arg; 252 253clear_int(level) 254int level; 255 256sim_stop() 257 258The 'event' functions will schedule the execution of the function 'cfunc' 259at time 'now + delta' clock cycles. The parameter 'arg' is passed as a 260parameter to 'cfunc'. 261 262The 'set_int' function set the processor interrupt 'level'. When the interrupt 263is taken, the function 'callback' is called with the argument 'arg'. This 264will also clear the interrupt. An interrupt can be cleared before it is 265taken by calling 'clear_int' with the appropriate interrupt level. 266 267The sim_stop function is called each time the simulator stops execution. 268It can be used to flush buffered devices to get a clean state during 269single stepping etc. 270 271See 'erc32.c' for examples on how to use events and interrupts. 272 2735. Memory module 274 275The supplied memory module (erc32.c) emulates the functions of memory and 276the MEC asic developed for the 90C601/2. It includes the following functions: 277 278* UART A & B 279* Real-time clock 280* General purpose timer 281* Interrupt controller 282* Breakpoint register 283* Watchpoint register 284* 512 Kbyte ROM 285* 4 Mbyte RAM 286 287See README.erc32 on how the MEC functions are emulated. For a detailed MEC 288specification, look at the ERC32 home page at URL: 289 290http://www.estec.esa.nl/wsmwww/erc32 291 2926. Compile and linking programs 293 294The directory 'examples' contain some code fragments for SIS. 295The script gccx indicates how the native sunos gcc and linker can be used 296to produce executables for the simulator. To compile and link the provided 297'hello.c', type 'gccx hello.c'. This will build the executable 'hello'. 298Start the simulator by running 'startsim hello', and issue the command 'run. 299After the program is terminated, the IU will be force to error mode through 300a software trap and halt. 301 302The programs are linked with a start-up file, srt0.S. This file includes 303the traptable and window underflow/overflow trap routines. 304 3057. IU and FPU instruction timing. 306 307The simulator provides cycle true simulation. The following table shows 308the emulated instruction timing for 90C601E & 90C602E: 309 310Instructions Cycles 311 312jmpl, rett 2 313load 2 314store 3 315load double 3 316store double 4 317other integer ops 1 318fabs 2 319fadds 4 320faddd 4 321fcmps 4 322fcmpd 4 323fdivs 20 324fdivd 35 325fmovs 2 326fmuls 5 327fmuld 9 328fnegs 2 329fsqrts 37 330fsqrtd 65 331fsubs 4 332fsubd 4 333fdtoi 7 334fdots 3 335fitos 6 336fitod 6 337fstoi 6 338fstod 2 339 340The parallel operation between the IU and FPU is modelled. This means 341that a FPU instruction will execute in parallel with other instructions as 342long as no data or resource dependency is detected. See the 90C602E data 343sheet for the various types of dependencies. Tracing using the 'trace' 344command will display the current simulator time in the left column. This 345time indicates when the instruction is fetched. If a dependency is detetected, 346the following fetch will be delayed until the conflict is resolved. 347 348The load dependency in the 90C601E is also modelled - if the destination 349register of a load instruction is used by the following instruction, an 350idle cycle is inserted. 351 3528. FPU implementation 353 354The simulator maps floating-point operations on the hosts floating point 355capabilities. This means that accuracy and generation of IEEE exceptions is 356host dependent. 357