1#include "config.h" 2#include <stdio.h> 3#include <ctype.h> 4#include <limits.h> 5#include "ansidecl.h" 6#include "gdb/callback.h" 7#include "opcode/d10v.h" 8#include "bfd.h" 9 10#define DEBUG_TRACE 0x00000001 11#define DEBUG_VALUES 0x00000002 12#define DEBUG_LINE_NUMBER 0x00000004 13#define DEBUG_MEMSIZE 0x00000008 14#define DEBUG_INSTRUCTION 0x00000010 15#define DEBUG_TRAP 0x00000020 16#define DEBUG_MEMORY 0x00000040 17 18#ifndef DEBUG 19#define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER) 20#endif 21 22extern int d10v_debug; 23 24#include "gdb/remote-sim.h" 25#include "sim-config.h" 26#include "sim-types.h" 27 28typedef unsigned8 uint8; 29typedef unsigned16 uint16; 30typedef signed16 int16; 31typedef unsigned32 uint32; 32typedef signed32 int32; 33typedef unsigned64 uint64; 34typedef signed64 int64; 35 36/* FIXME: D10V defines */ 37typedef uint16 reg_t; 38 39struct simops 40{ 41 long opcode; 42 int is_long; 43 long mask; 44 int format; 45 int cycles; 46 int unit; 47 int exec_type; 48 void (*func)(); 49 int numops; 50 int operands[9]; 51}; 52 53enum _ins_type 54{ 55 INS_UNKNOWN, /* unknown instruction */ 56 INS_COND_TRUE, /* # times EXExxx executed other instruction */ 57 INS_COND_FALSE, /* # times EXExxx did not execute other instruction */ 58 INS_COND_JUMP, /* # times JUMP skipped other instruction */ 59 INS_CYCLES, /* # cycles */ 60 INS_LONG, /* long instruction (both containers, ie FM == 11) */ 61 INS_LEFTRIGHT, /* # times instruction encoded as L -> R (ie, FM == 01) */ 62 INS_RIGHTLEFT, /* # times instruction encoded as L <- R (ie, FM == 10) */ 63 INS_PARALLEL, /* # times instruction encoded as L || R (ie, RM == 00) */ 64 65 INS_LEFT, /* normal left instructions */ 66 INS_LEFT_PARALLEL, /* left side of || */ 67 INS_LEFT_COND_TEST, /* EXExx test on left side */ 68 INS_LEFT_COND_EXE, /* execution after EXExxx test on right side succeeded */ 69 INS_LEFT_NOPS, /* NOP on left side */ 70 71 INS_RIGHT, /* normal right instructions */ 72 INS_RIGHT_PARALLEL, /* right side of || */ 73 INS_RIGHT_COND_TEST, /* EXExx test on right side */ 74 INS_RIGHT_COND_EXE, /* execution after EXExxx test on left side succeeded */ 75 INS_RIGHT_NOPS, /* NOP on right side */ 76 77 INS_MAX 78}; 79 80extern unsigned long ins_type_counters[ (int)INS_MAX ]; 81 82enum { 83 SP_IDX = 15, 84}; 85 86/* Write-back slots */ 87union slot_data { 88 unsigned_1 _1; 89 unsigned_2 _2; 90 unsigned_4 _4; 91 unsigned_8 _8; 92}; 93struct slot { 94 void *dest; 95 int size; 96 union slot_data data; 97 union slot_data mask; 98}; 99enum { 100 NR_SLOTS = 16, 101}; 102#define SLOT (State.slot) 103#define SLOT_NR (State.slot_nr) 104#define SLOT_PEND_MASK(DEST, MSK, VAL) \ 105 do \ 106 { \ 107 SLOT[SLOT_NR].dest = &(DEST); \ 108 SLOT[SLOT_NR].size = sizeof (DEST); \ 109 switch (sizeof (DEST)) \ 110 { \ 111 case 1: \ 112 SLOT[SLOT_NR].data._1 = (unsigned_1) (VAL); \ 113 SLOT[SLOT_NR].mask._1 = (unsigned_1) (MSK); \ 114 break; \ 115 case 2: \ 116 SLOT[SLOT_NR].data._2 = (unsigned_2) (VAL); \ 117 SLOT[SLOT_NR].mask._2 = (unsigned_2) (MSK); \ 118 break; \ 119 case 4: \ 120 SLOT[SLOT_NR].data._4 = (unsigned_4) (VAL); \ 121 SLOT[SLOT_NR].mask._4 = (unsigned_4) (MSK); \ 122 break; \ 123 case 8: \ 124 SLOT[SLOT_NR].data._8 = (unsigned_8) (VAL); \ 125 SLOT[SLOT_NR].mask._8 = (unsigned_8) (MSK); \ 126 break; \ 127 } \ 128 SLOT_NR = (SLOT_NR + 1); \ 129 } \ 130 while (0) 131#define SLOT_PEND(DEST, VAL) SLOT_PEND_MASK(DEST, 0, VAL) 132#define SLOT_DISCARD() (SLOT_NR = 0) 133#define SLOT_FLUSH() \ 134 do \ 135 { \ 136 int i; \ 137 for (i = 0; i < SLOT_NR; i++) \ 138 { \ 139 switch (SLOT[i].size) \ 140 { \ 141 case 1: \ 142 *(unsigned_1*) SLOT[i].dest &= SLOT[i].mask._1; \ 143 *(unsigned_1*) SLOT[i].dest |= SLOT[i].data._1; \ 144 break; \ 145 case 2: \ 146 *(unsigned_2*) SLOT[i].dest &= SLOT[i].mask._2; \ 147 *(unsigned_2*) SLOT[i].dest |= SLOT[i].data._2; \ 148 break; \ 149 case 4: \ 150 *(unsigned_4*) SLOT[i].dest &= SLOT[i].mask._4; \ 151 *(unsigned_4*) SLOT[i].dest |= SLOT[i].data._4; \ 152 break; \ 153 case 8: \ 154 *(unsigned_8*) SLOT[i].dest &= SLOT[i].mask._8; \ 155 *(unsigned_8*) SLOT[i].dest |= SLOT[i].data._8; \ 156 break; \ 157 } \ 158 } \ 159 SLOT_NR = 0; \ 160 } \ 161 while (0) 162#define SLOT_DUMP() \ 163 do \ 164 { \ 165 int i; \ 166 for (i = 0; i < SLOT_NR; i++) \ 167 { \ 168 switch (SLOT[i].size) \ 169 { \ 170 case 1: \ 171 printf ("SLOT %d *0x%08lx & 0x%02x | 0x%02x\n", i, \ 172 (long) SLOT[i].dest, \ 173 (unsigned) SLOT[i].mask._1, \ 174 (unsigned) SLOT[i].data._1); \ 175 break; \ 176 case 2: \ 177 printf ("SLOT %d *0x%08lx & 0x%04x | 0x%04x\n", i, \ 178 (long) SLOT[i].dest, \ 179 (unsigned) SLOT[i].mask._2, \ 180 (unsigned) SLOT[i].data._2); \ 181 break; \ 182 case 4: \ 183 printf ("SLOT %d *0x%08lx & 0x%08x | 0x%08x\n", i, \ 184 (long) SLOT[i].dest, \ 185 (unsigned) SLOT[i].mask._4, \ 186 (unsigned) SLOT[i].data._4); \ 187 break; \ 188 case 8: \ 189 printf ("SLOT %d *0x%08lx & 0x%08x%08x | 0x%08x%08x\n", i, \ 190 (long) SLOT[i].dest, \ 191 (unsigned) (SLOT[i].mask._8 >> 32), \ 192 (unsigned) SLOT[i].mask._8, \ 193 (unsigned) (SLOT[i].data._8 >> 32), \ 194 (unsigned) SLOT[i].data._8); \ 195 break; \ 196 } \ 197 } \ 198 } \ 199 while (0) 200 201/* d10v memory: There are three separate d10v memory regions IMEM, 202 UMEM and DMEM. The IMEM and DMEM are further broken down into 203 blocks (very like VM pages). */ 204 205enum 206{ 207 IMAP_BLOCK_SIZE = 0x20000, 208 DMAP_BLOCK_SIZE = 0x4000, 209}; 210 211/* Implement the three memory regions using sparse arrays. Allocate 212 memory using ``segments''. A segment must be at least as large as 213 a BLOCK - ensures that an access that doesn't cross a block 214 boundary can't cross a segment boundary */ 215 216enum 217{ 218 SEGMENT_SIZE = 0x20000, /* 128KB - MAX(IMAP_BLOCK_SIZE,DMAP_BLOCK_SIZE) */ 219 IMEM_SEGMENTS = 8, /* 1MB */ 220 DMEM_SEGMENTS = 8, /* 1MB */ 221 UMEM_SEGMENTS = 128 /* 16MB */ 222}; 223 224struct d10v_memory 225{ 226 uint8 *insn[IMEM_SEGMENTS]; 227 uint8 *data[DMEM_SEGMENTS]; 228 uint8 *unif[UMEM_SEGMENTS]; 229 uint8 fault[16]; 230}; 231 232struct _state 233{ 234 reg_t regs[16]; /* general-purpose registers */ 235#define GPR(N) (State.regs[(N)] + 0) 236#define SET_GPR(N,VAL) SLOT_PEND (State.regs[(N)], (VAL)) 237 238#define GPR32(N) ((((uint32) State.regs[(N) + 0]) << 16) \ 239 | (uint16) State.regs[(N) + 1]) 240#define SET_GPR32(N,VAL) do { SET_GPR (OP[0] + 0, (VAL) >> 16); SET_GPR (OP[0] + 1, (VAL)); } while (0) 241 242 reg_t cregs[16]; /* control registers */ 243#define CREG(N) (State.cregs[(N)] + 0) 244#define SET_CREG(N,VAL) move_to_cr ((N), 0, (VAL), 0) 245#define SET_HW_CREG(N,VAL) move_to_cr ((N), 0, (VAL), 1) 246 247 reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */ 248#define HELD_SP(N) (State.sp[(N)] + 0) 249#define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL)) 250 251 int64 a[2]; /* accumulators */ 252#define ACC(N) (State.a[(N)] + 0) 253#define SET_ACC(N,VAL) SLOT_PEND (State.a[(N)], (VAL) & MASK40) 254 255 /* writeback info */ 256 struct slot slot[NR_SLOTS]; 257 int slot_nr; 258 259 /* trace data */ 260 struct { 261 uint16 psw; 262 } trace; 263 264 uint8 exe; 265 int exception; 266 int pc_changed; 267 268 /* NOTE: everything below this line is not reset by 269 sim_create_inferior() */ 270 271 struct d10v_memory mem; 272 273 enum _ins_type ins_type; 274 275} State; 276 277 278extern host_callback *d10v_callback; 279extern uint16 OP[4]; 280extern struct simops Simops[]; 281extern asection *text; 282extern bfd_vma text_start; 283extern bfd_vma text_end; 284extern bfd *prog_bfd; 285 286enum 287{ 288 PSW_CR = 0, 289 BPSW_CR = 1, 290 PC_CR = 2, 291 BPC_CR = 3, 292 DPSW_CR = 4, 293 DPC_CR = 5, 294 RPT_C_CR = 7, 295 RPT_S_CR = 8, 296 RPT_E_CR = 9, 297 MOD_S_CR = 10, 298 MOD_E_CR = 11, 299 IBA_CR = 14, 300}; 301 302enum 303{ 304 PSW_SM_BIT = 0x8000, 305 PSW_EA_BIT = 0x2000, 306 PSW_DB_BIT = 0x1000, 307 PSW_DM_BIT = 0x0800, 308 PSW_IE_BIT = 0x0400, 309 PSW_RP_BIT = 0x0200, 310 PSW_MD_BIT = 0x0100, 311 PSW_FX_BIT = 0x0080, 312 PSW_ST_BIT = 0x0040, 313 PSW_F0_BIT = 0x0008, 314 PSW_F1_BIT = 0x0004, 315 PSW_C_BIT = 0x0001, 316}; 317 318#define PSW CREG (PSW_CR) 319#define SET_PSW(VAL) SET_CREG (PSW_CR, (VAL)) 320#define SET_HW_PSW(VAL) SET_HW_CREG (PSW_CR, (VAL)) 321#define SET_PSW_BIT(MASK,VAL) move_to_cr (PSW_CR, ~((reg_t) MASK), (VAL) ? (MASK) : 0, 1) 322 323#define PSW_SM ((PSW & PSW_SM_BIT) != 0) 324#define SET_PSW_SM(VAL) SET_PSW_BIT (PSW_SM_BIT, (VAL)) 325 326#define PSW_EA ((PSW & PSW_EA_BIT) != 0) 327#define SET_PSW_EA(VAL) SET_PSW_BIT (PSW_EA_BIT, (VAL)) 328 329#define PSW_DB ((PSW & PSW_DB_BIT) != 0) 330#define SET_PSW_DB(VAL) SET_PSW_BIT (PSW_DB_BIT, (VAL)) 331 332#define PSW_DM ((PSW & PSW_DM_BIT) != 0) 333#define SET_PSW_DM(VAL) SET_PSW_BIT (PSW_DM_BIT, (VAL)) 334 335#define PSW_IE ((PSW & PSW_IE_BIT) != 0) 336#define SET_PSW_IE(VAL) SET_PSW_BIT (PSW_IE_BIT, (VAL)) 337 338#define PSW_RP ((PSW & PSW_RP_BIT) != 0) 339#define SET_PSW_RP(VAL) SET_PSW_BIT (PSW_RP_BIT, (VAL)) 340 341#define PSW_MD ((PSW & PSW_MD_BIT) != 0) 342#define SET_PSW_MD(VAL) SET_PSW_BIT (PSW_MD_BIT, (VAL)) 343 344#define PSW_FX ((PSW & PSW_FX_BIT) != 0) 345#define SET_PSW_FX(VAL) SET_PSW_BIT (PSW_FX_BIT, (VAL)) 346 347#define PSW_ST ((PSW & PSW_ST_BIT) != 0) 348#define SET_PSW_ST(VAL) SET_PSW_BIT (PSW_ST_BIT, (VAL)) 349 350#define PSW_F0 ((PSW & PSW_F0_BIT) != 0) 351#define SET_PSW_F0(VAL) SET_PSW_BIT (PSW_F0_BIT, (VAL)) 352 353#define PSW_F1 ((PSW & PSW_F1_BIT) != 0) 354#define SET_PSW_F1(VAL) SET_PSW_BIT (PSW_F1_BIT, (VAL)) 355 356#define PSW_C ((PSW & PSW_C_BIT) != 0) 357#define SET_PSW_C(VAL) SET_PSW_BIT (PSW_C_BIT, (VAL)) 358 359/* See simopsc.:move_to_cr() for registers that can not be read-from 360 or assigned-to directly */ 361 362#define PC CREG (PC_CR) 363#define SET_PC(VAL) SET_CREG (PC_CR, (VAL)) 364 365#define BPSW CREG (BPSW_CR) 366#define SET_BPSW(VAL) SET_CREG (BPSW_CR, (VAL)) 367 368#define BPC CREG (BPC_CR) 369#define SET_BPC(VAL) SET_CREG (BPC_CR, (VAL)) 370 371#define DPSW CREG (DPSW_CR) 372#define SET_DPSW(VAL) SET_CREG (DPSW_CR, (VAL)) 373 374#define DPC CREG (DPC_CR) 375#define SET_DPC(VAL) SET_CREG (DPC_CR, (VAL)) 376 377#define RPT_C CREG (RPT_C_CR) 378#define SET_RPT_C(VAL) SET_CREG (RPT_C_CR, (VAL)) 379 380#define RPT_S CREG (RPT_S_CR) 381#define SET_RPT_S(VAL) SET_CREG (RPT_S_CR, (VAL)) 382 383#define RPT_E CREG (RPT_E_CR) 384#define SET_RPT_E(VAL) SET_CREG (RPT_E_CR, (VAL)) 385 386#define MOD_S CREG (MOD_S_CR) 387#define SET_MOD_S(VAL) SET_CREG (MOD_S_CR, (VAL)) 388 389#define MOD_E CREG (MOD_E_CR) 390#define SET_MOD_E(VAL) SET_CREG (MOD_E_CR, (VAL)) 391 392#define IBA CREG (IBA_CR) 393#define SET_IBA(VAL) SET_CREG (IBA_CR, (VAL)) 394 395 396#define SIG_D10V_STOP -1 397#define SIG_D10V_EXIT -2 398#define SIG_D10V_BUS -3 399 400#define SEXT3(x) ((((x)&0x7)^(~3))+4) 401 402/* sign-extend a 4-bit number */ 403#define SEXT4(x) ((((x)&0xf)^(~7))+8) 404 405/* sign-extend an 8-bit number */ 406#define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80) 407 408/* sign-extend a 16-bit number */ 409#define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000) 410 411/* sign-extend a 32-bit number */ 412#define SEXT32(x) ((((x)&SIGNED64(0xffffffff))^(~SIGNED64(0x7fffffff)))+SIGNED64(0x80000000)) 413 414/* sign extend a 40 bit number */ 415#define SEXT40(x) ((((x)&SIGNED64(0xffffffffff))^(~SIGNED64(0x7fffffffff)))+SIGNED64(0x8000000000)) 416 417/* sign extend a 44 bit number */ 418#define SEXT44(x) ((((x)&SIGNED64(0xfffffffffff))^(~SIGNED64(0x7ffffffffff)))+SIGNED64(0x80000000000)) 419 420/* sign extend a 56 bit number */ 421#define SEXT56(x) ((((x)&SIGNED64(0xffffffffffffff))^(~SIGNED64(0x7fffffffffffff)))+SIGNED64(0x80000000000000)) 422 423/* sign extend a 60 bit number */ 424#define SEXT60(x) ((((x)&SIGNED64(0xfffffffffffffff))^(~SIGNED64(0x7ffffffffffffff)))+SIGNED64(0x800000000000000)) 425 426#define MAX32 SIGNED64(0x7fffffff) 427#define MIN32 SIGNED64(0xff80000000) 428#define MASK32 SIGNED64(0xffffffff) 429#define MASK40 SIGNED64(0xffffffffff) 430 431/* The alignment of MOD_E in the following macro depends upon "i" 432 always being a power of 2. */ 433#define INC_ADDR(x,i) \ 434do \ 435 { \ 436 int test_i = i < 0 ? i : ~((i) - 1); \ 437 if (PSW_MD && GPR (x) == (MOD_E & test_i)) \ 438 SET_GPR (x, MOD_S & test_i); \ 439 else \ 440 SET_GPR (x, GPR (x) + (i)); \ 441 } \ 442while (0) 443 444extern uint8 *dmem_addr (uint16 offset); 445extern uint8 *imem_addr PARAMS ((uint32)); 446extern bfd_vma decode_pc PARAMS ((void)); 447 448#define RB(x) (*(dmem_addr(x))) 449#define SB(addr,data) ( RB(addr) = (data & 0xff)) 450 451#if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE) 452#define ENDIAN_INLINE static __inline__ 453#include "endian.c" 454#undef ENDIAN_INLINE 455 456#else 457extern uint32 get_longword PARAMS ((uint8 *)); 458extern uint16 get_word PARAMS ((uint8 *)); 459extern int64 get_longlong PARAMS ((uint8 *)); 460extern void write_word PARAMS ((uint8 *addr, uint16 data)); 461extern void write_longword PARAMS ((uint8 *addr, uint32 data)); 462extern void write_longlong PARAMS ((uint8 *addr, int64 data)); 463#endif 464 465#define SW(addr,data) write_word(dmem_addr(addr),data) 466#define RW(x) get_word(dmem_addr(x)) 467#define SLW(addr,data) write_longword(dmem_addr(addr),data) 468#define RLW(x) get_longword(dmem_addr(x)) 469#define READ_16(x) get_word(x) 470#define WRITE_16(addr,data) write_word(addr,data) 471#define READ_64(x) get_longlong(x) 472#define WRITE_64(addr,data) write_longlong(addr,data) 473 474#define JMP(x) do { SET_PC (x); State.pc_changed = 1; } while (0) 475 476#define RIE_VECTOR_START 0xffc2 477#define AE_VECTOR_START 0xffc3 478#define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */ 479#define DBT_VECTOR_START 0xffd4 480#define SDBT_VECTOR_START 0xffd5 481 482/* Scedule a store of VAL into cr[CR]. MASK indicates the bits in 483 cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) | 484 (VAL & ~MASK)). In addition, unless PSW_HW_P, a VAL intended for 485 PSW is masked for zero bits. */ 486 487extern reg_t move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p); 488