1/* Simulation code for the CR16 processor. 2 Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc. 3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com> 4 5 This file is part of GDB, the GNU debugger. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 21#include "config.h" 22 23#include <signal.h> 24#include <errno.h> 25#include <sys/types.h> 26#include <sys/stat.h> 27#ifdef HAVE_UNISTD_H 28#include <unistd.h> 29#endif 30#ifdef HAVE_STRING_H 31#include <string.h> 32#endif 33 34#include "cr16_sim.h" 35#include "simops.h" 36#include "targ-vals.h" 37 38extern char *strrchr (); 39 40enum op_types { 41 OP_VOID, 42 OP_CONSTANT3, 43 OP_UCONSTANT3, 44 OP_CONSTANT4, 45 OP_CONSTANT4_1, 46 OP_CONSTANT5, 47 OP_CONSTANT6, 48 OP_CONSTANT16, 49 OP_UCONSTANT16, 50 OP_CONSTANT20, 51 OP_UCONSTANT20, 52 OP_CONSTANT32, 53 OP_UCONSTANT32, 54 OP_MEMREF, 55 OP_MEMREF2, 56 OP_MEMREF3, 57 58 OP_DISP5, 59 OP_DISP17, 60 OP_DISP25, 61 OP_DISPE9, 62 //OP_ABS20, 63 OP_ABS20_OUTPUT, 64 //OP_ABS24, 65 OP_ABS24_OUTPUT, 66 67 OP_R_BASE_DISPS16, 68 OP_R_BASE_DISP20, 69 OP_R_BASE_DISPS20, 70 OP_R_BASE_DISPE20, 71 72 OP_RP_BASE_DISPE0, 73 OP_RP_BASE_DISP4, 74 OP_RP_BASE_DISPE4, 75 OP_RP_BASE_DISP14, 76 OP_RP_BASE_DISP16, 77 OP_RP_BASE_DISP20, 78 OP_RP_BASE_DISPS20, 79 OP_RP_BASE_DISPE20, 80 81 OP_R_INDEX7_ABS20, 82 OP_R_INDEX8_ABS20, 83 84 OP_RP_INDEX_DISP0, 85 OP_RP_INDEX_DISP14, 86 OP_RP_INDEX_DISP20, 87 OP_RP_INDEX_DISPS20, 88 89 OP_REG, 90 OP_REGP, 91 OP_PROC_REG, 92 OP_PROC_REGP, 93 OP_COND, 94 OP_RA 95}; 96 97 98enum { 99 PSR_MASK = (PSR_I_BIT 100 | PSR_P_BIT 101 | PSR_E_BIT 102 | PSR_N_BIT 103 | PSR_Z_BIT 104 | PSR_F_BIT 105 | PSR_U_BIT 106 | PSR_L_BIT 107 | PSR_T_BIT 108 | PSR_C_BIT), 109 /* The following bits in the PSR _can't_ be set by instructions such 110 as mvtc. */ 111 PSR_HW_MASK = (PSR_MASK) 112}; 113 114/* cond Code Condition True State 115 * EQ Equal Z flag is 1 116 * NE Not Equal Z flag is 0 117 * CS Carry Set C flag is 1 118 * CC Carry Clear C flag is 0 119 * HI Higher L flag is 1 120 * LS Lower or Same L flag is 0 121 * GT Greater Than N flag is 1 122 * LE Less Than or Equal To N flag is 0 123 * FS Flag Set F flag is 1 124 * FC Flag Clear F flag is 0 125 * LO Lower Z and L flags are 0 126 * HS Higher or Same Z or L flag is 1 127 * LT Less Than Z and N flags are 0 128 * GE Greater Than or Equal To Z or N flag is 1. */ 129 130int cond_stat(int cc) 131{ 132 switch (cc) 133 { 134 case 0: return PSR_Z; break; 135 case 1: return !PSR_Z; break; 136 case 2: return PSR_C; break; 137 case 3: return !PSR_C; break; 138 case 4: return PSR_L; break; 139 case 5: return !PSR_L; break; 140 case 6: return PSR_N; break; 141 case 7: return !PSR_N; break; 142 case 8: return PSR_F; break; 143 case 9: return !PSR_F; break; 144 case 10: return !PSR_Z && !PSR_L; break; 145 case 11: return PSR_Z || PSR_L; break; 146 case 12: return !PSR_Z && !PSR_N; break; 147 case 13: return PSR_Z || PSR_N; break; 148 case 14: return 1; break; /*ALWAYS. */ 149 default: 150 // case NEVER: return false; break; 151 //case NO_COND_CODE: 152 //panic("Shouldn't have NO_COND_CODE in an actual instruction!"); 153 return 0; break; 154 } 155 return 0; 156} 157 158 159creg_t 160move_to_cr (int cr, creg_t mask, creg_t val, int psw_hw_p) 161{ 162 /* A MASK bit is set when the corresponding bit in the CR should 163 be left alone. */ 164 /* This assumes that (VAL & MASK) == 0. */ 165 switch (cr) 166 { 167 case PSR_CR: 168 if (psw_hw_p) 169 val &= PSR_HW_MASK; 170#if 0 171 else 172 val &= PSR_MASK; 173 (*cr16_callback->printf_filtered) 174 (cr16_callback, 175 "ERROR at PC 0x%x: ST can only be set when FX is set.\n", PC); 176 State.exception = SIGILL; 177#endif 178 /* keep an up-to-date psw around for tracing. */ 179 State.trace.psw = (State.trace.psw & mask) | val; 180 break; 181 default: 182 break; 183 } 184 /* only issue an update if the register is being changed. */ 185 if ((State.cregs[cr] & ~mask) != val) 186 SLOT_PEND_MASK (State.cregs[cr], mask, val); 187 188 return val; 189} 190 191#ifdef DEBUG 192static void trace_input_func PARAMS ((char *name, 193 enum op_types in1, 194 enum op_types in2, 195 enum op_types in3)); 196 197#define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (name, in1, in2, in3); } while (0) 198 199#ifndef SIZE_INSTRUCTION 200#define SIZE_INSTRUCTION 8 201#endif 202 203#ifndef SIZE_OPERANDS 204#define SIZE_OPERANDS 18 205#endif 206 207#ifndef SIZE_VALUES 208#define SIZE_VALUES 13 209#endif 210 211#ifndef SIZE_LOCATION 212#define SIZE_LOCATION 20 213#endif 214 215#ifndef SIZE_PC 216#define SIZE_PC 4 217#endif 218 219#ifndef SIZE_LINE_NUMBER 220#define SIZE_LINE_NUMBER 2 221#endif 222 223static void 224trace_input_func (name, in1, in2, in3) 225 char *name; 226 enum op_types in1; 227 enum op_types in2; 228 enum op_types in3; 229{ 230 char *comma; 231 enum op_types in[3]; 232 int i; 233 char buf[1024]; 234 char *p; 235 long tmp; 236 char *type; 237 const char *filename; 238 const char *functionname; 239 unsigned int linenumber; 240 bfd_vma byte_pc; 241 242 if ((cr16_debug & DEBUG_TRACE) == 0) 243 return; 244 245 switch (State.ins_type) 246 { 247 default: 248 case INS_UNKNOWN: type = " ?"; break; 249 } 250 251 if ((cr16_debug & DEBUG_LINE_NUMBER) == 0) 252 (*cr16_callback->printf_filtered) (cr16_callback, 253 "0x%.*x %s: %-*s ", 254 SIZE_PC, (unsigned)PC, 255 type, 256 SIZE_INSTRUCTION, name); 257 258 else 259 { 260 buf[0] = '\0'; 261 byte_pc = decode_pc (); 262 if (text && byte_pc >= text_start && byte_pc < text_end) 263 { 264 filename = (const char *)0; 265 functionname = (const char *)0; 266 linenumber = 0; 267 if (bfd_find_nearest_line (prog_bfd, text, (struct bfd_symbol **)0, byte_pc - text_start, 268 &filename, &functionname, &linenumber)) 269 { 270 p = buf; 271 if (linenumber) 272 { 273 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber); 274 p += strlen (p); 275 } 276 else 277 { 278 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---"); 279 p += SIZE_LINE_NUMBER+2; 280 } 281 282 if (functionname) 283 { 284 sprintf (p, "%s ", functionname); 285 p += strlen (p); 286 } 287 else if (filename) 288 { 289 char *q = strrchr (filename, '/'); 290 sprintf (p, "%s ", (q) ? q+1 : filename); 291 p += strlen (p); 292 } 293 294 if (*p == ' ') 295 *p = '\0'; 296 } 297 } 298 299 (*cr16_callback->printf_filtered) (cr16_callback, 300 "0x%.*x %s: %-*.*s %-*s ", 301 SIZE_PC, (unsigned)PC, 302 type, 303 SIZE_LOCATION, SIZE_LOCATION, buf, 304 SIZE_INSTRUCTION, name); 305 } 306 307 in[0] = in1; 308 in[1] = in2; 309 in[2] = in3; 310 comma = ""; 311 p = buf; 312 for (i = 0; i < 3; i++) 313 { 314 switch (in[i]) 315 { 316 case OP_VOID: 317 break; 318 319 case OP_REG: 320 case OP_REGP: 321 sprintf (p, "%sr%d", comma, OP[i]); 322 p += strlen (p); 323 comma = ","; 324 break; 325 326 case OP_PROC_REG: 327 sprintf (p, "%scr%d", comma, OP[i]); 328 p += strlen (p); 329 comma = ","; 330 break; 331 332 case OP_CONSTANT16: 333 sprintf (p, "%s%d", comma, OP[i]); 334 p += strlen (p); 335 comma = ","; 336 break; 337 338 case OP_CONSTANT4: 339 sprintf (p, "%s%d", comma, SEXT4(OP[i])); 340 p += strlen (p); 341 comma = ","; 342 break; 343 344 case OP_CONSTANT3: 345 sprintf (p, "%s%d", comma, SEXT3(OP[i])); 346 p += strlen (p); 347 comma = ","; 348 break; 349 350 case OP_MEMREF: 351 sprintf (p, "%s@r%d", comma, OP[i]); 352 p += strlen (p); 353 comma = ","; 354 break; 355 356 case OP_MEMREF2: 357 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]); 358 p += strlen (p); 359 comma = ","; 360 break; 361 362 case OP_MEMREF3: 363 sprintf (p, "%s@%d", comma, OP[i]); 364 p += strlen (p); 365 comma = ","; 366 break; 367 } 368 } 369 370 if ((cr16_debug & DEBUG_VALUES) == 0) 371 { 372 *p++ = '\n'; 373 *p = '\0'; 374 (*cr16_callback->printf_filtered) (cr16_callback, "%s", buf); 375 } 376 else 377 { 378 *p = '\0'; 379 (*cr16_callback->printf_filtered) (cr16_callback, "%-*s", SIZE_OPERANDS, buf); 380 381 p = buf; 382 for (i = 0; i < 3; i++) 383 { 384 buf[0] = '\0'; 385 switch (in[i]) 386 { 387 case OP_VOID: 388 (*cr16_callback->printf_filtered) (cr16_callback, "%*s", SIZE_VALUES, ""); 389 break; 390 391 case OP_REG: 392 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", 393 (uint16) GPR (OP[i])); 394 break; 395 396 case OP_REGP: 397 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1))); 398 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp); 399 break; 400 401 case OP_PROC_REG: 402 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", 403 (uint16) CREG (OP[i])); 404 break; 405 406 case OP_CONSTANT16: 407 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", 408 (uint16)OP[i]); 409 break; 410 411 case OP_CONSTANT4: 412 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", 413 (uint16)SEXT4(OP[i])); 414 break; 415 416 case OP_CONSTANT3: 417 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", 418 (uint16)SEXT3(OP[i])); 419 break; 420 421 case OP_MEMREF2: 422 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", 423 (uint16)OP[i]); 424 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", 425 (uint16)GPR (OP[i + 1])); 426 i++; 427 break; 428 } 429 } 430 } 431 432 (*cr16_callback->flush_stdout) (cr16_callback); 433} 434 435static void 436do_trace_output_flush (void) 437{ 438 (*cr16_callback->flush_stdout) (cr16_callback); 439} 440 441static void 442do_trace_output_finish (void) 443{ 444 (*cr16_callback->printf_filtered) (cr16_callback, 445 " F0=%d F1=%d C=%d\n", 446 (State.trace.psw & PSR_F_BIT) != 0, 447 (State.trace.psw & PSR_F_BIT) != 0, 448 (State.trace.psw & PSR_C_BIT) != 0); 449 (*cr16_callback->flush_stdout) (cr16_callback); 450} 451 452static void 453trace_output_40 (uint64 val) 454{ 455 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) 456 { 457 (*cr16_callback->printf_filtered) (cr16_callback, 458 " :: %*s0x%.2x%.8lx", 459 SIZE_VALUES - 12, 460 "", 461 ((int)(val >> 32) & 0xff), 462 ((unsigned long) val) & 0xffffffff); 463 do_trace_output_finish (); 464 } 465} 466 467static void 468trace_output_32 (uint32 val) 469{ 470 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) 471 { 472 (*cr16_callback->printf_filtered) (cr16_callback, 473 " :: %*s0x%.8x", 474 SIZE_VALUES - 10, 475 "", 476 (int) val); 477 do_trace_output_finish (); 478 } 479} 480 481static void 482trace_output_16 (uint16 val) 483{ 484 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) 485 { 486 (*cr16_callback->printf_filtered) (cr16_callback, 487 " :: %*s0x%.4x", 488 SIZE_VALUES - 6, 489 "", 490 (int) val); 491 do_trace_output_finish (); 492 } 493} 494 495static void 496trace_output_void () 497{ 498 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) 499 { 500 (*cr16_callback->printf_filtered) (cr16_callback, "\n"); 501 do_trace_output_flush (); 502 } 503} 504 505static void 506trace_output_flag () 507{ 508 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) 509 { 510 (*cr16_callback->printf_filtered) (cr16_callback, 511 " :: %*s", 512 SIZE_VALUES, 513 ""); 514 do_trace_output_finish (); 515 } 516} 517 518 519 520 521#else 522#define trace_input(NAME, IN1, IN2, IN3) 523#define trace_output(RESULT) 524#endif 525 526/* addub. */ 527void 528OP_2C_8 () 529{ 530 uint8 tmp; 531 uint8 a = OP[0] & 0xff; 532 uint16 b = (GPR (OP[1])) & 0xff; 533 trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID); 534 tmp = (a + b) & 0xff; 535 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 536 trace_output_16 (tmp); 537} 538 539/* addub. */ 540void 541OP_2CB_C () 542{ 543 uint16 tmp; 544 uint8 a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff; 545 trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID); 546 tmp = (a + b) & 0xff; 547 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 548 trace_output_16 (tmp); 549} 550 551/* addub. */ 552void 553OP_2D_8 () 554{ 555 uint8 a = (GPR (OP[0])) & 0xff; 556 uint8 b = (GPR (OP[1])) & 0xff; 557 uint16 tmp = (a + b) & 0xff; 558 trace_input ("addub", OP_REG, OP_REG, OP_VOID); 559 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 560 trace_output_16 (tmp); 561} 562 563/* adduw. */ 564void 565OP_2E_8 () 566{ 567 uint16 a = OP[0]; 568 uint16 b = GPR (OP[1]); 569 uint16 tmp = (a + b); 570 trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID); 571 SET_GPR (OP[1], tmp); 572 trace_output_16 (tmp); 573} 574 575/* adduw. */ 576void 577OP_2EB_C () 578{ 579 uint16 a = OP[0]; 580 uint16 b = GPR (OP[1]); 581 uint16 tmp = (a + b); 582 trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID); 583 SET_GPR (OP[1], tmp); 584 trace_output_16 (tmp); 585} 586 587/* adduw. */ 588void 589OP_2F_8 () 590{ 591 uint16 a = GPR (OP[0]); 592 uint16 b = GPR (OP[1]); 593 uint16 tmp = (a + b); 594 trace_input ("adduw", OP_REG, OP_REG, OP_VOID); 595 SET_GPR (OP[1], tmp); 596 trace_output_16 (tmp); 597} 598 599/* addb. */ 600void 601OP_30_8 () 602{ 603 uint8 a = OP[0]; 604 uint8 b = (GPR (OP[1]) & 0xff); 605 trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID); 606 uint16 tmp = (a + b) & 0xff; 607 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 608 SET_PSR_C (tmp > 0xFF); 609 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 610 trace_output_16 (tmp); 611} 612 613/* addb. */ 614void 615OP_30B_C () 616{ 617 uint8 a = (OP[0]) & 0xff; 618 uint8 b = (GPR (OP[1]) & 0xff); 619 trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID); 620 uint16 tmp = (a + b) & 0xff; 621 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 622 SET_PSR_C (tmp > 0xFF); 623 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 624 trace_output_16 (tmp); 625} 626 627/* addb. */ 628void 629OP_31_8 () 630{ 631 uint8 a = (GPR (OP[0]) & 0xff); 632 uint8 b = (GPR (OP[1]) & 0xff); 633 trace_input ("addb", OP_REG, OP_REG, OP_VOID); 634 uint16 tmp = (a + b) & 0xff; 635 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 636 SET_PSR_C (tmp > 0xFF); 637 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 638 trace_output_16 (tmp); 639} 640 641/* addw. */ 642void 643OP_32_8 () 644{ 645 int16 a = OP[0]; 646 uint16 tmp, b = GPR (OP[1]); 647 trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID); 648 tmp = (a + b); 649 SET_GPR (OP[1], tmp); 650 SET_PSR_C (tmp > 0xFFFF); 651 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 652 trace_output_16 (tmp); 653} 654 655/* addw. */ 656void 657OP_32B_C () 658{ 659 int16 a = OP[0]; 660 uint16 tmp, b = GPR (OP[1]); 661 tmp = (a + b); 662 trace_input ("addw", OP_CONSTANT16, OP_REG, OP_VOID); 663 SET_GPR (OP[1], tmp); 664 SET_PSR_C (tmp > 0xFFFF); 665 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 666 trace_output_16 (tmp); 667} 668 669/* addw. */ 670void 671OP_33_8 () 672{ 673 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1])); 674 trace_input ("addw", OP_REG, OP_REG, OP_VOID); 675 tmp = (a + b); 676 SET_GPR (OP[1], tmp); 677 SET_PSR_C (tmp > 0xFFFF); 678 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 679 trace_output_16 (tmp); 680} 681 682/* addcb. */ 683void 684OP_34_8 () 685{ 686 uint8 tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff; 687 trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG); 688 tmp = (a + b + PSR_C) & 0xff; 689 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 690 SET_PSR_C (tmp > 0xFF); 691 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 692 trace_output_16 (tmp); 693} 694 695/* addcb. */ 696void 697OP_34B_C () 698{ 699 int8 a = OP[0] & 0xff; 700 uint8 b = (GPR (OP[1])) & 0xff; 701 trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID); 702 uint8 tmp = (a + b + PSR_C) & 0xff; 703 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 704 SET_PSR_C (tmp > 0xFF); 705 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 706 trace_output_16 (tmp); 707} 708 709/* addcb. */ 710void 711OP_35_8 () 712{ 713 uint8 a = (GPR (OP[0])) & 0xff; 714 uint8 b = (GPR (OP[1])) & 0xff; 715 trace_input ("addcb", OP_REG, OP_REG, OP_VOID); 716 uint8 tmp = (a + b + PSR_C) & 0xff; 717 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 718 SET_PSR_C (tmp > 0xFF); 719 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 720 trace_output_16 (tmp); 721} 722 723/* addcw. */ 724void 725OP_36_8 () 726{ 727 uint16 a = OP[0]; 728 uint16 b = GPR (OP[1]); 729 trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID); 730 uint16 tmp = (a + b + PSR_C); 731 SET_GPR (OP[1], tmp); 732 SET_PSR_C (tmp > 0xFFFF); 733 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 734 trace_output_16 (tmp); 735} 736 737/* addcw. */ 738void 739OP_36B_C () 740{ 741 int16 a = OP[0]; 742 uint16 b = GPR (OP[1]); 743 trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID); 744 uint16 tmp = (a + b + PSR_C); 745 SET_GPR (OP[1], tmp); 746 SET_PSR_C (tmp > 0xFFFF); 747 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 748 trace_output_16 (tmp); 749} 750 751/* addcw. */ 752void 753OP_37_8 () 754{ 755 uint16 a = GPR (OP[1]); 756 uint16 b = GPR (OP[1]); 757 trace_input ("addcw", OP_REG, OP_REG, OP_VOID); 758 uint16 tmp = (a + b + PSR_C); 759 SET_GPR (OP[1], tmp); 760 SET_PSR_C (tmp > 0xFFFF); 761 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 762 trace_output_16 (tmp); 763} 764 765/* addd. */ 766void 767OP_60_8 () 768{ 769 int16 a = (OP[0]); 770 uint32 b = GPR32 (OP[1]); 771 trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID); 772 uint32 tmp = (a + b); 773 SET_GPR32 (OP[1], tmp); 774 SET_PSR_C (tmp > 0xFFFFFFFF); 775 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); 776 trace_output_32 (tmp); 777} 778 779/* addd. */ 780void 781OP_60B_C () 782{ 783 int32 a = (SEXT16(OP[0])); 784 uint32 b = GPR32 (OP[1]); 785 trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID); 786 uint32 tmp = (a + b); 787 SET_GPR32 (OP[1], tmp); 788 SET_PSR_C (tmp > 0xFFFFFFFF); 789 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); 790 trace_output_32 (tmp); 791} 792 793/* addd. */ 794void 795OP_61_8 () 796{ 797 uint32 a = GPR32 (OP[0]); 798 uint32 b = GPR32 (OP[1]); 799 trace_input ("addd", OP_REGP, OP_REGP, OP_VOID); 800 uint32 tmp = (a + b); 801 SET_GPR32 (OP[1], tmp); 802 trace_output_32 (tmp); 803 SET_PSR_C (tmp > 0xFFFFFFFF); 804 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); 805} 806 807/* addd. */ 808void 809OP_4_8 () 810{ 811 uint32 a = OP[0]; 812 uint32 b = GPR32 (OP[1]); 813 uint32 tmp; 814 trace_input ("addd", OP_CONSTANT20, OP_REGP, OP_VOID); 815 tmp = (a + b); 816 SET_GPR32 (OP[1], tmp); 817 SET_PSR_C (tmp > 0xFFFFFFFF); 818 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); 819 trace_output_32 (tmp); 820} 821 822/* addd. */ 823void 824OP_2_C () 825{ 826 int32 a = OP[0]; 827 uint32 b = GPR32 (OP[1]); 828 uint32 tmp; 829 trace_input ("addd", OP_CONSTANT32, OP_REGP, OP_VOID); 830 tmp = (a + b); 831 SET_GPR32 (OP[1], tmp); 832 SET_PSR_C (tmp > 0xFFFFFFFF); 833 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); 834 trace_output_32 (tmp); 835} 836 837/* andb. */ 838void 839OP_20_8 () 840{ 841 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; 842 trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID); 843 tmp = a & b; 844 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 845 trace_output_16 (tmp); 846} 847 848/* andb. */ 849void 850OP_20B_C () 851{ 852 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; 853 trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID); 854 tmp = a & b; 855 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 856 trace_output_16 (tmp); 857} 858 859/* andb. */ 860void 861OP_21_8 () 862{ 863 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; 864 trace_input ("andb", OP_REG, OP_REG, OP_VOID); 865 tmp = a & b; 866 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 867 trace_output_16 (tmp); 868} 869 870/* andw. */ 871void 872OP_22_8 () 873{ 874 uint16 tmp, a = OP[0], b = GPR (OP[1]); 875 trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID); 876 tmp = a & b; 877 SET_GPR (OP[1], tmp); 878 trace_output_16 (tmp); 879} 880 881/* andw. */ 882void 883OP_22B_C () 884{ 885 uint16 tmp, a = OP[0], b = GPR (OP[1]); 886 trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID); 887 tmp = a & b; 888 SET_GPR (OP[1], tmp); 889 trace_output_16 (tmp); 890} 891 892/* andw. */ 893void 894OP_23_8 () 895{ 896 uint16 tmp, a = GPR (OP[0]), b = GPR (OP[1]); 897 trace_input ("andw", OP_REG, OP_REG, OP_VOID); 898 tmp = a & b; 899 SET_GPR (OP[1], tmp); 900 trace_output_16 (tmp); 901} 902 903/* andd. */ 904void 905OP_4_C () 906{ 907 uint32 tmp, a = OP[0], b = GPR32 (OP[1]); 908 trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID); 909 tmp = a & b; 910 SET_GPR32 (OP[1], tmp); 911 trace_output_32 (tmp); 912} 913 914/* andd. */ 915void 916OP_14B_14 () 917{ 918 uint32 tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1])); 919 trace_input ("andd", OP_REGP, OP_REGP, OP_VOID); 920 tmp = a & b; 921 SET_GPR32 (OP[1], tmp); 922 trace_output_32 (tmp); 923} 924 925/* ord. */ 926void 927OP_5_C () 928{ 929 uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]); 930 trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID); 931 tmp = a | b; 932 SET_GPR32 (OP[1], tmp); 933 trace_output_32 (tmp); 934} 935 936/* ord. */ 937void 938OP_149_14 () 939{ 940 uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]); 941 trace_input ("ord", OP_REGP, OP_REGP, OP_VOID); 942 tmp = a | b; 943 SET_GPR32 (OP[1], tmp); 944 trace_output_32 (tmp); 945} 946 947/* xord. */ 948void 949OP_6_C () 950{ 951 uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]); 952 trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID); 953 tmp = a ^ b; 954 SET_GPR32 (OP[1], tmp); 955 trace_output_32 (tmp); 956} 957 958/* xord. */ 959void 960OP_14A_14 () 961{ 962 uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]); 963 trace_input ("xord", OP_REGP, OP_REGP, OP_VOID); 964 tmp = a ^ b; 965 SET_GPR32 (OP[1], tmp); 966 trace_output_32 (tmp); 967} 968 969 970/* b. */ 971void 972OP_1_4 () 973{ 974 uint32 tmp, cc = cond_stat (OP[0]); 975 trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID); 976 if (cc) 977 { 978 if (sign_flag) 979 tmp = (PC - (OP[1])); 980 else 981 tmp = (PC + (OP[1])); 982 /* If the resulting PC value is less than 0x00_0000 or greater 983 than 0xFF_FFFF, this instruction causes an IAD trap.*/ 984 985 if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) 986 { 987 State.exception = SIG_CR16_BUS; 988 State.pc_changed = 1; /* Don't increment the PC. */ 989 trace_output_void (); 990 return; 991 } 992 else 993 JMP (tmp); 994 } 995 sign_flag = 0; /* Reset sign_flag. */ 996 trace_output_32 (tmp); 997} 998 999/* b. */ 1000void 1001OP_18_8 () 1002{ 1003 uint32 tmp, cc = cond_stat (OP[0]); 1004 trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID); 1005 if (cc) 1006 { 1007 if (sign_flag) 1008 tmp = (PC - OP[1]); 1009 else 1010 tmp = (PC + OP[1]); 1011 /* If the resulting PC value is less than 0x00_0000 or greater 1012 than 0xFF_FFFF, this instruction causes an IAD trap.*/ 1013 1014 if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) 1015 { 1016 State.exception = SIG_CR16_BUS; 1017 State.pc_changed = 1; /* Don't increment the PC. */ 1018 trace_output_void (); 1019 return; 1020 } 1021 else 1022 JMP (tmp); 1023 } 1024 sign_flag = 0; /* Reset sign_flag. */ 1025 trace_output_32 (tmp); 1026} 1027 1028/* b. */ 1029void 1030OP_10_10 () 1031{ 1032 uint32 tmp, cc = cond_stat (OP[0]); 1033 trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID); 1034 if (cc) 1035 { 1036 if (sign_flag) 1037 tmp = (PC - (OP[1])); 1038 else 1039 tmp = (PC + (OP[1])); 1040 /* If the resulting PC value is less than 0x00_0000 or greater 1041 than 0xFF_FFFF, this instruction causes an IAD trap.*/ 1042 1043 if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) 1044 { 1045 State.exception = SIG_CR16_BUS; 1046 State.pc_changed = 1; /* Don't increment the PC. */ 1047 trace_output_void (); 1048 return; 1049 } 1050 else 1051 JMP (tmp); 1052 } 1053 sign_flag = 0; /* Reset sign_flag. */ 1054 trace_output_32 (tmp); 1055} 1056 1057/* bal. */ 1058void 1059OP_C0_8 () 1060{ 1061 uint32 tmp; 1062 trace_input ("bal", OP_REG, OP_DISP17, OP_VOID); 1063 tmp = ((PC + 4) >> 1); /* Store PC in RA register. */ 1064 SET_GPR32 (14, tmp); 1065 if (sign_flag) 1066 tmp = (PC - (OP[1])); 1067 else 1068 tmp = (PC + (OP[1])); 1069 1070 /* If the resulting PC value is less than 0x00_0000 or greater 1071 than 0xFF_FFFF, this instruction causes an IAD trap. */ 1072 1073 if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) 1074 { 1075 State.exception = SIG_CR16_BUS; 1076 State.pc_changed = 1; /* Don't increment the PC. */ 1077 trace_output_void (); 1078 return; 1079 } 1080 else 1081 JMP (tmp); 1082 sign_flag = 0; /* Reset sign_flag. */ 1083 trace_output_32 (tmp); 1084} 1085 1086 1087/* bal. */ 1088void 1089OP_102_14 () 1090{ 1091 uint32 tmp; 1092 trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID); 1093 tmp = (((PC) + 4) >> 1); /* Store PC in reg pair. */ 1094 SET_GPR32 (OP[0], tmp); 1095 if (sign_flag) 1096 tmp = ((PC) - (OP[1])); 1097 else 1098 tmp = ((PC) + (OP[1])); 1099 /* If the resulting PC value is less than 0x00_0000 or greater 1100 than 0xFF_FFFF, this instruction causes an IAD trap.*/ 1101 1102 if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) 1103 { 1104 State.exception = SIG_CR16_BUS; 1105 State.pc_changed = 1; /* Don't increment the PC. */ 1106 trace_output_void (); 1107 return; 1108 } 1109 else 1110 JMP (tmp); 1111 sign_flag = 0; /* Reset sign_flag. */ 1112 trace_output_32 (tmp); 1113} 1114 1115/* jal. */ 1116void 1117OP_148_14 () 1118{ 1119 uint32 tmp; 1120 trace_input ("jal", OP_REGP, OP_REGP, OP_VOID); 1121 SET_GPR32 (OP[0], (((PC) + 4) >> 1)); /* Store next PC in RA */ 1122 tmp = GPR32 (OP[1]); 1123 tmp = SEXT24(tmp << 1); 1124 /* If the resulting PC value is less than 0x00_0000 or greater 1125 than 0xFF_FFFF, this instruction causes an IAD trap.*/ 1126 1127 if ((tmp < 0x0) || (tmp > 0xFFFFFF)) 1128 { 1129 State.exception = SIG_CR16_BUS; 1130 State.pc_changed = 1; /* Don't increment the PC. */ 1131 trace_output_void (); 1132 return; 1133 } 1134 else 1135 JMP (tmp); 1136 1137 trace_output_32 (tmp); 1138} 1139 1140 1141/* jal. */ 1142void 1143OP_D_C () 1144{ 1145 uint32 tmp; 1146 trace_input ("jal", OP_REGP, OP_VOID, OP_VOID); 1147 SET_GPR32 (14, (((PC) + 2) >> 1)); /* Store next PC in RA */ 1148 tmp = GPR32 (OP[0]); 1149 tmp = SEXT24(tmp << 1); 1150 /* If the resulting PC value is less than 0x00_0000 or greater 1151 than 0xFF_FFFF, this instruction causes an IAD trap.*/ 1152 1153 if ((tmp < 0x0) || (tmp > 0xFFFFFF)) 1154 { 1155 State.exception = SIG_CR16_BUS; 1156 State.pc_changed = 1; /* Don't increment the PC. */ 1157 trace_output_void (); 1158 return; 1159 } 1160 else 1161 JMP (tmp); 1162 1163 trace_output_32 (tmp); 1164} 1165 1166 1167/* beq0b. */ 1168void 1169OP_C_8 () 1170{ 1171 uint32 addr; 1172 uint8 a = (GPR (OP[0]) & 0xFF); 1173 trace_input ("beq0b", OP_REG, OP_DISP5, OP_VOID); 1174 addr = OP[1]; 1175 if (a == 0) 1176 { 1177 if (sign_flag) 1178 addr = (PC - OP[1]); 1179 else 1180 addr = (PC + OP[1]); 1181 1182 JMP (addr); 1183 } 1184 sign_flag = 0; /* Reset sign_flag. */ 1185 trace_output_void (); 1186} 1187 1188/* bne0b. */ 1189void 1190OP_D_8 () 1191{ 1192 uint32 addr; 1193 uint8 a = (GPR (OP[0]) & 0xFF); 1194 trace_input ("bne0b", OP_REG, OP_DISP5, OP_VOID); 1195 addr = OP[1]; 1196 if (a != 0) 1197 { 1198 if (sign_flag) 1199 addr = (PC - OP[1]); 1200 else 1201 addr = (PC + OP[1]); 1202 1203 JMP (addr); 1204 } 1205 sign_flag = 0; /* Reset sign_flag. */ 1206 trace_output_void (); 1207} 1208 1209/* beq0w. */ 1210void 1211OP_E_8() 1212{ 1213 uint32 addr; 1214 uint16 a = GPR (OP[0]); 1215 trace_input ("beq0w", OP_REG, OP_DISP5, OP_VOID); 1216 addr = OP[1]; 1217 if (a == 0) 1218 { 1219 if (sign_flag) 1220 addr = (PC - OP[1]); 1221 else 1222 addr = (PC + OP[1]); 1223 1224 JMP (addr); 1225 } 1226 sign_flag = 0; /* Reset sign_flag. */ 1227 trace_output_void (); 1228} 1229 1230/* bne0w. */ 1231void 1232OP_F_8 () 1233{ 1234 uint32 addr; 1235 uint16 a = GPR (OP[0]); 1236 trace_input ("bne0w", OP_REG, OP_DISP5, OP_VOID); 1237 addr = OP[1]; 1238 if (a != 0) 1239 { 1240 if (sign_flag) 1241 addr = (PC - OP[1]); 1242 else 1243 addr = (PC + OP[1]); 1244 1245 JMP (addr); 1246 } 1247 sign_flag = 0; /* Reset sign_flag. */ 1248 trace_output_void (); 1249} 1250 1251 1252/* jeq. */ 1253void 1254OP_A0_C () 1255{ 1256 uint32 tmp; 1257 trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID); 1258 if ((PSR_Z) == 1) 1259 { 1260 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */ 1261 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */ 1262 } 1263 trace_output_32 (tmp); 1264} 1265 1266/* jne. */ 1267void 1268OP_A1_C () 1269{ 1270 uint32 tmp; 1271 trace_input ("jne", OP_REGP, OP_VOID, OP_VOID); 1272 if ((PSR_Z) == 0) 1273 { 1274 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */ 1275 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */ 1276 } 1277 trace_output_32 (tmp); 1278} 1279 1280/* jcs. */ 1281void 1282OP_A2_C () 1283{ 1284 uint32 tmp; 1285 trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID); 1286 if ((PSR_C) == 1) 1287 { 1288 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1289 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1290 } 1291 trace_output_32 (tmp); 1292} 1293 1294/* jcc. */ 1295void 1296OP_A3_C () 1297{ 1298 uint32 tmp; 1299 trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID); 1300 if ((PSR_C) == 0) 1301 { 1302 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1303 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1304 } 1305 trace_output_32 (tmp); 1306} 1307 1308/* jhi. */ 1309void 1310OP_A4_C () 1311{ 1312 uint32 tmp; 1313 trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID); 1314 if ((PSR_L) == 1) 1315 { 1316 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1317 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1318 } 1319 trace_output_32 (tmp); 1320} 1321 1322/* jls. */ 1323void 1324OP_A5_C () 1325{ 1326 uint32 tmp; 1327 trace_input ("jls", OP_REGP, OP_VOID, OP_VOID); 1328 if ((PSR_L) == 0) 1329 { 1330 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1331 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1332 } 1333 trace_output_32 (tmp); 1334} 1335 1336/* jgt. */ 1337void 1338OP_A6_C () 1339{ 1340 uint32 tmp; 1341 trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID); 1342 if ((PSR_N) == 1) 1343 { 1344 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1345 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1346 } 1347 trace_output_32 (tmp); 1348} 1349 1350/* jle. */ 1351void 1352OP_A7_C () 1353{ 1354 uint32 tmp; 1355 trace_input ("jle", OP_REGP, OP_VOID, OP_VOID); 1356 if ((PSR_N) == 0) 1357 { 1358 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1359 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1360 } 1361 trace_output_32 (tmp); 1362} 1363 1364 1365/* jfs. */ 1366void 1367OP_A8_C () 1368{ 1369 uint32 tmp; 1370 trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID); 1371 if ((PSR_F) == 1) 1372 { 1373 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1374 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1375 } 1376 trace_output_32 (tmp); 1377} 1378 1379/* jfc. */ 1380void 1381OP_A9_C () 1382{ 1383 uint32 tmp; 1384 trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID); 1385 if ((PSR_F) == 0) 1386 { 1387 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1388 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1389 } 1390 trace_output_32 (tmp); 1391} 1392 1393/* jlo. */ 1394void 1395OP_AA_C () 1396{ 1397 uint32 tmp; 1398 trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID); 1399 if (((PSR_Z) == 0) & ((PSR_L) == 0)) 1400 { 1401 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1402 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1403 } 1404 trace_output_32 (tmp); 1405} 1406 1407/* jhs. */ 1408void 1409OP_AB_C () 1410{ 1411 uint32 tmp; 1412 trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID); 1413 if (((PSR_Z) == 1) | ((PSR_L) == 1)) 1414 { 1415 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1416 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1417 } 1418 trace_output_32 (tmp); 1419} 1420 1421/* jlt. */ 1422void 1423OP_AC_C () 1424{ 1425 uint32 tmp; 1426 trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID); 1427 if (((PSR_Z) == 0) & ((PSR_N) == 0)) 1428 { 1429 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1430 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1431 } 1432 trace_output_32 (tmp); 1433} 1434 1435/* jge. */ 1436void 1437OP_AD_C () 1438{ 1439 uint32 tmp; 1440 trace_input ("jge", OP_REGP, OP_VOID, OP_VOID); 1441 if (((PSR_Z) == 1) | ((PSR_N) == 1)) 1442 { 1443 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1444 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1445 } 1446 trace_output_32 (tmp); 1447} 1448 1449/* jump. */ 1450void 1451OP_AE_C () 1452{ 1453 uint32 tmp; 1454 trace_input ("jump", OP_REGP, OP_VOID, OP_VOID); 1455 tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */ 1456 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1457 trace_output_32 (tmp); 1458} 1459 1460/* jusr. */ 1461void 1462OP_AF_C () 1463{ 1464 uint32 tmp; 1465 trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID); 1466 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1467 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1468 SET_PSR_U(1); 1469 trace_output_32 (tmp); 1470} 1471 1472/* seq. */ 1473void 1474OP_80_C () 1475{ 1476 trace_input ("seq", OP_REG, OP_VOID, OP_VOID); 1477 if ((PSR_Z) == 1) 1478 SET_GPR (OP[0], 1); 1479 else 1480 SET_GPR (OP[0], 0); 1481 trace_output_void (); 1482} 1483/* sne. */ 1484void 1485OP_81_C () 1486{ 1487 trace_input ("sne", OP_REG, OP_VOID, OP_VOID); 1488 if ((PSR_Z) == 0) 1489 SET_GPR (OP[0], 1); 1490 else 1491 SET_GPR (OP[0], 0); 1492 trace_output_void (); 1493} 1494 1495/* scs. */ 1496void 1497OP_82_C () 1498{ 1499 trace_input ("scs", OP_REG, OP_VOID, OP_VOID); 1500 if ((PSR_C) == 1) 1501 SET_GPR (OP[0], 1); 1502 else 1503 SET_GPR (OP[0], 0); 1504 trace_output_void (); 1505} 1506 1507/* scc. */ 1508void 1509OP_83_C () 1510{ 1511 trace_input ("scc", OP_REG, OP_VOID, OP_VOID); 1512 if ((PSR_C) == 0) 1513 SET_GPR (OP[0], 1); 1514 else 1515 SET_GPR (OP[0], 0); 1516 trace_output_void (); 1517} 1518 1519/* shi. */ 1520void 1521OP_84_C () 1522{ 1523 trace_input ("shi", OP_REG, OP_VOID, OP_VOID); 1524 if ((PSR_L) == 1) 1525 SET_GPR (OP[0], 1); 1526 else 1527 SET_GPR (OP[0], 0); 1528 trace_output_void (); 1529} 1530 1531/* sls. */ 1532void 1533OP_85_C () 1534{ 1535 trace_input ("sls", OP_REG, OP_VOID, OP_VOID); 1536 if ((PSR_L) == 0) 1537 SET_GPR (OP[0], 1); 1538 else 1539 SET_GPR (OP[0], 0); 1540 trace_output_void (); 1541} 1542 1543/* sgt. */ 1544void 1545OP_86_C () 1546{ 1547 trace_input ("sgt", OP_REG, OP_VOID, OP_VOID); 1548 if ((PSR_N) == 1) 1549 SET_GPR (OP[0], 1); 1550 else 1551 SET_GPR (OP[0], 0); 1552 trace_output_void (); 1553} 1554 1555/* sle. */ 1556void 1557OP_87_C () 1558{ 1559 trace_input ("sle", OP_REG, OP_VOID, OP_VOID); 1560 if ((PSR_N) == 0) 1561 SET_GPR (OP[0], 1); 1562 else 1563 SET_GPR (OP[0], 0); 1564 trace_output_void (); 1565} 1566 1567/* sfs. */ 1568void 1569OP_88_C () 1570{ 1571 trace_input ("sfs", OP_REG, OP_VOID, OP_VOID); 1572 if ((PSR_F) == 1) 1573 SET_GPR (OP[0], 1); 1574 else 1575 SET_GPR (OP[0], 0); 1576 trace_output_void (); 1577} 1578 1579/* sfc. */ 1580void 1581OP_89_C () 1582{ 1583 trace_input ("sfc", OP_REG, OP_VOID, OP_VOID); 1584 if ((PSR_F) == 0) 1585 SET_GPR (OP[0], 1); 1586 else 1587 SET_GPR (OP[0], 0); 1588 trace_output_void (); 1589} 1590 1591 1592/* slo. */ 1593void 1594OP_8A_C () 1595{ 1596 trace_input ("slo", OP_REG, OP_VOID, OP_VOID); 1597 if (((PSR_Z) == 0) & ((PSR_L) == 0)) 1598 SET_GPR (OP[0], 1); 1599 else 1600 SET_GPR (OP[0], 0); 1601 trace_output_void (); 1602} 1603 1604/* shs. */ 1605void 1606OP_8B_C () 1607{ 1608 trace_input ("shs", OP_REG, OP_VOID, OP_VOID); 1609 if ( ((PSR_Z) == 1) | ((PSR_L) == 1)) 1610 SET_GPR (OP[0], 1); 1611 else 1612 SET_GPR (OP[0], 0); 1613 trace_output_void (); 1614} 1615 1616/* slt. */ 1617void 1618OP_8C_C () 1619{ 1620 trace_input ("slt", OP_REG, OP_VOID, OP_VOID); 1621 if (((PSR_Z) == 0) & ((PSR_N) == 0)) 1622 SET_GPR (OP[0], 1); 1623 else 1624 SET_GPR (OP[0], 0); 1625 trace_output_void (); 1626} 1627 1628/* sge. */ 1629void 1630OP_8D_C () 1631{ 1632 trace_input ("sge", OP_REG, OP_VOID, OP_VOID); 1633 if (((PSR_Z) == 1) | ((PSR_N) == 1)) 1634 SET_GPR (OP[0], 1); 1635 else 1636 SET_GPR (OP[0], 0); 1637 trace_output_void (); 1638} 1639 1640/* cbitb. */ 1641void 1642OP_D7_9 () 1643{ 1644 uint8 a = OP[0] & 0xff; 1645 uint32 addr = OP[1], tmp; 1646 trace_input ("cbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); 1647 tmp = RB (addr); 1648 SET_PSR_F (tmp & (1 << a)); 1649 tmp = tmp & ~(1 << a); 1650 SB (addr, tmp); 1651 trace_output_32 (tmp); 1652} 1653 1654/* cbitb. */ 1655void 1656OP_107_14 () 1657{ 1658 uint8 a = OP[0] & 0xff; 1659 uint32 addr = OP[1], tmp; 1660 trace_input ("cbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); 1661 tmp = RB (addr); 1662 SET_PSR_F (tmp & (1 << a)); 1663 tmp = tmp & ~(1 << a); 1664 SB (addr, tmp); 1665 trace_output_32 (tmp); 1666} 1667 1668/* cbitb. */ 1669void 1670OP_68_8 () 1671{ 1672 uint8 a = (OP[0]) & 0xff; 1673 uint32 addr = (GPR (OP[2])) + OP[1], tmp; 1674 trace_input ("cbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID); 1675 tmp = RB (addr); 1676 SET_PSR_F (tmp & (1 << a)); 1677 tmp = tmp & ~(1 << a); 1678 SB (addr, tmp); 1679 trace_output_32 (addr); 1680} 1681 1682/* cbitb. */ 1683void 1684OP_1AA_A () 1685{ 1686 uint8 a = (OP[0]) & 0xff; 1687 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 1688 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); 1689 tmp = RB (addr); 1690 SET_PSR_F (tmp & (1 << a)); 1691 tmp = tmp & ~(1 << a); 1692 SB (addr, tmp); 1693 trace_output_32 (addr); 1694} 1695 1696/* cbitb. */ 1697void 1698OP_104_14 () 1699{ 1700 uint8 a = (OP[0]) & 0xff; 1701 uint32 addr = (GPR (OP[2])) + OP[1], tmp; 1702 trace_input ("cbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); 1703 tmp = RB (addr); 1704 SET_PSR_F (tmp & (1 << a)); 1705 tmp = tmp & ~(1 << a); 1706 SB (addr, tmp); 1707 trace_output_32 (addr); 1708} 1709 1710/* cbitb. */ 1711void 1712OP_D4_9 () 1713{ 1714 uint8 a = (OP[0]) & 0xff; 1715 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 1716 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); 1717 tmp = RB (addr); 1718 SET_PSR_F (tmp & (1 << a)); 1719 tmp = tmp & ~(1 << a); 1720 SB (addr, tmp); 1721 trace_output_32 (addr); 1722} 1723 1724/* cbitb. */ 1725void 1726OP_D6_9 () 1727{ 1728 uint8 a = (OP[0]) & 0xff; 1729 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 1730 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); 1731 tmp = RB (addr); 1732 SET_PSR_F (tmp & (1 << a)); 1733 tmp = tmp & ~(1 << a); 1734 SB (addr, tmp); 1735 trace_output_32 (addr); 1736 1737} 1738 1739/* cbitb. */ 1740void 1741OP_105_14 () 1742{ 1743 uint8 a = (OP[0]) & 0xff; 1744 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 1745 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); 1746 tmp = RB (addr); 1747 SET_PSR_F (tmp & (1 << a)); 1748 tmp = tmp & ~(1 << a); 1749 SB (addr, tmp); 1750 trace_output_32 (addr); 1751} 1752 1753/* cbitb. */ 1754void 1755OP_106_14 () 1756{ 1757 uint8 a = (OP[0]) & 0xff; 1758 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 1759 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); 1760 tmp = RB (addr); 1761 SET_PSR_F (tmp & (1 << a)); 1762 tmp = tmp & ~(1 << a); 1763 SB (addr, tmp); 1764 trace_output_32 (addr); 1765} 1766 1767 1768/* cbitw. */ 1769void 1770OP_6F_8 () 1771{ 1772 uint16 a = OP[0]; 1773 uint32 addr = OP[1], tmp; 1774 trace_input ("cbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); 1775 tmp = RW (addr); 1776 SET_PSR_F (tmp & (1 << a)); 1777 tmp = tmp & ~(1 << a); 1778 SW (addr, tmp); 1779 trace_output_32 (tmp); 1780} 1781 1782/* cbitw. */ 1783void 1784OP_117_14 () 1785{ 1786 uint16 a = OP[0]; 1787 uint32 addr = OP[1], tmp; 1788 trace_input ("cbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); 1789 tmp = RW (addr); 1790 SET_PSR_F (tmp & (1 << a)); 1791 tmp = tmp & ~(1 << a); 1792 SW (addr, tmp); 1793 trace_output_32 (tmp); 1794} 1795 1796/* cbitw. */ 1797void 1798OP_36_7 () 1799{ 1800 uint32 addr; 1801 uint16 a = (OP[0]), tmp; 1802 trace_input ("cbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID); 1803 1804 if (OP[1] == 0) 1805 addr = (GPR32 (12)) + OP[2]; 1806 else 1807 addr = (GPR32 (13)) + OP[2]; 1808 1809 tmp = RW (addr); 1810 SET_PSR_F (tmp & (1 << a)); 1811 tmp = tmp & ~(1 << a); 1812 SW (addr, tmp); 1813 trace_output_32 (addr); 1814 1815} 1816 1817/* cbitw. */ 1818void 1819OP_1AB_A () 1820{ 1821 uint16 a = (OP[0]); 1822 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 1823 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); 1824 tmp = RW (addr); 1825 SET_PSR_F (tmp & (1 << a)); 1826 tmp = tmp & ~(1 << a); 1827 SW (addr, tmp); 1828 trace_output_32 (addr); 1829} 1830 1831/* cbitw. */ 1832void 1833OP_114_14 () 1834{ 1835 uint16 a = (OP[0]); 1836 uint32 addr = (GPR (OP[2])) + OP[1], tmp; 1837 trace_input ("cbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); 1838 tmp = RW (addr); 1839 SET_PSR_F (tmp & (1 << a)); 1840 tmp = tmp & ~(1 << a); 1841 SW (addr, tmp); 1842 trace_output_32 (addr); 1843} 1844 1845 1846/* cbitw. */ 1847void 1848OP_6E_8 () 1849{ 1850 uint16 a = (OP[0]); 1851 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 1852 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); 1853 tmp = RW (addr); 1854 SET_PSR_F (tmp & (1 << a)); 1855 tmp = tmp & ~(1 << a); 1856 SW (addr, tmp); 1857 trace_output_32 (addr); 1858} 1859 1860/* cbitw. */ 1861void 1862OP_69_8 () 1863{ 1864 uint16 a = (OP[0]); 1865 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 1866 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); 1867 tmp = RW (addr); 1868 SET_PSR_F (tmp & (1 << a)); 1869 tmp = tmp & ~(1 << a); 1870 SW (addr, tmp); 1871 trace_output_32 (addr); 1872} 1873 1874 1875/* cbitw. */ 1876void 1877OP_115_14 () 1878{ 1879 uint16 a = (OP[0]); 1880 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 1881 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); 1882 tmp = RW (addr); 1883 SET_PSR_F (tmp & (1 << a)); 1884 tmp = tmp & ~(1 << a); 1885 SW (addr, tmp); 1886 trace_output_32 (addr); 1887} 1888 1889/* cbitw. */ 1890void 1891OP_116_14 () 1892{ 1893 uint16 a = (OP[0]); 1894 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 1895 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); 1896 tmp = RW (addr); 1897 SET_PSR_F (tmp & (1 << a)); 1898 tmp = tmp & ~(1 << a); 1899 SW (addr, tmp); 1900 trace_output_32 (addr); 1901} 1902 1903/* sbitb. */ 1904void 1905OP_E7_9 () 1906{ 1907 uint8 a = OP[0] & 0xff; 1908 uint32 addr = OP[1], tmp; 1909 trace_input ("sbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); 1910 tmp = RB (addr); 1911 SET_PSR_F (tmp & (1 << a)); 1912 tmp = tmp | (1 << a); 1913 SB (addr, tmp); 1914 trace_output_32 (tmp); 1915} 1916 1917/* sbitb. */ 1918void 1919OP_10B_14 () 1920{ 1921 uint8 a = OP[0] & 0xff; 1922 uint32 addr = OP[1], tmp; 1923 trace_input ("sbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); 1924 tmp = RB (addr); 1925 SET_PSR_F (tmp & (1 << a)); 1926 tmp = tmp | (1 << a); 1927 SB (addr, tmp); 1928 trace_output_32 (tmp); 1929} 1930 1931/* sbitb. */ 1932void 1933OP_70_8 () 1934{ 1935 uint8 a = OP[0] & 0xff; 1936 uint32 addr = (GPR (OP[2])) + OP[1], tmp; 1937 trace_input ("sbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID); 1938 tmp = RB (addr); 1939 SET_PSR_F (tmp & (1 << a)); 1940 tmp = tmp | (1 << a); 1941 SB (addr, tmp); 1942 trace_output_32 (tmp); 1943} 1944 1945/* sbitb. */ 1946void 1947OP_1CA_A () 1948{ 1949 uint8 a = OP[0] & 0xff; 1950 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 1951 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); 1952 tmp = RB (addr); 1953 SET_PSR_F (tmp & (1 << a)); 1954 tmp = tmp | (1 << a); 1955 SB (addr, tmp); 1956 trace_output_32 (tmp); 1957} 1958 1959/* sbitb. */ 1960void 1961OP_108_14 () 1962{ 1963 uint8 a = OP[0] & 0xff; 1964 uint32 addr = (GPR (OP[2])) + OP[1], tmp; 1965 trace_input ("sbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); 1966 tmp = RB (addr); 1967 SET_PSR_F (tmp & (1 << a)); 1968 tmp = tmp | (1 << a); 1969 SB (addr, tmp); 1970 trace_output_32 (tmp); 1971} 1972 1973 1974/* sbitb. */ 1975void 1976OP_E4_9 () 1977{ 1978 uint8 a = OP[0] & 0xff; 1979 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 1980 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); 1981 tmp = RB (addr); 1982 SET_PSR_F (tmp & (1 << a)); 1983 tmp = tmp | (1 << a); 1984 SB (addr, tmp); 1985 trace_output_32 (tmp); 1986} 1987 1988/* sbitb. */ 1989void 1990OP_E6_9 () 1991{ 1992 uint8 a = OP[0] & 0xff; 1993 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 1994 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); 1995 tmp = RB (addr); 1996 SET_PSR_F (tmp & (1 << a)); 1997 tmp = tmp | (1 << a); 1998 SB (addr, tmp); 1999 trace_output_32 (tmp); 2000} 2001 2002 2003/* sbitb. */ 2004void 2005OP_109_14 () 2006{ 2007 uint8 a = OP[0] & 0xff; 2008 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 2009 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); 2010 tmp = RB (addr); 2011 SET_PSR_F (tmp & (1 << a)); 2012 tmp = tmp | (1 << a); 2013 SB (addr, tmp); 2014 trace_output_32 (tmp); 2015} 2016 2017 2018/* sbitb. */ 2019void 2020OP_10A_14 () 2021{ 2022 uint8 a = OP[0] & 0xff; 2023 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 2024 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); 2025 tmp = RB (addr); 2026 SET_PSR_F (tmp & (1 << a)); 2027 tmp = tmp | (1 << a); 2028 SB (addr, tmp); 2029 trace_output_32 (tmp); 2030} 2031 2032 2033/* sbitw. */ 2034void 2035OP_77_8 () 2036{ 2037 uint16 a = OP[0]; 2038 uint32 addr = OP[1], tmp; 2039 trace_input ("sbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); 2040 tmp = RW (addr); 2041 SET_PSR_F (tmp & (1 << a)); 2042 tmp = tmp | (1 << a); 2043 SW (addr, tmp); 2044 trace_output_32 (tmp); 2045} 2046 2047/* sbitw. */ 2048void 2049OP_11B_14 () 2050{ 2051 uint16 a = OP[0]; 2052 uint32 addr = OP[1], tmp; 2053 trace_input ("sbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); 2054 tmp = RW (addr); 2055 SET_PSR_F (tmp & (1 << a)); 2056 tmp = tmp | (1 << a); 2057 SW (addr, tmp); 2058 trace_output_32 (tmp); 2059} 2060 2061/* sbitw. */ 2062void 2063OP_3A_7 () 2064{ 2065 uint32 addr; 2066 uint16 a = (OP[0]), tmp; 2067 trace_input ("sbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID); 2068 2069 if (OP[1] == 0) 2070 addr = (GPR32 (12)) + OP[2]; 2071 else 2072 addr = (GPR32 (13)) + OP[2]; 2073 2074 tmp = RW (addr); 2075 SET_PSR_F (tmp & (1 << a)); 2076 tmp = tmp | (1 << a); 2077 SW (addr, tmp); 2078 trace_output_32 (addr); 2079} 2080 2081/* sbitw. */ 2082void 2083OP_1CB_A () 2084{ 2085 uint16 a = (OP[0]); 2086 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 2087 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); 2088 tmp = RW (addr); 2089 SET_PSR_F (tmp & (1 << a)); 2090 tmp = tmp | (1 << a); 2091 SW (addr, tmp); 2092 trace_output_32 (addr); 2093} 2094 2095/* sbitw. */ 2096void 2097OP_118_14 () 2098{ 2099 uint16 a = (OP[0]); 2100 uint32 addr = (GPR (OP[2])) + OP[1], tmp; 2101 trace_input ("sbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); 2102 tmp = RW (addr); 2103 SET_PSR_F (tmp & (1 << a)); 2104 tmp = tmp | (1 << a); 2105 SW (addr, tmp); 2106 trace_output_32 (addr); 2107} 2108 2109/* sbitw. */ 2110void 2111OP_76_8 () 2112{ 2113 uint16 a = (OP[0]); 2114 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 2115 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); 2116 tmp = RW (addr); 2117 SET_PSR_F (tmp & (1 << a)); 2118 tmp = tmp | (1 << a); 2119 SW (addr, tmp); 2120 trace_output_32 (addr); 2121} 2122 2123/* sbitw. */ 2124void 2125OP_71_8 () 2126{ 2127 uint16 a = (OP[0]); 2128 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 2129 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); 2130 tmp = RW (addr); 2131 SET_PSR_F (tmp & (1 << a)); 2132 tmp = tmp | (1 << a); 2133 SW (addr, tmp); 2134 trace_output_32 (addr); 2135} 2136 2137/* sbitw. */ 2138void 2139OP_119_14 () 2140{ 2141 uint16 a = (OP[0]); 2142 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 2143 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); 2144 tmp = RW (addr); 2145 SET_PSR_F (tmp & (1 << a)); 2146 tmp = tmp | (1 << a); 2147 SW (addr, tmp); 2148 trace_output_32 (addr); 2149} 2150 2151/* sbitw. */ 2152void 2153OP_11A_14 () 2154{ 2155 uint16 a = (OP[0]); 2156 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 2157 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); 2158 tmp = RW (addr); 2159 SET_PSR_F (tmp & (1 << a)); 2160 tmp = tmp | (1 << a); 2161 SW (addr, tmp); 2162 trace_output_32 (addr); 2163} 2164 2165 2166/* tbitb. */ 2167void 2168OP_F7_9 () 2169{ 2170 uint8 a = OP[0] & 0xff; 2171 uint32 addr = OP[1], tmp; 2172 trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); 2173 tmp = RB (addr); 2174 SET_PSR_F (tmp & (1 << a)); 2175 trace_output_32 (tmp); 2176} 2177 2178/* tbitb. */ 2179void 2180OP_10F_14 () 2181{ 2182 uint8 a = OP[0] & 0xff; 2183 uint32 addr = OP[1], tmp; 2184 trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); 2185 tmp = RB (addr); 2186 SET_PSR_F (tmp & (1 << a)); 2187 trace_output_32 (tmp); 2188} 2189 2190/* tbitb. */ 2191void 2192OP_78_8 () 2193{ 2194 uint8 a = (OP[0]) & 0xff; 2195 uint32 addr = (GPR (OP[2])) + OP[1], tmp; 2196 trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID); 2197 tmp = RB (addr); 2198 SET_PSR_F (tmp & (1 << a)); 2199 trace_output_32 (addr); 2200} 2201 2202/* tbitb. */ 2203void 2204OP_1EA_A () 2205{ 2206 uint8 a = (OP[0]) & 0xff; 2207 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 2208 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); 2209 tmp = RB (addr); 2210 SET_PSR_F (tmp & (1 << a)); 2211 trace_output_32 (addr); 2212} 2213 2214/* tbitb. */ 2215void 2216OP_10C_14 () 2217{ 2218 uint8 a = (OP[0]) & 0xff; 2219 uint32 addr = (GPR (OP[2])) + OP[1], tmp; 2220 trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); 2221 tmp = RB (addr); 2222 SET_PSR_F (tmp & (1 << a)); 2223 trace_output_32 (addr); 2224} 2225 2226/* tbitb. */ 2227void 2228OP_F4_9 () 2229{ 2230 uint8 a = (OP[0]) & 0xff; 2231 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 2232 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); 2233 tmp = RB (addr); 2234 SET_PSR_F (tmp & (1 << a)); 2235 trace_output_32 (addr); 2236} 2237 2238/* tbitb. */ 2239void 2240OP_F6_9 () 2241{ 2242 uint8 a = (OP[0]) & 0xff; 2243 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 2244 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); 2245 tmp = RB (addr); 2246 SET_PSR_F (tmp & (1 << a)); 2247 trace_output_32 (addr); 2248} 2249 2250/* tbitb. */ 2251void 2252OP_10D_14 () 2253{ 2254 uint8 a = (OP[0]) & 0xff; 2255 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 2256 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); 2257 tmp = RB (addr); 2258 SET_PSR_F (tmp & (1 << a)); 2259 trace_output_32 (addr); 2260} 2261 2262/* tbitb. */ 2263void 2264OP_10E_14 () 2265{ 2266 uint8 a = (OP[0]) & 0xff; 2267 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 2268 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); 2269 tmp = RB (addr); 2270 SET_PSR_F (tmp & (1 << a)); 2271 trace_output_32 (addr); 2272} 2273 2274 2275/* tbitw. */ 2276void 2277OP_7F_8 () 2278{ 2279 uint16 a = OP[0]; 2280 uint32 addr = OP[1], tmp; 2281 trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); 2282 tmp = RW (addr); 2283 SET_PSR_F (tmp & (1 << a)); 2284 trace_output_32 (tmp); 2285} 2286 2287/* tbitw. */ 2288void 2289OP_11F_14 () 2290{ 2291 uint16 a = OP[0]; 2292 uint32 addr = OP[1], tmp; 2293 trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); 2294 tmp = RW (addr); 2295 SET_PSR_F (tmp & (1 << a)); 2296 trace_output_32 (tmp); 2297} 2298 2299 2300/* tbitw. */ 2301void 2302OP_3E_7 () 2303{ 2304 uint32 addr; 2305 uint16 a = (OP[0]), tmp; 2306 trace_input ("tbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID); 2307 2308 if (OP[1] == 0) 2309 addr = (GPR32 (12)) + OP[2]; 2310 else 2311 addr = (GPR32 (13)) + OP[2]; 2312 2313 tmp = RW (addr); 2314 SET_PSR_F (tmp & (1 << a)); 2315 trace_output_32 (addr); 2316} 2317 2318/* tbitw. */ 2319void 2320OP_1EB_A () 2321{ 2322 uint16 a = (OP[0]); 2323 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 2324 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); 2325 tmp = RW (addr); 2326 SET_PSR_F (tmp & (1 << a)); 2327 trace_output_32 (addr); 2328} 2329 2330/* tbitw. */ 2331void 2332OP_11C_14 () 2333{ 2334 uint16 a = (OP[0]); 2335 uint32 addr = (GPR (OP[2])) + OP[1], tmp; 2336 trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); 2337 tmp = RW (addr); 2338 SET_PSR_F (tmp & (1 << a)); 2339 trace_output_32 (addr); 2340} 2341 2342/* tbitw. */ 2343void 2344OP_7E_8 () 2345{ 2346 uint16 a = (OP[0]); 2347 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 2348 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); 2349 tmp = RW (addr); 2350 SET_PSR_F (tmp & (1 << a)); 2351 trace_output_32 (addr); 2352} 2353 2354/* tbitw. */ 2355void 2356OP_79_8 () 2357{ 2358 uint16 a = (OP[0]); 2359 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 2360 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); 2361 tmp = RW (addr); 2362 SET_PSR_F (tmp & (1 << a)); 2363 trace_output_32 (addr); 2364} 2365 2366/* tbitw. */ 2367void 2368OP_11D_14 () 2369{ 2370 uint16 a = (OP[0]); 2371 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 2372 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); 2373 tmp = RW (addr); 2374 SET_PSR_F (tmp & (1 << a)); 2375 trace_output_32 (addr); 2376} 2377 2378 2379/* tbitw. */ 2380void 2381OP_11E_14 () 2382{ 2383 uint16 a = (OP[0]); 2384 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; 2385 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); 2386 tmp = RW (addr); 2387 SET_PSR_F (tmp & (1 << a)); 2388 trace_output_32 (addr); 2389} 2390 2391 2392/* tbit. */ 2393void 2394OP_6_8 () 2395{ 2396 uint16 a = OP[0]; 2397 uint16 b = (GPR (OP[1])); 2398 trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID); 2399 SET_PSR_F (b & (1 << a)); 2400 trace_output_16 (b); 2401} 2402 2403/* tbit. */ 2404void 2405OP_7_8 () 2406{ 2407 uint16 a = GPR (OP[0]); 2408 uint16 b = (GPR (OP[1])); 2409 trace_input ("tbit", OP_REG, OP_REG, OP_VOID); 2410 SET_PSR_F (b & (1 << a)); 2411 trace_output_16 (b); 2412} 2413 2414 2415/* cmpb. */ 2416void 2417OP_50_8 () 2418{ 2419 uint8 a = (OP[0]) & 0xFF; 2420 uint8 b = (GPR (OP[1])) & 0xFF; 2421 trace_input ("cmpb", OP_CONSTANT4, OP_REG, OP_VOID); 2422 SET_PSR_Z (a == b); 2423 SET_PSR_N ((int8)a > (int8)b); 2424 SET_PSR_L (a > b); 2425 trace_output_flag (); 2426} 2427 2428/* cmpb. */ 2429void 2430OP_50B_C () 2431{ 2432 uint8 a = (OP[0]) & 0xFF; 2433 uint8 b = (GPR (OP[1])) & 0xFF; 2434 trace_input ("cmpb", OP_CONSTANT16, OP_REG, OP_VOID); 2435 SET_PSR_Z (a == b); 2436 SET_PSR_N ((int8)a > (int8)b); 2437 SET_PSR_L (a > b); 2438 trace_output_flag (); 2439} 2440 2441/* cmpb. */ 2442void 2443OP_51_8 () 2444{ 2445 uint8 a = (GPR (OP[0])) & 0xFF; 2446 uint8 b = (GPR (OP[1])) & 0xFF; 2447 trace_input ("cmpb", OP_REG, OP_REG, OP_VOID); 2448 SET_PSR_Z (a == b); 2449 SET_PSR_N ((int8)a > (int8)b); 2450 SET_PSR_L (a > b); 2451 trace_output_flag (); 2452} 2453 2454/* cmpw. */ 2455void 2456OP_52_8 () 2457{ 2458 uint16 a = (OP[0]); 2459 uint16 b = GPR (OP[1]); 2460 trace_input ("cmpw", OP_CONSTANT4, OP_REG, OP_VOID); 2461 SET_PSR_Z (a == b); 2462 SET_PSR_N ((int16)a > (int16)b); 2463 SET_PSR_L (a > b); 2464 trace_output_flag (); 2465} 2466 2467/* cmpw. */ 2468void 2469OP_52B_C () 2470{ 2471 uint16 a = (OP[0]); 2472 uint16 b = GPR (OP[1]); 2473 trace_input ("cmpw", OP_CONSTANT16, OP_REG, OP_VOID); 2474 SET_PSR_Z (a == b); 2475 SET_PSR_N ((int16)a > (int16)b); 2476 SET_PSR_L (a > b); 2477 trace_output_flag (); 2478} 2479 2480/* cmpw. */ 2481void 2482OP_53_8 () 2483{ 2484 uint16 a = GPR (OP[0]) ; 2485 uint16 b = GPR (OP[1]) ; 2486 trace_input ("cmpw", OP_REG, OP_REG, OP_VOID); 2487 SET_PSR_Z (a == b); 2488 SET_PSR_N ((int16)a > (int16)b); 2489 SET_PSR_L (a > b); 2490 trace_output_flag (); 2491} 2492 2493/* cmpd. */ 2494void 2495OP_56_8 () 2496{ 2497 uint32 a = (OP[0]); 2498 uint32 b = GPR32 (OP[1]); 2499 trace_input ("cmpd", OP_CONSTANT4, OP_REGP, OP_VOID); 2500 SET_PSR_Z (a == b); 2501 SET_PSR_N ((int32)a > (int32)b); 2502 SET_PSR_L (a > b); 2503 trace_output_flag (); 2504} 2505 2506/* cmpd. */ 2507void 2508OP_56B_C () 2509{ 2510 uint32 a = (SEXT16(OP[0])); 2511 uint32 b = GPR32 (OP[1]); 2512 trace_input ("cmpd", OP_CONSTANT16, OP_REGP, OP_VOID); 2513 SET_PSR_Z (a == b); 2514 SET_PSR_N ((int32)a > (int32)b); 2515 SET_PSR_L (a > b); 2516 trace_output_flag (); 2517} 2518 2519/* cmpd. */ 2520void 2521OP_57_8 () 2522{ 2523 uint32 a = GPR32 (OP[0]) ; 2524 uint32 b = GPR32 (OP[1]) ; 2525 trace_input ("cmpd", OP_REGP, OP_REGP, OP_VOID); 2526 SET_PSR_Z (a == b); 2527 SET_PSR_N ((int32)a > (int32)b); 2528 SET_PSR_L (a > b); 2529 trace_output_flag (); 2530} 2531 2532/* cmpd. */ 2533void 2534OP_9_C() 2535{ 2536 uint32 a = (OP[0]); 2537 uint32 b = GPR32 (OP[1]); 2538 trace_input ("cmpd", OP_CONSTANT32, OP_REGP, OP_VOID); 2539 SET_PSR_Z (a == b); 2540 SET_PSR_N ((int32)a > (int32)b); 2541 SET_PSR_L (a > b); 2542 trace_output_flag (); 2543} 2544 2545 2546/* movb. */ 2547void 2548OP_58_8 () 2549{ 2550 uint8 tmp = OP[0] & 0xFF; 2551 trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID); 2552 uint16 a = (GPR (OP[1])) & 0xFF00; 2553 SET_GPR (OP[1], (a | tmp)); 2554 trace_output_16 (tmp); 2555} 2556 2557/* movb. */ 2558void 2559OP_58B_C () 2560{ 2561 uint8 tmp = OP[0] & 0xFF; 2562 trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID); 2563 uint16 a = (GPR (OP[1])) & 0xFF00; 2564 SET_GPR (OP[1], (a | tmp)); 2565 trace_output_16 (tmp); 2566} 2567 2568/* movb. */ 2569void 2570OP_59_8 () 2571{ 2572 uint8 tmp = (GPR (OP[0])) & 0xFF; 2573 trace_input ("movb", OP_REG, OP_REG, OP_VOID); 2574 uint16 a = (GPR (OP[1])) & 0xFF00; 2575 SET_GPR (OP[1], (a | tmp)); 2576 trace_output_16 (tmp); 2577} 2578 2579/* movw. */ 2580void 2581OP_5A_8 () 2582{ 2583 uint16 tmp = OP[0]; 2584 trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID); 2585 SET_GPR (OP[1], (tmp & 0xffff)); 2586 trace_output_16 (tmp); 2587} 2588 2589/* movw. */ 2590void 2591OP_5AB_C () 2592{ 2593 int16 tmp = OP[0]; 2594 trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID); 2595 SET_GPR (OP[1], (tmp & 0xffff)); 2596 trace_output_16 (tmp); 2597} 2598 2599/* movw. */ 2600void 2601OP_5B_8 () 2602{ 2603 uint16 tmp = GPR (OP[0]); 2604 trace_input ("movw", OP_REG, OP_REGP, OP_VOID); 2605 uint32 a = GPR32 (OP[1]); 2606 a = (a & 0xffff0000) | tmp; 2607 SET_GPR32 (OP[1], a); 2608 trace_output_16 (tmp); 2609} 2610 2611/* movxb. */ 2612void 2613OP_5C_8 () 2614{ 2615 uint8 tmp = (GPR (OP[0])) & 0xFF; 2616 trace_input ("movxb", OP_REG, OP_REG, OP_VOID); 2617 SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff)); 2618 trace_output_16 (tmp); 2619} 2620 2621/* movzb. */ 2622void 2623OP_5D_8 () 2624{ 2625 uint8 tmp = (GPR (OP[0])) & 0xFF; 2626 trace_input ("movzb", OP_REG, OP_REG, OP_VOID); 2627 SET_GPR (OP[1], tmp); 2628 trace_output_16 (tmp); 2629} 2630 2631/* movxw. */ 2632void 2633OP_5E_8 () 2634{ 2635 uint16 tmp = GPR (OP[0]); 2636 trace_input ("movxw", OP_REG, OP_REGP, OP_VOID); 2637 SET_GPR32 (OP[1], SEXT16(tmp)); 2638 trace_output_16 (tmp); 2639} 2640 2641/* movzw. */ 2642void 2643OP_5F_8 () 2644{ 2645 uint16 tmp = GPR (OP[0]); 2646 trace_input ("movzw", OP_REG, OP_REGP, OP_VOID); 2647 SET_GPR32 (OP[1], (tmp & 0x0000FFFF)); 2648 trace_output_16 (tmp); 2649} 2650 2651/* movd. */ 2652void 2653OP_54_8 () 2654{ 2655 int32 tmp = OP[0]; 2656 trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID); 2657 SET_GPR32 (OP[1], tmp); 2658 trace_output_32 (tmp); 2659} 2660 2661/* movd. */ 2662void 2663OP_54B_C () 2664{ 2665 int32 tmp = SEXT16(OP[0]); 2666 trace_input ("movd", OP_CONSTANT16, OP_REGP, OP_VOID); 2667 SET_GPR32 (OP[1], tmp); 2668 trace_output_32 (tmp); 2669} 2670 2671/* movd. */ 2672void 2673OP_55_8 () 2674{ 2675 uint32 tmp = GPR32 (OP[0]); 2676 trace_input ("movd", OP_REGP, OP_REGP, OP_VOID); 2677 SET_GPR32 (OP[1], tmp); 2678 trace_output_32 (tmp); 2679} 2680 2681/* movd. */ 2682void 2683OP_5_8 () 2684{ 2685 uint32 tmp = OP[0]; 2686 trace_input ("movd", OP_CONSTANT20, OP_REGP, OP_VOID); 2687 SET_GPR32 (OP[1], tmp); 2688 trace_output_32 (tmp); 2689} 2690 2691/* movd. */ 2692void 2693OP_7_C () 2694{ 2695 int32 tmp = OP[0]; 2696 trace_input ("movd", OP_CONSTANT32, OP_REGP, OP_VOID); 2697 SET_GPR32 (OP[1], tmp); 2698 trace_output_32 (tmp); 2699} 2700 2701/* loadm. */ 2702void 2703OP_14_D () 2704{ 2705 uint32 addr = GPR (0); 2706 uint16 count = OP[0], reg = 2, tmp; 2707 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID); 2708 if ((addr & 1)) 2709 { 2710 State.exception = SIG_CR16_BUS; 2711 State.pc_changed = 1; /* Don't increment the PC. */ 2712 trace_output_void (); 2713 return; 2714 } 2715 2716 while (count) 2717 { 2718 tmp = RW (addr); 2719 SET_GPR (reg, tmp); 2720 addr +=2; 2721 --count; 2722 reg++; 2723 if (reg == 6) reg = 8; 2724 }; 2725 2726 SET_GPR (0, addr); 2727 trace_output_void (); 2728} 2729 2730 2731/* loadmp. */ 2732void 2733OP_15_D () 2734{ 2735 uint32 addr = GPR32 (0); 2736 uint16 count = OP[0], reg = 2, tmp; 2737 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID); 2738 if ((addr & 1)) 2739 { 2740 State.exception = SIG_CR16_BUS; 2741 State.pc_changed = 1; /* Don't increment the PC. */ 2742 trace_output_void (); 2743 return; 2744 } 2745 2746 while (count) 2747 { 2748 tmp = RW (addr); 2749 SET_GPR (reg, tmp); 2750 addr +=2; 2751 --count; 2752 reg++; 2753 if (reg == 6) reg = 8; 2754 }; 2755 2756 SET_GPR32 (0, addr); 2757 trace_output_void (); 2758} 2759 2760 2761/* loadb. */ 2762void 2763OP_88_8 () 2764{ 2765 /* loadb ABS20, REG 2766 * ADDR = zext24(abs20) | remap (ie 0xF00000) 2767 * REG = [ADDR] 2768 * NOTE: remap is 2769 * If (abs20 > 0xEFFFF) the resulting address is logically ORed 2770 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped 2771 * by the core to 16M-64k to 16M. */ 2772 2773 uint16 tmp, a = (GPR (OP[1])) & 0xFF00; 2774 uint32 addr = OP[0]; 2775 trace_input ("loadb", OP_ABS20, OP_REG, OP_VOID); 2776 if (addr > 0xEFFFF) addr |= 0xF00000; 2777 tmp = (RB (addr)); 2778 SET_GPR (OP[1], (a | tmp)); 2779 trace_output_16 (tmp); 2780} 2781 2782/* loadb. */ 2783void 2784OP_127_14 () 2785{ 2786 /* loadb ABS24, REG 2787 * ADDR = abs24 2788 * REGR = [ADDR]. */ 2789 2790 uint16 tmp, a = (GPR (OP[1])) & 0xFF00; 2791 uint32 addr = OP[0]; 2792 trace_input ("loadb", OP_ABS24, OP_REG, OP_VOID); 2793 tmp = (RB (addr)); 2794 SET_GPR (OP[1], (a | tmp)); 2795 trace_output_16 (tmp); 2796} 2797 2798/* loadb. */ 2799void 2800OP_45_7 () 2801{ 2802 /* loadb [Rindex]ABS20 REG 2803 * ADDR = Rindex + zext24(disp20) 2804 * REGR = [ADDR]. */ 2805 2806 uint32 addr; 2807 uint16 tmp, a = (GPR (OP[2])) & 0xFF00; 2808 trace_input ("loadb", OP_R_INDEX8_ABS20, OP_REG, OP_VOID); 2809 2810 if (OP[0] == 0) 2811 addr = (GPR32 (12)) + OP[1]; 2812 else 2813 addr = (GPR32 (13)) + OP[1]; 2814 2815 tmp = (RB (addr)); 2816 SET_GPR (OP[2], (a | tmp)); 2817 trace_output_16 (tmp); 2818} 2819 2820 2821/* loadb. */ 2822void 2823OP_B_4 () 2824{ 2825 /* loadb DIPS4(REGP) REG 2826 * ADDR = RPBASE + zext24(DISP4) 2827 * REG = [ADDR]. */ 2828 uint16 tmp, a = (GPR (OP[2])) & 0xFF00; 2829 uint32 addr = (GPR32 (OP[1])) + OP[0]; 2830 trace_input ("loadb", OP_RP_BASE_DISP4, OP_REG, OP_VOID); 2831 tmp = (RB (addr)); 2832 SET_GPR (OP[2], (a | tmp)); 2833 trace_output_16 (tmp); 2834} 2835 2836/* loadb. */ 2837void 2838OP_BE_8 () 2839{ 2840 /* loadb [Rindex]disp0(RPbasex) REG 2841 * ADDR = Rpbasex + Rindex 2842 * REGR = [ADDR] */ 2843 2844 uint32 addr; 2845 uint16 tmp, a = (GPR (OP[3])) & 0xFF00; 2846 trace_input ("loadb", OP_RP_INDEX_DISP0, OP_REG, OP_VOID); 2847 2848 addr = (GPR32 (OP[2])) + OP[1]; 2849 2850 if (OP[0] == 0) 2851 addr = (GPR32 (12)) + addr; 2852 else 2853 addr = (GPR32 (13)) + addr; 2854 2855 tmp = (RB (addr)); 2856 SET_GPR (OP[3], (a | tmp)); 2857 trace_output_16 (tmp); 2858} 2859 2860/* loadb. */ 2861void 2862OP_219_A () 2863{ 2864 /* loadb [Rindex]disp14(RPbasex) REG 2865 * ADDR = Rpbasex + Rindex + zext24(disp14) 2866 * REGR = [ADDR] */ 2867 2868 uint32 addr; 2869 uint16 tmp, a = (GPR (OP[3])) & 0xFF00; 2870 2871 addr = (GPR32 (OP[2])) + OP[1]; 2872 2873 if (OP[0] == 0) 2874 addr = (GPR32 (12)) + addr; 2875 else 2876 addr = (GPR32 (13)) + addr; 2877 2878 trace_input ("loadb", OP_RP_INDEX_DISP14, OP_REG, OP_VOID); 2879 tmp = (RB (addr)); 2880 SET_GPR (OP[3], (a | tmp)); 2881 trace_output_16 (tmp); 2882} 2883 2884 2885/* loadb. */ 2886void 2887OP_184_14 () 2888{ 2889 /* loadb DISPE20(REG) REG 2890 * zext24(Rbase) + zext24(dispe20) 2891 * REG = [ADDR] */ 2892 2893 uint16 tmp,a = (GPR (OP[2])) & 0xFF00; 2894 uint32 addr = OP[0] + (GPR (OP[1])); 2895 trace_input ("loadb", OP_R_BASE_DISPE20, OP_REG, OP_VOID); 2896 tmp = (RB (addr)); 2897 SET_GPR (OP[2], (a | tmp)); 2898 trace_output_16 (tmp); 2899} 2900 2901/* loadb. */ 2902void 2903OP_124_14 () 2904{ 2905 /* loadb DISP20(REG) REG 2906 * ADDR = zext24(Rbase) + zext24(disp20) 2907 * REG = [ADDR] */ 2908 2909 uint16 tmp,a = (GPR (OP[2])) & 0xFF00; 2910 uint32 addr = OP[0] + (GPR (OP[1])); 2911 trace_input ("loadb", OP_R_BASE_DISP20, OP_REG, OP_VOID); 2912 tmp = (RB (addr)); 2913 SET_GPR (OP[2], (a | tmp)); 2914 trace_output_16 (tmp); 2915} 2916 2917/* loadb. */ 2918void 2919OP_BF_8 () 2920{ 2921 /* loadb disp16(REGP) REG 2922 * ADDR = RPbase + zext24(disp16) 2923 * REGR = [ADDR] */ 2924 2925 uint16 tmp,a = (GPR (OP[2])) & 0xFF00; 2926 uint32 addr = (GPR32 (OP[1])) + OP[0]; 2927 trace_input ("loadb", OP_RP_BASE_DISP16, OP_REG, OP_VOID); 2928 tmp = (RB (addr)); 2929 SET_GPR (OP[2], (a | tmp)); 2930 trace_output_16 (tmp); 2931} 2932 2933/* loadb. */ 2934void 2935OP_125_14 () 2936{ 2937 /* loadb disp20(REGP) REG 2938 * ADDR = RPbase + zext24(disp20) 2939 * REGR = [ADDR] */ 2940 uint16 tmp,a = (GPR (OP[2])) & 0xFF00; 2941 uint32 addr = (GPR32 (OP[1])) + OP[0]; 2942 trace_input ("loadb", OP_RP_BASE_DISP20, OP_REG, OP_VOID); 2943 tmp = (RB (addr)); 2944 SET_GPR (OP[2], (a | tmp)); 2945 trace_output_16 (tmp); 2946} 2947 2948 2949/* loadb. */ 2950void 2951OP_185_14 () 2952{ 2953 /* loadb -disp20(REGP) REG 2954 * ADDR = RPbase + zext24(-disp20) 2955 * REGR = [ADDR] */ 2956 uint16 tmp,a = (GPR (OP[2])) & 0xFF00; 2957 uint32 addr = (GPR32 (OP[1])) + OP[1]; 2958 trace_input ("loadb", OP_RP_BASE_DISPE20, OP_REG, OP_VOID); 2959 tmp = (RB (addr)); 2960 SET_GPR (OP[2], (a | tmp)); 2961 trace_output_16 (tmp); 2962} 2963 2964/* loadb. */ 2965void 2966OP_126_14 () 2967{ 2968 /* loadb [Rindex]disp20(RPbasexb) REG 2969 * ADDR = RPbasex + Rindex + zext24(disp20) 2970 * REGR = [ADDR] */ 2971 2972 uint32 addr; 2973 uint16 tmp, a = (GPR (OP[3])) & 0xFF00; 2974 trace_input ("loadb", OP_RP_INDEX_DISP20, OP_REG, OP_VOID); 2975 2976 addr = (GPR32 (OP[2])) + OP[1]; 2977 2978 if (OP[0] == 0) 2979 addr = (GPR32 (12)) + addr; 2980 else 2981 addr = (GPR32 (13)) + addr; 2982 2983 tmp = (RB (addr)); 2984 SET_GPR (OP[3], (a | tmp)); 2985 trace_output_16 (tmp); 2986} 2987 2988 2989/* loadw. */ 2990void 2991OP_89_8 () 2992{ 2993 /* loadw ABS20, REG 2994 * ADDR = zext24(abs20) | remap 2995 * REGR = [ADDR] 2996 * NOTE: remap is 2997 * If (abs20 > 0xEFFFF) the resulting address is logically ORed 2998 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped 2999 * by the core to 16M-64k to 16M. */ 3000 3001 uint16 tmp; 3002 uint32 addr = OP[0]; 3003 trace_input ("loadw", OP_ABS20, OP_REG, OP_VOID); 3004 if (addr > 0xEFFFF) addr |= 0xF00000; 3005 tmp = (RW (addr)); 3006 SET_GPR (OP[1], tmp); 3007 trace_output_16 (tmp); 3008} 3009 3010 3011/* loadw. */ 3012void 3013OP_12F_14 () 3014{ 3015 /* loadw ABS24, REG 3016 * ADDR = abs24 3017 * REGR = [ADDR] */ 3018 uint16 tmp; 3019 uint32 addr = OP[0]; 3020 trace_input ("loadw", OP_ABS24, OP_REG, OP_VOID); 3021 tmp = (RW (addr)); 3022 SET_GPR (OP[1], tmp); 3023 trace_output_16 (tmp); 3024} 3025 3026/* loadw. */ 3027void 3028OP_47_7 () 3029{ 3030 /* loadw [Rindex]ABS20 REG 3031 * ADDR = Rindex + zext24(disp20) 3032 * REGR = [ADDR] */ 3033 3034 uint32 addr; 3035 uint16 tmp; 3036 trace_input ("loadw", OP_R_INDEX8_ABS20, OP_REG, OP_VOID); 3037 3038 if (OP[0] == 0) 3039 addr = (GPR32 (12)) + OP[1]; 3040 else 3041 addr = (GPR32 (13)) + OP[1]; 3042 3043 tmp = (RW (addr)); 3044 SET_GPR (OP[2], tmp); 3045 trace_output_16 (tmp); 3046} 3047 3048 3049/* loadw. */ 3050void 3051OP_9_4 () 3052{ 3053 /* loadw DIPS4(REGP) REGP 3054 * ADDR = RPBASE + zext24(DISP4) 3055 * REGP = [ADDR]. */ 3056 uint16 tmp; 3057 uint32 addr, a; 3058 trace_input ("loadw", OP_RP_BASE_DISP4, OP_REG, OP_VOID); 3059 addr = (GPR32 (OP[1])) + OP[0]; 3060 tmp = (RW (addr)); 3061 if (OP[2] > 11) 3062 { 3063 a = (GPR32 (OP[2])) & 0xffff0000; 3064 SET_GPR32 (OP[2], (a | tmp)); 3065 } 3066 else 3067 SET_GPR (OP[2], tmp); 3068 3069 trace_output_16 (tmp); 3070} 3071 3072 3073/* loadw. */ 3074void 3075OP_9E_8 () 3076{ 3077 /* loadw [Rindex]disp0(RPbasex) REG 3078 * ADDR = Rpbasex + Rindex 3079 * REGR = [ADDR] */ 3080 3081 uint32 addr; 3082 uint16 tmp; 3083 trace_input ("loadw", OP_RP_INDEX_DISP0, OP_REG, OP_VOID); 3084 3085 addr = (GPR32 (OP[2])) + OP[1]; 3086 3087 if (OP[0] == 0) 3088 addr = (GPR32 (12)) + addr; 3089 else 3090 addr = (GPR32 (13)) + addr; 3091 3092 tmp = RW (addr); 3093 SET_GPR (OP[3], tmp); 3094 trace_output_16 (tmp); 3095} 3096 3097 3098/* loadw. */ 3099void 3100OP_21B_A () 3101{ 3102 /* loadw [Rindex]disp14(RPbasex) REG 3103 * ADDR = Rpbasex + Rindex + zext24(disp14) 3104 * REGR = [ADDR] */ 3105 3106 uint32 addr; 3107 uint16 tmp; 3108 trace_input ("loadw", OP_RP_INDEX_DISP14, OP_REG, OP_VOID); 3109 addr = (GPR32 (OP[2])) + OP[1]; 3110 3111 if (OP[0] == 0) 3112 addr = (GPR32 (12)) + addr; 3113 else 3114 addr = (GPR32 (13)) + addr; 3115 3116 tmp = (RW (addr)); 3117 SET_GPR (OP[3], tmp); 3118 trace_output_16 (tmp); 3119} 3120 3121/* loadw. */ 3122void 3123OP_18C_14 () 3124{ 3125 /* loadw dispe20(REG) REGP 3126 * REGP = [DISPE20+[REG]] */ 3127 3128 uint16 tmp; 3129 uint32 addr, a; 3130 trace_input ("loadw", OP_R_BASE_DISPE20, OP_REGP, OP_VOID); 3131 addr = OP[0] + (GPR (OP[1])); 3132 tmp = (RW (addr)); 3133 if (OP[2] > 11) 3134 { 3135 a = (GPR32 (OP[2])) & 0xffff0000; 3136 SET_GPR32 (OP[2], (a | tmp)); 3137 } 3138 else 3139 SET_GPR (OP[2], tmp); 3140 3141 trace_output_16 (tmp); 3142} 3143 3144 3145/* loadw. */ 3146void 3147OP_12C_14 () 3148{ 3149 /* loadw DISP20(REG) REGP 3150 * ADDR = zext24(Rbase) + zext24(disp20) 3151 * REGP = [ADDR] */ 3152 3153 uint16 tmp; 3154 uint32 addr, a; 3155 trace_input ("loadw", OP_R_BASE_DISP20, OP_REGP, OP_VOID); 3156 addr = OP[0] + (GPR (OP[1])); 3157 tmp = (RW (addr)); 3158 if (OP[2] > 11) 3159 { 3160 a = (GPR32 (OP[2])) & 0xffff0000; 3161 SET_GPR32 (OP[2], (a | tmp)); 3162 } 3163 else 3164 SET_GPR (OP[2], tmp); 3165 3166 trace_output_16 (tmp); 3167} 3168 3169/* loadw. */ 3170void 3171OP_9F_8 () 3172{ 3173 /* loadw disp16(REGP) REGP 3174 * ADDR = RPbase + zext24(disp16) 3175 * REGP = [ADDR] */ 3176 uint16 tmp; 3177 uint32 addr, a; 3178 trace_input ("loadw", OP_RP_BASE_DISP16, OP_REGP, OP_VOID); 3179 addr = (GPR32 (OP[1])) + OP[0]; 3180 tmp = (RW (addr)); 3181 if (OP[2] > 11) 3182 { 3183 a = (GPR32 (OP[2])) & 0xffff0000; 3184 SET_GPR32 (OP[2], (a | tmp)); 3185 } 3186 else 3187 SET_GPR (OP[2], tmp); 3188 3189 trace_output_16 (tmp); 3190} 3191 3192/* loadw. */ 3193void 3194OP_12D_14 () 3195{ 3196 /* loadw disp20(REGP) REGP 3197 * ADDR = RPbase + zext24(disp20) 3198 * REGP = [ADDR] */ 3199 uint16 tmp; 3200 uint32 addr, a; 3201 trace_input ("loadw", OP_RP_BASE_DISP20, OP_REG, OP_VOID); 3202 addr = (GPR32 (OP[1])) + OP[0]; 3203 tmp = (RW (addr)); 3204 if (OP[2] > 11) 3205 { 3206 a = (GPR32 (OP[2])) & 0xffff0000; 3207 SET_GPR32 (OP[2], (a | tmp)); 3208 } 3209 else 3210 SET_GPR (OP[2], tmp); 3211 3212 trace_output_16 (tmp); 3213} 3214 3215/* loadw. */ 3216void 3217OP_18D_14 () 3218{ 3219 /* loadw -disp20(REGP) REG 3220 * ADDR = RPbase + zext24(-disp20) 3221 * REGR = [ADDR] */ 3222 3223 uint16 tmp; 3224 uint32 addr, a; 3225 trace_input ("loadw", OP_RP_BASE_DISPE20, OP_REG, OP_VOID); 3226 addr = (GPR32 (OP[1])) + OP[0]; 3227 tmp = (RB (addr)); 3228 if (OP[2] > 11) 3229 { 3230 a = (GPR32 (OP[2])) & 0xffff0000; 3231 SET_GPR32 (OP[2], (a | tmp)); 3232 } 3233 else 3234 SET_GPR (OP[2], tmp); 3235 3236 trace_output_16 (tmp); 3237} 3238 3239 3240/* loadw. */ 3241void 3242OP_12E_14 () 3243{ 3244 /* loadw [Rindex]disp20(RPbasexb) REG 3245 * ADDR = RPbasex + Rindex + zext24(disp20) 3246 * REGR = [ADDR] */ 3247 3248 uint32 addr; 3249 uint16 tmp; 3250 trace_input ("loadw", OP_RP_INDEX_DISP20, OP_REG, OP_VOID); 3251 3252 if (OP[0] == 0) 3253 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2])); 3254 else 3255 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2])); 3256 3257 tmp = (RW (addr)); 3258 SET_GPR (OP[3], tmp); 3259 trace_output_16 (tmp); 3260} 3261 3262 3263/* loadd. */ 3264void 3265OP_87_8 () 3266{ 3267 /* loadd ABS20, REGP 3268 * ADDR = zext24(abs20) | remap 3269 * REGP = [ADDR] 3270 * NOTE: remap is 3271 * If (abs20 > 0xEFFFF) the resulting address is logically ORed 3272 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped 3273 * by the core to 16M-64k to 16M. */ 3274 3275 uint32 addr, tmp; 3276 addr = OP[0]; 3277 trace_input ("loadd", OP_ABS20, OP_REGP, OP_VOID); 3278 if (addr > 0xEFFFF) addr |= 0xF00000; 3279 tmp = RLW (addr); 3280 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff); 3281 SET_GPR32 (OP[1], tmp); 3282 trace_output_32 (tmp); 3283} 3284 3285/* loadd. */ 3286void 3287OP_12B_14 () 3288{ 3289 /* loadd ABS24, REGP 3290 * ADDR = abs24 3291 * REGP = [ADDR] */ 3292 3293 uint32 addr = OP[0]; 3294 uint32 tmp; 3295 trace_input ("loadd", OP_ABS24, OP_REGP, OP_VOID); 3296 tmp = RLW (addr); 3297 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3298 SET_GPR32 (OP[1],tmp); 3299 trace_output_32 (tmp); 3300} 3301 3302 3303/* loadd. */ 3304void 3305OP_46_7 () 3306{ 3307 /* loadd [Rindex]ABS20 REGP 3308 * ADDR = Rindex + zext24(disp20) 3309 * REGP = [ADDR] */ 3310 3311 uint32 addr, tmp; 3312 trace_input ("loadd", OP_R_INDEX8_ABS20, OP_REGP, OP_VOID); 3313 3314 if (OP[0] == 0) 3315 addr = (GPR32 (12)) + OP[1]; 3316 else 3317 addr = (GPR32 (13)) + OP[1]; 3318 3319 tmp = RLW (addr); 3320 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3321 SET_GPR32 (OP[2], tmp); 3322 trace_output_32 (tmp); 3323} 3324 3325 3326/* loadd. */ 3327void 3328OP_A_4 () 3329{ 3330 /* loadd dips4(regp) REGP 3331 * ADDR = Rpbase + zext24(disp4) 3332 * REGP = [ADDR] */ 3333 3334 uint32 tmp, addr = (GPR32 (OP[1])) + OP[0]; 3335 trace_input ("loadd", OP_RP_BASE_DISP4, OP_REGP, OP_VOID); 3336 tmp = RLW (addr); 3337 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3338 SET_GPR32 (OP[2], tmp); 3339 trace_output_32 (tmp); 3340} 3341 3342 3343/* loadd. */ 3344void 3345OP_AE_8 () 3346{ 3347 /* loadd [Rindex]disp0(RPbasex) REGP 3348 * ADDR = Rpbasex + Rindex 3349 * REGP = [ADDR] */ 3350 3351 uint32 addr, tmp; 3352 trace_input ("loadd", OP_RP_INDEX_DISP0, OP_REGP, OP_VOID); 3353 3354 if (OP[0] == 0) 3355 addr = (GPR32 (12)) + (GPR32 (OP[2])) + OP[1]; 3356 else 3357 addr = (GPR32 (13)) + (GPR32 (OP[2])) + OP[1]; 3358 3359 tmp = RLW (addr); 3360 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3361 SET_GPR32 (OP[3], tmp); 3362 trace_output_32 (tmp); 3363} 3364 3365 3366/* loadd. */ 3367void 3368OP_21A_A () 3369{ 3370 /* loadd [Rindex]disp14(RPbasex) REGP 3371 * ADDR = Rpbasex + Rindex + zext24(disp14) 3372 * REGR = [ADDR] */ 3373 3374 uint32 addr, tmp; 3375 trace_input ("loadd", OP_RP_INDEX_DISP14, OP_REGP, OP_VOID); 3376 3377 if (OP[0] == 0) 3378 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2])); 3379 else 3380 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2])); 3381 3382 tmp = RLW (addr); 3383 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3384 SET_GPR (OP[3],tmp); 3385 trace_output_32 (tmp); 3386} 3387 3388 3389/* loadd. */ 3390void 3391OP_188_14 () 3392{ 3393 /* loadd dispe20(REG) REG 3394 * zext24(Rbase) + zext24(dispe20) 3395 * REG = [ADDR] */ 3396 3397 uint32 tmp, addr = OP[0] + (GPR (OP[1])); 3398 trace_input ("loadd", OP_R_BASE_DISPE20, OP_REGP, OP_VOID); 3399 tmp = RLW (addr); 3400 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3401 SET_GPR32 (OP[2], tmp); 3402 trace_output_32 (tmp); 3403} 3404 3405 3406/* loadd. */ 3407void 3408OP_128_14 () 3409{ 3410 /* loadd DISP20(REG) REG 3411 * ADDR = zext24(Rbase) + zext24(disp20) 3412 * REG = [ADDR] */ 3413 3414 uint32 tmp, addr = OP[0] + (GPR (OP[1])); 3415 trace_input ("loadd", OP_R_BASE_DISP20, OP_REGP, OP_VOID); 3416 tmp = RLW (addr); 3417 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3418 SET_GPR32 (OP[2], tmp); 3419 trace_output_32 (tmp); 3420} 3421 3422/* loadd. */ 3423void 3424OP_AF_8 () 3425{ 3426 /* loadd disp16(REGP) REGP 3427 * ADDR = RPbase + zext24(disp16) 3428 * REGR = [ADDR] */ 3429 uint32 tmp, addr = OP[0] + (GPR32 (OP[1])); 3430 trace_input ("loadd", OP_RP_BASE_DISP16, OP_REGP, OP_VOID); 3431 tmp = RLW (addr); 3432 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3433 SET_GPR32 (OP[2], tmp); 3434 trace_output_32 (tmp); 3435} 3436 3437 3438/* loadd. */ 3439void 3440OP_129_14 () 3441{ 3442 /* loadd disp20(REGP) REGP 3443 * ADDR = RPbase + zext24(disp20) 3444 * REGP = [ADDR] */ 3445 uint32 tmp, addr = OP[0] + (GPR32 (OP[1])); 3446 trace_input ("loadd", OP_RP_BASE_DISP20, OP_REGP, OP_VOID); 3447 tmp = RLW (addr); 3448 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3449 SET_GPR32 (OP[2], tmp); 3450 trace_output_32 (tmp); 3451} 3452 3453/* loadd. */ 3454void 3455OP_189_14 () 3456{ 3457 /* loadd -disp20(REGP) REGP 3458 * ADDR = RPbase + zext24(-disp20) 3459 * REGP = [ADDR] */ 3460 3461 uint32 tmp, addr = OP[0] + (GPR32 (OP[1])); 3462 trace_input ("loadd", OP_RP_BASE_DISPE20, OP_REGP, OP_VOID); 3463 tmp = RLW (addr); 3464 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3465 SET_GPR32 (OP[2], tmp); 3466 trace_output_32 (tmp); 3467} 3468 3469/* loadd. */ 3470void 3471OP_12A_14 () 3472{ 3473 /* loadd [Rindex]disp20(RPbasexb) REGP 3474 * ADDR = RPbasex + Rindex + zext24(disp20) 3475 * REGP = [ADDR] */ 3476 3477 uint32 addr, tmp; 3478 trace_input ("loadd", OP_RP_INDEX_DISP20, OP_REGP, OP_VOID); 3479 3480 if (OP[0] == 0) 3481 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2])); 3482 else 3483 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2])); 3484 3485 tmp = RLW (addr); 3486 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff); 3487 SET_GPR32 (OP[3], tmp); 3488 trace_output_32 (tmp); 3489} 3490 3491 3492/* storb. */ 3493void 3494OP_C8_8 () 3495{ 3496 /* storb REG, ABS20 3497 * ADDR = zext24(abs20) | remap 3498 * [ADDR] = REGR 3499 * NOTE: remap is 3500 * If (abs20 > 0xEFFFF) the resulting address is logically ORed 3501 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped 3502 * by the core to 16M-64k to 16M. */ 3503 3504 uint8 a = ((GPR (OP[0])) & 0xff); 3505 uint32 addr = OP[1]; 3506 trace_input ("storb", OP_REG, OP_ABS20_OUTPUT, OP_VOID); 3507 SB (addr, a); 3508 trace_output_32 (addr); 3509} 3510 3511/* storb. */ 3512void 3513OP_137_14 () 3514{ 3515 /* storb REG, ABS24 3516 * ADDR = abs24 3517 * [ADDR] = REGR. */ 3518 3519 uint8 a = ((GPR (OP[0])) & 0xff); 3520 uint32 addr = OP[1]; 3521 trace_input ("storb", OP_REG, OP_ABS24_OUTPUT, OP_VOID); 3522 SB (addr, a); 3523 trace_output_32 (addr); 3524} 3525 3526/* storb. */ 3527void 3528OP_65_7 () 3529{ 3530 /* storb REG, [Rindex]ABS20 3531 * ADDR = Rindex + zext24(disp20) 3532 * [ADDR] = REGR */ 3533 3534 uint32 addr; 3535 uint8 a = ((GPR (OP[0])) & 0xff); 3536 trace_input ("storb", OP_REG, OP_R_INDEX8_ABS20, OP_VOID); 3537 3538 if (OP[1] == 0) 3539 addr = (GPR32 (12)) + OP[2]; 3540 else 3541 addr = (GPR32 (13)) + OP[2]; 3542 3543 SB (addr, a); 3544 trace_output_32 (addr); 3545} 3546 3547/* storb. */ 3548void 3549OP_F_4 () 3550{ 3551 /* storb REG, DIPS4(REGP) 3552 * ADDR = RPBASE + zext24(DISP4) 3553 * [ADDR] = REG. */ 3554 3555 uint16 a = ((GPR (OP[0])) & 0xff); 3556 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE4, OP_VOID); 3557 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3558 SB (addr, a); 3559 trace_output_32 (addr); 3560} 3561 3562/* storb. */ 3563void 3564OP_FE_8 () 3565{ 3566 /* storb [Rindex]disp0(RPbasex) REG 3567 * ADDR = Rpbasex + Rindex 3568 * [ADDR] = REGR */ 3569 3570 uint32 addr; 3571 uint8 a = ((GPR (OP[0])) & 0xff); 3572 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP0, OP_VOID); 3573 3574 if (OP[1] == 0) 3575 addr = (GPR32 (12)) + (GPR32 (OP[3])) + OP[2]; 3576 else 3577 addr = (GPR32 (13)) + (GPR32 (OP[3])) + OP[2]; 3578 3579 SB (addr, a); 3580 trace_output_32 (addr); 3581} 3582 3583/* storb. */ 3584void 3585OP_319_A () 3586{ 3587 /* storb REG, [Rindex]disp14(RPbasex) 3588 * ADDR = Rpbasex + Rindex + zext24(disp14) 3589 * [ADDR] = REGR */ 3590 3591 uint8 a = ((GPR (OP[0])) & 0xff); 3592 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID); 3593 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3594 SB (addr, a); 3595 trace_output_32 (addr); 3596} 3597 3598/* storb. */ 3599void 3600OP_194_14 () 3601{ 3602 /* storb REG, DISPE20(REG) 3603 * zext24(Rbase) + zext24(dispe20) 3604 * [ADDR] = REG */ 3605 3606 uint8 a = ((GPR (OP[0])) & 0xff); 3607 trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID); 3608 uint32 addr = OP[1] + (GPR (OP[2])); 3609 SB (addr, a); 3610 trace_output_32 (addr); 3611} 3612 3613/* storb. */ 3614void 3615OP_134_14 () 3616{ 3617 /* storb REG, DISP20(REG) 3618 * ADDR = zext24(Rbase) + zext24(disp20) 3619 * [ADDR] = REG */ 3620 3621 uint8 a = (GPR (OP[0]) & 0xff); 3622 trace_input ("storb", OP_REG, OP_R_BASE_DISPS20, OP_VOID); 3623 uint32 addr = OP[1] + (GPR (OP[2])); 3624 SB (addr, a); 3625 trace_output_32 (addr); 3626} 3627 3628/* storb. */ 3629void 3630OP_FF_8 () 3631{ 3632 /* storb REG, disp16(REGP) 3633 * ADDR = RPbase + zext24(disp16) 3634 * [ADDR] = REGP */ 3635 3636 uint8 a = ((GPR (OP[0])) & 0xff); 3637 trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID); 3638 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3639 SB (addr, a); 3640 trace_output_32 (addr); 3641} 3642 3643/* storb. */ 3644void 3645OP_135_14 () 3646{ 3647 /* storb REG, disp20(REGP) 3648 * ADDR = RPbase + zext24(disp20) 3649 * [ADDR] = REGP */ 3650 3651 uint8 a = ((GPR (OP[0])) & 0xff); 3652 trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID); 3653 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3654 SB (addr, a); 3655 trace_output_32 (addr); 3656} 3657 3658/* storb. */ 3659void 3660OP_195_14 () 3661{ 3662 /* storb REG, -disp20(REGP) 3663 * ADDR = RPbase + zext24(-disp20) 3664 * [ADDR] = REGP */ 3665 3666 uint8 a = (GPR (OP[0]) & 0xff); 3667 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID); 3668 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3669 SB (addr, a); 3670 trace_output_32 (addr); 3671} 3672 3673/* storb. */ 3674void 3675OP_136_14 () 3676{ 3677 /* storb REG, [Rindex]disp20(RPbase) 3678 * ADDR = RPbasex + Rindex + zext24(disp20) 3679 * [ADDR] = REGP */ 3680 3681 uint8 a = (GPR (OP[0])) & 0xff; 3682 trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID); 3683 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3684 SB (addr, a); 3685 trace_output_32 (addr); 3686} 3687 3688/* STR_IMM instructions. */ 3689/* storb . */ 3690void 3691OP_81_8 () 3692{ 3693 uint8 a = (OP[0]) & 0xff; 3694 trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); 3695 uint32 addr = OP[1]; 3696 SB (addr, a); 3697 trace_output_32 (addr); 3698} 3699 3700/* storb. */ 3701void 3702OP_123_14 () 3703{ 3704 uint8 a = (OP[0]) & 0xff; 3705 trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); 3706 uint32 addr = OP[1]; 3707 SB (addr, a); 3708 trace_output_32 (addr); 3709} 3710 3711/* storb. */ 3712void 3713OP_42_7 () 3714{ 3715 uint32 addr; 3716 uint8 a = (OP[0]) & 0xff; 3717 trace_input ("storb", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID); 3718 3719 if (OP[1] == 0) 3720 addr = (GPR32 (12)) + OP[2]; 3721 else 3722 addr = (GPR32 (13)) + OP[2]; 3723 3724 SB (addr, a); 3725 trace_output_32 (addr); 3726} 3727 3728/* storb. */ 3729void 3730OP_218_A () 3731{ 3732 uint8 a = (OP[0]) & 0xff; 3733 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID); 3734 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3735 SB (addr, a); 3736 trace_output_32 (addr); 3737} 3738 3739/* storb. */ 3740void 3741OP_82_8 () 3742{ 3743 uint8 a = (OP[0]) & 0xff; 3744 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); 3745 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3746 SB (addr, a); 3747 trace_output_32 (addr); 3748} 3749 3750/* storb. */ 3751void 3752OP_120_14 () 3753{ 3754 uint8 a = (OP[0]) & 0xff; 3755 trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); 3756 uint32 addr = (GPR (OP[2])) + OP[1]; 3757 SB (addr, a); 3758 trace_output_32 (addr); 3759} 3760 3761/* storb. */ 3762void 3763OP_83_8 () 3764{ 3765 uint8 a = (OP[0]) & 0xff; 3766 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); 3767 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3768 SB (addr, a); 3769 trace_output_32 (addr); 3770} 3771 3772/* storb. */ 3773void 3774OP_121_14 () 3775{ 3776 uint8 a = (OP[0]) & 0xff; 3777 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); 3778 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3779 SB (addr, a); 3780 trace_output_32 (addr); 3781} 3782 3783/* storb. */ 3784void 3785OP_122_14 () 3786{ 3787 uint8 a = (OP[0]) & 0xff; 3788 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); 3789 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3790 SB (addr, a); 3791 trace_output_32 (addr); 3792} 3793/* endif for STR_IMM. */ 3794 3795/* storw . */ 3796void 3797OP_C9_8 () 3798{ 3799 uint16 a = GPR (OP[0]); 3800 trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID); 3801 uint32 addr = OP[1]; 3802 SW (addr, a); 3803 trace_output_32 (addr); 3804} 3805 3806/* storw. */ 3807void 3808OP_13F_14 () 3809{ 3810 uint16 a = GPR (OP[0]); 3811 trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID); 3812 uint32 addr = OP[1]; 3813 SW (addr, a); 3814 trace_output_32 (addr); 3815} 3816 3817/* storw. */ 3818void 3819OP_67_7 () 3820{ 3821 uint32 addr; 3822 uint16 a = GPR (OP[0]); 3823 trace_input ("storw", OP_REG, OP_R_INDEX8_ABS20, OP_VOID); 3824 3825 if (OP[1] == 0) 3826 addr = (GPR32 (12)) + OP[2]; 3827 else 3828 addr = (GPR32 (13)) + OP[2]; 3829 3830 SW (addr, a); 3831 trace_output_32 (addr); 3832} 3833 3834 3835/* storw. */ 3836void 3837OP_D_4 () 3838{ 3839 uint16 a = (GPR (OP[0])); 3840 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID); 3841 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3842 SW (addr, a); 3843 trace_output_32 (addr); 3844} 3845 3846/* storw. */ 3847void 3848OP_DE_8 () 3849{ 3850 uint16 a = GPR (OP[0]); 3851 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID); 3852 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3853 SW (addr, a); 3854 trace_output_32 (addr); 3855} 3856 3857/* storw. */ 3858void 3859OP_31B_A () 3860{ 3861 uint16 a = GPR (OP[0]); 3862 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID); 3863 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3864 SW (addr, a); 3865 trace_output_32 (addr); 3866} 3867 3868/* storw. */ 3869void 3870OP_19C_14 () 3871{ 3872 uint16 a = (GPR (OP[0])); 3873 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID); 3874 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3875 SW (addr, a); 3876 trace_output_32 (addr); 3877} 3878 3879/* storw. */ 3880void 3881OP_13C_14 () 3882{ 3883 uint16 a = (GPR (OP[0])); 3884 trace_input ("storw", OP_REG, OP_R_BASE_DISPS20, OP_VOID); 3885 uint32 addr = (GPR (OP[2])) + OP[1]; 3886 SW (addr, a); 3887 trace_output_32 (addr); 3888} 3889 3890/* storw. */ 3891void 3892OP_DF_8 () 3893{ 3894 uint16 a = (GPR (OP[0])); 3895 trace_input ("storw", OP_REG, OP_RP_BASE_DISP16, OP_VOID); 3896 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3897 SW (addr, a); 3898 trace_output_32 (addr); 3899} 3900 3901/* storw. */ 3902void 3903OP_13D_14 () 3904{ 3905 uint16 a = (GPR (OP[0])); 3906 trace_input ("storw", OP_REG, OP_RP_BASE_DISPS20, OP_VOID); 3907 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3908 SW (addr, a); 3909 trace_output_32 (addr); 3910} 3911 3912/* storw. */ 3913void 3914OP_19D_14 () 3915{ 3916 uint16 a = (GPR (OP[0])); 3917 trace_input ("storw", OP_REG, OP_RP_BASE_DISPE20, OP_VOID); 3918 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3919 SW (addr, a); 3920 trace_output_32 (addr); 3921} 3922 3923/* storw. */ 3924void 3925OP_13E_14 () 3926{ 3927 uint16 a = (GPR (OP[0])); 3928 trace_input ("storw", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID); 3929 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3930 SW (addr, a); 3931 trace_output_32 (addr); 3932} 3933 3934/* STORE-w IMM instruction *****/ 3935/* storw . */ 3936void 3937OP_C1_8 () 3938{ 3939 uint16 a = OP[0]; 3940 trace_input ("storw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); 3941 uint32 addr = OP[1]; 3942 SW (addr, a); 3943 trace_output_32 (addr); 3944} 3945 3946/* storw. */ 3947void 3948OP_133_14 () 3949{ 3950 uint16 a = OP[0]; 3951 trace_input ("storw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); 3952 uint32 addr = OP[1]; 3953 SW (addr, a); 3954 trace_output_32 (addr); 3955} 3956 3957/* storw. */ 3958void 3959OP_62_7 () 3960{ 3961 uint32 addr; 3962 uint16 a = OP[0]; 3963 trace_input ("storw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID); 3964 3965 if (OP[1] == 0) 3966 addr = (GPR32 (12)) + OP[2]; 3967 else 3968 addr = (GPR32 (13)) + OP[2]; 3969 3970 SW (addr, a); 3971 trace_output_32 (addr); 3972} 3973 3974/* storw. */ 3975void 3976OP_318_A () 3977{ 3978 uint16 a = OP[0]; 3979 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID); 3980 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3981 SW (addr, a); 3982 trace_output_32 (addr); 3983} 3984 3985/* storw. */ 3986void 3987OP_C2_8 () 3988{ 3989 uint16 a = OP[0]; 3990 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); 3991 uint32 addr = (GPR32 (OP[2])) + OP[1]; 3992 SW (addr, a); 3993 trace_output_32 (addr); 3994} 3995 3996/* storw. */ 3997void 3998OP_130_14 () 3999{ 4000 uint16 a = OP[0]; 4001 trace_input ("storw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); 4002 uint32 addr = (GPR32 (OP[2])) + OP[1]; 4003 SW (addr, a); 4004 trace_output_32 (addr); 4005} 4006 4007/* storw. */ 4008void 4009OP_C3_8 () 4010{ 4011 uint16 a = OP[0]; 4012 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); 4013 uint32 addr = (GPR32 (OP[2])) + OP[1]; 4014 SW (addr, a); 4015 trace_output_32 (addr); 4016} 4017 4018 4019/* storw. */ 4020void 4021OP_131_14 () 4022{ 4023 uint16 a = OP[0]; 4024 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); 4025 uint32 addr = (GPR32 (OP[2])) + OP[1]; 4026 SW (addr, a); 4027 trace_output_32 (addr); 4028} 4029 4030/* storw. */ 4031void 4032OP_132_14 () 4033{ 4034 uint16 a = OP[0]; 4035 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); 4036 uint32 addr = (GPR32 (OP[2])) + OP[1]; 4037 SW (addr, a); 4038 trace_output_32 (addr); 4039} 4040 4041 4042/* stord. */ 4043void 4044OP_C7_8 () 4045{ 4046 uint32 a = GPR32 (OP[0]); 4047 trace_input ("stord", OP_REGP, OP_ABS20_OUTPUT, OP_VOID); 4048 uint32 addr = OP[1]; 4049 SLW (addr, a); 4050 trace_output_32 (addr); 4051} 4052 4053/* stord. */ 4054void 4055OP_13B_14 () 4056{ 4057 uint32 a = GPR32 (OP[0]); 4058 trace_input ("stord", OP_REGP, OP_ABS24_OUTPUT, OP_VOID); 4059 uint32 addr = OP[1]; 4060 SLW (addr, a); 4061 trace_output_32 (addr); 4062} 4063 4064/* stord. */ 4065void 4066OP_66_7 () 4067{ 4068 uint32 addr, a = GPR32 (OP[0]); 4069 trace_input ("stord", OP_REGP, OP_R_INDEX8_ABS20, OP_VOID); 4070 4071 if (OP[1] == 0) 4072 addr = (GPR32 (12)) + OP[2]; 4073 else 4074 addr = (GPR32 (13)) + OP[2]; 4075 4076 SLW (addr, a); 4077 trace_output_32 (addr); 4078} 4079 4080/* stord. */ 4081void 4082OP_E_4 () 4083{ 4084 uint32 a = GPR32 (OP[0]); 4085 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID); 4086 uint32 addr = (GPR32 (OP[2])) + OP[1]; 4087 SLW (addr, a); 4088 trace_output_32 (addr); 4089} 4090 4091/* stord. */ 4092void 4093OP_EE_8 () 4094{ 4095 uint32 a = GPR32 (OP[0]); 4096 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP0, OP_VOID); 4097 uint32 addr = (GPR32 (OP[2])) + OP[1]; 4098 SLW (addr, a); 4099 trace_output_32 (addr); 4100} 4101 4102/* stord. */ 4103void 4104OP_31A_A () 4105{ 4106 uint32 a = GPR32 (OP[0]); 4107 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP14, OP_VOID); 4108 uint32 addr = (GPR32 (OP[2])) + OP[1]; 4109 SLW (addr, a); 4110 trace_output_32 (addr); 4111} 4112 4113/* stord. */ 4114void 4115OP_198_14 () 4116{ 4117 uint32 a = GPR32 (OP[0]); 4118 trace_input ("stord", OP_REGP, OP_R_BASE_DISPE20, OP_VOID); 4119 uint32 addr = (GPR32 (OP[2])) + OP[1]; 4120 SLW (addr, a); 4121 trace_output_32 (addr); 4122} 4123 4124/* stord. */ 4125void 4126OP_138_14 () 4127{ 4128 uint32 a = GPR32 (OP[0]); 4129 trace_input ("stord", OP_REGP, OP_R_BASE_DISPS20, OP_VOID); 4130 uint32 addr = (GPR32 (OP[2])) + OP[1]; 4131 SLW (addr, a); 4132 trace_output_32 (addr); 4133} 4134 4135/* stord. */ 4136void 4137OP_EF_8 () 4138{ 4139 uint32 a = GPR32 (OP[0]); 4140 trace_input ("stord", OP_REGP, OP_RP_BASE_DISP16, OP_VOID); 4141 uint32 addr = (GPR32 (OP[2])) + OP[1]; 4142 SLW (addr, a); 4143 trace_output_32 (addr); 4144} 4145 4146/* stord. */ 4147void 4148OP_139_14 () 4149{ 4150 uint32 a = GPR32 (OP[0]); 4151 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPS20, OP_VOID); 4152 uint32 addr = (GPR32 (OP[2])) + OP[1]; 4153 SLW (addr, a); 4154 trace_output_32 (addr); 4155} 4156 4157/* stord. */ 4158void 4159OP_199_14 () 4160{ 4161 uint32 a = GPR32 (OP[0]); 4162 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID); 4163 uint32 addr = (GPR32 (OP[2])) + OP[1]; 4164 SLW (addr, a); 4165 trace_output_32 (addr); 4166} 4167 4168/* stord. */ 4169void 4170OP_13A_14 () 4171{ 4172 uint32 a = GPR32 (OP[0]); 4173 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISPS20, OP_VOID); 4174 uint32 addr = (GPR32 (OP[2])) + OP[1]; 4175 SLW (addr, a); 4176 trace_output_32 (addr); 4177} 4178 4179/* macqu. */ 4180void 4181OP_14D_14 () 4182{ 4183 int32 tmp; 4184 int16 src1, src2; 4185 trace_input ("macuw", OP_REG, OP_REG, OP_REGP); 4186 src1 = GPR (OP[0]); 4187 src2 = GPR (OP[1]); 4188 tmp = src1 * src2; 4189 /*REVISIT FOR SATURATION and Q FORMAT. */ 4190 SET_GPR32 (OP[2], tmp); 4191 trace_output_32 (tmp); 4192} 4193 4194/* macuw. */ 4195void 4196OP_14E_14 () 4197{ 4198 uint32 tmp; 4199 uint16 src1, src2; 4200 trace_input ("macuw", OP_REG, OP_REG, OP_REGP); 4201 src1 = GPR (OP[0]); 4202 src2 = GPR (OP[1]); 4203 tmp = src1 * src2; 4204 /*REVISIT FOR SATURATION. */ 4205 SET_GPR32 (OP[2], tmp); 4206 trace_output_32 (tmp); 4207} 4208 4209/* macsw. */ 4210void 4211OP_14F_14 () 4212{ 4213 int32 tmp; 4214 int16 src1, src2; 4215 trace_input ("macsw", OP_REG, OP_REG, OP_REGP); 4216 src1 = GPR (OP[0]); 4217 src2 = GPR (OP[1]); 4218 tmp = src1 * src2; 4219 /*REVISIT FOR SATURATION. */ 4220 SET_GPR32 (OP[2], tmp); 4221 trace_output_32 (tmp); 4222} 4223 4224 4225/* mulb. */ 4226void 4227OP_64_8 () 4228{ 4229 int16 tmp; 4230 int8 a = (OP[0]) & 0xff; 4231 int8 b = (GPR (OP[1])) & 0xff; 4232 trace_input ("mulb", OP_CONSTANT4_1, OP_REG, OP_VOID); 4233 tmp = (a * b) & 0xff; 4234 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 4235 trace_output_16 (tmp); 4236} 4237 4238/* mulb. */ 4239void 4240OP_64B_C () 4241{ 4242 int16 tmp; 4243 int8 a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; 4244 trace_input ("mulb", OP_CONSTANT4, OP_REG, OP_VOID); 4245 tmp = (a * b) & 0xff; 4246 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 4247 trace_output_16 (tmp); 4248} 4249 4250 4251/* mulb. */ 4252void 4253OP_65_8 () 4254{ 4255 int16 tmp; 4256 int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; 4257 trace_input ("mulb", OP_REG, OP_REG, OP_VOID); 4258 tmp = (a * b) & 0xff; 4259 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 4260 trace_output_16 (tmp); 4261} 4262 4263 4264/* mulw. */ 4265void 4266OP_66_8 () 4267{ 4268 int32 tmp; 4269 uint16 a = OP[0]; 4270 int16 b = (GPR (OP[1])); 4271 trace_input ("mulw", OP_CONSTANT4_1, OP_REG, OP_VOID); 4272 tmp = (a * b) & 0xffff; 4273 SET_GPR (OP[1], tmp); 4274 trace_output_32 (tmp); 4275} 4276 4277/* mulw. */ 4278void 4279OP_66B_C () 4280{ 4281 int32 tmp; 4282 int16 a = OP[0], b = (GPR (OP[1])); 4283 trace_input ("mulw", OP_CONSTANT4, OP_REG, OP_VOID); 4284 tmp = (a * b) & 0xffff; 4285 SET_GPR (OP[1], tmp); 4286 trace_output_32 (tmp); 4287} 4288 4289 4290/* mulw. */ 4291void 4292OP_67_8 () 4293{ 4294 int32 tmp; 4295 int16 a = (GPR (OP[0])), b = (GPR (OP[1])); 4296 trace_input ("mulw", OP_REG, OP_REG, OP_VOID); 4297 tmp = (a * b) & 0xffff; 4298 SET_GPR (OP[1], tmp); 4299 trace_output_32 (tmp); 4300} 4301 4302 4303/* mulsb. */ 4304void 4305OP_B_8 () 4306{ 4307 int16 tmp; 4308 int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; 4309 trace_input ("mulsb", OP_REG, OP_REG, OP_VOID); 4310 tmp = a * b; 4311 SET_GPR (OP[1], tmp); 4312 trace_output_32 (tmp); 4313} 4314 4315/* mulsw. */ 4316void 4317OP_62_8 () 4318{ 4319 int32 tmp; 4320 int16 a = (GPR (OP[0])), b = (GPR (OP[1])); 4321 trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID); 4322 tmp = a * b; 4323 SET_GPR32 (OP[1], tmp); 4324 trace_output_32 (tmp); 4325} 4326 4327/* muluw. */ 4328void 4329OP_63_8 () 4330{ 4331 uint32 tmp; 4332 uint16 a = (GPR (OP[0])), b = (GPR (OP[1])); 4333 trace_input ("muluw", OP_REG, OP_REGP, OP_VOID); 4334 tmp = a * b; 4335 SET_GPR32 (OP[1], tmp); 4336 trace_output_32 (tmp); 4337} 4338 4339 4340/* nop. */ 4341void 4342OP_2C00_10 () 4343{ 4344 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID); 4345 4346#if 0 4347 State.exception = SIGTRAP; 4348 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */ 4349 switch (State.ins_type) 4350 { 4351 default: 4352 ins_type_counters[ (int)INS_UNKNOWN ]++; 4353 break; 4354 4355 } 4356 4357#endif 4358 trace_output_void (); 4359} 4360 4361 4362/* orb. */ 4363void 4364OP_24_8 () 4365{ 4366 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; 4367 trace_input ("orb", OP_CONSTANT4, OP_REG, OP_VOID); 4368 tmp = a | b; 4369 SET_GPR (OP[1], ((GPR (OP[1]) | tmp))); 4370 trace_output_16 (tmp); 4371} 4372 4373/* orb. */ 4374void 4375OP_24B_C () 4376{ 4377 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; 4378 trace_input ("orb", OP_CONSTANT16, OP_REG, OP_VOID); 4379 tmp = a | b; 4380 SET_GPR (OP[1], ((GPR (OP[1]) | tmp))); 4381 trace_output_16 (tmp); 4382} 4383 4384/* orb. */ 4385void 4386OP_25_8 () 4387{ 4388 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; 4389 trace_input ("orb", OP_REG, OP_REG, OP_VOID); 4390 tmp = a | b; 4391 SET_GPR (OP[1], ((GPR (OP[1]) | tmp))); 4392 trace_output_16 (tmp); 4393} 4394 4395/* orw. */ 4396void 4397OP_26_8 () 4398{ 4399 uint16 tmp, a = (OP[0]), b = (GPR (OP[1])); 4400 trace_input ("orw", OP_CONSTANT4, OP_REG, OP_VOID); 4401 tmp = a | b; 4402 SET_GPR (OP[1], tmp); 4403 trace_output_16 (tmp); 4404} 4405 4406 4407/* orw. */ 4408void 4409OP_26B_C () 4410{ 4411 uint16 tmp, a = (OP[0]), b = (GPR (OP[1])); 4412 trace_input ("orw", OP_CONSTANT16, OP_REG, OP_VOID); 4413 tmp = a | b; 4414 SET_GPR (OP[1], tmp); 4415 trace_output_16 (tmp); 4416} 4417 4418/* orw. */ 4419void 4420OP_27_8 () 4421{ 4422 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1])); 4423 trace_input ("orw", OP_REG, OP_REG, OP_VOID); 4424 tmp = a | b; 4425 SET_GPR (OP[1], tmp); 4426 trace_output_16 (tmp); 4427} 4428 4429 4430/* lshb. */ 4431void 4432OP_13_9 () 4433{ 4434 uint16 a = OP[0]; 4435 uint16 tmp, b = (GPR (OP[1])) & 0xFF; 4436 trace_input ("lshb", OP_CONSTANT4, OP_REG, OP_VOID); 4437 /* A positive count specifies a shift to the left; 4438 * A negative count specifies a shift to the right. */ 4439 if (sign_flag) 4440 tmp = b >> a; 4441 else 4442 tmp = b << a; 4443 4444 sign_flag = 0; /* Reset sign_flag. */ 4445 4446 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); 4447 trace_output_16 (tmp); 4448} 4449 4450/* lshb. */ 4451void 4452OP_44_8 () 4453{ 4454 uint16 a = (GPR (OP[0])) & 0xff; 4455 uint16 tmp, b = (GPR (OP[1])) & 0xFF; 4456 trace_input ("lshb", OP_REG, OP_REG, OP_VOID); 4457 if (a & ((long)1 << 3)) 4458 { 4459 sign_flag = 1; 4460 a = ~(a) + 1; 4461 } 4462 a = (unsigned int) (a & 0x7); 4463 4464 /* A positive count specifies a shift to the left; 4465 * A negative count specifies a shift to the right. */ 4466 if (sign_flag) 4467 tmp = b >> a; 4468 else 4469 tmp = b << a; 4470 4471 sign_flag = 0; /* Reset sign_flag. */ 4472 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); 4473 trace_output_16 (tmp); 4474} 4475 4476/* lshw. */ 4477void 4478OP_46_8 () 4479{ 4480 uint16 tmp, b = GPR (OP[1]); 4481 int16 a = GPR (OP[0]); 4482 trace_input ("lshw", OP_REG, OP_REG, OP_VOID); 4483 if (a & ((long)1 << 4)) 4484 { 4485 sign_flag = 1; 4486 a = ~(a) + 1; 4487 } 4488 a = (unsigned int) (a & 0xf); 4489 4490 /* A positive count specifies a shift to the left; 4491 * A negative count specifies a shift to the right. */ 4492 if (sign_flag) 4493 tmp = b >> a; 4494 else 4495 tmp = b << a; 4496 4497 sign_flag = 0; /* Reset sign_flag. */ 4498 SET_GPR (OP[1], (tmp & 0xffff)); 4499 trace_output_16 (tmp); 4500} 4501 4502/* lshw. */ 4503void 4504OP_49_8 () 4505{ 4506 uint16 tmp, b = GPR (OP[1]); 4507 uint16 a = OP[0]; 4508 trace_input ("lshw", OP_CONSTANT5, OP_REG, OP_VOID); 4509 /* A positive count specifies a shift to the left; 4510 * A negative count specifies a shift to the right. */ 4511 if (sign_flag) 4512 tmp = b >> a; 4513 else 4514 tmp = b << a; 4515 4516 sign_flag = 0; /* Reset sign_flag. */ 4517 SET_GPR (OP[1], (tmp & 0xffff)); 4518 trace_output_16 (tmp); 4519} 4520 4521/* lshd. */ 4522void 4523OP_25_7 () 4524{ 4525 uint32 tmp, b = GPR32 (OP[1]); 4526 uint16 a = OP[0]; 4527 trace_input ("lshd", OP_CONSTANT6, OP_REGP, OP_VOID); 4528 /* A positive count specifies a shift to the left; 4529 * A negative count specifies a shift to the right. */ 4530 if (sign_flag) 4531 tmp = b >> a; 4532 else 4533 tmp = b << a; 4534 4535 sign_flag = 0; /* Reset sign flag. */ 4536 4537 SET_GPR32 (OP[1], tmp); 4538 trace_output_32 (tmp); 4539} 4540 4541/* lshd. */ 4542void 4543OP_47_8 () 4544{ 4545 uint32 tmp, b = GPR32 (OP[1]); 4546 uint16 a = GPR (OP[0]); 4547 trace_input ("lshd", OP_REG, OP_REGP, OP_VOID); 4548 if (a & ((long)1 << 5)) 4549 { 4550 sign_flag = 1; 4551 a = ~(a) + 1; 4552 } 4553 a = (unsigned int) (a & 0x1f); 4554 /* A positive count specifies a shift to the left; 4555 * A negative count specifies a shift to the right. */ 4556 if (sign_flag) 4557 tmp = b >> a; 4558 else 4559 tmp = b << a; 4560 4561 sign_flag = 0; /* Reset sign flag. */ 4562 4563 SET_GPR32 (OP[1], tmp); 4564 trace_output_32 (tmp); 4565} 4566 4567/* ashub. */ 4568void 4569OP_80_9 () 4570{ 4571 uint16 a = OP[0]; 4572 int8 tmp, b = (GPR (OP[1])) & 0xFF; 4573 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID); 4574 /* A positive count specifies a shift to the left; 4575 * A negative count specifies a shift to the right. */ 4576 if (sign_flag) 4577 tmp = b >> a; 4578 else 4579 tmp = b << a; 4580 4581 sign_flag = 0; /* Reset sign flag. */ 4582 4583 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xff00))); 4584 trace_output_16 (tmp); 4585} 4586 4587/* ashub. */ 4588void 4589OP_81_9 () 4590{ 4591 uint16 a = OP[0]; 4592 int8 tmp, b = (GPR (OP[1])) & 0xFF; 4593 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID); 4594 /* A positive count specifies a shift to the left; 4595 * A negative count specifies a shift to the right. */ 4596 if (sign_flag) 4597 tmp = b >> a; 4598 else 4599 tmp = b << a; 4600 4601 sign_flag = 0; /* Reset sign flag. */ 4602 4603 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); 4604 trace_output_16 (tmp); 4605} 4606 4607 4608/* ashub. */ 4609void 4610OP_41_8 () 4611{ 4612 int16 a = (GPR (OP[0])); 4613 int8 tmp, b = (GPR (OP[1])) & 0xFF; 4614 trace_input ("ashub", OP_REG, OP_REG, OP_VOID); 4615 4616 if (a & ((long)1 << 3)) 4617 { 4618 sign_flag = 1; 4619 a = ~(a) + 1; 4620 } 4621 a = (unsigned int) (a & 0x7); 4622 4623 /* A positive count specifies a shift to the left; 4624 * A negative count specifies a shift to the right. */ 4625 if (sign_flag) 4626 tmp = b >> a; 4627 else 4628 tmp = b << a; 4629 4630 sign_flag = 0; /* Reset sign flag. */ 4631 4632 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); 4633 trace_output_16 (tmp); 4634} 4635 4636 4637/* ashuw. */ 4638void 4639OP_42_8 () 4640{ 4641 int16 tmp, b = GPR (OP[1]); 4642 uint16 a = OP[0]; 4643 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID); 4644 /* A positive count specifies a shift to the left; 4645 * A negative count specifies a shift to the right. */ 4646 if (sign_flag) 4647 tmp = b >> a; 4648 else 4649 tmp = b << a; 4650 4651 sign_flag = 0; /* Reset sign flag. */ 4652 4653 SET_GPR (OP[1], (tmp & 0xffff)); 4654 trace_output_16 (tmp); 4655} 4656 4657/* ashuw. */ 4658void 4659OP_43_8 () 4660{ 4661 int16 tmp, b = GPR (OP[1]); 4662 uint16 a = OP[0]; 4663 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID); 4664 /* A positive count specifies a shift to the left; 4665 * A negative count specifies a shift to the right. */ 4666 if (sign_flag) 4667 tmp = b >> a; 4668 else 4669 tmp = b << a; 4670 4671 sign_flag = 0; /* Reset sign flag. */ 4672 SET_GPR (OP[1], (tmp & 0xffff)); 4673 trace_output_16 (tmp); 4674} 4675 4676/* ashuw. */ 4677void 4678OP_45_8 () 4679{ 4680 int16 tmp; 4681 int16 a = GPR (OP[0]), b = GPR (OP[1]); 4682 trace_input ("ashuw", OP_REG, OP_REG, OP_VOID); 4683 4684 if (a & ((long)1 << 4)) 4685 { 4686 sign_flag = 1; 4687 a = ~(a) + 1; 4688 } 4689 a = (unsigned int) (a & 0xf); 4690 /* A positive count specifies a shift to the left; 4691 * A negative count specifies a shift to the right. */ 4692 4693 if (sign_flag) 4694 tmp = b >> a; 4695 else 4696 tmp = b << a; 4697 4698 sign_flag = 0; /* Reset sign flag. */ 4699 SET_GPR (OP[1], (tmp & 0xffff)); 4700 trace_output_16 (tmp); 4701} 4702 4703/* ashud. */ 4704void 4705OP_26_7 () 4706{ 4707 int32 tmp,b = GPR32 (OP[1]); 4708 uint32 a = OP[0]; 4709 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID); 4710 /* A positive count specifies a shift to the left; 4711 * A negative count specifies a shift to the right. */ 4712 if (sign_flag) 4713 tmp = b >> a; 4714 else 4715 tmp = b << a; 4716 4717 sign_flag = 0; /* Reset sign flag. */ 4718 SET_GPR32 (OP[1], tmp); 4719 trace_output_32 (tmp); 4720} 4721 4722/* ashud. */ 4723void 4724OP_27_7 () 4725{ 4726 int32 tmp; 4727 int32 a = OP[0], b = GPR32 (OP[1]); 4728 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID); 4729 /* A positive count specifies a shift to the left; 4730 * A negative count specifies a shift to the right. */ 4731 if (sign_flag) 4732 tmp = b >> a; 4733 else 4734 tmp = b << a; 4735 4736 sign_flag = 0; /* Reset sign flag. */ 4737 SET_GPR32 (OP[1], tmp); 4738 trace_output_32 (tmp); 4739} 4740 4741/* ashud. */ 4742void 4743OP_48_8 () 4744{ 4745 int32 tmp; 4746 int32 a = GPR32 (OP[0]), b = GPR32 (OP[1]); 4747 trace_input ("ashud", OP_REGP, OP_REGP, OP_VOID); 4748 4749 if (a & ((long)1 << 5)) 4750 { 4751 sign_flag = 1; 4752 a = ~(a) + 1; 4753 } 4754 a = (unsigned int) (a & 0x1f); 4755 /* A positive count specifies a shift to the left; 4756 * A negative count specifies a shift to the right. */ 4757 if (sign_flag) 4758 tmp = b >> a; 4759 else 4760 tmp = b << a; 4761 4762 sign_flag = 0; /* Reset sign flag. */ 4763 SET_GPR32 (OP[1], tmp); 4764 trace_output_32 (tmp); 4765} 4766 4767 4768/* storm. */ 4769void 4770OP_16_D () 4771{ 4772 uint32 addr = GPR (1); 4773 uint16 count = OP[0], reg = 2; 4774 trace_input ("storm", OP_CONSTANT4, OP_VOID, OP_VOID); 4775 if ((addr & 1)) 4776 { 4777 State.exception = SIG_CR16_BUS; 4778 State.pc_changed = 1; /* Don't increment the PC. */ 4779 trace_output_void (); 4780 return; 4781 } 4782 4783 while (count) 4784 { 4785 SW (addr, (GPR (reg))); 4786 addr +=2; 4787 --count; 4788 reg++; 4789 if (reg == 6) reg = 8; 4790 }; 4791 4792 SET_GPR (1, addr); 4793 4794 trace_output_void (); 4795} 4796 4797 4798/* stormp. */ 4799void 4800OP_17_D () 4801{ 4802 uint32 addr = GPR32 (6); 4803 uint16 count = OP[0], reg = 2; 4804 trace_input ("stormp", OP_CONSTANT4, OP_VOID, OP_VOID); 4805 if ((addr & 1)) 4806 { 4807 State.exception = SIG_CR16_BUS; 4808 State.pc_changed = 1; /* Don't increment the PC. */ 4809 trace_output_void (); 4810 return; 4811 } 4812 4813 while (count) 4814 { 4815 SW (addr, (GPR (reg))); 4816 addr +=2; 4817 --count; 4818 reg++; 4819 if (reg == 6) reg = 8; 4820 }; 4821 4822 SET_GPR32 (6, addr); 4823 trace_output_void (); 4824} 4825 4826/* subb. */ 4827void 4828OP_38_8 () 4829{ 4830 uint8 a = OP[0]; 4831 uint8 b = (GPR (OP[1])) & 0xff; 4832 uint16 tmp = (~a + 1 + b) & 0xff; 4833 trace_input ("subb", OP_CONSTANT4, OP_REG, OP_VOID); 4834 /* see ../common/sim-alu.h for a more extensive discussion on how to 4835 compute the carry/overflow bits. */ 4836 SET_PSR_C (tmp > 0xff); 4837 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 4838 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 4839 trace_output_16 (tmp); 4840} 4841 4842/* subb. */ 4843void 4844OP_38B_C () 4845{ 4846 uint8 a = OP[0] & 0xFF; 4847 uint8 b = (GPR (OP[1])) & 0xFF; 4848 uint16 tmp = (~a + 1 + b) & 0xFF; 4849 trace_input ("subb", OP_CONSTANT16, OP_REG, OP_VOID); 4850 /* see ../common/sim-alu.h for a more extensive discussion on how to 4851 compute the carry/overflow bits. */ 4852 SET_PSR_C (tmp > 0xff); 4853 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 4854 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 4855 trace_output_16 (tmp); 4856} 4857 4858/* subb. */ 4859void 4860OP_39_8 () 4861{ 4862 uint8 a = (GPR (OP[0])) & 0xFF; 4863 uint8 b = (GPR (OP[1])) & 0xFF; 4864 uint16 tmp = (~a + 1 + b) & 0xff; 4865 trace_input ("subb", OP_REG, OP_REG, OP_VOID); 4866 /* see ../common/sim-alu.h for a more extensive discussion on how to 4867 compute the carry/overflow bits. */ 4868 SET_PSR_C (tmp > 0xff); 4869 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 4870 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 4871 trace_output_16 (tmp); 4872} 4873 4874/* subw. */ 4875void 4876OP_3A_8 () 4877{ 4878 uint16 a = OP[0]; 4879 uint16 b = GPR (OP[1]); 4880 uint16 tmp = (~a + 1 + b); 4881 trace_input ("subw", OP_CONSTANT4, OP_REG, OP_VOID); 4882 /* see ../common/sim-alu.h for a more extensive discussion on how to 4883 compute the carry/overflow bits. */ 4884 SET_PSR_C (tmp > 0xffff); 4885 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 4886 SET_GPR (OP[1], tmp); 4887 trace_output_16 (tmp); 4888} 4889 4890/* subw. */ 4891void 4892OP_3AB_C () 4893{ 4894 uint16 a = OP[0]; 4895 uint16 b = GPR (OP[1]); 4896 uint32 tmp = (~a + 1 + b); 4897 trace_input ("subw", OP_CONSTANT16, OP_REG, OP_VOID); 4898 /* see ../common/sim-alu.h for a more extensive discussion on how to 4899 compute the carry/overflow bits. */ 4900 SET_PSR_C (tmp > 0xffff); 4901 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 4902 SET_GPR (OP[1], tmp & 0xffff); 4903 trace_output_16 (tmp); 4904} 4905 4906/* subw. */ 4907void 4908OP_3B_8 () 4909{ 4910 uint16 a = GPR (OP[0]); 4911 uint16 b = GPR (OP[1]); 4912 uint32 tmp = (~a + 1 + b); 4913 trace_input ("subw", OP_REG, OP_REG, OP_VOID); 4914 /* see ../common/sim-alu.h for a more extensive discussion on how to 4915 compute the carry/overflow bits. */ 4916 SET_PSR_C (tmp > 0xffff); 4917 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 4918 SET_GPR (OP[1], tmp & 0xffff); 4919 trace_output_16 (tmp); 4920} 4921 4922/* subcb. */ 4923void 4924OP_3C_8 () 4925{ 4926 uint8 a = OP[0]; 4927 uint8 b = (GPR (OP[1])) & 0xff; 4928 //uint16 tmp1 = a + 1; 4929 uint16 tmp1 = a + (PSR_C); 4930 uint16 tmp = (~tmp1 + 1 + b); 4931 trace_input ("subcb", OP_CONSTANT4, OP_REG, OP_VOID); 4932 /* see ../common/sim-alu.h for a more extensive discussion on how to 4933 compute the carry/overflow bits. */ 4934 SET_PSR_C (tmp > 0xff); 4935 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 4936 SET_GPR (OP[1], tmp); 4937 trace_output_16 (tmp); 4938} 4939 4940/* subcb. */ 4941void 4942OP_3CB_C () 4943{ 4944 uint16 a = OP[0]; 4945 uint16 b = (GPR (OP[1])) & 0xff; 4946 //uint16 tmp1 = a + 1; 4947 uint16 tmp1 = a + (PSR_C); 4948 uint16 tmp = (~tmp1 + 1 + b); 4949 trace_input ("subcb", OP_CONSTANT16, OP_REG, OP_VOID); 4950 /* see ../common/sim-alu.h for a more extensive discussion on how to 4951 compute the carry/overflow bits. */ 4952 SET_PSR_C (tmp > 0xff); 4953 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 4954 SET_GPR (OP[1], tmp); 4955 trace_output_16 (tmp); 4956} 4957 4958/* subcb. */ 4959void 4960OP_3D_8 () 4961{ 4962 uint16 a = (GPR (OP[0])) & 0xff; 4963 uint16 b = (GPR (OP[1])) & 0xff; 4964 uint16 tmp1 = a + (PSR_C); 4965 uint16 tmp = (~tmp1 + 1 + b); 4966 trace_input ("subcb", OP_REG, OP_REG, OP_VOID); 4967 /* see ../common/sim-alu.h for a more extensive discussion on how to 4968 compute the carry/overflow bits. */ 4969 SET_PSR_C (tmp > 0xff); 4970 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 4971 SET_GPR (OP[1], tmp); 4972 trace_output_16 (tmp); 4973} 4974 4975/* subcw. */ 4976void 4977OP_3E_8 () 4978{ 4979 uint16 a = OP[0], b = (GPR (OP[1])); 4980 uint16 tmp1 = a + (PSR_C); 4981 uint16 tmp = (~tmp1 + 1 + b); 4982 trace_input ("subcw", OP_CONSTANT4, OP_REG, OP_VOID); 4983 /* see ../common/sim-alu.h for a more extensive discussion on how to 4984 compute the carry/overflow bits. */ 4985 SET_PSR_C (tmp > 0xffff); 4986 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 4987 SET_GPR (OP[1], tmp); 4988 trace_output_16 (tmp); 4989} 4990 4991/* subcw. */ 4992void 4993OP_3EB_C () 4994{ 4995 int16 a = OP[0]; 4996 uint16 b = GPR (OP[1]); 4997 uint16 tmp1 = a + (PSR_C); 4998 uint16 tmp = (~tmp1 + 1 + b); 4999 trace_input ("subcw", OP_CONSTANT16, OP_REG, OP_VOID); 5000 /* see ../common/sim-alu.h for a more extensive discussion on how to 5001 compute the carry/overflow bits. */ 5002 SET_PSR_C (tmp > 0xffff); 5003 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 5004 SET_GPR (OP[1], tmp); 5005 trace_output_16 (tmp); 5006} 5007 5008/* subcw. */ 5009void 5010OP_3F_8 () 5011{ 5012 uint16 a = (GPR (OP[0])), b = (GPR (OP[1])); 5013 uint16 tmp1 = a + (PSR_C); 5014 uint16 tmp = (~tmp1 + 1 + b); 5015 trace_input ("subcw", OP_REG, OP_REG, OP_VOID); 5016 /* see ../common/sim-alu.h for a more extensive discussion on how to 5017 compute the carry/overflow bits. */ 5018 SET_PSR_C (tmp > 0xffff); 5019 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 5020 SET_GPR (OP[1], tmp); 5021 trace_output_16 (tmp); 5022} 5023 5024/* subd. */ 5025void 5026OP_3_C () 5027{ 5028 int32 a = OP[0]; 5029 uint32 b = GPR32 (OP[1]); 5030 uint32 tmp = (~a + 1 + b); 5031 trace_input ("subd", OP_CONSTANT32, OP_REGP, OP_VOID); 5032 /* see ../common/sim-alu.h for a more extensive discussion on how to 5033 compute the carry/overflow bits. */ 5034 SET_PSR_C (tmp > 0xffffffff); 5035 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) && 5036 ((b & 0x80000000) != (tmp & 0x80000000))); 5037 SET_GPR32 (OP[1], tmp); 5038 trace_output_32 (tmp); 5039} 5040 5041/* subd. */ 5042void 5043OP_14C_14 () 5044{ 5045 uint32 a = GPR32 (OP[0]); 5046 uint32 b = GPR32 (OP[1]); 5047 uint32 tmp = (~a + 1 + b); 5048 trace_input ("subd", OP_REGP, OP_REGP, OP_VOID); 5049 /* see ../common/sim-alu.h for a more extensive discussion on how to 5050 compute the carry/overflow bits. */ 5051 SET_PSR_C (tmp > 0xffffffff); 5052 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) && 5053 ((b & 0x80000000) != (tmp & 0x80000000))); 5054 SET_GPR32 (OP[1], tmp); 5055 trace_output_32 (tmp); 5056} 5057 5058/* excp. */ 5059void 5060OP_C_C () 5061{ 5062 trace_input ("excp", OP_CONSTANT4, OP_VOID, OP_VOID); 5063 switch (OP[0]) 5064 { 5065 default: 5066#if (DEBUG & DEBUG_TRAP) == 0 5067 { 5068#if 0 5069 uint16 vec = OP[0] + TRAP_VECTOR_START; 5070 SET_BPC (PC + 1); 5071 SET_BPSR (PSR); 5072 SET_PSR (PSR & PSR_SM_BIT); 5073 JMP (vec); 5074 break; 5075#endif 5076 } 5077#else /* if debugging use trap to print registers */ 5078 { 5079 int i; 5080 static int first_time = 1; 5081 5082 if (first_time) 5083 { 5084 first_time = 0; 5085 (*cr16_callback->printf_filtered) (cr16_callback, "Trap # PC "); 5086 for (i = 0; i < 16; i++) 5087 (*cr16_callback->printf_filtered) (cr16_callback, " %sr%d", (i > 9) ? "" : " ", i); 5088 (*cr16_callback->printf_filtered) (cr16_callback, " a0 a1 f0 f1 c\n"); 5089 } 5090 5091 (*cr16_callback->printf_filtered) (cr16_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC); 5092 5093 for (i = 0; i < 16; i++) 5094 (*cr16_callback->printf_filtered) (cr16_callback, " %.4x", (int) GPR (i)); 5095 5096 for (i = 0; i < 2; i++) 5097 (*cr16_callback->printf_filtered) (cr16_callback, " %.2x%.8lx", 5098 ((int)(ACC (i) >> 32) & 0xff), 5099 ((unsigned long) ACC (i)) & 0xffffffff); 5100 5101 (*cr16_callback->printf_filtered) (cr16_callback, " %d %d %d\n", 5102 PSR_F != 0, PSR_F != 0, PSR_C != 0); 5103 (*cr16_callback->flush_stdout) (cr16_callback); 5104 break; 5105 } 5106#endif 5107 case 8: /* new system call trap */ 5108 /* Trap 8 is used for simulating low-level I/O */ 5109 { 5110 unsigned32 result = 0; 5111 errno = 0; 5112 5113/* Registers passed to trap 0. */ 5114 5115#define FUNC GPR (0) /* function number. */ 5116#define PARM1 GPR (2) /* optional parm 1. */ 5117#define PARM2 GPR (3) /* optional parm 2. */ 5118#define PARM3 GPR (4) /* optional parm 3. */ 5119#define PARM4 GPR (5) /* optional parm 4. */ 5120 5121/* Registers set by trap 0 */ 5122 5123#define RETVAL(X) do { result = (0xffff & (X));SET_GPR (0, result);} while (0) 5124#define RETVAL32(X) do { result = (X); SET_GPR32 (0, result);} while (0) 5125#define RETERR(X) SET_GPR (4, (X)) /* return error code. */ 5126 5127/* Turn a pointer in a register into a pointer into real memory. */ 5128 5129#define MEMPTR(x) ((char *)(dmem_addr(x))) 5130 5131 switch (FUNC) 5132 { 5133#if !defined(__GO32__) && !defined(_WIN32) 5134 case TARGET_SYS_fork: 5135 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID); 5136 RETVAL (fork ()); 5137 trace_output_16 (result); 5138 break; 5139 5140#define getpid() 47 5141 case TARGET_SYS_getpid: 5142 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); 5143 RETVAL (getpid ()); 5144 trace_output_16 (result); 5145 break; 5146 5147 case TARGET_SYS_kill: 5148 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID); 5149 if (PARM1 == getpid ()) 5150 { 5151 trace_output_void (); 5152 State.exception = PARM2; 5153 } 5154 else 5155 { 5156 int os_sig = -1; 5157 switch (PARM2) 5158 { 5159#ifdef SIGHUP 5160 case 1: os_sig = SIGHUP; break; 5161#endif 5162#ifdef SIGINT 5163 case 2: os_sig = SIGINT; break; 5164#endif 5165#ifdef SIGQUIT 5166 case 3: os_sig = SIGQUIT; break; 5167#endif 5168#ifdef SIGILL 5169 case 4: os_sig = SIGILL; break; 5170#endif 5171#ifdef SIGTRAP 5172 case 5: os_sig = SIGTRAP; break; 5173#endif 5174#ifdef SIGABRT 5175 case 6: os_sig = SIGABRT; break; 5176#elif defined(SIGIOT) 5177 case 6: os_sig = SIGIOT; break; 5178#endif 5179#ifdef SIGEMT 5180 case 7: os_sig = SIGEMT; break; 5181#endif 5182#ifdef SIGFPE 5183 case 8: os_sig = SIGFPE; break; 5184#endif 5185#ifdef SIGKILL 5186 case 9: os_sig = SIGKILL; break; 5187#endif 5188#ifdef SIGBUS 5189 case 10: os_sig = SIGBUS; break; 5190#endif 5191#ifdef SIGSEGV 5192 case 11: os_sig = SIGSEGV; break; 5193#endif 5194#ifdef SIGSYS 5195 case 12: os_sig = SIGSYS; break; 5196#endif 5197#ifdef SIGPIPE 5198 case 13: os_sig = SIGPIPE; break; 5199#endif 5200#ifdef SIGALRM 5201 case 14: os_sig = SIGALRM; break; 5202#endif 5203#ifdef SIGTERM 5204 case 15: os_sig = SIGTERM; break; 5205#endif 5206#ifdef SIGURG 5207 case 16: os_sig = SIGURG; break; 5208#endif 5209#ifdef SIGSTOP 5210 case 17: os_sig = SIGSTOP; break; 5211#endif 5212#ifdef SIGTSTP 5213 case 18: os_sig = SIGTSTP; break; 5214#endif 5215#ifdef SIGCONT 5216 case 19: os_sig = SIGCONT; break; 5217#endif 5218#ifdef SIGCHLD 5219 case 20: os_sig = SIGCHLD; break; 5220#elif defined(SIGCLD) 5221 case 20: os_sig = SIGCLD; break; 5222#endif 5223#ifdef SIGTTIN 5224 case 21: os_sig = SIGTTIN; break; 5225#endif 5226#ifdef SIGTTOU 5227 case 22: os_sig = SIGTTOU; break; 5228#endif 5229#ifdef SIGIO 5230 case 23: os_sig = SIGIO; break; 5231#elif defined (SIGPOLL) 5232 case 23: os_sig = SIGPOLL; break; 5233#endif 5234#ifdef SIGXCPU 5235 case 24: os_sig = SIGXCPU; break; 5236#endif 5237#ifdef SIGXFSZ 5238 case 25: os_sig = SIGXFSZ; break; 5239#endif 5240#ifdef SIGVTALRM 5241 case 26: os_sig = SIGVTALRM; break; 5242#endif 5243#ifdef SIGPROF 5244 case 27: os_sig = SIGPROF; break; 5245#endif 5246#ifdef SIGWINCH 5247 case 28: os_sig = SIGWINCH; break; 5248#endif 5249#ifdef SIGLOST 5250 case 29: os_sig = SIGLOST; break; 5251#endif 5252#ifdef SIGUSR1 5253 case 30: os_sig = SIGUSR1; break; 5254#endif 5255#ifdef SIGUSR2 5256 case 31: os_sig = SIGUSR2; break; 5257#endif 5258 } 5259 5260 if (os_sig == -1) 5261 { 5262 trace_output_void (); 5263 (*cr16_callback->printf_filtered) (cr16_callback, "Unknown signal %d\n", PARM2); 5264 (*cr16_callback->flush_stdout) (cr16_callback); 5265 State.exception = SIGILL; 5266 } 5267 else 5268 { 5269 RETVAL (kill (PARM1, PARM2)); 5270 trace_output_16 (result); 5271 } 5272 } 5273 break; 5274 5275 case TARGET_SYS_execve: 5276 trace_input ("<execve>", OP_VOID, OP_VOID, OP_VOID); 5277 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2<<16|PARM3), 5278 (char **)MEMPTR (PARM4))); 5279 trace_output_16 (result); 5280 break; 5281 5282#ifdef TARGET_SYS_execv 5283 case TARGET_SYS_execv: 5284 trace_input ("<execv>", OP_VOID, OP_VOID, OP_VOID); 5285 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL)); 5286 trace_output_16 (result); 5287 break; 5288#endif 5289 5290 case TARGET_SYS_pipe: 5291 { 5292 reg_t buf; 5293 int host_fd[2]; 5294 5295 trace_input ("<pipe>", OP_VOID, OP_VOID, OP_VOID); 5296 buf = PARM1; 5297 RETVAL (pipe (host_fd)); 5298 SW (buf, host_fd[0]); 5299 buf += sizeof(uint16); 5300 SW (buf, host_fd[1]); 5301 trace_output_16 (result); 5302 } 5303 break; 5304 5305#ifdef TARGET_SYS_wait 5306 case TARGET_SYS_wait: 5307 { 5308 int status; 5309 trace_input ("<wait>", OP_REG, OP_VOID, OP_VOID); 5310 RETVAL (wait (&status)); 5311 if (PARM1) 5312 SW (PARM1, status); 5313 trace_output_16 (result); 5314 } 5315 break; 5316#endif 5317#else 5318 case TARGET_SYS_getpid: 5319 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); 5320 RETVAL (1); 5321 trace_output_16 (result); 5322 break; 5323 5324 case TARGET_SYS_kill: 5325 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID); 5326 trace_output_void (); 5327 State.exception = PARM2; 5328 break; 5329#endif 5330 5331 case TARGET_SYS_read: 5332 trace_input ("<read>", OP_REG, OP_MEMREF, OP_REG); 5333 RETVAL (cr16_callback->read (cr16_callback, PARM1, 5334 MEMPTR (((unsigned long)PARM3 << 16) 5335 |((unsigned long)PARM2)), PARM4)); 5336 trace_output_16 (result); 5337 break; 5338 5339 case TARGET_SYS_write: 5340 trace_input ("<write>", OP_REG, OP_MEMREF, OP_REG); 5341 RETVAL ((int)cr16_callback->write (cr16_callback, PARM1, 5342 MEMPTR (((unsigned long)PARM3 << 16) | PARM2), PARM4)); 5343 trace_output_16 (result); 5344 break; 5345 5346 case TARGET_SYS_lseek: 5347 trace_input ("<lseek>", OP_REG, OP_REGP, OP_REG); 5348 RETVAL32 (cr16_callback->lseek (cr16_callback, PARM1, 5349 ((((long) PARM3) << 16) | PARM2), 5350 PARM4)); 5351 trace_output_32 (result); 5352 break; 5353 5354 case TARGET_SYS_close: 5355 trace_input ("<close>", OP_REG, OP_VOID, OP_VOID); 5356 RETVAL (cr16_callback->close (cr16_callback, PARM1)); 5357 trace_output_16 (result); 5358 break; 5359 5360 case TARGET_SYS_open: 5361 trace_input ("<open>", OP_MEMREF, OP_REG, OP_VOID); 5362 RETVAL32 (cr16_callback->open (cr16_callback, 5363 MEMPTR ((((unsigned long)PARM2)<<16)|PARM1), 5364 PARM3)); 5365 trace_output_32 (result); 5366 break; 5367 5368 case TARGET_SYS_rename: 5369 trace_input ("<rename>", OP_MEMREF, OP_MEMREF, OP_VOID); 5370 RETVAL (cr16_callback->rename (cr16_callback, 5371 MEMPTR ((((unsigned long)PARM2)<<16) |PARM1), 5372 MEMPTR ((((unsigned long)PARM4)<<16) |PARM3))); 5373 trace_output_16 (result); 5374 break; 5375 5376 case 0x408: /* REVISIT: Added a dummy getenv call. */ 5377 trace_input ("<getenv>", OP_MEMREF, OP_MEMREF, OP_VOID); 5378 RETVAL32(NULL); 5379 trace_output_32 (result); 5380 break; 5381 5382 case TARGET_SYS_exit: 5383 trace_input ("<exit>", OP_VOID, OP_VOID, OP_VOID); 5384 State.exception = SIG_CR16_EXIT; 5385 trace_output_void (); 5386 break; 5387 5388 case TARGET_SYS_unlink: 5389 trace_input ("<unlink>", OP_MEMREF, OP_VOID, OP_VOID); 5390 RETVAL (cr16_callback->unlink (cr16_callback, 5391 MEMPTR (((unsigned long)PARM2<<16)|PARM1))); 5392 trace_output_16 (result); 5393 break; 5394 5395 5396#ifdef TARGET_SYS_stat 5397 case TARGET_SYS_stat: 5398 trace_input ("<stat>", OP_VOID, OP_VOID, OP_VOID); 5399 /* stat system call. */ 5400 { 5401 struct stat host_stat; 5402 reg_t buf; 5403 5404 RETVAL (stat (MEMPTR ((((unsigned long)PARM2) << 16)|PARM1), &host_stat)); 5405 5406 buf = PARM2; 5407 5408 /* The hard-coded offsets and sizes were determined by using 5409 * the CR16 compiler on a test program that used struct stat. 5410 */ 5411 SW (buf, host_stat.st_dev); 5412 SW (buf+2, host_stat.st_ino); 5413 SW (buf+4, host_stat.st_mode); 5414 SW (buf+6, host_stat.st_nlink); 5415 SW (buf+8, host_stat.st_uid); 5416 SW (buf+10, host_stat.st_gid); 5417 SW (buf+12, host_stat.st_rdev); 5418 SLW (buf+16, host_stat.st_size); 5419 SLW (buf+20, host_stat.st_atime); 5420 SLW (buf+28, host_stat.st_mtime); 5421 SLW (buf+36, host_stat.st_ctime); 5422 } 5423 trace_output_16 (result); 5424 break; 5425#endif 5426 5427 case TARGET_SYS_chown: 5428 trace_input ("<chown>", OP_VOID, OP_VOID, OP_VOID); 5429 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3)); 5430 trace_output_16 (result); 5431 break; 5432 5433 case TARGET_SYS_chmod: 5434 trace_input ("<chmod>", OP_VOID, OP_VOID, OP_VOID); 5435 RETVAL (chmod (MEMPTR (PARM1), PARM2)); 5436 trace_output_16 (result); 5437 break; 5438 5439#ifdef TARGET_SYS_utime 5440 case TARGET_SYS_utime: 5441 trace_input ("<utime>", OP_REG, OP_REG, OP_REG); 5442 /* Cast the second argument to void *, to avoid type mismatch 5443 if a prototype is present. */ 5444 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2))); 5445 trace_output_16 (result); 5446 break; 5447#endif 5448 5449#ifdef TARGET_SYS_time 5450 case TARGET_SYS_time: 5451 trace_input ("<time>", OP_VOID, OP_VOID, OP_REG); 5452 RETVAL32 (time (NULL)); 5453 trace_output_32 (result); 5454 break; 5455#endif 5456 5457 default: 5458 cr16_callback->error (cr16_callback, "Unknown syscall %d", FUNC); 5459 } 5460 5461 if ((uint16) result == (uint16) -1) 5462 RETERR (cr16_callback->get_errno(cr16_callback)); 5463 else 5464 RETERR (0); 5465 break; 5466 } 5467 } 5468} 5469 5470 5471/* push. */ 5472void 5473OP_3_9 () 5474{ 5475 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0; 5476 uint32 tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0; 5477 trace_input ("push", OP_CONSTANT3, OP_REG, OP_REG); 5478 5479 for (; i < a; ++i) 5480 { 5481 if ((b+i) <= 11) 5482 { 5483 SW (sp_addr, (GPR (b+i))); 5484 sp_addr +=2; 5485 } 5486 else 5487 { 5488 if (is_regp == 0) 5489 tmp = (GPR32 (b+i)); 5490 else 5491 tmp = (GPR32 (b+i-1)); 5492 5493 if ((a-i) > 1) 5494 { 5495 SLW (sp_addr, tmp); 5496 sp_addr +=4; 5497 } 5498 else 5499 { 5500 SW (sp_addr, tmp); 5501 sp_addr +=2; 5502 } 5503 ++i; 5504 is_regp = 1; 5505 } 5506 } 5507 5508 sp_addr +=4; 5509 5510 /* Store RA address. */ 5511 tmp = (GPR32 (14)); 5512 SLW(sp_addr,tmp); 5513 5514 sp_addr = (GPR32 (15)) - (a * 2) - 4; 5515 SET_GPR32 (15, sp_addr); /* Update SP address. */ 5516 5517 trace_output_void (); 5518} 5519 5520/* push. */ 5521void 5522OP_1_8 () 5523{ 5524 uint32 sp_addr, tmp, is_regp = 0; 5525 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0; 5526 trace_input ("push", OP_CONSTANT3, OP_REG, OP_VOID); 5527 5528 if (c == 1) 5529 sp_addr = (GPR32 (15)) - (a * 2) - 4; 5530 else 5531 sp_addr = (GPR32 (15)) - (a * 2); 5532 5533 for (; i < a; ++i) 5534 { 5535 if ((b+i) <= 11) 5536 { 5537 SW (sp_addr, (GPR (b+i))); 5538 sp_addr +=2; 5539 } 5540 else 5541 { 5542 if (is_regp == 0) 5543 tmp = (GPR32 (b+i)); 5544 else 5545 tmp = (GPR32 (b+i-1)); 5546 5547 if ((a-i) > 1) 5548 { 5549 SLW (sp_addr, tmp); 5550 sp_addr +=4; 5551 } 5552 else 5553 { 5554 SW (sp_addr, tmp); 5555 sp_addr +=2; 5556 } 5557 ++i; 5558 is_regp = 1; 5559 } 5560 } 5561 5562 if (c == 1) 5563 { 5564 /* Store RA address. */ 5565 tmp = (GPR32 (14)); 5566 SLW(sp_addr,tmp); 5567 sp_addr = (GPR32 (15)) - (a * 2) - 4; 5568 } 5569 else 5570 sp_addr = (GPR32 (15)) - (a * 2); 5571 5572 SET_GPR32 (15, sp_addr); /* Update SP address. */ 5573 5574 trace_output_void (); 5575} 5576 5577 5578/* push. */ 5579void 5580OP_11E_10 () 5581{ 5582 uint32 sp_addr = (GPR32 (15)), tmp; 5583 trace_input ("push", OP_VOID, OP_VOID, OP_VOID); 5584 tmp = (GPR32 (14)); 5585 SLW(sp_addr-4,tmp); /* Store RA address. */ 5586 SET_GPR32 (15, (sp_addr - 4)); /* Update SP address. */ 5587 trace_output_void (); 5588} 5589 5590 5591/* pop. */ 5592void 5593OP_5_9 () 5594{ 5595 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0; 5596 uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;; 5597 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_REG); 5598 5599 for (; i < a; ++i) 5600 { 5601 if ((b+i) <= 11) 5602 { 5603 SET_GPR ((b+i), RW(sp_addr)); 5604 sp_addr +=2; 5605 } 5606 else 5607 { 5608 if ((a-i) > 1) 5609 { 5610 tmp = RLW(sp_addr); 5611 sp_addr +=4; 5612 } 5613 else 5614 { 5615 tmp = RW(sp_addr); 5616 sp_addr +=2; 5617 5618 if (is_regp == 0) 5619 tmp = (tmp << 16) | (GPR32 (b+i)); 5620 else 5621 tmp = (tmp << 16) | (GPR32 (b+i-1)); 5622 } 5623 5624 if (is_regp == 0) 5625 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16) 5626 | ((tmp >> 16) & 0xffff))); 5627 else 5628 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16) 5629 | ((tmp >> 16) & 0xffff))); 5630 5631 ++i; 5632 is_regp = 1; 5633 } 5634 } 5635 5636 tmp = RLW(sp_addr); /* store RA also. */ 5637 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff))); 5638 5639 SET_GPR32 (15, (sp_addr + 4)); /* Update SP address. */ 5640 5641 trace_output_void (); 5642} 5643 5644/* pop. */ 5645void 5646OP_2_8 () 5647{ 5648 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0; 5649 uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0; 5650 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_VOID); 5651 5652 for (; i < a; ++i) 5653 { 5654 if ((b+i) <= 11) 5655 { 5656 SET_GPR ((b+i), RW(sp_addr)); 5657 sp_addr +=2; 5658 } 5659 else 5660 { 5661 if ((a-i) > 1) 5662 { 5663 tmp = RLW(sp_addr); 5664 sp_addr +=4; 5665 } 5666 else 5667 { 5668 tmp = RW(sp_addr); 5669 sp_addr +=2; 5670 5671 if (is_regp == 0) 5672 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i)); 5673 else 5674 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i-1)); 5675 } 5676 5677 if (is_regp == 0) 5678 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff))); 5679 else 5680 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff))); 5681 ++i; 5682 is_regp = 1; 5683 } 5684 } 5685 5686 if (c == 1) 5687 { 5688 tmp = RLW(sp_addr); /* Store RA Reg. */ 5689 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff))); 5690 sp_addr +=4; 5691 } 5692 5693 SET_GPR32 (15, sp_addr); /* Update SP address. */ 5694 5695 trace_output_void (); 5696} 5697 5698/* pop. */ 5699void 5700OP_21E_10 () 5701{ 5702 uint32 sp_addr = GPR32 (15); 5703 uint32 tmp; 5704 trace_input ("pop", OP_VOID, OP_VOID, OP_VOID); 5705 5706 tmp = RLW(sp_addr); 5707 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff))); 5708 SET_GPR32 (15, (sp_addr+4)); /* Update SP address. */ 5709 5710 trace_output_void (); 5711} 5712 5713/* popret. */ 5714void 5715OP_7_9 () 5716{ 5717 uint16 a = OP[0], b = OP[1]; 5718 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_REG); 5719 OP_5_9 (); 5720 JMP(((GPR32(14)) << 1) & 0xffffff); 5721 5722 trace_output_void (); 5723} 5724 5725/* popret. */ 5726void 5727OP_3_8 () 5728{ 5729 uint16 a = OP[0], b = OP[1]; 5730 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_VOID); 5731 OP_2_8 (); 5732 JMP(((GPR32(14)) << 1) & 0xffffff); 5733 5734 trace_output_void (); 5735} 5736 5737/* popret. */ 5738void 5739OP_31E_10 () 5740{ 5741 uint32 tmp; 5742 trace_input ("popret", OP_VOID, OP_VOID, OP_VOID); 5743 OP_21E_10 (); 5744 tmp = (((GPR32(14)) << 1) & 0xffffff); 5745 /* If the resulting PC value is less than 0x00_0000 or greater 5746 than 0xFF_FFFF, this instruction causes an IAD trap.*/ 5747 5748 if ((tmp < 0x0) || (tmp > 0xFFFFFF)) 5749 { 5750 State.exception = SIG_CR16_BUS; 5751 State.pc_changed = 1; /* Don't increment the PC. */ 5752 trace_output_void (); 5753 return; 5754 } 5755 else 5756 JMP (tmp); 5757 5758 trace_output_32 (tmp); 5759} 5760 5761 5762/* cinv[i]. */ 5763void 5764OP_A_10 () 5765{ 5766 trace_input ("cinv[i]", OP_VOID, OP_VOID, OP_VOID); 5767 SET_PSR_I (1); 5768 trace_output_void (); 5769} 5770 5771/* cinv[i,u]. */ 5772void 5773OP_B_10 () 5774{ 5775 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID); 5776 SET_PSR_I (1); 5777 trace_output_void (); 5778} 5779 5780/* cinv[d]. */ 5781void 5782OP_C_10 () 5783{ 5784 trace_input ("cinv[d]", OP_VOID, OP_VOID, OP_VOID); 5785 SET_PSR_I (1); 5786 trace_output_void (); 5787} 5788 5789/* cinv[d,u]. */ 5790void 5791OP_D_10 () 5792{ 5793 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID); 5794 SET_PSR_I (1); 5795 trace_output_void (); 5796} 5797 5798/* cinv[d,i]. */ 5799void 5800OP_E_10 () 5801{ 5802 trace_input ("cinv[d,i]", OP_VOID, OP_VOID, OP_VOID); 5803 SET_PSR_I (1); 5804 trace_output_void (); 5805} 5806 5807/* cinv[d,i,u]. */ 5808void 5809OP_F_10 () 5810{ 5811 trace_input ("cinv[d,i,u]", OP_VOID, OP_VOID, OP_VOID); 5812 SET_PSR_I (1); 5813 trace_output_void (); 5814} 5815 5816/* retx. */ 5817void 5818OP_3_10 () 5819{ 5820 trace_input ("retx", OP_VOID, OP_VOID, OP_VOID); 5821 SET_PSR_I (1); 5822 trace_output_void (); 5823} 5824 5825/* di. */ 5826void 5827OP_4_10 () 5828{ 5829 trace_input ("di", OP_VOID, OP_VOID, OP_VOID); 5830 SET_PSR_I (1); 5831 trace_output_void (); 5832} 5833 5834/* ei. */ 5835void 5836OP_5_10 () 5837{ 5838 trace_input ("ei", OP_VOID, OP_VOID, OP_VOID); 5839 SET_PSR_I (1); 5840 trace_output_void (); 5841} 5842 5843/* wait. */ 5844void 5845OP_6_10 () 5846{ 5847 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID); 5848 State.exception = SIGTRAP; 5849 trace_output_void (); 5850} 5851 5852/* ewait. */ 5853void 5854OP_7_10 () 5855{ 5856 trace_input ("ewait", OP_VOID, OP_VOID, OP_VOID); 5857 SET_PSR_I (1); 5858 trace_output_void (); 5859} 5860 5861/* xorb. */ 5862void 5863OP_28_8 () 5864{ 5865 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; 5866 trace_input ("xorb", OP_CONSTANT4, OP_REG, OP_VOID); 5867 tmp = a ^ b; 5868 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 5869 trace_output_16 (tmp); 5870} 5871 5872/* xorb. */ 5873void 5874OP_28B_C () 5875{ 5876 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; 5877 trace_input ("xorb", OP_CONSTANT16, OP_REG, OP_VOID); 5878 tmp = a ^ b; 5879 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 5880 trace_output_16 (tmp); 5881} 5882 5883/* xorb. */ 5884void 5885OP_29_8 () 5886{ 5887 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; 5888 trace_input ("xorb", OP_REG, OP_REG, OP_VOID); 5889 tmp = a ^ b; 5890 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 5891 trace_output_16 (tmp); 5892} 5893 5894/* xorw. */ 5895void 5896OP_2A_8 () 5897{ 5898 uint16 tmp, a = (OP[0]), b = (GPR (OP[1])); 5899 trace_input ("xorw", OP_CONSTANT4, OP_REG, OP_VOID); 5900 tmp = a ^ b; 5901 SET_GPR (OP[1], tmp); 5902 trace_output_16 (tmp); 5903} 5904 5905/* xorw. */ 5906void 5907OP_2AB_C () 5908{ 5909 uint16 tmp, a = (OP[0]), b = (GPR (OP[1])); 5910 trace_input ("xorw", OP_CONSTANT16, OP_REG, OP_VOID); 5911 tmp = a ^ b; 5912 SET_GPR (OP[1], tmp); 5913 trace_output_16 (tmp); 5914} 5915 5916/* xorw. */ 5917void 5918OP_2B_8 () 5919{ 5920 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1])); 5921 trace_input ("xorw", OP_REG, OP_REG, OP_VOID); 5922 tmp = a ^ b; 5923 SET_GPR (OP[1], tmp); 5924 trace_output_16 (tmp); 5925} 5926 5927/*REVISIT FOR LPR/SPR . */ 5928 5929/* lpr. */ 5930void 5931OP_140_14 () 5932{ 5933 uint16 a = GPR (OP[0]); 5934 trace_input ("lpr", OP_REG, OP_REG, OP_VOID); 5935 SET_CREG (OP[1], a); 5936 trace_output_16 (a); 5937} 5938 5939/* lprd. */ 5940void 5941OP_141_14 () 5942{ 5943 uint32 a = GPR32 (OP[0]); 5944 trace_input ("lprd", OP_REGP, OP_REG, OP_VOID); 5945 SET_CREG (OP[1], a); 5946 trace_output_flag (); 5947} 5948 5949/* spr. */ 5950void 5951OP_142_14 () 5952{ 5953 uint16 a = CREG (OP[0]); 5954 trace_input ("spr", OP_REG, OP_REG, OP_VOID); 5955 SET_GPR (OP[1], a); 5956 trace_output_16 (a); 5957} 5958 5959/* sprd. */ 5960void 5961OP_143_14 () 5962{ 5963 uint32 a = CREG (OP[0]); 5964 trace_input ("sprd", OP_REGP, OP_REGP, OP_VOID); 5965 SET_GPR32 (OP[1], a); 5966 trace_output_32 (a); 5967} 5968 5969/* null. */ 5970void 5971OP_0_20 () 5972{ 5973 trace_input ("null", OP_VOID, OP_VOID, OP_VOID); 5974 State.exception = SIG_CR16_STOP; 5975} 5976