1/* ppc.h -- Header file for PowerPC opcode table 2 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 3 2007, 2008, 2009, 2010 Free Software Foundation, Inc. 4 Written by Ian Lance Taylor, Cygnus Support 5 6 This file is part of GDB, GAS, and the GNU binutils. 7 8 GDB, GAS, and the GNU binutils are free software; you can redistribute 9 them and/or modify them under the terms of the GNU General Public 10 License as published by the Free Software Foundation; either version 3, 11 or (at your option) any later version. 12 13 GDB, GAS, and the GNU binutils are distributed in the hope that they 14 will be useful, but WITHOUT ANY WARRANTY; without even the implied 15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 16 the GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING3. If not, write to the Free 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23#ifndef PPC_H 24#define PPC_H 25 26#include "bfd_stdint.h" 27 28typedef uint64_t ppc_cpu_t; 29 30/* The opcode table is an array of struct powerpc_opcode. */ 31 32struct powerpc_opcode 33{ 34 /* The opcode name. */ 35 const char *name; 36 37 /* The opcode itself. Those bits which will be filled in with 38 operands are zeroes. */ 39 unsigned long opcode; 40 41 /* The opcode mask. This is used by the disassembler. This is a 42 mask containing ones indicating those bits which must match the 43 opcode field, and zeroes indicating those bits which need not 44 match (and are presumably filled in by operands). */ 45 unsigned long mask; 46 47 /* One bit flags for the opcode. These are used to indicate which 48 specific processors support the instructions. The defined values 49 are listed below. */ 50 ppc_cpu_t flags; 51 52 /* One bit flags for the opcode. These are used to indicate which 53 specific processors no longer support the instructions. The defined 54 values are listed below. */ 55 ppc_cpu_t deprecated; 56 57 /* An array of operand codes. Each code is an index into the 58 operand table. They appear in the order which the operands must 59 appear in assembly code, and are terminated by a zero. */ 60 unsigned char operands[8]; 61}; 62 63/* The table itself is sorted by major opcode number, and is otherwise 64 in the order in which the disassembler should consider 65 instructions. */ 66extern const struct powerpc_opcode powerpc_opcodes[]; 67extern const int powerpc_num_opcodes; 68 69/* Values defined for the flags field of a struct powerpc_opcode. */ 70 71/* Opcode is defined for the PowerPC architecture. */ 72#define PPC_OPCODE_PPC 1 73 74/* Opcode is defined for the POWER (RS/6000) architecture. */ 75#define PPC_OPCODE_POWER 2 76 77/* Opcode is defined for the POWER2 (Rios 2) architecture. */ 78#define PPC_OPCODE_POWER2 4 79 80/* Opcode is supported by the Motorola PowerPC 601 processor. The 601 81 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, 82 but it also supports many additional POWER instructions. */ 83#define PPC_OPCODE_601 8 84 85/* Opcode is supported in both the Power and PowerPC architectures 86 (ie, compiler's -mcpu=common or assembler's -mcom). More than just 87 the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER 88 and PPC_OPCODE_POWER2 because many instructions changed mnemonics 89 between POWER and POWERPC. */ 90#define PPC_OPCODE_COMMON 0x10 91 92/* Opcode is supported for any Power or PowerPC platform (this is 93 for the assembler's -many option, and it eliminates duplicates). */ 94#define PPC_OPCODE_ANY 0x20 95 96/* Opcode is only defined on 64 bit architectures. */ 97#define PPC_OPCODE_64 0x40 98 99/* Opcode is supported as part of the 64-bit bridge. */ 100#define PPC_OPCODE_64_BRIDGE 0x80 101 102/* Opcode is supported by Altivec Vector Unit */ 103#define PPC_OPCODE_ALTIVEC 0x100 104 105/* Opcode is supported by PowerPC 403 processor. */ 106#define PPC_OPCODE_403 0x200 107 108/* Opcode is supported by PowerPC BookE processor. */ 109#define PPC_OPCODE_BOOKE 0x400 110 111/* Opcode is supported by PowerPC 440 processor. */ 112#define PPC_OPCODE_440 0x800 113 114/* Opcode is only supported by Power4 architecture. */ 115#define PPC_OPCODE_POWER4 0x1000 116 117/* Opcode is only supported by Power7 architecture. */ 118#define PPC_OPCODE_POWER7 0x2000 119 120/* Opcode is only supported by e500x2 Core. */ 121#define PPC_OPCODE_SPE 0x4000 122 123/* Opcode is supported by e500x2 Integer select APU. */ 124#define PPC_OPCODE_ISEL 0x8000 125 126/* Opcode is an e500 SPE floating point instruction. */ 127#define PPC_OPCODE_EFS 0x10000 128 129/* Opcode is supported by branch locking APU. */ 130#define PPC_OPCODE_BRLOCK 0x20000 131 132/* Opcode is supported by performance monitor APU. */ 133#define PPC_OPCODE_PMR 0x40000 134 135/* Opcode is supported by cache locking APU. */ 136#define PPC_OPCODE_CACHELCK 0x80000 137 138/* Opcode is supported by machine check APU. */ 139#define PPC_OPCODE_RFMCI 0x100000 140 141/* Opcode is only supported by Power5 architecture. */ 142#define PPC_OPCODE_POWER5 0x200000 143 144/* Opcode is supported by PowerPC e300 family. */ 145#define PPC_OPCODE_E300 0x400000 146 147/* Opcode is only supported by Power6 architecture. */ 148#define PPC_OPCODE_POWER6 0x800000 149 150/* Opcode is only supported by PowerPC Cell family. */ 151#define PPC_OPCODE_CELL 0x1000000 152 153/* Opcode is supported by CPUs with paired singles support. */ 154#define PPC_OPCODE_PPCPS 0x2000000 155 156/* Opcode is supported by Power E500MC */ 157#define PPC_OPCODE_E500MC 0x4000000 158 159/* Opcode is supported by PowerPC 405 processor. */ 160#define PPC_OPCODE_405 0x8000000 161 162/* Opcode is supported by Vector-Scalar (VSX) Unit */ 163#define PPC_OPCODE_VSX 0x10000000 164 165/* Opcode is supported by A2. */ 166#define PPC_OPCODE_A2 0x20000000 167 168/* Opcode is supported by PowerPC 476 processor. */ 169#define PPC_OPCODE_476 0x40000000 170 171/* Opcode is supported by AppliedMicro Titan core */ 172#define PPC_OPCODE_TITAN 0x80000000 173 174/* Opcode which is supported by the e500 family */ 175#define PPC_OPCODE_E500 0x100000000ull 176 177/* A macro to extract the major opcode from an instruction. */ 178#define PPC_OP(i) (((i) >> 26) & 0x3f) 179 180/* The operands table is an array of struct powerpc_operand. */ 181 182struct powerpc_operand 183{ 184 /* A bitmask of bits in the operand. */ 185 unsigned int bitm; 186 187 /* How far the operand is left shifted in the instruction. 188 -1 to indicate that BITM and SHIFT cannot be used to determine 189 where the operand goes in the insn. */ 190 int shift; 191 192 /* Insertion function. This is used by the assembler. To insert an 193 operand value into an instruction, check this field. 194 195 If it is NULL, execute 196 i |= (op & o->bitm) << o->shift; 197 (i is the instruction which we are filling in, o is a pointer to 198 this structure, and op is the operand value). 199 200 If this field is not NULL, then simply call it with the 201 instruction and the operand value. It will return the new value 202 of the instruction. If the ERRMSG argument is not NULL, then if 203 the operand value is illegal, *ERRMSG will be set to a warning 204 string (the operand will be inserted in any case). If the 205 operand value is legal, *ERRMSG will be unchanged (most operands 206 can accept any value). */ 207 unsigned long (*insert) 208 (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg); 209 210 /* Extraction function. This is used by the disassembler. To 211 extract this operand type from an instruction, check this field. 212 213 If it is NULL, compute 214 op = (i >> o->shift) & o->bitm; 215 if ((o->flags & PPC_OPERAND_SIGNED) != 0) 216 sign_extend (op); 217 (i is the instruction, o is a pointer to this structure, and op 218 is the result). 219 220 If this field is not NULL, then simply call it with the 221 instruction value. It will return the value of the operand. If 222 the INVALID argument is not NULL, *INVALID will be set to 223 non-zero if this operand type can not actually be extracted from 224 this operand (i.e., the instruction does not match). If the 225 operand is valid, *INVALID will not be changed. */ 226 long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid); 227 228 /* One bit syntax flags. */ 229 unsigned long flags; 230}; 231 232/* Elements in the table are retrieved by indexing with values from 233 the operands field of the powerpc_opcodes table. */ 234 235extern const struct powerpc_operand powerpc_operands[]; 236extern const unsigned int num_powerpc_operands; 237 238/* Values defined for the flags field of a struct powerpc_operand. */ 239 240/* This operand takes signed values. */ 241#define PPC_OPERAND_SIGNED (0x1) 242 243/* This operand takes signed values, but also accepts a full positive 244 range of values when running in 32 bit mode. That is, if bits is 245 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, 246 this flag is ignored. */ 247#define PPC_OPERAND_SIGNOPT (0x2) 248 249/* This operand does not actually exist in the assembler input. This 250 is used to support extended mnemonics such as mr, for which two 251 operands fields are identical. The assembler should call the 252 insert function with any op value. The disassembler should call 253 the extract function, ignore the return value, and check the value 254 placed in the valid argument. */ 255#define PPC_OPERAND_FAKE (0x4) 256 257/* The next operand should be wrapped in parentheses rather than 258 separated from this one by a comma. This is used for the load and 259 store instructions which want their operands to look like 260 reg,displacement(reg) 261 */ 262#define PPC_OPERAND_PARENS (0x8) 263 264/* This operand may use the symbolic names for the CR fields, which 265 are 266 lt 0 gt 1 eq 2 so 3 un 3 267 cr0 0 cr1 1 cr2 2 cr3 3 268 cr4 4 cr5 5 cr6 6 cr7 7 269 These may be combined arithmetically, as in cr2*4+gt. These are 270 only supported on the PowerPC, not the POWER. */ 271#define PPC_OPERAND_CR (0x10) 272 273/* This operand names a register. The disassembler uses this to print 274 register names with a leading 'r'. */ 275#define PPC_OPERAND_GPR (0x20) 276 277/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ 278#define PPC_OPERAND_GPR_0 (0x40) 279 280/* This operand names a floating point register. The disassembler 281 prints these with a leading 'f'. */ 282#define PPC_OPERAND_FPR (0x80) 283 284/* This operand is a relative branch displacement. The disassembler 285 prints these symbolically if possible. */ 286#define PPC_OPERAND_RELATIVE (0x100) 287 288/* This operand is an absolute branch address. The disassembler 289 prints these symbolically if possible. */ 290#define PPC_OPERAND_ABSOLUTE (0x200) 291 292/* This operand is optional, and is zero if omitted. This is used for 293 example, in the optional BF field in the comparison instructions. The 294 assembler must count the number of operands remaining on the line, 295 and the number of operands remaining for the opcode, and decide 296 whether this operand is present or not. The disassembler should 297 print this operand out only if it is not zero. */ 298#define PPC_OPERAND_OPTIONAL (0x400) 299 300/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand 301 is omitted, then for the next operand use this operand value plus 302 1, ignoring the next operand field for the opcode. This wretched 303 hack is needed because the Power rotate instructions can take 304 either 4 or 5 operands. The disassembler should print this operand 305 out regardless of the PPC_OPERAND_OPTIONAL field. */ 306#define PPC_OPERAND_NEXT (0x800) 307 308/* This operand should be regarded as a negative number for the 309 purposes of overflow checking (i.e., the normal most negative 310 number is disallowed and one more than the normal most positive 311 number is allowed). This flag will only be set for a signed 312 operand. */ 313#define PPC_OPERAND_NEGATIVE (0x1000) 314 315/* This operand names a vector unit register. The disassembler 316 prints these with a leading 'v'. */ 317#define PPC_OPERAND_VR (0x2000) 318 319/* This operand is for the DS field in a DS form instruction. */ 320#define PPC_OPERAND_DS (0x4000) 321 322/* This operand is for the DQ field in a DQ form instruction. */ 323#define PPC_OPERAND_DQ (0x8000) 324 325/* Valid range of operand is 0..n rather than 0..n-1. */ 326#define PPC_OPERAND_PLUS1 (0x10000) 327 328/* Xilinx APU and FSL related operands */ 329#define PPC_OPERAND_FSL (0x20000) 330#define PPC_OPERAND_FCR (0x40000) 331#define PPC_OPERAND_UDI (0x80000) 332 333/* This operand names a vector-scalar unit register. The disassembler 334 prints these with a leading 'vs'. */ 335#define PPC_OPERAND_VSR (0x100000) 336 337/* The POWER and PowerPC assemblers use a few macros. We keep them 338 with the operands table for simplicity. The macro table is an 339 array of struct powerpc_macro. */ 340 341struct powerpc_macro 342{ 343 /* The macro name. */ 344 const char *name; 345 346 /* The number of operands the macro takes. */ 347 unsigned int operands; 348 349 /* One bit flags for the opcode. These are used to indicate which 350 specific processors support the instructions. The values are the 351 same as those for the struct powerpc_opcode flags field. */ 352 ppc_cpu_t flags; 353 354 /* A format string to turn the macro into a normal instruction. 355 Each %N in the string is replaced with operand number N (zero 356 based). */ 357 const char *format; 358}; 359 360extern const struct powerpc_macro powerpc_macros[]; 361extern const int powerpc_num_macros; 362 363extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, const char *); 364 365#endif /* PPC_H */ 366