12011-03-22 Eric B. Weddington <eric.weddington@atmel.com> 2 3 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA): 4 New instruction set flags. 5 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA. 6 72011-02-28 Maciej W. Rozycki <macro@codesourcery.com> 8 9 * mips.h (M_PREF_AB): New enum value. 10 112011-02-12 Mike Frysinger <vapier@gentoo.org> 12 13 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH, 14 M_IU): Define. 15 (is_macmod_pmove, is_macmod_hmove): New functions. 16 172011-02-11 Mike Frysinger <vapier@gentoo.org> 18 19 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection. 20 212011-02-04 Bernd Schmidt <bernds@codesourcery.com> 22 23 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP. 24 * tic6x.h (TIC6X_INSN_ATOMIC): Remove. 25 262010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 27 28 PR gas/11395 29 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit 30 "bb" entries. 31 322010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 33 34 PR gas/11395 35 * hppa.h: Clear "d" bit in "add" and "sub" patterns. 36 372010-12-18 Richard Sandiford <rdsandiford@googlemail.com> 38 39 * mips.h: Update commentary after last commit. 40 412010-12-18 Mingjie Xing <mingjie.xing@gmail.com> 42 43 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C) 44 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z) 45 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define. 46 472010-11-23 Richard Sandiford <rdsandiford@googlemail.com> 48 49 * mips.h: Fix previous commit. 50 512010-11-23 Maciej W. Rozycki <macro@linux-mips.org> 52 53 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A. 54 (INSN_LOONGSON_3A): Clear bit 31. 55 562010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 57 58 PR gas/12198 59 * arm.h (ARM_AEXT_V6M_ONLY): New define. 60 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY. 61 (ARM_ARCH_V6M_ONLY): New define. 62 632010-11-11 Mingming Sun <mingm.sun@gmail.com> 64 65 * mips.h (INSN_LOONGSON_3A): Defined. 66 (CPU_LOONGSON_3A): Defined. 67 (OPCODE_IS_MEMBER): Add LOONGSON_3A. 68 692010-10-09 Matt Rice <ratmice@gmail.com> 70 71 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_. 72 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise. 73 742010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 75 76 * arm.h (ARM_EXT_VIRT): New define. 77 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename... 78 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization 79 Extensions. 80 812010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 82 83 * arm.h (ARM_AEXT_ADIV): New define. 84 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise. 85 862010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 87 88 * arm.h (ARM_EXT_OS): New define. 89 (ARM_AEXT_V6SM): Likewise. 90 (ARM_ARCH_V6SM): Likewise. 91 922010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 93 94 * arm.h (ARM_EXT_MP): Add. 95 (ARM_ARCH_V7A_MP): Likewise. 96 972010-09-22 Mike Frysinger <vapier@gentoo.org> 98 99 * bfin.h: Declare pseudoChr structs/defines. 100 1012010-09-21 Mike Frysinger <vapier@gentoo.org> 102 103 * bfin.h: Strip trailing whitespace. 104 1052010-07-29 DJ Delorie <dj@redhat.com> 106 107 * rx.h (RX_Operand_Type): Add TwoReg. 108 (RX_Opcode_ID): Remove ediv and ediv2. 109 1102010-07-27 DJ Delorie <dj@redhat.com> 111 112 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics. 113 1142010-07-23 Naveen.H.S <naveen.S@kpitcummins.com> 115 Ina Pandit <ina.pandit@kpitcummins.com> 116 117 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION, 118 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and 119 PROCESSOR_V850E2_ALL. 120 Remove PROCESSOR_V850EA support. 121 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC, 122 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI, 123 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED, 124 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP, 125 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and 126 V850_OPERAND_PERCENT. 127 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and 128 V850_NOT_R0. 129 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP 130 and V850E_PUSH_POP 131 1322010-07-06 Maciej W. Rozycki <macro@codesourcery.com> 133 134 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro. 135 (MIPS16_INSN_BRANCH): Rename to... 136 (MIPS16_INSN_COND_BRANCH): ... this. 137 1382010-07-03 Alan Modra <amodra@gmail.com> 139 140 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete. 141 Renumber other PPC_OPCODE defines. 142 1432010-07-03 Alan Modra <amodra@gmail.com> 144 145 * ppc.h (PPC_OPCODE_COMMON): Expand comment. 146 1472010-06-29 Alan Modra <amodra@gmail.com> 148 149 * maxq.h: Delete file. 150 1512010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de> 152 153 * ppc.h (PPC_OPCODE_E500): Define. 154 1552010-05-26 Catherine Moore <clm@codesourcery.com> 156 157 * opcode/mips.h (INSN_MIPS16): Remove. 158 1592010-04-21 Joseph Myers <joseph@codesourcery.com> 160 161 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask. 162 1632010-04-15 Nick Clifton <nickc@redhat.com> 164 165 * alpha.h: Update copyright notice to use GPLv3. 166 * arc.h: Likewise. 167 * arm.h: Likewise. 168 * avr.h: Likewise. 169 * bfin.h: Likewise. 170 * cgen.h: Likewise. 171 * convex.h: Likewise. 172 * cr16.h: Likewise. 173 * cris.h: Likewise. 174 * crx.h: Likewise. 175 * d10v.h: Likewise. 176 * d30v.h: Likewise. 177 * dlx.h: Likewise. 178 * h8300.h: Likewise. 179 * hppa.h: Likewise. 180 * i370.h: Likewise. 181 * i386.h: Likewise. 182 * i860.h: Likewise. 183 * i960.h: Likewise. 184 * ia64.h: Likewise. 185 * m68hc11.h: Likewise. 186 * m68k.h: Likewise. 187 * m88k.h: Likewise. 188 * maxq.h: Likewise. 189 * mips.h: Likewise. 190 * mmix.h: Likewise. 191 * mn10200.h: Likewise. 192 * mn10300.h: Likewise. 193 * msp430.h: Likewise. 194 * np1.h: Likewise. 195 * ns32k.h: Likewise. 196 * or32.h: Likewise. 197 * pdp11.h: Likewise. 198 * pj.h: Likewise. 199 * pn.h: Likewise. 200 * ppc.h: Likewise. 201 * pyr.h: Likewise. 202 * rx.h: Likewise. 203 * s390.h: Likewise. 204 * score-datadep.h: Likewise. 205 * score-inst.h: Likewise. 206 * sparc.h: Likewise. 207 * spu-insns.h: Likewise. 208 * spu.h: Likewise. 209 * tic30.h: Likewise. 210 * tic4x.h: Likewise. 211 * tic54x.h: Likewise. 212 * tic80.h: Likewise. 213 * v850.h: Likewise. 214 * vax.h: Likewise. 215 2162010-03-25 Joseph Myers <joseph@codesourcery.com> 217 218 * tic6x-control-registers.h, tic6x-insn-formats.h, 219 tic6x-opcode-table.h, tic6x.h: New. 220 2212010-02-25 Wu Zhangjin <wuzhangjin@gmail.com> 222 223 * mips.h: (LOONGSON2F_NOP_INSN): New macro. 224 2252010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com> 226 227 * opcode/ppc.h (PPC_OPCODE_TITAN): Define. 228 2292010-01-14 H.J. Lu <hongjiu.lu@intel.com> 230 231 * ia64.h (ia64_find_opcode): Remove argument name. 232 (ia64_find_next_opcode): Likewise. 233 (ia64_dis_opcode): Likewise. 234 (ia64_free_opcode): Likewise. 235 (ia64_find_dependency): Likewise. 236 2372009-11-22 Doug Evans <dje@sebabeach.org> 238 239 * cgen.h: Include bfd_stdint.h. 240 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types. 241 2422009-11-18 Paul Brook <paul@codesourcery.com> 243 244 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define. 245 2462009-11-17 Paul Brook <paul@codesourcery.com> 247 Daniel Jacobowitz <dan@codesourcery.com> 248 249 * arm.h (ARM_EXT_V6_DSP): Define. 250 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP. 251 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define. 252 2532009-11-04 DJ Delorie <dj@redhat.com> 254 255 * rx.h (rx_decode_opcode) (mvtipl): Add. 256 (mvtcp, mvfcp, opecp): Remove. 257 2582009-11-02 Paul Brook <paul@codesourcery.com> 259 260 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA, 261 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define. 262 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD, 263 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16, 264 FPU_ARCH_NEON_VFP_V4): Define. 265 2662009-10-23 Doug Evans <dje@sebabeach.org> 267 268 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h. 269 * cgen.h: Update. Improve multi-inclusion macro name. 270 2712009-10-02 Peter Bergner <bergner@vnet.ibm.com> 272 273 * ppc.h (PPC_OPCODE_476): Define. 274 2752009-10-01 Peter Bergner <bergner@vnet.ibm.com> 276 277 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2. 278 2792009-09-29 DJ Delorie <dj@redhat.com> 280 281 * rx.h: New file. 282 2832009-09-22 Peter Bergner <bergner@vnet.ibm.com> 284 285 * ppc.h (ppc_cpu_t): Typedef to uint64_t. 286 2872009-09-21 Ben Elliston <bje@au.ibm.com> 288 289 * ppc.h (PPC_OPCODE_PPCA2): New. 290 2912009-09-05 Martin Thuresson <martin@mtme.org> 292 293 * ia64.h (struct ia64_operand): Renamed member class to op_class. 294 2952009-08-29 Martin Thuresson <martin@mtme.org> 296 297 * tic30.h (template): Rename type template to 298 insn_template. Updated code to use new name. 299 * tic54x.h (template): Rename type template to 300 insn_template. 301 3022009-08-20 Nick Hudson <nick.hudson@gmx.co.uk> 303 304 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT. 305 3062009-06-11 Anthony Green <green@moxielogic.com> 307 308 * moxie.h (MOXIE_F3_PCREL): Define. 309 (moxie_form3_opc_info): Grow. 310 3112009-06-06 Anthony Green <green@moxielogic.com> 312 313 * moxie.h (MOXIE_F1_M): Define. 314 3152009-04-15 Anthony Green <green@moxielogic.com> 316 317 * moxie.h: Created. 318 3192009-04-06 DJ Delorie <dj@redhat.com> 320 321 * h8300.h: Add relaxation attributes to MOVA opcodes. 322 3232009-03-10 Alan Modra <amodra@bigpond.net.au> 324 325 * ppc.h (ppc_parse_cpu): Declare. 326 3272009-03-02 Qinwei <qinwei@sunnorth.com.cn> 328 329 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5 330 and _IMM11 for mbitclr and mbitset. 331 * score-datadep.h: Update dependency information. 332 3332009-02-26 Peter Bergner <bergner@vnet.ibm.com> 334 335 * ppc.h (PPC_OPCODE_POWER7): New. 336 3372009-02-06 Doug Evans <dje@google.com> 338 339 * i386.h: Add comment regarding sse* insns and prefixes. 340 3412009-02-03 Sandip Matte <sandip@rmicorp.com> 342 343 * mips.h (INSN_XLR): Define. 344 (INSN_CHIP_MASK): Update. 345 (CPU_XLR): Define. 346 (OPCODE_IS_MEMBER): Update. 347 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define. 348 3492009-01-28 Doug Evans <dje@google.com> 350 351 * opcode/i386.h: Add multiple inclusion protection. 352 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM) 353 (EDI_REG_NUM): New macros. 354 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros. 355 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros. 356 (REX_PREFIX_P): New macro. 357 3582009-01-09 Peter Bergner <bergner@vnet.ibm.com> 359 360 * ppc.h (struct powerpc_opcode): New field "deprecated". 361 (PPC_OPCODE_NOPOWER4): Delete. 362 3632008-11-28 Joshua Kinard <kumba@gentoo.org> 364 365 * mips.h: Define CPU_R14000, CPU_R16000. 366 (OPCODE_IS_MEMBER): Include R14000, R16000 in test. 367 3682008-11-18 Catherine Moore <clm@codesourcery.com> 369 370 * arm.h (FPU_NEON_FP16): New. 371 (FPU_ARCH_NEON_FP16): New. 372 3732008-11-06 Chao-ying Fu <fu@mips.com> 374 375 * mips.h: Doucument '1' for 5-bit sync type. 376 3772008-08-28 H.J. Lu <hongjiu.lu@intel.com> 378 379 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update 380 IA64_RS_CR. 381 3822008-08-01 Peter Bergner <bergner@vnet.ibm.com> 383 384 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New. 385 3862008-07-30 Michael J. Eager <eager@eagercon.com> 387 388 * ppc.h (PPC_OPCODE_405): Define. 389 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define. 390 3912008-06-13 Peter Bergner <bergner@vnet.ibm.com> 392 393 * ppc.h (ppc_cpu_t): New typedef. 394 (struct powerpc_opcode <flags>): Use it. 395 (struct powerpc_operand <insert, extract>): Likewise. 396 (struct powerpc_macro <flags>): Likewise. 397 3982008-06-12 Adam Nemet <anemet@caviumnetworks.com> 399 400 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S. 401 Update comment before MIPS16 field descriptors to mention MIPS16. 402 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for 403 BBIT. 404 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1): 405 New bit masks and shift counts for cins and exts. 406 407 * mips.h: Document new field descriptors +Q. 408 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI. 409 4102008-04-28 Adam Nemet <anemet@caviumnetworks.com> 411 412 * mips.h (INSN_MACRO): Move it up to the the pinfo macros. 413 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros. 414 4152008-04-14 Edmar Wienskoski <edmar@freescale.com> 416 417 * ppc.h: (PPC_OPCODE_E500MC): New. 418 4192008-04-03 H.J. Lu <hongjiu.lu@intel.com> 420 421 * i386.h (MAX_OPERANDS): Set to 5. 422 (MAX_MNEM_SIZE): Changed to 20. 423 4242008-03-28 Eric B. Weddington <eric.weddington@atmel.com> 425 426 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167. 427 4282008-03-09 Paul Brook <paul@codesourcery.com> 429 430 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define. 431 4322008-03-04 Paul Brook <paul@codesourcery.com> 433 434 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define. 435 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags. 436 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define. 437 4382008-02-27 Denis Vlasenko <vda.linux@googlemail.com> 439 Nick Clifton <nickc@redhat.com> 440 441 PR 3134 442 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction 443 with a 32-bit displacement but without the top bit of the 4th byte 444 set. 445 4462008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com> 447 448 * cr16.h (cr16_num_optab): Declared. 449 4502008-02-14 Hakan Ardo <hakan@debian.org> 451 452 PR gas/2626 453 * avr.h (AVR_ISA_2xxe): Define. 454 4552008-02-04 Adam Nemet <anemet@caviumnetworks.com> 456 457 * mips.h: Update copyright. 458 (INSN_CHIP_MASK): New macro. 459 (INSN_OCTEON): New macro. 460 (CPU_OCTEON): New macro. 461 (OPCODE_IS_MEMBER): Handle Octeon instructions. 462 4632008-01-23 Eric B. Weddington <eric.weddington@atmel.com> 464 465 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401. 466 4672008-01-03 Eric B. Weddington <eric.weddington@atmel.com> 468 469 * avr.h (AVR_ISA_USB162): Add new opcode set. 470 (AVR_ISA_AVR3): Likewise. 471 4722007-11-29 Mark Shinwell <shinwell@codesourcery.com> 473 474 * mips.h (INSN_LOONGSON_2E): New. 475 (INSN_LOONGSON_2F): New. 476 (CPU_LOONGSON_2E): New. 477 (CPU_LOONGSON_2F): New. 478 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags. 479 4802007-11-29 Mark Shinwell <shinwell@codesourcery.com> 481 482 * mips.h (INSN_ISA*): Redefine certain values as an 483 enumeration. Update comments. 484 (mips_isa_table): New. 485 (ISA_MIPS*): Redefine to match enumeration. 486 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA* 487 values. 488 4892007-08-08 Ben Elliston <bje@au.ibm.com> 490 491 * ppc.h (PPC_OPCODE_PPCPS): New. 492 4932007-07-03 Nathan Sidwell <nathan@codesourcery.com> 494 495 * m68k.h: Document j K & E. 496 4972007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com> 498 499 * cr16.h: New file for CR16 target. 500 5012007-05-02 Alan Modra <amodra@bigpond.net.au> 502 503 * ppc.h (PPC_OPERAND_PLUS1): Update comment. 504 5052007-04-23 Nathan Sidwell <nathan@codesourcery.com> 506 507 * m68k.h (mcfisa_c): New. 508 (mcfusp, mcf_mask): Adjust. 509 5102007-04-20 Alan Modra <amodra@bigpond.net.au> 511 512 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm". 513 (num_powerpc_operands): Declare. 514 (PPC_OPERAND_SIGNED et al): Redefine as hex. 515 (PPC_OPERAND_PLUS1): Define. 516 5172007-03-21 H.J. Lu <hongjiu.lu@intel.com> 518 519 * i386.h (REX_MODE64): Renamed to ... 520 (REX_W): This. 521 (REX_EXTX): Renamed to ... 522 (REX_R): This. 523 (REX_EXTY): Renamed to ... 524 (REX_X): This. 525 (REX_EXTZ): Renamed to ... 526 (REX_B): This. 527 5282007-03-15 H.J. Lu <hongjiu.lu@intel.com> 529 530 * i386.h: Add entries from config/tc-i386.h and move tables 531 to opcodes/i386-opc.h. 532 5332007-03-13 H.J. Lu <hongjiu.lu@intel.com> 534 535 * i386.h (FloatDR): Removed. 536 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR. 537 5382007-03-01 Alan Modra <amodra@bigpond.net.au> 539 540 * spu-insns.h: Add soma double-float insns. 541 5422007-02-20 Thiemo Seufer <ths@mips.com> 543 Chao-Ying Fu <fu@mips.com> 544 545 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction. 546 (INSN_DSPR2): Add flag for DSP R2 instructions. 547 (M_BALIGN): New macro. 548 5492007-02-14 Alan Modra <amodra@bigpond.net.au> 550 551 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm 552 and Seg3ShortFrom with Shortform. 553 5542007-02-11 H.J. Lu <hongjiu.lu@intel.com> 555 556 PR gas/4027 557 * i386.h (i386_optab): Put the real "test" before the pseudo 558 one. 559 5602007-01-08 Kazu Hirata <kazu@codesourcery.com> 561 562 * m68k.h (m68010up): OR fido_a. 563 5642006-12-25 Kazu Hirata <kazu@codesourcery.com> 565 566 * m68k.h (fido_a): New. 567 5682006-12-24 Kazu Hirata <kazu@codesourcery.com> 569 570 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a, 571 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined 572 values. 573 5742006-11-08 H.J. Lu <hongjiu.lu@intel.com> 575 576 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3. 577 5782006-10-31 Mei Ligang <ligang@sunnorth.com.cn> 579 580 * score-inst.h (enum score_insn_type): Add Insn_internal. 581 5822006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> 583 Yukishige Shibata <shibata@rd.scei.sony.co.jp> 584 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp> 585 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp> 586 Alan Modra <amodra@bigpond.net.au> 587 588 * spu-insns.h: New file. 589 * spu.h: New file. 590 5912006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com> 592 593 * ppc.h (PPC_OPCODE_CELL): Define. 594 5952006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> 596 597 * i386.h : Modify opcode to support for the change in POPCNT opcode 598 in amdfam10 architecture. 599 6002006-09-28 H.J. Lu <hongjiu.lu@intel.com> 601 602 * i386.h: Replace CpuMNI with CpuSSSE3. 603 6042006-09-26 Mark Shinwell <shinwell@codesourcery.com> 605 Joseph Myers <joseph@codesourcery.com> 606 Ian Lance Taylor <ian@wasabisystems.com> 607 Ben Elliston <bje@wasabisystems.com> 608 609 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. 610 6112006-09-17 Mei Ligang <ligang@sunnorth.com.cn> 612 613 * score-datadep.h: New file. 614 * score-inst.h: New file. 615 6162006-07-14 H.J. Lu <hongjiu.lu@intel.com> 617 618 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps, 619 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu, 620 movdq2q and movq2dq. 621 6222006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> 623 Michael Meissner <michael.meissner@amd.com> 624 625 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions). 626 6272006-06-12 H.J. Lu <hongjiu.lu@intel.com> 628 629 * i386.h (i386_optab): Add "nop" with memory reference. 630 6312006-06-12 H.J. Lu <hongjiu.lu@intel.com> 632 633 * i386.h (i386_optab): Update comment for 64bit NOP. 634 6352006-06-06 Ben Elliston <bje@au.ibm.com> 636 Anton Blanchard <anton@samba.org> 637 638 * ppc.h (PPC_OPCODE_POWER6): Define. 639 Adjust whitespace. 640 6412006-06-05 Thiemo Seufer <ths@mips.com> 642 643 * mips.h: Improve description of MT flags. 644 6452006-05-25 Richard Sandiford <richard@codesourcery.com> 646 647 * m68k.h (mcf_mask): Define. 648 6492006-05-05 Thiemo Seufer <ths@mips.com> 650 David Ung <davidu@mips.com> 651 652 * mips.h (enum): Add macro M_CACHE_AB. 653 6542006-05-04 Thiemo Seufer <ths@mips.com> 655 Nigel Stephens <nigel@mips.com> 656 David Ung <davidu@mips.com> 657 658 * mips.h: Add INSN_SMARTMIPS define. 659 6602006-04-30 Thiemo Seufer <ths@mips.com> 661 David Ung <davidu@mips.com> 662 663 * mips.h: Defines udi bits and masks. Add description of 664 characters which may appear in the args field of udi 665 instructions. 666 6672006-04-26 Thiemo Seufer <ths@networkno.de> 668 669 * mips.h: Improve comments describing the bitfield instruction 670 fields. 671 6722006-04-26 Julian Brown <julian@codesourcery.com> 673 674 * arm.h (FPU_VFP_EXT_V3): Define constant. 675 (FPU_NEON_EXT_V1): Likewise. 676 (FPU_VFP_HARD): Update. 677 (FPU_VFP_V3): Define macro. 678 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros. 679 6802006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de> 681 682 * avr.h (AVR_ISA_PWMx): New. 683 6842006-03-28 Nathan Sidwell <nathan@codesourcery.com> 685 686 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010, 687 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851, 688 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e, 689 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x, 690 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove. 691 6922006-03-10 Paul Brook <paul@codesourcery.com> 693 694 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions. 695 6962006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 697 698 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come 699 first. Correct mask of bb "B" opcode. 700 7012006-02-27 H.J. Lu <hongjiu.lu@intel.com> 702 703 * i386.h (i386_optab): Support Intel Merom New Instructions. 704 7052006-02-24 Paul Brook <paul@codesourcery.com> 706 707 * arm.h: Add V7 feature bits. 708 7092006-02-23 H.J. Lu <hongjiu.lu@intel.com> 710 711 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. 712 7132006-01-31 Paul Brook <paul@codesourcery.com> 714 Richard Earnshaw <rearnsha@arm.com> 715 716 * arm.h: Use ARM_CPU_FEATURE. 717 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New. 718 (arm_feature_set): Change to a structure. 719 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, 720 ARM_FEATURE): New macros. 721 7222005-12-07 Hans-Peter Nilsson <hp@axis.com> 723 724 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS) 725 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros. 726 (ADD_PC_INCR_OPCODE): Don't define. 727 7282005-12-06 H.J. Lu <hongjiu.lu@intel.com> 729 730 PR gas/1874 731 * i386.h (i386_optab): Add 64bit support for monitor and mwait. 732 7332005-11-14 David Ung <davidu@mips.com> 734 735 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore 736 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for 737 save/restore encoding of the args field. 738 7392005-10-28 Dave Brolley <brolley@redhat.com> 740 741 Contribute the following changes: 742 2005-02-16 Dave Brolley <brolley@redhat.com> 743 744 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename 745 cgen_isa_mask_* to cgen_bitset_*. 746 * cgen.h: Likewise. 747 748 2003-10-21 Richard Sandiford <rsandifo@redhat.com> 749 750 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition. 751 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned". 752 (CGEN_CPU_TABLE): Make isas a ponter. 753 754 2003-09-29 Dave Brolley <brolley@redhat.com> 755 756 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef. 757 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto. 758 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs. 759 760 2002-12-13 Dave Brolley <brolley@redhat.com> 761 762 * cgen.h (symcat.h): #include it. 763 (cgen-bitset.h): #include it. 764 (CGEN_ATTR_VALUE_TYPE): Now a union. 765 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h. 766 (CGEN_ATTR_ENTRY): 'value' now unsigned. 767 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*). 768 * cgen-bitset.h: New file. 769 7702005-09-30 Catherine Moore <clm@cm00re.com> 771 772 * bfin.h: New file. 773 7742005-10-24 Jan Beulich <jbeulich@novell.com> 775 776 * ia64.h (enum ia64_opnd): Move memory operand out of set of 777 indirect operands. 778 7792005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 780 781 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes. 782 Add FLAG_STRICT to pa10 ftest opcode. 783 7842005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 785 786 * hppa.h (pa_opcodes): Remove lha entries. 787 7882005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 789 790 * hppa.h (FLAG_STRICT): Revise comment. 791 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants 792 before corresponding pa11 opcodes. Add strict pa10 register-immediate 793 entries for "fdc". 794 7952005-09-30 Catherine Moore <clm@cm00re.com> 796 797 * bfin.h: New file. 798 7992005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 800 801 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries. 802 8032005-09-06 Chao-ying Fu <fu@mips.com> 804 805 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H, 806 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New 807 define. 808 Document !, $, *, &, g, +t, +T operand formats for MT instructions. 809 (INSN_ASE_MASK): Update to include INSN_MT. 810 (INSN_MT): New define for MT ASE. 811 8122005-08-25 Chao-ying Fu <fu@mips.com> 813 814 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S, 815 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7, 816 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4, 817 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP, 818 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define. 819 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP 820 instructions. 821 (INSN_DSP): New define for DSP ASE. 822 8232005-08-18 Alan Modra <amodra@bigpond.net.au> 824 825 * a29k.h: Delete. 826 8272005-08-15 Daniel Jacobowitz <dan@codesourcery.com> 828 829 * ppc.h (PPC_OPCODE_E300): Define. 830 8312005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com> 832 833 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109. 834 8352005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 836 837 PR gas/336 838 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb 839 and pitlb. 840 8412005-07-27 Jan Beulich <jbeulich@novell.com> 842 843 * i386.h (i386_optab): Add comment to movd. Use LongMem for all 844 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers. 845 Add movq-s as 64-bit variants of movd-s. 846 8472005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 848 849 * hppa.h: Fix punctuation in comment. 850 851 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for 852 implicit space-register addressing. Set space-register bits on opcodes 853 using implicit space-register addressing. Add various missing pa20 854 long-immediate opcodes. Remove various opcodes using implicit 3-bit 855 space-register addressing. Use "fE" instead of "fe" in various 856 fstw opcodes. 857 8582005-07-18 Jan Beulich <jbeulich@novell.com> 859 860 * i386.h (i386_optab): Operands of aam and aad are unsigned. 861 8622007-07-15 H.J. Lu <hongjiu.lu@intel.com> 863 864 * i386.h (i386_optab): Support Intel VMX Instructions. 865 8662005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 867 868 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores. 869 8702005-07-05 Jan Beulich <jbeulich@novell.com> 871 872 * i386.h (i386_optab): Add new insns. 873 8742005-07-01 Nick Clifton <nickc@redhat.com> 875 876 * sparc.h: Add typedefs to structure declarations. 877 8782005-06-20 H.J. Lu <hongjiu.lu@intel.com> 879 880 PR 1013 881 * i386.h (i386_optab): Update comments for 64bit addressing on 882 mov. Allow 64bit addressing for mov and movq. 883 8842005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 885 886 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx, 887 respectively, in various floating-point load and store patterns. 888 8892005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 890 891 * hppa.h (FLAG_STRICT): Correct comment. 892 (pa_opcodes): Update load and store entries to allow both PA 1.X and 893 PA 2.0 mneumonics when equivalent. Entries with cache control 894 completers now require PA 1.1. Adjust whitespace. 895 8962005-05-19 Anton Blanchard <anton@samba.org> 897 898 * ppc.h (PPC_OPCODE_POWER5): Define. 899 9002005-05-10 Nick Clifton <nickc@redhat.com> 901 902 * Update the address and phone number of the FSF organization in 903 the GPL notices in the following files: 904 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h, 905 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h, 906 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h, 907 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h, 908 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h, 909 tic54x.h, tic80.h, v850.h, vax.h 910 9112005-05-09 Jan Beulich <jbeulich@novell.com> 912 913 * i386.h (i386_optab): Add ht and hnt. 914 9152005-04-18 Mark Kettenis <kettenis@gnu.org> 916 917 * i386.h: Insert hyphens into selected VIA PadLock extensions. 918 Add xcrypt-ctr. Provide aliases without hyphens. 919 9202005-04-13 H.J. Lu <hongjiu.lu@intel.com> 921 922 Moved from ../ChangeLog 923 924 2005-04-12 Paul Brook <paul@codesourcery.com> 925 * m88k.h: Rename psr macros to avoid conflicts. 926 927 2005-03-12 Zack Weinberg <zack@codesourcery.com> 928 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. 929 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, 930 and ARM_ARCH_V6ZKT2. 931 932 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com> 933 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4. 934 Remove redundant instruction types. 935 (struct argument): X_op - new field. 936 (struct cst4_entry): Remove. 937 (no_op_insn): Declare. 938 939 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com> 940 * crx.h (enum argtype): Rename types, remove unused types. 941 942 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com> 943 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'. 944 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE. 945 (enum operand_type): Rearrange operands, edit comments. 946 replace us<N> with ui<N> for unsigned immediate. 947 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped 948 displacements (respectively). 949 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index. 950 (instruction type): Add NO_TYPE_INS. 951 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR. 952 (operand_entry): New field - 'flags'. 953 (operand flags): New. 954 955 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com> 956 * crx.h (operand_type): Remove redundant types i3, i4, 957 i5, i8, i12. 958 Add new unsigned immediate types us3, us4, us5, us16. 959 9602005-04-12 Mark Kettenis <kettenis@gnu.org> 961 962 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and 963 adjust them accordingly. 964 9652005-04-01 Jan Beulich <jbeulich@novell.com> 966 967 * i386.h (i386_optab): Add rdtscp. 968 9692005-03-29 H.J. Lu <hongjiu.lu@intel.com> 970 971 * i386.h (i386_optab): Don't allow the `l' suffix for moving 972 between memory and segment register. Allow movq for moving between 973 general-purpose register and segment register. 974 9752005-02-09 Jan Beulich <jbeulich@novell.com> 976 977 PR gas/707 978 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and 979 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and 980 fnstsw. 981 9822006-02-07 Nathan Sidwell <nathan@codesourcery.com> 983 984 * m68k.h (m68008, m68ec030, m68882): Remove. 985 (m68k_mask): New. 986 (cpu_m68k, cpu_cf): New. 987 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407, 988 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants. 989 9902005-01-25 Alexandre Oliva <aoliva@redhat.com> 991 992 2004-11-10 Alexandre Oliva <aoliva@redhat.com> 993 * cgen.h (enum cgen_parse_operand_type): Add 994 CGEN_PARSE_OPERAND_SYMBOLIC. 995 9962005-01-21 Fred Fish <fnf@specifixinc.com> 997 998 * mips.h: Change INSN_ALIAS to INSN2_ALIAS. 999 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. 1000 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. 1001 10022005-01-19 Fred Fish <fnf@specifixinc.com> 1003 1004 * mips.h (struct mips_opcode): Add new pinfo2 member. 1005 (INSN_ALIAS): New define for opcode table entries that are 1006 specific instances of another entry, such as 'move' for an 'or' 1007 with a zero operand. 1008 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. 1009 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4. 1010 10112004-12-09 Ian Lance Taylor <ian@wasabisystems.com> 1012 1013 * mips.h (CPU_RM9000): Define. 1014 (OPCODE_IS_MEMBER): Handle CPU_RM9000. 1015 10162004-11-25 Jan Beulich <jbeulich@novell.com> 1017 1018 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves 1019 to/from test registers are illegal in 64-bit mode. Add missing 1020 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix 1021 (previously one had to explicitly encode a rex64 prefix). Re-enable 1022 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings 1023 support it there. Add cmpxchg16b as per Intel's 64-bit documentation. 1024 10252004-11-23 Jan Beulich <jbeulich@novell.com> 1026 1027 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are 1028 available only with SSE2. Change the MMX additions introduced by SSE 1029 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A 1030 instructions by their now designated identifier (since combining i686 1031 and 3DNow! does not really imply 3DNow!A). 1032 10332004-11-19 Alan Modra <amodra@bigpond.net.au> 1034 1035 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, 1036 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. 1037 10382004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com> 1039 Vineet Sharma <vineets@noida.hcltech.com> 1040 1041 * maxq.h: New file: Disassembly information for the maxq port. 1042 10432004-11-05 H.J. Lu <hongjiu.lu@intel.com> 1044 1045 * i386.h (i386_optab): Put back "movzb". 1046 10472004-11-04 Hans-Peter Nilsson <hp@axis.com> 1048 1049 * cris.h (enum cris_insn_version_usage): Tweak formatting and 1050 comments. Remove member cris_ver_sim. Add members 1051 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, 1052 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. 1053 (struct cris_support_reg, struct cris_cond15): New types. 1054 (cris_conds15): Declare. 1055 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) 1056 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) 1057 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. 1058 (NOP_Z_BITS): Define in terms of NOP_OPCODE. 1059 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and 1060 SIZE_FIELD_UNSIGNED. 1061 10622004-11-04 Jan Beulich <jbeulich@novell.com> 1063 1064 * i386.h (sldx_Suf): Remove. 1065 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. 1066 (q_FP): Define, implying no REX64. 1067 (x_FP, sl_FP): Imply FloatMF. 1068 (i386_optab): Split reg and mem forms of moving from segment registers 1069 so that the memory forms can ignore the 16-/32-bit operand size 1070 distinction. Adjust a few others for Intel mode. Remove *FP uses from 1071 all non-floating-point instructions. Unite 32- and 64-bit forms of 1072 movsx, movzx, and movd. Adjust floating point operations for the above 1073 changes to the *FP macros. Add DefaultSize to floating point control 1074 insns operating on larger memory ranges. Remove left over comments 1075 hinting at certain insns being Intel-syntax ones where the ones 1076 actually meant are already gone. 1077 10782004-10-07 Tomer Levi <Tomer.Levi@nsc.com> 1079 1080 * crx.h: Add COPS_REG_INS - Coprocessor Special register 1081 instruction type. 1082 10832004-09-30 Paul Brook <paul@codesourcery.com> 1084 1085 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. 1086 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. 1087 10882004-09-11 Theodore A. Roth <troth@openavr.org> 1089 1090 * avr.h: Add support for 1091 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. 1092 10932004-09-09 Segher Boessenkool <segher@kernel.crashing.org> 1094 1095 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. 1096 10972004-08-24 Dmitry Diky <diwil@spec.ru> 1098 1099 * msp430.h (msp430_opc): Add new instructions. 1100 (msp430_rcodes): Declare new instructions. 1101 (msp430_hcodes): Likewise.. 1102 11032004-08-13 Nick Clifton <nickc@redhat.com> 1104 1105 PR/301 1106 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX 1107 processors. 1108 11092004-08-30 Michal Ludvig <mludvig@suse.cz> 1110 1111 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. 1112 11132004-07-22 H.J. Lu <hongjiu.lu@intel.com> 1114 1115 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. 1116 11172004-07-21 Jan Beulich <jbeulich@novell.com> 1118 1119 * i386.h: Adjust instruction descriptions to better match the 1120 specification. 1121 11222004-07-16 Richard Earnshaw <rearnsha@arm.com> 1123 1124 * arm.h: Remove all old content. Replace with architecture defines 1125 from gas/config/tc-arm.c. 1126 11272004-07-09 Andreas Schwab <schwab@suse.de> 1128 1129 * m68k.h: Fix comment. 1130 11312004-07-07 Tomer Levi <Tomer.Levi@nsc.com> 1132 1133 * crx.h: New file. 1134 11352004-06-24 Alan Modra <amodra@bigpond.net.au> 1136 1137 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. 1138 11392004-05-24 Peter Barada <peter@the-baradas.com> 1140 1141 * m68k.h: Add 'size' to m68k_opcode. 1142 11432004-05-05 Peter Barada <peter@the-baradas.com> 1144 1145 * m68k.h: Switch from ColdFire chip name to core variant. 1146 11472004-04-22 Peter Barada <peter@the-baradas.com> 1148 1149 * m68k.h: Add mcfmac/mcfemac definitions. Update operand 1150 descriptions for new EMAC cases. 1151 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly 1152 handle Motorola MAC syntax. 1153 Allow disassembly of ColdFire V4e object files. 1154 11552004-03-16 Alan Modra <amodra@bigpond.net.au> 1156 1157 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. 1158 11592004-03-12 Jakub Jelinek <jakub@redhat.com> 1160 1161 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. 1162 11632004-03-12 Michal Ludvig <mludvig@suse.cz> 1164 1165 * i386.h (i386_optab): Added xstore as an alias for xstorerng. 1166 11672004-03-12 Michal Ludvig <mludvig@suse.cz> 1168 1169 * i386.h (i386_optab): Added xstore/xcrypt insns. 1170 11712004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> 1172 1173 * h8300.h (32bit ldc/stc): Add relaxing support. 1174 11752004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> 1176 1177 * h8300.h (BITOP): Pass MEMRELAX flag. 1178 11792004-01-09 Anil Paranjpe <anilp1@KPITCummins.com> 1180 1181 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32 1182 except for the H8S. 1183 1184For older changes see ChangeLog-9103 1185 1186Local Variables: 1187mode: change-log 1188left-margin: 8 1189fill-column: 74 1190version-control: never 1191End: 1192