1/* Target-dependent code for Renesas Super-H, for GDB. 2 3 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 4 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011 5 Free Software Foundation, Inc. 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 21 22/* Contributed by Steve Chamberlain 23 sac@cygnus.com. */ 24 25#include "defs.h" 26#include "frame.h" 27#include "frame-base.h" 28#include "frame-unwind.h" 29#include "dwarf2-frame.h" 30#include "symtab.h" 31#include "gdbtypes.h" 32#include "gdbcmd.h" 33#include "gdbcore.h" 34#include "value.h" 35#include "dis-asm.h" 36#include "inferior.h" 37#include "gdb_string.h" 38#include "gdb_assert.h" 39#include "arch-utils.h" 40#include "floatformat.h" 41#include "regcache.h" 42#include "doublest.h" 43#include "osabi.h" 44#include "reggroups.h" 45#include "regset.h" 46 47#include "sh-tdep.h" 48 49#include "elf-bfd.h" 50#include "solib-svr4.h" 51 52/* sh flags */ 53#include "elf/sh.h" 54#include "dwarf2.h" 55/* registers numbers shared with the simulator. */ 56#include "gdb/sim-sh.h" 57 58/* List of "set sh ..." and "show sh ..." commands. */ 59static struct cmd_list_element *setshcmdlist = NULL; 60static struct cmd_list_element *showshcmdlist = NULL; 61 62static const char sh_cc_gcc[] = "gcc"; 63static const char sh_cc_renesas[] = "renesas"; 64static const char *sh_cc_enum[] = { 65 sh_cc_gcc, 66 sh_cc_renesas, 67 NULL 68}; 69 70static const char *sh_active_calling_convention = sh_cc_gcc; 71 72static void (*sh_show_regs) (struct frame_info *); 73 74#define SH_NUM_REGS 67 75 76struct sh_frame_cache 77{ 78 /* Base address. */ 79 CORE_ADDR base; 80 LONGEST sp_offset; 81 CORE_ADDR pc; 82 83 /* Flag showing that a frame has been created in the prologue code. */ 84 int uses_fp; 85 86 /* Saved registers. */ 87 CORE_ADDR saved_regs[SH_NUM_REGS]; 88 CORE_ADDR saved_sp; 89}; 90 91static int 92sh_is_renesas_calling_convention (struct type *func_type) 93{ 94 return ((func_type 95 && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh) 96 || sh_active_calling_convention == sh_cc_renesas); 97} 98 99static const char * 100sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr) 101{ 102 static char *register_names[] = { 103 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 104 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 105 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 106 "", "", 107 "", "", "", "", "", "", "", "", 108 "", "", "", "", "", "", "", "", 109 "", "", 110 "", "", "", "", "", "", "", "", 111 "", "", "", "", "", "", "", "", 112 "", "", "", "", "", "", "", "", 113 }; 114 if (reg_nr < 0) 115 return NULL; 116 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 117 return NULL; 118 return register_names[reg_nr]; 119} 120 121static const char * 122sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr) 123{ 124 static char *register_names[] = { 125 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 126 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 127 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 128 "", "", 129 "", "", "", "", "", "", "", "", 130 "", "", "", "", "", "", "", "", 131 "ssr", "spc", 132 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", 133 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1" 134 "", "", "", "", "", "", "", "", 135 }; 136 if (reg_nr < 0) 137 return NULL; 138 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 139 return NULL; 140 return register_names[reg_nr]; 141} 142 143static const char * 144sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr) 145{ 146 static char *register_names[] = { 147 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 148 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 149 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 150 "fpul", "fpscr", 151 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", 152 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", 153 "ssr", "spc", 154 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", 155 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", 156 "", "", "", "", "", "", "", "", 157 }; 158 if (reg_nr < 0) 159 return NULL; 160 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 161 return NULL; 162 return register_names[reg_nr]; 163} 164 165static const char * 166sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr) 167{ 168 static char *register_names[] = { 169 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 170 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 171 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 172 "fpul", "fpscr", 173 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", 174 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", 175 "", "", 176 "", "", "", "", "", "", "", "", 177 "", "", "", "", "", "", "", "", 178 "", "", "", "", "", "", "", "", 179 }; 180 if (reg_nr < 0) 181 return NULL; 182 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 183 return NULL; 184 return register_names[reg_nr]; 185} 186 187static const char * 188sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr) 189{ 190 static char *register_names[] = { 191 /* general registers 0-15 */ 192 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 193 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 194 /* 16 - 22 */ 195 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 196 /* 23, 24 */ 197 "fpul", "fpscr", 198 /* floating point registers 25 - 40 */ 199 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", 200 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", 201 /* 41, 42 */ 202 "", "", 203 /* 43 - 62. Banked registers. The bank number used is determined by 204 the bank register (63). */ 205 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", 206 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", 207 "machb", "ivnb", "prb", "gbrb", "maclb", 208 /* 63: register bank number, not a real register but used to 209 communicate the register bank currently get/set. This register 210 is hidden to the user, who manipulates it using the pseudo 211 register called "bank" (67). See below. */ 212 "", 213 /* 64 - 66 */ 214 "ibcr", "ibnr", "tbr", 215 /* 67: register bank number, the user visible pseudo register. */ 216 "bank", 217 /* double precision (pseudo) 68 - 75 */ 218 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", 219 }; 220 if (reg_nr < 0) 221 return NULL; 222 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 223 return NULL; 224 return register_names[reg_nr]; 225} 226 227static const char * 228sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) 229{ 230 static char *register_names[] = { 231 /* general registers 0-15 */ 232 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 233 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 234 /* 16 - 22 */ 235 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 236 /* 23, 24 */ 237 "", "", 238 /* floating point registers 25 - 40 */ 239 "", "", "", "", "", "", "", "", 240 "", "", "", "", "", "", "", "", 241 /* 41, 42 */ 242 "", "", 243 /* 43 - 62. Banked registers. The bank number used is determined by 244 the bank register (63). */ 245 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", 246 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", 247 "machb", "ivnb", "prb", "gbrb", "maclb", 248 /* 63: register bank number, not a real register but used to 249 communicate the register bank currently get/set. This register 250 is hidden to the user, who manipulates it using the pseudo 251 register called "bank" (67). See below. */ 252 "", 253 /* 64 - 66 */ 254 "ibcr", "ibnr", "tbr", 255 /* 67: register bank number, the user visible pseudo register. */ 256 "bank", 257 /* double precision (pseudo) 68 - 75 */ 258 "", "", "", "", "", "", "", "", 259 }; 260 if (reg_nr < 0) 261 return NULL; 262 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 263 return NULL; 264 return register_names[reg_nr]; 265} 266 267static const char * 268sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) 269{ 270 static char *register_names[] = { 271 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 272 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 273 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 274 "", "dsr", 275 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", 276 "y0", "y1", "", "", "", "", "", "mod", 277 "", "", 278 "rs", "re", "", "", "", "", "", "", 279 "", "", "", "", "", "", "", "", 280 "", "", "", "", "", "", "", "", 281 }; 282 if (reg_nr < 0) 283 return NULL; 284 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 285 return NULL; 286 return register_names[reg_nr]; 287} 288 289static const char * 290sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) 291{ 292 static char *register_names[] = { 293 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 294 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 295 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 296 "", "dsr", 297 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", 298 "y0", "y1", "", "", "", "", "", "mod", 299 "ssr", "spc", 300 "rs", "re", "", "", "", "", "", "", 301 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", 302 "", "", "", "", "", "", "", "", 303 "", "", "", "", "", "", "", "", 304 }; 305 if (reg_nr < 0) 306 return NULL; 307 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 308 return NULL; 309 return register_names[reg_nr]; 310} 311 312static const char * 313sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr) 314{ 315 static char *register_names[] = { 316 /* general registers 0-15 */ 317 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 318 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 319 /* 16 - 22 */ 320 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 321 /* 23, 24 */ 322 "fpul", "fpscr", 323 /* floating point registers 25 - 40 */ 324 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", 325 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", 326 /* 41, 42 */ 327 "ssr", "spc", 328 /* bank 0 43 - 50 */ 329 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", 330 /* bank 1 51 - 58 */ 331 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", 332 "", "", "", "", "", "", "", "", 333 /* pseudo bank register. */ 334 "", 335 /* double precision (pseudo) 59 - 66 */ 336 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", 337 /* vectors (pseudo) 67 - 70 */ 338 "fv0", "fv4", "fv8", "fv12", 339 /* FIXME: missing XF 71 - 86 */ 340 /* FIXME: missing XD 87 - 94 */ 341 }; 342 if (reg_nr < 0) 343 return NULL; 344 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 345 return NULL; 346 return register_names[reg_nr]; 347} 348 349static const char * 350sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) 351{ 352 static char *register_names[] = { 353 /* general registers 0-15 */ 354 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 355 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 356 /* 16 - 22 */ 357 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 358 /* 23, 24 */ 359 "", "", 360 /* floating point registers 25 - 40 -- not for nofpu target */ 361 "", "", "", "", "", "", "", "", 362 "", "", "", "", "", "", "", "", 363 /* 41, 42 */ 364 "ssr", "spc", 365 /* bank 0 43 - 50 */ 366 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", 367 /* bank 1 51 - 58 */ 368 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", 369 "", "", "", "", "", "", "", "", 370 /* pseudo bank register. */ 371 "", 372 /* double precision (pseudo) 59 - 66 -- not for nofpu target */ 373 "", "", "", "", "", "", "", "", 374 /* vectors (pseudo) 67 - 70 -- not for nofpu target */ 375 "", "", "", "", 376 }; 377 if (reg_nr < 0) 378 return NULL; 379 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 380 return NULL; 381 return register_names[reg_nr]; 382} 383 384static const char * 385sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) 386{ 387 static char *register_names[] = { 388 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 389 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 390 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 391 "", "dsr", 392 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", 393 "y0", "y1", "", "", "", "", "", "mod", 394 "ssr", "spc", 395 "rs", "re", "", "", "", "", "", "", 396 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", 397 "", "", "", "", "", "", "", "", 398 "", "", "", "", "", "", "", "", 399 }; 400 if (reg_nr < 0) 401 return NULL; 402 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 403 return NULL; 404 return register_names[reg_nr]; 405} 406 407static const unsigned char * 408sh_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) 409{ 410 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes. */ 411 static unsigned char breakpoint[] = { 0xc3, 0xc3 }; 412 413 /* For remote stub targets, trapa #20 is used. */ 414 if (strcmp (target_shortname, "remote") == 0) 415 { 416 static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 }; 417 static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 }; 418 419 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 420 { 421 *lenptr = sizeof (big_remote_breakpoint); 422 return big_remote_breakpoint; 423 } 424 else 425 { 426 *lenptr = sizeof (little_remote_breakpoint); 427 return little_remote_breakpoint; 428 } 429 } 430 431 *lenptr = sizeof (breakpoint); 432 return breakpoint; 433} 434 435/* Prologue looks like 436 mov.l r14,@-r15 437 sts.l pr,@-r15 438 mov.l <regs>,@-r15 439 sub <room_for_loca_vars>,r15 440 mov r15,r14 441 442 Actually it can be more complicated than this but that's it, basically. */ 443 444#define GET_SOURCE_REG(x) (((x) >> 4) & 0xf) 445#define GET_TARGET_REG(x) (((x) >> 8) & 0xf) 446 447/* JSR @Rm 0100mmmm00001011 */ 448#define IS_JSR(x) (((x) & 0xf0ff) == 0x400b) 449 450/* STS.L PR,@-r15 0100111100100010 451 r15-4-->r15, PR-->(r15) */ 452#define IS_STS(x) ((x) == 0x4f22) 453 454/* STS.L MACL,@-r15 0100111100010010 455 r15-4-->r15, MACL-->(r15) */ 456#define IS_MACL_STS(x) ((x) == 0x4f12) 457 458/* MOV.L Rm,@-r15 00101111mmmm0110 459 r15-4-->r15, Rm-->(R15) */ 460#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) 461 462/* MOV r15,r14 0110111011110011 463 r15-->r14 */ 464#define IS_MOV_SP_FP(x) ((x) == 0x6ef3) 465 466/* ADD #imm,r15 01111111iiiiiiii 467 r15+imm-->r15 */ 468#define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00) 469 470#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) 471#define IS_SHLL_R3(x) ((x) == 0x4300) 472 473/* ADD r3,r15 0011111100111100 474 r15+r3-->r15 */ 475#define IS_ADD_R3SP(x) ((x) == 0x3f3c) 476 477/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011 478 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011 479 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */ 480/* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to 481 make this entirely clear. */ 482/* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */ 483#define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b) 484 485/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */ 486#define IS_MOV_ARG_TO_REG(x) \ 487 (((x) & 0xf00f) == 0x6003 && \ 488 ((x) & 0x00f0) >= 0x0040 && \ 489 ((x) & 0x00f0) <= 0x0070) 490/* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */ 491#define IS_MOV_ARG_TO_IND_R14(x) \ 492 (((x) & 0xff0f) == 0x2e02 && \ 493 ((x) & 0x00f0) >= 0x0040 && \ 494 ((x) & 0x00f0) <= 0x0070) 495/* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */ 496#define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \ 497 (((x) & 0xff00) == 0x1e00 && \ 498 ((x) & 0x00f0) >= 0x0040 && \ 499 ((x) & 0x00f0) <= 0x0070) 500 501/* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */ 502#define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000) 503/* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */ 504#define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000) 505/* MOVI20 #imm20,Rn 0000nnnniiii0000 */ 506#define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000) 507/* SUB Rn,R15 00111111nnnn1000 */ 508#define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08) 509 510#define FPSCR_SZ (1 << 20) 511 512/* The following instructions are used for epilogue testing. */ 513#define IS_RESTORE_FP(x) ((x) == 0x6ef6) 514#define IS_RTS(x) ((x) == 0x000b) 515#define IS_LDS(x) ((x) == 0x4f26) 516#define IS_MACL_LDS(x) ((x) == 0x4f16) 517#define IS_MOV_FP_SP(x) ((x) == 0x6fe3) 518#define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c) 519#define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00) 520 521static CORE_ADDR 522sh_analyze_prologue (struct gdbarch *gdbarch, 523 CORE_ADDR pc, CORE_ADDR current_pc, 524 struct sh_frame_cache *cache, 525 struct frame_info *fpscr_frame) 526{ 527 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 528 ULONGEST inst; 529 CORE_ADDR opc; 530 ULONGEST fpscr = 0; 531 int have_fpscr = (fpscr_frame == NULL); 532 int offset; 533 int sav_offset = 0; 534 int r3_val = 0; 535 int reg, sav_reg = -1; 536 537 if (pc >= current_pc) 538 return current_pc; 539 540 cache->uses_fp = 0; 541 for (opc = pc + (2 * 28); pc < opc; pc += 2) 542 { 543 inst = read_memory_unsigned_integer (pc, 2, byte_order); 544 /* See where the registers will be saved to. */ 545 if (IS_PUSH (inst)) 546 { 547 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset; 548 cache->sp_offset += 4; 549 } 550 else if (IS_STS (inst)) 551 { 552 cache->saved_regs[PR_REGNUM] = cache->sp_offset; 553 cache->sp_offset += 4; 554 } 555 else if (IS_MACL_STS (inst)) 556 { 557 cache->saved_regs[MACL_REGNUM] = cache->sp_offset; 558 cache->sp_offset += 4; 559 } 560 else if (IS_MOV_R3 (inst)) 561 { 562 r3_val = ((inst & 0xff) ^ 0x80) - 0x80; 563 } 564 else if (IS_SHLL_R3 (inst)) 565 { 566 r3_val <<= 1; 567 } 568 else if (IS_ADD_R3SP (inst)) 569 { 570 cache->sp_offset += -r3_val; 571 } 572 else if (IS_ADD_IMM_SP (inst)) 573 { 574 offset = ((inst & 0xff) ^ 0x80) - 0x80; 575 cache->sp_offset -= offset; 576 } 577 else if (IS_MOVW_PCREL_TO_REG (inst)) 578 { 579 if (sav_reg < 0) 580 { 581 reg = GET_TARGET_REG (inst); 582 if (reg < 14) 583 { 584 sav_reg = reg; 585 offset = (inst & 0xff) << 1; 586 sav_offset = 587 read_memory_integer ((pc + 4) + offset, 2, byte_order); 588 } 589 } 590 } 591 else if (IS_MOVL_PCREL_TO_REG (inst)) 592 { 593 if (sav_reg < 0) 594 { 595 reg = GET_TARGET_REG (inst); 596 if (reg < 14) 597 { 598 sav_reg = reg; 599 offset = (inst & 0xff) << 2; 600 sav_offset = 601 read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 602 4, byte_order); 603 } 604 } 605 } 606 else if (IS_MOVI20 (inst)) 607 { 608 if (sav_reg < 0) 609 { 610 reg = GET_TARGET_REG (inst); 611 if (reg < 14) 612 { 613 sav_reg = reg; 614 sav_offset = GET_SOURCE_REG (inst) << 16; 615 /* MOVI20 is a 32 bit instruction! */ 616 pc += 2; 617 sav_offset 618 |= read_memory_unsigned_integer (pc, 2, byte_order); 619 /* Now sav_offset contains an unsigned 20 bit value. 620 It must still get sign extended. */ 621 if (sav_offset & 0x00080000) 622 sav_offset |= 0xfff00000; 623 } 624 } 625 } 626 else if (IS_SUB_REG_FROM_SP (inst)) 627 { 628 reg = GET_SOURCE_REG (inst); 629 if (sav_reg > 0 && reg == sav_reg) 630 { 631 sav_reg = -1; 632 } 633 cache->sp_offset += sav_offset; 634 } 635 else if (IS_FPUSH (inst)) 636 { 637 if (!have_fpscr) 638 { 639 fpscr = get_frame_register_unsigned (fpscr_frame, FPSCR_REGNUM); 640 have_fpscr = 1; 641 } 642 643 if (fpscr & FPSCR_SZ) 644 { 645 cache->sp_offset += 8; 646 } 647 else 648 { 649 cache->sp_offset += 4; 650 } 651 } 652 else if (IS_MOV_SP_FP (inst)) 653 { 654 cache->uses_fp = 1; 655 /* At this point, only allow argument register moves to other 656 registers or argument register moves to @(X,fp) which are 657 moving the register arguments onto the stack area allocated 658 by a former add somenumber to SP call. Don't allow moving 659 to an fp indirect address above fp + cache->sp_offset. */ 660 pc += 2; 661 for (opc = pc + 12; pc < opc; pc += 2) 662 { 663 inst = read_memory_integer (pc, 2, byte_order); 664 if (IS_MOV_ARG_TO_IND_R14 (inst)) 665 { 666 reg = GET_SOURCE_REG (inst); 667 if (cache->sp_offset > 0) 668 cache->saved_regs[reg] = cache->sp_offset; 669 } 670 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst)) 671 { 672 reg = GET_SOURCE_REG (inst); 673 offset = (inst & 0xf) * 4; 674 if (cache->sp_offset > offset) 675 cache->saved_regs[reg] = cache->sp_offset - offset; 676 } 677 else if (IS_MOV_ARG_TO_REG (inst)) 678 continue; 679 else 680 break; 681 } 682 break; 683 } 684 else if (IS_JSR (inst)) 685 { 686 /* We have found a jsr that has been scheduled into the prologue. 687 If we continue the scan and return a pc someplace after this, 688 then setting a breakpoint on this function will cause it to 689 appear to be called after the function it is calling via the 690 jsr, which will be very confusing. Most likely the next 691 instruction is going to be IS_MOV_SP_FP in the delay slot. If 692 so, note that before returning the current pc. */ 693 inst = read_memory_integer (pc + 2, 2, byte_order); 694 if (IS_MOV_SP_FP (inst)) 695 cache->uses_fp = 1; 696 break; 697 } 698#if 0 /* This used to just stop when it found an instruction 699 that was not considered part of the prologue. Now, 700 we just keep going looking for likely 701 instructions. */ 702 else 703 break; 704#endif 705 } 706 707 return pc; 708} 709 710/* Skip any prologue before the guts of a function. */ 711 712/* Skip the prologue using the debug information. If this fails we'll 713 fall back on the 'guess' method below. */ 714static CORE_ADDR 715after_prologue (CORE_ADDR pc) 716{ 717 struct symtab_and_line sal; 718 CORE_ADDR func_addr, func_end; 719 720 /* If we can not find the symbol in the partial symbol table, then 721 there is no hope we can determine the function's start address 722 with this code. */ 723 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 724 return 0; 725 726 /* Get the line associated with FUNC_ADDR. */ 727 sal = find_pc_line (func_addr, 0); 728 729 /* There are only two cases to consider. First, the end of the source line 730 is within the function bounds. In that case we return the end of the 731 source line. Second is the end of the source line extends beyond the 732 bounds of the current function. We need to use the slow code to 733 examine instructions in that case. */ 734 if (sal.end < func_end) 735 return sal.end; 736 else 737 return 0; 738} 739 740static CORE_ADDR 741sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) 742{ 743 CORE_ADDR pc; 744 struct sh_frame_cache cache; 745 746 /* See if we can determine the end of the prologue via the symbol table. 747 If so, then return either PC, or the PC after the prologue, whichever 748 is greater. */ 749 pc = after_prologue (start_pc); 750 751 /* If after_prologue returned a useful address, then use it. Else 752 fall back on the instruction skipping code. */ 753 if (pc) 754 return max (pc, start_pc); 755 756 cache.sp_offset = -4; 757 pc = sh_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache, NULL); 758 if (!cache.uses_fp) 759 return start_pc; 760 761 return pc; 762} 763 764/* The ABI says: 765 766 Aggregate types not bigger than 8 bytes that have the same size and 767 alignment as one of the integer scalar types are returned in the 768 same registers as the integer type they match. 769 770 For example, a 2-byte aligned structure with size 2 bytes has the 771 same size and alignment as a short int, and will be returned in R0. 772 A 4-byte aligned structure with size 8 bytes has the same size and 773 alignment as a long long int, and will be returned in R0 and R1. 774 775 When an aggregate type is returned in R0 and R1, R0 contains the 776 first four bytes of the aggregate, and R1 contains the 777 remainder. If the size of the aggregate type is not a multiple of 4 778 bytes, the aggregate is tail-padded up to a multiple of 4 779 bytes. The value of the padding is undefined. For little-endian 780 targets the padding will appear at the most significant end of the 781 last element, for big-endian targets the padding appears at the 782 least significant end of the last element. 783 784 All other aggregate types are returned by address. The caller 785 function passes the address of an area large enough to hold the 786 aggregate value in R2. The called function stores the result in 787 this location. 788 789 To reiterate, structs smaller than 8 bytes could also be returned 790 in memory, if they don't pass the "same size and alignment as an 791 integer type" rule. 792 793 For example, in 794 795 struct s { char c[3]; } wibble; 796 struct s foo(void) { return wibble; } 797 798 the return value from foo() will be in memory, not 799 in R0, because there is no 3-byte integer type. 800 801 Similarly, in 802 803 struct s { char c[2]; } wibble; 804 struct s foo(void) { return wibble; } 805 806 because a struct containing two chars has alignment 1, that matches 807 type char, but size 2, that matches type short. There's no integer 808 type that has alignment 1 and size 2, so the struct is returned in 809 memory. */ 810 811static int 812sh_use_struct_convention (int renesas_abi, struct type *type) 813{ 814 int len = TYPE_LENGTH (type); 815 int nelem = TYPE_NFIELDS (type); 816 817 /* The Renesas ABI returns aggregate types always on stack. */ 818 if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT 819 || TYPE_CODE (type) == TYPE_CODE_UNION)) 820 return 1; 821 822 /* Non-power of 2 length types and types bigger than 8 bytes (which don't 823 fit in two registers anyway) use struct convention. */ 824 if (len != 1 && len != 2 && len != 4 && len != 8) 825 return 1; 826 827 /* Scalar types and aggregate types with exactly one field are aligned 828 by definition. They are returned in registers. */ 829 if (nelem <= 1) 830 return 0; 831 832 /* If the first field in the aggregate has the same length as the entire 833 aggregate type, the type is returned in registers. */ 834 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len) 835 return 0; 836 837 /* If the size of the aggregate is 8 bytes and the first field is 838 of size 4 bytes its alignment is equal to long long's alignment, 839 so it's returned in registers. */ 840 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4) 841 return 0; 842 843 /* Otherwise use struct convention. */ 844 return 1; 845} 846 847static int 848sh_use_struct_convention_nofpu (int renesas_abi, struct type *type) 849{ 850 /* The Renesas ABI returns long longs/doubles etc. always on stack. */ 851 if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8) 852 return 1; 853 return sh_use_struct_convention (renesas_abi, type); 854} 855 856static CORE_ADDR 857sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp) 858{ 859 return sp & ~3; 860} 861 862/* Function: push_dummy_call (formerly push_arguments) 863 Setup the function arguments for calling a function in the inferior. 864 865 On the Renesas SH architecture, there are four registers (R4 to R7) 866 which are dedicated for passing function arguments. Up to the first 867 four arguments (depending on size) may go into these registers. 868 The rest go on the stack. 869 870 MVS: Except on SH variants that have floating point registers. 871 In that case, float and double arguments are passed in the same 872 manner, but using FP registers instead of GP registers. 873 874 Arguments that are smaller than 4 bytes will still take up a whole 875 register or a whole 32-bit word on the stack, and will be 876 right-justified in the register or the stack word. This includes 877 chars, shorts, and small aggregate types. 878 879 Arguments that are larger than 4 bytes may be split between two or 880 more registers. If there are not enough registers free, an argument 881 may be passed partly in a register (or registers), and partly on the 882 stack. This includes doubles, long longs, and larger aggregates. 883 As far as I know, there is no upper limit to the size of aggregates 884 that will be passed in this way; in other words, the convention of 885 passing a pointer to a large aggregate instead of a copy is not used. 886 887 MVS: The above appears to be true for the SH variants that do not 888 have an FPU, however those that have an FPU appear to copy the 889 aggregate argument onto the stack (and not place it in registers) 890 if it is larger than 16 bytes (four GP registers). 891 892 An exceptional case exists for struct arguments (and possibly other 893 aggregates such as arrays) if the size is larger than 4 bytes but 894 not a multiple of 4 bytes. In this case the argument is never split 895 between the registers and the stack, but instead is copied in its 896 entirety onto the stack, AND also copied into as many registers as 897 there is room for. In other words, space in registers permitting, 898 two copies of the same argument are passed in. As far as I can tell, 899 only the one on the stack is used, although that may be a function 900 of the level of compiler optimization. I suspect this is a compiler 901 bug. Arguments of these odd sizes are left-justified within the 902 word (as opposed to arguments smaller than 4 bytes, which are 903 right-justified). 904 905 If the function is to return an aggregate type such as a struct, it 906 is either returned in the normal return value register R0 (if its 907 size is no greater than one byte), or else the caller must allocate 908 space into which the callee will copy the return value (if the size 909 is greater than one byte). In this case, a pointer to the return 910 value location is passed into the callee in register R2, which does 911 not displace any of the other arguments passed in via registers R4 912 to R7. */ 913 914/* Helper function to justify value in register according to endianess. */ 915static char * 916sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len) 917{ 918 static char valbuf[4]; 919 920 memset (valbuf, 0, sizeof (valbuf)); 921 if (len < 4) 922 { 923 /* value gets right-justified in the register or stack word. */ 924 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 925 memcpy (valbuf + (4 - len), (char *) value_contents (val), len); 926 else 927 memcpy (valbuf, (char *) value_contents (val), len); 928 return valbuf; 929 } 930 return (char *) value_contents (val); 931} 932 933/* Helper function to eval number of bytes to allocate on stack. */ 934static CORE_ADDR 935sh_stack_allocsize (int nargs, struct value **args) 936{ 937 int stack_alloc = 0; 938 while (nargs-- > 0) 939 stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3); 940 return stack_alloc; 941} 942 943/* Helper functions for getting the float arguments right. Registers usage 944 depends on the ABI and the endianess. The comments should enlighten how 945 it's intended to work. */ 946 947/* This array stores which of the float arg registers are already in use. */ 948static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1]; 949 950/* This function just resets the above array to "no reg used so far". */ 951static void 952sh_init_flt_argreg (void) 953{ 954 memset (flt_argreg_array, 0, sizeof flt_argreg_array); 955} 956 957/* This function returns the next register to use for float arg passing. 958 It returns either a valid value between FLOAT_ARG0_REGNUM and 959 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns 960 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available. 961 962 Note that register number 0 in flt_argreg_array corresponds with the 963 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is 964 29) the parity of the register number is preserved, which is important 965 for the double register passing test (see the "argreg & 1" test below). */ 966static int 967sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type) 968{ 969 int argreg; 970 971 /* First search for the next free register. */ 972 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM; 973 ++argreg) 974 if (!flt_argreg_array[argreg]) 975 break; 976 977 /* No register left? */ 978 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) 979 return FLOAT_ARGLAST_REGNUM + 1; 980 981 if (len == 8) 982 { 983 /* Doubles are always starting in a even register number. */ 984 if (argreg & 1) 985 { 986 /* In gcc ABI, the skipped register is lost for further argument 987 passing now. Not so in Renesas ABI. */ 988 if (!sh_is_renesas_calling_convention (func_type)) 989 flt_argreg_array[argreg] = 1; 990 991 ++argreg; 992 993 /* No register left? */ 994 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) 995 return FLOAT_ARGLAST_REGNUM + 1; 996 } 997 /* Also mark the next register as used. */ 998 flt_argreg_array[argreg + 1] = 1; 999 } 1000 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE 1001 && !sh_is_renesas_calling_convention (func_type)) 1002 { 1003 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */ 1004 if (!flt_argreg_array[argreg + 1]) 1005 ++argreg; 1006 } 1007 flt_argreg_array[argreg] = 1; 1008 return FLOAT_ARG0_REGNUM + argreg; 1009} 1010 1011/* Helper function which figures out, if a type is treated like a float type. 1012 1013 The FPU ABIs have a special way how to treat types as float types. 1014 Structures with exactly one member, which is of type float or double, are 1015 treated exactly as the base types float or double: 1016 1017 struct sf { 1018 float f; 1019 }; 1020 1021 struct sd { 1022 double d; 1023 }; 1024 1025 are handled the same way as just 1026 1027 float f; 1028 1029 double d; 1030 1031 As a result, arguments of these struct types are pushed into floating point 1032 registers exactly as floats or doubles, using the same decision algorithm. 1033 1034 The same is valid if these types are used as function return types. The 1035 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1 1036 or even using struct convention as it is for other structs. */ 1037 1038static int 1039sh_treat_as_flt_p (struct type *type) 1040{ 1041 int len = TYPE_LENGTH (type); 1042 1043 /* Ordinary float types are obviously treated as float. */ 1044 if (TYPE_CODE (type) == TYPE_CODE_FLT) 1045 return 1; 1046 /* Otherwise non-struct types are not treated as float. */ 1047 if (TYPE_CODE (type) != TYPE_CODE_STRUCT) 1048 return 0; 1049 /* Otherwise structs with more than one memeber are not treated as float. */ 1050 if (TYPE_NFIELDS (type) != 1) 1051 return 0; 1052 /* Otherwise if the type of that member is float, the whole type is 1053 treated as float. */ 1054 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT) 1055 return 1; 1056 /* Otherwise it's not treated as float. */ 1057 return 0; 1058} 1059 1060static CORE_ADDR 1061sh_push_dummy_call_fpu (struct gdbarch *gdbarch, 1062 struct value *function, 1063 struct regcache *regcache, 1064 CORE_ADDR bp_addr, int nargs, 1065 struct value **args, 1066 CORE_ADDR sp, int struct_return, 1067 CORE_ADDR struct_addr) 1068{ 1069 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1070 int stack_offset = 0; 1071 int argreg = ARG0_REGNUM; 1072 int flt_argreg = 0; 1073 int argnum; 1074 struct type *func_type = value_type (function); 1075 struct type *type; 1076 CORE_ADDR regval; 1077 char *val; 1078 int len, reg_size = 0; 1079 int pass_on_stack = 0; 1080 int treat_as_flt; 1081 int last_reg_arg = INT_MAX; 1082 1083 /* The Renesas ABI expects all varargs arguments, plus the last 1084 non-vararg argument to be on the stack, no matter how many 1085 registers have been used so far. */ 1086 if (sh_is_renesas_calling_convention (func_type) 1087 && TYPE_VARARGS (func_type)) 1088 last_reg_arg = TYPE_NFIELDS (func_type) - 2; 1089 1090 /* First force sp to a 4-byte alignment. */ 1091 sp = sh_frame_align (gdbarch, sp); 1092 1093 /* Make room on stack for args. */ 1094 sp -= sh_stack_allocsize (nargs, args); 1095 1096 /* Initialize float argument mechanism. */ 1097 sh_init_flt_argreg (); 1098 1099 /* Now load as many as possible of the first arguments into 1100 registers, and push the rest onto the stack. There are 16 bytes 1101 in four registers available. Loop thru args from first to last. */ 1102 for (argnum = 0; argnum < nargs; argnum++) 1103 { 1104 type = value_type (args[argnum]); 1105 len = TYPE_LENGTH (type); 1106 val = sh_justify_value_in_reg (gdbarch, args[argnum], len); 1107 1108 /* Some decisions have to be made how various types are handled. 1109 This also differs in different ABIs. */ 1110 pass_on_stack = 0; 1111 1112 /* Find out the next register to use for a floating point value. */ 1113 treat_as_flt = sh_treat_as_flt_p (type); 1114 if (treat_as_flt) 1115 flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type); 1116 /* In Renesas ABI, long longs and aggregate types are always passed 1117 on stack. */ 1118 else if (sh_is_renesas_calling_convention (func_type) 1119 && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8) 1120 || TYPE_CODE (type) == TYPE_CODE_STRUCT 1121 || TYPE_CODE (type) == TYPE_CODE_UNION)) 1122 pass_on_stack = 1; 1123 /* In contrast to non-FPU CPUs, arguments are never split between 1124 registers and stack. If an argument doesn't fit in the remaining 1125 registers it's always pushed entirely on the stack. */ 1126 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4)) 1127 pass_on_stack = 1; 1128 1129 while (len > 0) 1130 { 1131 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM) 1132 || (!treat_as_flt && (argreg > ARGLAST_REGNUM 1133 || pass_on_stack)) 1134 || argnum > last_reg_arg) 1135 { 1136 /* The data goes entirely on the stack, 4-byte aligned. */ 1137 reg_size = (len + 3) & ~3; 1138 write_memory (sp + stack_offset, val, reg_size); 1139 stack_offset += reg_size; 1140 } 1141 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM) 1142 { 1143 /* Argument goes in a float argument register. */ 1144 reg_size = register_size (gdbarch, flt_argreg); 1145 regval = extract_unsigned_integer (val, reg_size, byte_order); 1146 /* In little endian mode, float types taking two registers 1147 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must 1148 be stored swapped in the argument registers. The below 1149 code first writes the first 32 bits in the next but one 1150 register, increments the val and len values accordingly 1151 and then proceeds as normal by writing the second 32 bits 1152 into the next register. */ 1153 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE 1154 && TYPE_LENGTH (type) == 2 * reg_size) 1155 { 1156 regcache_cooked_write_unsigned (regcache, flt_argreg + 1, 1157 regval); 1158 val += reg_size; 1159 len -= reg_size; 1160 regval = extract_unsigned_integer (val, reg_size, 1161 byte_order); 1162 } 1163 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval); 1164 } 1165 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM) 1166 { 1167 /* there's room in a register */ 1168 reg_size = register_size (gdbarch, argreg); 1169 regval = extract_unsigned_integer (val, reg_size, byte_order); 1170 regcache_cooked_write_unsigned (regcache, argreg++, regval); 1171 } 1172 /* Store the value one register at a time or in one step on 1173 stack. */ 1174 len -= reg_size; 1175 val += reg_size; 1176 } 1177 } 1178 1179 if (struct_return) 1180 { 1181 if (sh_is_renesas_calling_convention (func_type)) 1182 /* If the function uses the Renesas ABI, subtract another 4 bytes from 1183 the stack and store the struct return address there. */ 1184 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr); 1185 else 1186 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has 1187 its own dedicated register. */ 1188 regcache_cooked_write_unsigned (regcache, 1189 STRUCT_RETURN_REGNUM, struct_addr); 1190 } 1191 1192 /* Store return address. */ 1193 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); 1194 1195 /* Update stack pointer. */ 1196 regcache_cooked_write_unsigned (regcache, 1197 gdbarch_sp_regnum (gdbarch), sp); 1198 1199 return sp; 1200} 1201 1202static CORE_ADDR 1203sh_push_dummy_call_nofpu (struct gdbarch *gdbarch, 1204 struct value *function, 1205 struct regcache *regcache, 1206 CORE_ADDR bp_addr, 1207 int nargs, struct value **args, 1208 CORE_ADDR sp, int struct_return, 1209 CORE_ADDR struct_addr) 1210{ 1211 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1212 int stack_offset = 0; 1213 int argreg = ARG0_REGNUM; 1214 int argnum; 1215 struct type *func_type = value_type (function); 1216 struct type *type; 1217 CORE_ADDR regval; 1218 char *val; 1219 int len, reg_size = 0; 1220 int pass_on_stack = 0; 1221 int last_reg_arg = INT_MAX; 1222 1223 /* The Renesas ABI expects all varargs arguments, plus the last 1224 non-vararg argument to be on the stack, no matter how many 1225 registers have been used so far. */ 1226 if (sh_is_renesas_calling_convention (func_type) 1227 && TYPE_VARARGS (func_type)) 1228 last_reg_arg = TYPE_NFIELDS (func_type) - 2; 1229 1230 /* First force sp to a 4-byte alignment. */ 1231 sp = sh_frame_align (gdbarch, sp); 1232 1233 /* Make room on stack for args. */ 1234 sp -= sh_stack_allocsize (nargs, args); 1235 1236 /* Now load as many as possible of the first arguments into 1237 registers, and push the rest onto the stack. There are 16 bytes 1238 in four registers available. Loop thru args from first to last. */ 1239 for (argnum = 0; argnum < nargs; argnum++) 1240 { 1241 type = value_type (args[argnum]); 1242 len = TYPE_LENGTH (type); 1243 val = sh_justify_value_in_reg (gdbarch, args[argnum], len); 1244 1245 /* Some decisions have to be made how various types are handled. 1246 This also differs in different ABIs. */ 1247 pass_on_stack = 0; 1248 /* Renesas ABI pushes doubles and long longs entirely on stack. 1249 Same goes for aggregate types. */ 1250 if (sh_is_renesas_calling_convention (func_type) 1251 && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8) 1252 || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8) 1253 || TYPE_CODE (type) == TYPE_CODE_STRUCT 1254 || TYPE_CODE (type) == TYPE_CODE_UNION)) 1255 pass_on_stack = 1; 1256 while (len > 0) 1257 { 1258 if (argreg > ARGLAST_REGNUM || pass_on_stack 1259 || argnum > last_reg_arg) 1260 { 1261 /* The remainder of the data goes entirely on the stack, 1262 4-byte aligned. */ 1263 reg_size = (len + 3) & ~3; 1264 write_memory (sp + stack_offset, val, reg_size); 1265 stack_offset += reg_size; 1266 } 1267 else if (argreg <= ARGLAST_REGNUM) 1268 { 1269 /* There's room in a register. */ 1270 reg_size = register_size (gdbarch, argreg); 1271 regval = extract_unsigned_integer (val, reg_size, byte_order); 1272 regcache_cooked_write_unsigned (regcache, argreg++, regval); 1273 } 1274 /* Store the value reg_size bytes at a time. This means that things 1275 larger than reg_size bytes may go partly in registers and partly 1276 on the stack. */ 1277 len -= reg_size; 1278 val += reg_size; 1279 } 1280 } 1281 1282 if (struct_return) 1283 { 1284 if (sh_is_renesas_calling_convention (func_type)) 1285 /* If the function uses the Renesas ABI, subtract another 4 bytes from 1286 the stack and store the struct return address there. */ 1287 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr); 1288 else 1289 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has 1290 its own dedicated register. */ 1291 regcache_cooked_write_unsigned (regcache, 1292 STRUCT_RETURN_REGNUM, struct_addr); 1293 } 1294 1295 /* Store return address. */ 1296 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); 1297 1298 /* Update stack pointer. */ 1299 regcache_cooked_write_unsigned (regcache, 1300 gdbarch_sp_regnum (gdbarch), sp); 1301 1302 return sp; 1303} 1304 1305/* Find a function's return value in the appropriate registers (in 1306 regbuf), and copy it into valbuf. Extract from an array REGBUF 1307 containing the (raw) register state a function return value of type 1308 TYPE, and copy that, in virtual format, into VALBUF. */ 1309static void 1310sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache, 1311 void *valbuf) 1312{ 1313 struct gdbarch *gdbarch = get_regcache_arch (regcache); 1314 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1315 int len = TYPE_LENGTH (type); 1316 int return_register = R0_REGNUM; 1317 int offset; 1318 1319 if (len <= 4) 1320 { 1321 ULONGEST c; 1322 1323 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c); 1324 store_unsigned_integer (valbuf, len, byte_order, c); 1325 } 1326 else if (len == 8) 1327 { 1328 int i, regnum = R0_REGNUM; 1329 for (i = 0; i < len; i += 4) 1330 regcache_raw_read (regcache, regnum++, (char *) valbuf + i); 1331 } 1332 else 1333 error (_("bad size for return value")); 1334} 1335 1336static void 1337sh_extract_return_value_fpu (struct type *type, struct regcache *regcache, 1338 void *valbuf) 1339{ 1340 struct gdbarch *gdbarch = get_regcache_arch (regcache); 1341 if (sh_treat_as_flt_p (type)) 1342 { 1343 int len = TYPE_LENGTH (type); 1344 int i, regnum = gdbarch_fp0_regnum (gdbarch); 1345 for (i = 0; i < len; i += 4) 1346 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) 1347 regcache_raw_read (regcache, regnum++, 1348 (char *) valbuf + len - 4 - i); 1349 else 1350 regcache_raw_read (regcache, regnum++, (char *) valbuf + i); 1351 } 1352 else 1353 sh_extract_return_value_nofpu (type, regcache, valbuf); 1354} 1355 1356/* Write into appropriate registers a function return value 1357 of type TYPE, given in virtual format. 1358 If the architecture is sh4 or sh3e, store a function's return value 1359 in the R0 general register or in the FP0 floating point register, 1360 depending on the type of the return value. In all the other cases 1361 the result is stored in r0, left-justified. */ 1362static void 1363sh_store_return_value_nofpu (struct type *type, struct regcache *regcache, 1364 const void *valbuf) 1365{ 1366 struct gdbarch *gdbarch = get_regcache_arch (regcache); 1367 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1368 ULONGEST val; 1369 int len = TYPE_LENGTH (type); 1370 1371 if (len <= 4) 1372 { 1373 val = extract_unsigned_integer (valbuf, len, byte_order); 1374 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val); 1375 } 1376 else 1377 { 1378 int i, regnum = R0_REGNUM; 1379 for (i = 0; i < len; i += 4) 1380 regcache_raw_write (regcache, regnum++, (char *) valbuf + i); 1381 } 1382} 1383 1384static void 1385sh_store_return_value_fpu (struct type *type, struct regcache *regcache, 1386 const void *valbuf) 1387{ 1388 struct gdbarch *gdbarch = get_regcache_arch (regcache); 1389 if (sh_treat_as_flt_p (type)) 1390 { 1391 int len = TYPE_LENGTH (type); 1392 int i, regnum = gdbarch_fp0_regnum (gdbarch); 1393 for (i = 0; i < len; i += 4) 1394 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) 1395 regcache_raw_write (regcache, regnum++, 1396 (char *) valbuf + len - 4 - i); 1397 else 1398 regcache_raw_write (regcache, regnum++, (char *) valbuf + i); 1399 } 1400 else 1401 sh_store_return_value_nofpu (type, regcache, valbuf); 1402} 1403 1404static enum return_value_convention 1405sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *func_type, 1406 struct type *type, struct regcache *regcache, 1407 gdb_byte *readbuf, const gdb_byte *writebuf) 1408{ 1409 if (sh_use_struct_convention_nofpu ( 1410 sh_is_renesas_calling_convention (func_type), type)) 1411 return RETURN_VALUE_STRUCT_CONVENTION; 1412 if (writebuf) 1413 sh_store_return_value_nofpu (type, regcache, writebuf); 1414 else if (readbuf) 1415 sh_extract_return_value_nofpu (type, regcache, readbuf); 1416 return RETURN_VALUE_REGISTER_CONVENTION; 1417} 1418 1419static enum return_value_convention 1420sh_return_value_fpu (struct gdbarch *gdbarch, struct type *func_type, 1421 struct type *type, struct regcache *regcache, 1422 gdb_byte *readbuf, const gdb_byte *writebuf) 1423{ 1424 if (sh_use_struct_convention ( 1425 sh_is_renesas_calling_convention (func_type), type)) 1426 return RETURN_VALUE_STRUCT_CONVENTION; 1427 if (writebuf) 1428 sh_store_return_value_fpu (type, regcache, writebuf); 1429 else if (readbuf) 1430 sh_extract_return_value_fpu (type, regcache, readbuf); 1431 return RETURN_VALUE_REGISTER_CONVENTION; 1432} 1433 1434/* Print the registers in a form similar to the E7000. */ 1435 1436static void 1437sh_generic_show_regs (struct frame_info *frame) 1438{ 1439 printf_filtered 1440 (" PC %s SR %08lx PR %08lx MACH %08lx\n", 1441 phex (get_frame_register_unsigned (frame, 1442 gdbarch_pc_regnum 1443 (get_frame_arch (frame))), 4), 1444 (long) get_frame_register_unsigned (frame, SR_REGNUM), 1445 (long) get_frame_register_unsigned (frame, PR_REGNUM), 1446 (long) get_frame_register_unsigned (frame, MACH_REGNUM)); 1447 1448 printf_filtered 1449 (" GBR %08lx VBR %08lx MACL %08lx\n", 1450 (long) get_frame_register_unsigned (frame, GBR_REGNUM), 1451 (long) get_frame_register_unsigned (frame, VBR_REGNUM), 1452 (long) get_frame_register_unsigned (frame, MACL_REGNUM)); 1453 1454 printf_filtered 1455 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1456 (long) get_frame_register_unsigned (frame, 0), 1457 (long) get_frame_register_unsigned (frame, 1), 1458 (long) get_frame_register_unsigned (frame, 2), 1459 (long) get_frame_register_unsigned (frame, 3), 1460 (long) get_frame_register_unsigned (frame, 4), 1461 (long) get_frame_register_unsigned (frame, 5), 1462 (long) get_frame_register_unsigned (frame, 6), 1463 (long) get_frame_register_unsigned (frame, 7)); 1464 printf_filtered 1465 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1466 (long) get_frame_register_unsigned (frame, 8), 1467 (long) get_frame_register_unsigned (frame, 9), 1468 (long) get_frame_register_unsigned (frame, 10), 1469 (long) get_frame_register_unsigned (frame, 11), 1470 (long) get_frame_register_unsigned (frame, 12), 1471 (long) get_frame_register_unsigned (frame, 13), 1472 (long) get_frame_register_unsigned (frame, 14), 1473 (long) get_frame_register_unsigned (frame, 15)); 1474} 1475 1476static void 1477sh3_show_regs (struct frame_info *frame) 1478{ 1479 printf_filtered 1480 (" PC %s SR %08lx PR %08lx MACH %08lx\n", 1481 phex (get_frame_register_unsigned (frame, 1482 gdbarch_pc_regnum 1483 (get_frame_arch (frame))), 4), 1484 (long) get_frame_register_unsigned (frame, SR_REGNUM), 1485 (long) get_frame_register_unsigned (frame, PR_REGNUM), 1486 (long) get_frame_register_unsigned (frame, MACH_REGNUM)); 1487 1488 printf_filtered 1489 (" GBR %08lx VBR %08lx MACL %08lx\n", 1490 (long) get_frame_register_unsigned (frame, GBR_REGNUM), 1491 (long) get_frame_register_unsigned (frame, VBR_REGNUM), 1492 (long) get_frame_register_unsigned (frame, MACL_REGNUM)); 1493 printf_filtered 1494 (" SSR %08lx SPC %08lx\n", 1495 (long) get_frame_register_unsigned (frame, SSR_REGNUM), 1496 (long) get_frame_register_unsigned (frame, SPC_REGNUM)); 1497 1498 printf_filtered 1499 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1500 (long) get_frame_register_unsigned (frame, 0), 1501 (long) get_frame_register_unsigned (frame, 1), 1502 (long) get_frame_register_unsigned (frame, 2), 1503 (long) get_frame_register_unsigned (frame, 3), 1504 (long) get_frame_register_unsigned (frame, 4), 1505 (long) get_frame_register_unsigned (frame, 5), 1506 (long) get_frame_register_unsigned (frame, 6), 1507 (long) get_frame_register_unsigned (frame, 7)); 1508 printf_filtered 1509 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1510 (long) get_frame_register_unsigned (frame, 8), 1511 (long) get_frame_register_unsigned (frame, 9), 1512 (long) get_frame_register_unsigned (frame, 10), 1513 (long) get_frame_register_unsigned (frame, 11), 1514 (long) get_frame_register_unsigned (frame, 12), 1515 (long) get_frame_register_unsigned (frame, 13), 1516 (long) get_frame_register_unsigned (frame, 14), 1517 (long) get_frame_register_unsigned (frame, 15)); 1518} 1519 1520static void 1521sh2e_show_regs (struct frame_info *frame) 1522{ 1523 struct gdbarch *gdbarch = get_frame_arch (frame); 1524 printf_filtered 1525 (" PC %s SR %08lx PR %08lx MACH %08lx\n", 1526 phex (get_frame_register_unsigned (frame, 1527 gdbarch_pc_regnum (gdbarch)), 4), 1528 (long) get_frame_register_unsigned (frame, SR_REGNUM), 1529 (long) get_frame_register_unsigned (frame, PR_REGNUM), 1530 (long) get_frame_register_unsigned (frame, MACH_REGNUM)); 1531 1532 printf_filtered 1533 (" GBR %08lx VBR %08lx MACL %08lx\n", 1534 (long) get_frame_register_unsigned (frame, GBR_REGNUM), 1535 (long) get_frame_register_unsigned (frame, VBR_REGNUM), 1536 (long) get_frame_register_unsigned (frame, MACL_REGNUM)); 1537 printf_filtered 1538 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", 1539 (long) get_frame_register_unsigned (frame, SSR_REGNUM), 1540 (long) get_frame_register_unsigned (frame, SPC_REGNUM), 1541 (long) get_frame_register_unsigned (frame, FPUL_REGNUM), 1542 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM)); 1543 1544 printf_filtered 1545 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1546 (long) get_frame_register_unsigned (frame, 0), 1547 (long) get_frame_register_unsigned (frame, 1), 1548 (long) get_frame_register_unsigned (frame, 2), 1549 (long) get_frame_register_unsigned (frame, 3), 1550 (long) get_frame_register_unsigned (frame, 4), 1551 (long) get_frame_register_unsigned (frame, 5), 1552 (long) get_frame_register_unsigned (frame, 6), 1553 (long) get_frame_register_unsigned (frame, 7)); 1554 printf_filtered 1555 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1556 (long) get_frame_register_unsigned (frame, 8), 1557 (long) get_frame_register_unsigned (frame, 9), 1558 (long) get_frame_register_unsigned (frame, 10), 1559 (long) get_frame_register_unsigned (frame, 11), 1560 (long) get_frame_register_unsigned (frame, 12), 1561 (long) get_frame_register_unsigned (frame, 13), 1562 (long) get_frame_register_unsigned (frame, 14), 1563 (long) get_frame_register_unsigned (frame, 15)); 1564 1565 printf_filtered 1566 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1567 (long) get_frame_register_unsigned 1568 (frame, gdbarch_fp0_regnum (gdbarch) + 0), 1569 (long) get_frame_register_unsigned 1570 (frame, gdbarch_fp0_regnum (gdbarch) + 1), 1571 (long) get_frame_register_unsigned 1572 (frame, gdbarch_fp0_regnum (gdbarch) + 2), 1573 (long) get_frame_register_unsigned 1574 (frame, gdbarch_fp0_regnum (gdbarch) + 3), 1575 (long) get_frame_register_unsigned 1576 (frame, gdbarch_fp0_regnum (gdbarch) + 4), 1577 (long) get_frame_register_unsigned 1578 (frame, gdbarch_fp0_regnum (gdbarch) + 5), 1579 (long) get_frame_register_unsigned 1580 (frame, gdbarch_fp0_regnum (gdbarch) + 6), 1581 (long) get_frame_register_unsigned 1582 (frame, gdbarch_fp0_regnum (gdbarch) + 7)); 1583 printf_filtered 1584 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1585 (long) get_frame_register_unsigned 1586 (frame, gdbarch_fp0_regnum (gdbarch) + 8), 1587 (long) get_frame_register_unsigned 1588 (frame, gdbarch_fp0_regnum (gdbarch) + 9), 1589 (long) get_frame_register_unsigned 1590 (frame, gdbarch_fp0_regnum (gdbarch) + 10), 1591 (long) get_frame_register_unsigned 1592 (frame, gdbarch_fp0_regnum (gdbarch) + 11), 1593 (long) get_frame_register_unsigned 1594 (frame, gdbarch_fp0_regnum (gdbarch) + 12), 1595 (long) get_frame_register_unsigned 1596 (frame, gdbarch_fp0_regnum (gdbarch) + 13), 1597 (long) get_frame_register_unsigned 1598 (frame, gdbarch_fp0_regnum (gdbarch) + 14), 1599 (long) get_frame_register_unsigned 1600 (frame, gdbarch_fp0_regnum (gdbarch) + 15)); 1601} 1602 1603static void 1604sh2a_show_regs (struct frame_info *frame) 1605{ 1606 struct gdbarch *gdbarch = get_frame_arch (frame); 1607 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000; 1608 1609 printf_filtered 1610 (" PC %s SR %08lx PR %08lx MACH %08lx\n", 1611 phex (get_frame_register_unsigned (frame, 1612 gdbarch_pc_regnum (gdbarch)), 4), 1613 (long) get_frame_register_unsigned (frame, SR_REGNUM), 1614 (long) get_frame_register_unsigned (frame, PR_REGNUM), 1615 (long) get_frame_register_unsigned (frame, MACH_REGNUM)); 1616 1617 printf_filtered 1618 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n", 1619 (long) get_frame_register_unsigned (frame, GBR_REGNUM), 1620 (long) get_frame_register_unsigned (frame, VBR_REGNUM), 1621 (long) get_frame_register_unsigned (frame, TBR_REGNUM), 1622 (long) get_frame_register_unsigned (frame, MACL_REGNUM)); 1623 printf_filtered 1624 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", 1625 (long) get_frame_register_unsigned (frame, SSR_REGNUM), 1626 (long) get_frame_register_unsigned (frame, SPC_REGNUM), 1627 (long) get_frame_register_unsigned (frame, FPUL_REGNUM), 1628 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM)); 1629 1630 printf_filtered 1631 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1632 (long) get_frame_register_unsigned (frame, 0), 1633 (long) get_frame_register_unsigned (frame, 1), 1634 (long) get_frame_register_unsigned (frame, 2), 1635 (long) get_frame_register_unsigned (frame, 3), 1636 (long) get_frame_register_unsigned (frame, 4), 1637 (long) get_frame_register_unsigned (frame, 5), 1638 (long) get_frame_register_unsigned (frame, 6), 1639 (long) get_frame_register_unsigned (frame, 7)); 1640 printf_filtered 1641 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1642 (long) get_frame_register_unsigned (frame, 8), 1643 (long) get_frame_register_unsigned (frame, 9), 1644 (long) get_frame_register_unsigned (frame, 10), 1645 (long) get_frame_register_unsigned (frame, 11), 1646 (long) get_frame_register_unsigned (frame, 12), 1647 (long) get_frame_register_unsigned (frame, 13), 1648 (long) get_frame_register_unsigned (frame, 14), 1649 (long) get_frame_register_unsigned (frame, 15)); 1650 1651 printf_filtered 1652 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" 1653 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1654 (long) get_frame_register_unsigned 1655 (frame, gdbarch_fp0_regnum (gdbarch) + 0), 1656 (long) get_frame_register_unsigned 1657 (frame, gdbarch_fp0_regnum (gdbarch) + 1), 1658 (long) get_frame_register_unsigned 1659 (frame, gdbarch_fp0_regnum (gdbarch) + 2), 1660 (long) get_frame_register_unsigned 1661 (frame, gdbarch_fp0_regnum (gdbarch) + 3), 1662 (long) get_frame_register_unsigned 1663 (frame, gdbarch_fp0_regnum (gdbarch) + 4), 1664 (long) get_frame_register_unsigned 1665 (frame, gdbarch_fp0_regnum (gdbarch) + 5), 1666 (long) get_frame_register_unsigned 1667 (frame, gdbarch_fp0_regnum (gdbarch) + 6), 1668 (long) get_frame_register_unsigned 1669 (frame, gdbarch_fp0_regnum (gdbarch) + 7)); 1670 printf_filtered 1671 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" 1672 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1673 (long) get_frame_register_unsigned 1674 (frame, gdbarch_fp0_regnum (gdbarch) + 8), 1675 (long) get_frame_register_unsigned 1676 (frame, gdbarch_fp0_regnum (gdbarch) + 9), 1677 (long) get_frame_register_unsigned 1678 (frame, gdbarch_fp0_regnum (gdbarch) + 10), 1679 (long) get_frame_register_unsigned 1680 (frame, gdbarch_fp0_regnum (gdbarch) + 11), 1681 (long) get_frame_register_unsigned 1682 (frame, gdbarch_fp0_regnum (gdbarch) + 12), 1683 (long) get_frame_register_unsigned 1684 (frame, gdbarch_fp0_regnum (gdbarch) + 13), 1685 (long) get_frame_register_unsigned 1686 (frame, gdbarch_fp0_regnum (gdbarch) + 14), 1687 (long) get_frame_register_unsigned 1688 (frame, gdbarch_fp0_regnum (gdbarch) + 15)); 1689 printf_filtered 1690 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM)); 1691 printf_filtered 1692 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1693 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0), 1694 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1), 1695 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2), 1696 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3), 1697 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4), 1698 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5), 1699 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6), 1700 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7)); 1701 printf_filtered 1702 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1703 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8), 1704 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9), 1705 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10), 1706 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11), 1707 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12), 1708 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13), 1709 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14)); 1710 printf_filtered 1711 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n", 1712 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15), 1713 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16), 1714 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17), 1715 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18), 1716 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19)); 1717} 1718 1719static void 1720sh2a_nofpu_show_regs (struct frame_info *frame) 1721{ 1722 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000; 1723 1724 printf_filtered 1725 (" PC %s SR %08lx PR %08lx MACH %08lx\n", 1726 phex (get_frame_register_unsigned (frame, 1727 gdbarch_pc_regnum 1728 (get_frame_arch (frame))), 4), 1729 (long) get_frame_register_unsigned (frame, SR_REGNUM), 1730 (long) get_frame_register_unsigned (frame, PR_REGNUM), 1731 (long) get_frame_register_unsigned (frame, MACH_REGNUM)); 1732 1733 printf_filtered 1734 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n", 1735 (long) get_frame_register_unsigned (frame, GBR_REGNUM), 1736 (long) get_frame_register_unsigned (frame, VBR_REGNUM), 1737 (long) get_frame_register_unsigned (frame, TBR_REGNUM), 1738 (long) get_frame_register_unsigned (frame, MACL_REGNUM)); 1739 printf_filtered 1740 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", 1741 (long) get_frame_register_unsigned (frame, SSR_REGNUM), 1742 (long) get_frame_register_unsigned (frame, SPC_REGNUM), 1743 (long) get_frame_register_unsigned (frame, FPUL_REGNUM), 1744 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM)); 1745 1746 printf_filtered 1747 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1748 (long) get_frame_register_unsigned (frame, 0), 1749 (long) get_frame_register_unsigned (frame, 1), 1750 (long) get_frame_register_unsigned (frame, 2), 1751 (long) get_frame_register_unsigned (frame, 3), 1752 (long) get_frame_register_unsigned (frame, 4), 1753 (long) get_frame_register_unsigned (frame, 5), 1754 (long) get_frame_register_unsigned (frame, 6), 1755 (long) get_frame_register_unsigned (frame, 7)); 1756 printf_filtered 1757 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1758 (long) get_frame_register_unsigned (frame, 8), 1759 (long) get_frame_register_unsigned (frame, 9), 1760 (long) get_frame_register_unsigned (frame, 10), 1761 (long) get_frame_register_unsigned (frame, 11), 1762 (long) get_frame_register_unsigned (frame, 12), 1763 (long) get_frame_register_unsigned (frame, 13), 1764 (long) get_frame_register_unsigned (frame, 14), 1765 (long) get_frame_register_unsigned (frame, 15)); 1766 1767 printf_filtered 1768 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM)); 1769 printf_filtered 1770 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1771 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0), 1772 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1), 1773 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2), 1774 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3), 1775 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4), 1776 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5), 1777 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6), 1778 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7)); 1779 printf_filtered 1780 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1781 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8), 1782 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9), 1783 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10), 1784 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11), 1785 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12), 1786 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13), 1787 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14)); 1788 printf_filtered 1789 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n", 1790 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15), 1791 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16), 1792 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17), 1793 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18), 1794 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19)); 1795} 1796 1797static void 1798sh3e_show_regs (struct frame_info *frame) 1799{ 1800 struct gdbarch *gdbarch = get_frame_arch (frame); 1801 printf_filtered 1802 (" PC %s SR %08lx PR %08lx MACH %08lx\n", 1803 phex (get_frame_register_unsigned (frame, 1804 gdbarch_pc_regnum (gdbarch)), 4), 1805 (long) get_frame_register_unsigned (frame, SR_REGNUM), 1806 (long) get_frame_register_unsigned (frame, PR_REGNUM), 1807 (long) get_frame_register_unsigned (frame, MACH_REGNUM)); 1808 1809 printf_filtered 1810 (" GBR %08lx VBR %08lx MACL %08lx\n", 1811 (long) get_frame_register_unsigned (frame, GBR_REGNUM), 1812 (long) get_frame_register_unsigned (frame, VBR_REGNUM), 1813 (long) get_frame_register_unsigned (frame, MACL_REGNUM)); 1814 printf_filtered 1815 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", 1816 (long) get_frame_register_unsigned (frame, SSR_REGNUM), 1817 (long) get_frame_register_unsigned (frame, SPC_REGNUM), 1818 (long) get_frame_register_unsigned (frame, FPUL_REGNUM), 1819 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM)); 1820 1821 printf_filtered 1822 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1823 (long) get_frame_register_unsigned (frame, 0), 1824 (long) get_frame_register_unsigned (frame, 1), 1825 (long) get_frame_register_unsigned (frame, 2), 1826 (long) get_frame_register_unsigned (frame, 3), 1827 (long) get_frame_register_unsigned (frame, 4), 1828 (long) get_frame_register_unsigned (frame, 5), 1829 (long) get_frame_register_unsigned (frame, 6), 1830 (long) get_frame_register_unsigned (frame, 7)); 1831 printf_filtered 1832 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1833 (long) get_frame_register_unsigned (frame, 8), 1834 (long) get_frame_register_unsigned (frame, 9), 1835 (long) get_frame_register_unsigned (frame, 10), 1836 (long) get_frame_register_unsigned (frame, 11), 1837 (long) get_frame_register_unsigned (frame, 12), 1838 (long) get_frame_register_unsigned (frame, 13), 1839 (long) get_frame_register_unsigned (frame, 14), 1840 (long) get_frame_register_unsigned (frame, 15)); 1841 1842 printf_filtered 1843 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1844 (long) get_frame_register_unsigned 1845 (frame, gdbarch_fp0_regnum (gdbarch) + 0), 1846 (long) get_frame_register_unsigned 1847 (frame, gdbarch_fp0_regnum (gdbarch) + 1), 1848 (long) get_frame_register_unsigned 1849 (frame, gdbarch_fp0_regnum (gdbarch) + 2), 1850 (long) get_frame_register_unsigned 1851 (frame, gdbarch_fp0_regnum (gdbarch) + 3), 1852 (long) get_frame_register_unsigned 1853 (frame, gdbarch_fp0_regnum (gdbarch) + 4), 1854 (long) get_frame_register_unsigned 1855 (frame, gdbarch_fp0_regnum (gdbarch) + 5), 1856 (long) get_frame_register_unsigned 1857 (frame, gdbarch_fp0_regnum (gdbarch) + 6), 1858 (long) get_frame_register_unsigned 1859 (frame, gdbarch_fp0_regnum (gdbarch) + 7)); 1860 printf_filtered 1861 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1862 (long) get_frame_register_unsigned 1863 (frame, gdbarch_fp0_regnum (gdbarch) + 8), 1864 (long) get_frame_register_unsigned 1865 (frame, gdbarch_fp0_regnum (gdbarch) + 9), 1866 (long) get_frame_register_unsigned 1867 (frame, gdbarch_fp0_regnum (gdbarch) + 10), 1868 (long) get_frame_register_unsigned 1869 (frame, gdbarch_fp0_regnum (gdbarch) + 11), 1870 (long) get_frame_register_unsigned 1871 (frame, gdbarch_fp0_regnum (gdbarch) + 12), 1872 (long) get_frame_register_unsigned 1873 (frame, gdbarch_fp0_regnum (gdbarch) + 13), 1874 (long) get_frame_register_unsigned 1875 (frame, gdbarch_fp0_regnum (gdbarch) + 14), 1876 (long) get_frame_register_unsigned 1877 (frame, gdbarch_fp0_regnum (gdbarch) + 15)); 1878} 1879 1880static void 1881sh3_dsp_show_regs (struct frame_info *frame) 1882{ 1883 printf_filtered 1884 (" PC %s SR %08lx PR %08lx MACH %08lx\n", 1885 phex (get_frame_register_unsigned (frame, 1886 gdbarch_pc_regnum 1887 (get_frame_arch (frame))), 4), 1888 (long) get_frame_register_unsigned (frame, SR_REGNUM), 1889 (long) get_frame_register_unsigned (frame, PR_REGNUM), 1890 (long) get_frame_register_unsigned (frame, MACH_REGNUM)); 1891 1892 printf_filtered 1893 (" GBR %08lx VBR %08lx MACL %08lx\n", 1894 (long) get_frame_register_unsigned (frame, GBR_REGNUM), 1895 (long) get_frame_register_unsigned (frame, VBR_REGNUM), 1896 (long) get_frame_register_unsigned (frame, MACL_REGNUM)); 1897 1898 printf_filtered 1899 (" SSR %08lx SPC %08lx DSR %08lx\n", 1900 (long) get_frame_register_unsigned (frame, SSR_REGNUM), 1901 (long) get_frame_register_unsigned (frame, SPC_REGNUM), 1902 (long) get_frame_register_unsigned (frame, DSR_REGNUM)); 1903 1904 printf_filtered 1905 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1906 (long) get_frame_register_unsigned (frame, 0), 1907 (long) get_frame_register_unsigned (frame, 1), 1908 (long) get_frame_register_unsigned (frame, 2), 1909 (long) get_frame_register_unsigned (frame, 3), 1910 (long) get_frame_register_unsigned (frame, 4), 1911 (long) get_frame_register_unsigned (frame, 5), 1912 (long) get_frame_register_unsigned (frame, 6), 1913 (long) get_frame_register_unsigned (frame, 7)); 1914 printf_filtered 1915 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1916 (long) get_frame_register_unsigned (frame, 8), 1917 (long) get_frame_register_unsigned (frame, 9), 1918 (long) get_frame_register_unsigned (frame, 10), 1919 (long) get_frame_register_unsigned (frame, 11), 1920 (long) get_frame_register_unsigned (frame, 12), 1921 (long) get_frame_register_unsigned (frame, 13), 1922 (long) get_frame_register_unsigned (frame, 14), 1923 (long) get_frame_register_unsigned (frame, 15)); 1924 1925 printf_filtered 1926 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", 1927 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff, 1928 (long) get_frame_register_unsigned (frame, A0_REGNUM), 1929 (long) get_frame_register_unsigned (frame, M0_REGNUM), 1930 (long) get_frame_register_unsigned (frame, X0_REGNUM), 1931 (long) get_frame_register_unsigned (frame, Y0_REGNUM), 1932 (long) get_frame_register_unsigned (frame, RS_REGNUM), 1933 (long) get_frame_register_unsigned (frame, MOD_REGNUM)); 1934 printf_filtered 1935 ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", 1936 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff, 1937 (long) get_frame_register_unsigned (frame, A1_REGNUM), 1938 (long) get_frame_register_unsigned (frame, M1_REGNUM), 1939 (long) get_frame_register_unsigned (frame, X1_REGNUM), 1940 (long) get_frame_register_unsigned (frame, Y1_REGNUM), 1941 (long) get_frame_register_unsigned (frame, RE_REGNUM)); 1942} 1943 1944static void 1945sh4_show_regs (struct frame_info *frame) 1946{ 1947 struct gdbarch *gdbarch = get_frame_arch (frame); 1948 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000; 1949 1950 printf_filtered 1951 (" PC %s SR %08lx PR %08lx MACH %08lx\n", 1952 phex (get_frame_register_unsigned (frame, 1953 gdbarch_pc_regnum (gdbarch)), 4), 1954 (long) get_frame_register_unsigned (frame, SR_REGNUM), 1955 (long) get_frame_register_unsigned (frame, PR_REGNUM), 1956 (long) get_frame_register_unsigned (frame, MACH_REGNUM)); 1957 1958 printf_filtered 1959 (" GBR %08lx VBR %08lx MACL %08lx\n", 1960 (long) get_frame_register_unsigned (frame, GBR_REGNUM), 1961 (long) get_frame_register_unsigned (frame, VBR_REGNUM), 1962 (long) get_frame_register_unsigned (frame, MACL_REGNUM)); 1963 printf_filtered 1964 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", 1965 (long) get_frame_register_unsigned (frame, SSR_REGNUM), 1966 (long) get_frame_register_unsigned (frame, SPC_REGNUM), 1967 (long) get_frame_register_unsigned (frame, FPUL_REGNUM), 1968 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM)); 1969 1970 printf_filtered 1971 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1972 (long) get_frame_register_unsigned (frame, 0), 1973 (long) get_frame_register_unsigned (frame, 1), 1974 (long) get_frame_register_unsigned (frame, 2), 1975 (long) get_frame_register_unsigned (frame, 3), 1976 (long) get_frame_register_unsigned (frame, 4), 1977 (long) get_frame_register_unsigned (frame, 5), 1978 (long) get_frame_register_unsigned (frame, 6), 1979 (long) get_frame_register_unsigned (frame, 7)); 1980 printf_filtered 1981 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1982 (long) get_frame_register_unsigned (frame, 8), 1983 (long) get_frame_register_unsigned (frame, 9), 1984 (long) get_frame_register_unsigned (frame, 10), 1985 (long) get_frame_register_unsigned (frame, 11), 1986 (long) get_frame_register_unsigned (frame, 12), 1987 (long) get_frame_register_unsigned (frame, 13), 1988 (long) get_frame_register_unsigned (frame, 14), 1989 (long) get_frame_register_unsigned (frame, 15)); 1990 1991 printf_filtered 1992 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" 1993 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1994 (long) get_frame_register_unsigned 1995 (frame, gdbarch_fp0_regnum (gdbarch) + 0), 1996 (long) get_frame_register_unsigned 1997 (frame, gdbarch_fp0_regnum (gdbarch) + 1), 1998 (long) get_frame_register_unsigned 1999 (frame, gdbarch_fp0_regnum (gdbarch) + 2), 2000 (long) get_frame_register_unsigned 2001 (frame, gdbarch_fp0_regnum (gdbarch) + 3), 2002 (long) get_frame_register_unsigned 2003 (frame, gdbarch_fp0_regnum (gdbarch) + 4), 2004 (long) get_frame_register_unsigned 2005 (frame, gdbarch_fp0_regnum (gdbarch) + 5), 2006 (long) get_frame_register_unsigned 2007 (frame, gdbarch_fp0_regnum (gdbarch) + 6), 2008 (long) get_frame_register_unsigned 2009 (frame, gdbarch_fp0_regnum (gdbarch) + 7)); 2010 printf_filtered 2011 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" 2012 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 2013 (long) get_frame_register_unsigned 2014 (frame, gdbarch_fp0_regnum (gdbarch) + 8), 2015 (long) get_frame_register_unsigned 2016 (frame, gdbarch_fp0_regnum (gdbarch) + 9), 2017 (long) get_frame_register_unsigned 2018 (frame, gdbarch_fp0_regnum (gdbarch) + 10), 2019 (long) get_frame_register_unsigned 2020 (frame, gdbarch_fp0_regnum (gdbarch) + 11), 2021 (long) get_frame_register_unsigned 2022 (frame, gdbarch_fp0_regnum (gdbarch) + 12), 2023 (long) get_frame_register_unsigned 2024 (frame, gdbarch_fp0_regnum (gdbarch) + 13), 2025 (long) get_frame_register_unsigned 2026 (frame, gdbarch_fp0_regnum (gdbarch) + 14), 2027 (long) get_frame_register_unsigned 2028 (frame, gdbarch_fp0_regnum (gdbarch) + 15)); 2029} 2030 2031static void 2032sh4_nofpu_show_regs (struct frame_info *frame) 2033{ 2034 printf_filtered 2035 (" PC %s SR %08lx PR %08lx MACH %08lx\n", 2036 phex (get_frame_register_unsigned (frame, 2037 gdbarch_pc_regnum 2038 (get_frame_arch (frame))), 4), 2039 (long) get_frame_register_unsigned (frame, SR_REGNUM), 2040 (long) get_frame_register_unsigned (frame, PR_REGNUM), 2041 (long) get_frame_register_unsigned (frame, MACH_REGNUM)); 2042 2043 printf_filtered 2044 (" GBR %08lx VBR %08lx MACL %08lx\n", 2045 (long) get_frame_register_unsigned (frame, GBR_REGNUM), 2046 (long) get_frame_register_unsigned (frame, VBR_REGNUM), 2047 (long) get_frame_register_unsigned (frame, MACL_REGNUM)); 2048 printf_filtered 2049 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", 2050 (long) get_frame_register_unsigned (frame, SSR_REGNUM), 2051 (long) get_frame_register_unsigned (frame, SPC_REGNUM), 2052 (long) get_frame_register_unsigned (frame, FPUL_REGNUM), 2053 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM)); 2054 2055 printf_filtered 2056 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 2057 (long) get_frame_register_unsigned (frame, 0), 2058 (long) get_frame_register_unsigned (frame, 1), 2059 (long) get_frame_register_unsigned (frame, 2), 2060 (long) get_frame_register_unsigned (frame, 3), 2061 (long) get_frame_register_unsigned (frame, 4), 2062 (long) get_frame_register_unsigned (frame, 5), 2063 (long) get_frame_register_unsigned (frame, 6), 2064 (long) get_frame_register_unsigned (frame, 7)); 2065 printf_filtered 2066 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 2067 (long) get_frame_register_unsigned (frame, 8), 2068 (long) get_frame_register_unsigned (frame, 9), 2069 (long) get_frame_register_unsigned (frame, 10), 2070 (long) get_frame_register_unsigned (frame, 11), 2071 (long) get_frame_register_unsigned (frame, 12), 2072 (long) get_frame_register_unsigned (frame, 13), 2073 (long) get_frame_register_unsigned (frame, 14), 2074 (long) get_frame_register_unsigned (frame, 15)); 2075} 2076 2077static void 2078sh_dsp_show_regs (struct frame_info *frame) 2079{ 2080 printf_filtered 2081 (" PC %s SR %08lx PR %08lx MACH %08lx\n", 2082 phex (get_frame_register_unsigned (frame, 2083 gdbarch_pc_regnum 2084 (get_frame_arch (frame))), 4), 2085 (long) get_frame_register_unsigned (frame, SR_REGNUM), 2086 (long) get_frame_register_unsigned (frame, PR_REGNUM), 2087 (long) get_frame_register_unsigned (frame, MACH_REGNUM)); 2088 2089 printf_filtered 2090 (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n", 2091 (long) get_frame_register_unsigned (frame, GBR_REGNUM), 2092 (long) get_frame_register_unsigned (frame, VBR_REGNUM), 2093 (long) get_frame_register_unsigned (frame, DSR_REGNUM), 2094 (long) get_frame_register_unsigned (frame, MACL_REGNUM)); 2095 2096 printf_filtered 2097 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 2098 (long) get_frame_register_unsigned (frame, 0), 2099 (long) get_frame_register_unsigned (frame, 1), 2100 (long) get_frame_register_unsigned (frame, 2), 2101 (long) get_frame_register_unsigned (frame, 3), 2102 (long) get_frame_register_unsigned (frame, 4), 2103 (long) get_frame_register_unsigned (frame, 5), 2104 (long) get_frame_register_unsigned (frame, 6), 2105 (long) get_frame_register_unsigned (frame, 7)); 2106 printf_filtered 2107 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 2108 (long) get_frame_register_unsigned (frame, 8), 2109 (long) get_frame_register_unsigned (frame, 9), 2110 (long) get_frame_register_unsigned (frame, 10), 2111 (long) get_frame_register_unsigned (frame, 11), 2112 (long) get_frame_register_unsigned (frame, 12), 2113 (long) get_frame_register_unsigned (frame, 13), 2114 (long) get_frame_register_unsigned (frame, 14), 2115 (long) get_frame_register_unsigned (frame, 15)); 2116 2117 printf_filtered 2118 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", 2119 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff, 2120 (long) get_frame_register_unsigned (frame, A0_REGNUM), 2121 (long) get_frame_register_unsigned (frame, M0_REGNUM), 2122 (long) get_frame_register_unsigned (frame, X0_REGNUM), 2123 (long) get_frame_register_unsigned (frame, Y0_REGNUM), 2124 (long) get_frame_register_unsigned (frame, RS_REGNUM), 2125 (long) get_frame_register_unsigned (frame, MOD_REGNUM)); 2126 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", 2127 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff, 2128 (long) get_frame_register_unsigned (frame, A1_REGNUM), 2129 (long) get_frame_register_unsigned (frame, M1_REGNUM), 2130 (long) get_frame_register_unsigned (frame, X1_REGNUM), 2131 (long) get_frame_register_unsigned (frame, Y1_REGNUM), 2132 (long) get_frame_register_unsigned (frame, RE_REGNUM)); 2133} 2134 2135static void 2136sh_show_regs_command (char *args, int from_tty) 2137{ 2138 if (sh_show_regs) 2139 (*sh_show_regs) (get_current_frame ()); 2140} 2141 2142static struct type * 2143sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr) 2144{ 2145 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) 2146 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) 2147 return builtin_type (gdbarch)->builtin_float; 2148 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) 2149 return builtin_type (gdbarch)->builtin_double; 2150 else 2151 return builtin_type (gdbarch)->builtin_int; 2152} 2153 2154/* Return the GDB type object for the "standard" data type 2155 of data in register N. */ 2156static struct type * 2157sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr) 2158{ 2159 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) 2160 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) 2161 return builtin_type (gdbarch)->builtin_float; 2162 else 2163 return builtin_type (gdbarch)->builtin_int; 2164} 2165 2166static struct type * 2167sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high) 2168{ 2169 return lookup_array_range_type (builtin_type (gdbarch)->builtin_float, 2170 0, high); 2171} 2172 2173static struct type * 2174sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr) 2175{ 2176 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) 2177 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) 2178 return builtin_type (gdbarch)->builtin_float; 2179 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) 2180 return builtin_type (gdbarch)->builtin_double; 2181 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) 2182 return sh_sh4_build_float_register_type (gdbarch, 3); 2183 else 2184 return builtin_type (gdbarch)->builtin_int; 2185} 2186 2187static struct type * 2188sh_default_register_type (struct gdbarch *gdbarch, int reg_nr) 2189{ 2190 return builtin_type (gdbarch)->builtin_int; 2191} 2192 2193/* Is a register in a reggroup? 2194 The default code in reggroup.c doesn't identify system registers, some 2195 float registers or any of the vector registers. 2196 TODO: sh2a and dsp registers. */ 2197static int 2198sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 2199 struct reggroup *reggroup) 2200{ 2201 if (gdbarch_register_name (gdbarch, regnum) == NULL 2202 || *gdbarch_register_name (gdbarch, regnum) == '\0') 2203 return 0; 2204 2205 if (reggroup == float_reggroup 2206 && (regnum == FPUL_REGNUM 2207 || regnum == FPSCR_REGNUM)) 2208 return 1; 2209 2210 if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM) 2211 { 2212 if (reggroup == vector_reggroup || reggroup == float_reggroup) 2213 return 1; 2214 if (reggroup == general_reggroup) 2215 return 0; 2216 } 2217 2218 if (regnum == VBR_REGNUM 2219 || regnum == SR_REGNUM 2220 || regnum == FPSCR_REGNUM 2221 || regnum == SSR_REGNUM 2222 || regnum == SPC_REGNUM) 2223 { 2224 if (reggroup == system_reggroup) 2225 return 1; 2226 if (reggroup == general_reggroup) 2227 return 0; 2228 } 2229 2230 /* The default code can cope with any other registers. */ 2231 return default_register_reggroup_p (gdbarch, regnum, reggroup); 2232} 2233 2234/* On the sh4, the DRi pseudo registers are problematic if the target 2235 is little endian. When the user writes one of those registers, for 2236 instance with 'ser var $dr0=1', we want the double to be stored 2237 like this: 2238 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f 2239 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 2240 2241 This corresponds to little endian byte order & big endian word 2242 order. However if we let gdb write the register w/o conversion, it 2243 will write fr0 and fr1 this way: 2244 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 2245 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f 2246 because it will consider fr0 and fr1 as a single LE stretch of memory. 2247 2248 To achieve what we want we must force gdb to store things in 2249 floatformat_ieee_double_littlebyte_bigword (which is defined in 2250 include/floatformat.h and libiberty/floatformat.c. 2251 2252 In case the target is big endian, there is no problem, the 2253 raw bytes will look like: 2254 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00 2255 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 2256 2257 The other pseudo registers (the FVs) also don't pose a problem 2258 because they are stored as 4 individual FP elements. */ 2259 2260static void 2261sh_register_convert_to_virtual (int regnum, struct type *type, 2262 char *from, char *to) 2263{ 2264 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) 2265 { 2266 DOUBLEST val; 2267 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, 2268 from, &val); 2269 store_typed_floating (to, type, val); 2270 } 2271 else 2272 error 2273 ("sh_register_convert_to_virtual called with non DR register number"); 2274} 2275 2276static void 2277sh_register_convert_to_raw (struct type *type, int regnum, 2278 const void *from, void *to) 2279{ 2280 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) 2281 { 2282 DOUBLEST val = extract_typed_floating (from, type); 2283 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, 2284 &val, to); 2285 } 2286 else 2287 error (_("sh_register_convert_to_raw called with non DR register number")); 2288} 2289 2290/* For vectors of 4 floating point registers. */ 2291static int 2292fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum) 2293{ 2294 int fp_regnum; 2295 2296 fp_regnum = gdbarch_fp0_regnum (gdbarch) 2297 + (fv_regnum - FV0_REGNUM) * 4; 2298 return fp_regnum; 2299} 2300 2301/* For double precision floating point registers, i.e 2 fp regs. */ 2302static int 2303dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum) 2304{ 2305 int fp_regnum; 2306 2307 fp_regnum = gdbarch_fp0_regnum (gdbarch) 2308 + (dr_regnum - DR0_REGNUM) * 2; 2309 return fp_regnum; 2310} 2311 2312/* Concatenate PORTIONS contiguous raw registers starting at 2313 BASE_REGNUM into BUFFER. */ 2314 2315static enum register_status 2316pseudo_register_read_portions (struct gdbarch *gdbarch, 2317 struct regcache *regcache, 2318 int portions, 2319 int base_regnum, gdb_byte *buffer) 2320{ 2321 int portion; 2322 2323 for (portion = 0; portion < portions; portion++) 2324 { 2325 enum register_status status; 2326 gdb_byte *b; 2327 2328 b = buffer + register_size (gdbarch, base_regnum) * portion; 2329 status = regcache_raw_read (regcache, base_regnum + portion, b); 2330 if (status != REG_VALID) 2331 return status; 2332 } 2333 2334 return REG_VALID; 2335} 2336 2337static enum register_status 2338sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, 2339 int reg_nr, gdb_byte *buffer) 2340{ 2341 int base_regnum; 2342 char temp_buffer[MAX_REGISTER_SIZE]; 2343 enum register_status status; 2344 2345 if (reg_nr == PSEUDO_BANK_REGNUM) 2346 return regcache_raw_read (regcache, BANK_REGNUM, buffer); 2347 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) 2348 { 2349 base_regnum = dr_reg_base_num (gdbarch, reg_nr); 2350 2351 /* Build the value in the provided buffer. */ 2352 /* Read the real regs for which this one is an alias. */ 2353 status = pseudo_register_read_portions (gdbarch, regcache, 2354 2, base_regnum, temp_buffer); 2355 if (status == REG_VALID) 2356 { 2357 /* We must pay attention to the endiannes. */ 2358 sh_register_convert_to_virtual (reg_nr, 2359 register_type (gdbarch, reg_nr), 2360 temp_buffer, buffer); 2361 } 2362 return status; 2363 } 2364 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) 2365 { 2366 base_regnum = fv_reg_base_num (gdbarch, reg_nr); 2367 2368 /* Read the real regs for which this one is an alias. */ 2369 return pseudo_register_read_portions (gdbarch, regcache, 2370 4, base_regnum, buffer); 2371 } 2372 else 2373 gdb_assert_not_reached ("invalid pseudo register number"); 2374} 2375 2376static void 2377sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 2378 int reg_nr, const gdb_byte *buffer) 2379{ 2380 int base_regnum, portion; 2381 char temp_buffer[MAX_REGISTER_SIZE]; 2382 2383 if (reg_nr == PSEUDO_BANK_REGNUM) 2384 { 2385 /* When the bank register is written to, the whole register bank 2386 is switched and all values in the bank registers must be read 2387 from the target/sim again. We're just invalidating the regcache 2388 so that a re-read happens next time it's necessary. */ 2389 int bregnum; 2390 2391 regcache_raw_write (regcache, BANK_REGNUM, buffer); 2392 for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum) 2393 regcache_invalidate (regcache, bregnum); 2394 } 2395 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) 2396 { 2397 base_regnum = dr_reg_base_num (gdbarch, reg_nr); 2398 2399 /* We must pay attention to the endiannes. */ 2400 sh_register_convert_to_raw (register_type (gdbarch, reg_nr), 2401 reg_nr, buffer, temp_buffer); 2402 2403 /* Write the real regs for which this one is an alias. */ 2404 for (portion = 0; portion < 2; portion++) 2405 regcache_raw_write (regcache, base_regnum + portion, 2406 (temp_buffer 2407 + register_size (gdbarch, 2408 base_regnum) * portion)); 2409 } 2410 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) 2411 { 2412 base_regnum = fv_reg_base_num (gdbarch, reg_nr); 2413 2414 /* Write the real regs for which this one is an alias. */ 2415 for (portion = 0; portion < 4; portion++) 2416 regcache_raw_write (regcache, base_regnum + portion, 2417 ((char *) buffer 2418 + register_size (gdbarch, 2419 base_regnum) * portion)); 2420 } 2421} 2422 2423static int 2424sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr) 2425{ 2426 if (legacy_register_sim_regno (gdbarch, nr) < 0) 2427 return legacy_register_sim_regno (gdbarch, nr); 2428 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM) 2429 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM; 2430 if (nr == MOD_REGNUM) 2431 return SIM_SH_MOD_REGNUM; 2432 if (nr == RS_REGNUM) 2433 return SIM_SH_RS_REGNUM; 2434 if (nr == RE_REGNUM) 2435 return SIM_SH_RE_REGNUM; 2436 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM) 2437 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM; 2438 return nr; 2439} 2440 2441static int 2442sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr) 2443{ 2444 switch (nr) 2445 { 2446 case TBR_REGNUM: 2447 return SIM_SH_TBR_REGNUM; 2448 case IBNR_REGNUM: 2449 return SIM_SH_IBNR_REGNUM; 2450 case IBCR_REGNUM: 2451 return SIM_SH_IBCR_REGNUM; 2452 case BANK_REGNUM: 2453 return SIM_SH_BANK_REGNUM; 2454 case MACLB_REGNUM: 2455 return SIM_SH_BANK_MACL_REGNUM; 2456 case GBRB_REGNUM: 2457 return SIM_SH_BANK_GBR_REGNUM; 2458 case PRB_REGNUM: 2459 return SIM_SH_BANK_PR_REGNUM; 2460 case IVNB_REGNUM: 2461 return SIM_SH_BANK_IVN_REGNUM; 2462 case MACHB_REGNUM: 2463 return SIM_SH_BANK_MACH_REGNUM; 2464 default: 2465 break; 2466 } 2467 return legacy_register_sim_regno (gdbarch, nr); 2468} 2469 2470/* Set up the register unwinding such that call-clobbered registers are 2471 not displayed in frames >0 because the true value is not certain. 2472 The 'undefined' registers will show up as 'not available' unless the 2473 CFI says otherwise. 2474 2475 This function is currently set up for SH4 and compatible only. */ 2476 2477static void 2478sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, 2479 struct dwarf2_frame_state_reg *reg, 2480 struct frame_info *this_frame) 2481{ 2482 /* Mark the PC as the destination for the return address. */ 2483 if (regnum == gdbarch_pc_regnum (gdbarch)) 2484 reg->how = DWARF2_FRAME_REG_RA; 2485 2486 /* Mark the stack pointer as the call frame address. */ 2487 else if (regnum == gdbarch_sp_regnum (gdbarch)) 2488 reg->how = DWARF2_FRAME_REG_CFA; 2489 2490 /* The above was taken from the default init_reg in dwarf2-frame.c 2491 while the below is SH specific. */ 2492 2493 /* Caller save registers. */ 2494 else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7) 2495 || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11) 2496 || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5) 2497 || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2) 2498 || (regnum == MACH_REGNUM) 2499 || (regnum == MACL_REGNUM) 2500 || (regnum == FPUL_REGNUM) 2501 || (regnum == SR_REGNUM)) 2502 reg->how = DWARF2_FRAME_REG_UNDEFINED; 2503 2504 /* Callee save registers. */ 2505 else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15) 2506 || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15) 2507 || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8) 2508 || (regnum == FV0_REGNUM+3)) 2509 reg->how = DWARF2_FRAME_REG_SAME_VALUE; 2510 2511 /* Other registers. These are not in the ABI and may or may not 2512 mean anything in frames >0 so don't show them. */ 2513 else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15) 2514 || (regnum == GBR_REGNUM) 2515 || (regnum == VBR_REGNUM) 2516 || (regnum == FPSCR_REGNUM) 2517 || (regnum == SSR_REGNUM) 2518 || (regnum == SPC_REGNUM)) 2519 reg->how = DWARF2_FRAME_REG_UNDEFINED; 2520} 2521 2522static struct sh_frame_cache * 2523sh_alloc_frame_cache (void) 2524{ 2525 struct sh_frame_cache *cache; 2526 int i; 2527 2528 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache); 2529 2530 /* Base address. */ 2531 cache->base = 0; 2532 cache->saved_sp = 0; 2533 cache->sp_offset = 0; 2534 cache->pc = 0; 2535 2536 /* Frameless until proven otherwise. */ 2537 cache->uses_fp = 0; 2538 2539 /* Saved registers. We initialize these to -1 since zero is a valid 2540 offset (that's where fp is supposed to be stored). */ 2541 for (i = 0; i < SH_NUM_REGS; i++) 2542 { 2543 cache->saved_regs[i] = -1; 2544 } 2545 2546 return cache; 2547} 2548 2549static struct sh_frame_cache * 2550sh_frame_cache (struct frame_info *this_frame, void **this_cache) 2551{ 2552 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2553 struct sh_frame_cache *cache; 2554 CORE_ADDR current_pc; 2555 int i; 2556 2557 if (*this_cache) 2558 return *this_cache; 2559 2560 cache = sh_alloc_frame_cache (); 2561 *this_cache = cache; 2562 2563 /* In principle, for normal frames, fp holds the frame pointer, 2564 which holds the base address for the current stack frame. 2565 However, for functions that don't need it, the frame pointer is 2566 optional. For these "frameless" functions the frame pointer is 2567 actually the frame pointer of the calling frame. */ 2568 cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM); 2569 if (cache->base == 0) 2570 return cache; 2571 2572 cache->pc = get_frame_func (this_frame); 2573 current_pc = get_frame_pc (this_frame); 2574 if (cache->pc != 0) 2575 sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, this_frame); 2576 2577 if (!cache->uses_fp) 2578 { 2579 /* We didn't find a valid frame, which means that CACHE->base 2580 currently holds the frame pointer for our calling frame. If 2581 we're at the start of a function, or somewhere half-way its 2582 prologue, the function's frame probably hasn't been fully 2583 setup yet. Try to reconstruct the base address for the stack 2584 frame by looking at the stack pointer. For truly "frameless" 2585 functions this might work too. */ 2586 cache->base = get_frame_register_unsigned 2587 (this_frame, gdbarch_sp_regnum (gdbarch)); 2588 } 2589 2590 /* Now that we have the base address for the stack frame we can 2591 calculate the value of sp in the calling frame. */ 2592 cache->saved_sp = cache->base + cache->sp_offset; 2593 2594 /* Adjust all the saved registers such that they contain addresses 2595 instead of offsets. */ 2596 for (i = 0; i < SH_NUM_REGS; i++) 2597 if (cache->saved_regs[i] != -1) 2598 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4; 2599 2600 return cache; 2601} 2602 2603static struct value * 2604sh_frame_prev_register (struct frame_info *this_frame, 2605 void **this_cache, int regnum) 2606{ 2607 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2608 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); 2609 2610 gdb_assert (regnum >= 0); 2611 2612 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) 2613 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); 2614 2615 /* The PC of the previous frame is stored in the PR register of 2616 the current frame. Frob regnum so that we pull the value from 2617 the correct place. */ 2618 if (regnum == gdbarch_pc_regnum (gdbarch)) 2619 regnum = PR_REGNUM; 2620 2621 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1) 2622 return frame_unwind_got_memory (this_frame, regnum, 2623 cache->saved_regs[regnum]); 2624 2625 return frame_unwind_got_register (this_frame, regnum, regnum); 2626} 2627 2628static void 2629sh_frame_this_id (struct frame_info *this_frame, void **this_cache, 2630 struct frame_id *this_id) 2631{ 2632 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); 2633 2634 /* This marks the outermost frame. */ 2635 if (cache->base == 0) 2636 return; 2637 2638 *this_id = frame_id_build (cache->saved_sp, cache->pc); 2639} 2640 2641static const struct frame_unwind sh_frame_unwind = { 2642 NORMAL_FRAME, 2643 default_frame_unwind_stop_reason, 2644 sh_frame_this_id, 2645 sh_frame_prev_register, 2646 NULL, 2647 default_frame_sniffer 2648}; 2649 2650static CORE_ADDR 2651sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) 2652{ 2653 return frame_unwind_register_unsigned (next_frame, 2654 gdbarch_sp_regnum (gdbarch)); 2655} 2656 2657static CORE_ADDR 2658sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 2659{ 2660 return frame_unwind_register_unsigned (next_frame, 2661 gdbarch_pc_regnum (gdbarch)); 2662} 2663 2664static struct frame_id 2665sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 2666{ 2667 CORE_ADDR sp = get_frame_register_unsigned (this_frame, 2668 gdbarch_sp_regnum (gdbarch)); 2669 return frame_id_build (sp, get_frame_pc (this_frame)); 2670} 2671 2672static CORE_ADDR 2673sh_frame_base_address (struct frame_info *this_frame, void **this_cache) 2674{ 2675 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); 2676 2677 return cache->base; 2678} 2679 2680static const struct frame_base sh_frame_base = { 2681 &sh_frame_unwind, 2682 sh_frame_base_address, 2683 sh_frame_base_address, 2684 sh_frame_base_address 2685}; 2686 2687/* The epilogue is defined here as the area at the end of a function, 2688 either on the `ret' instruction itself or after an instruction which 2689 destroys the function's stack frame. */ 2690static int 2691sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) 2692{ 2693 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2694 CORE_ADDR func_addr = 0, func_end = 0; 2695 2696 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 2697 { 2698 ULONGEST inst; 2699 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes 2700 for a nop and some fixed data (e.g. big offsets) which are 2701 unfortunately also treated as part of the function (which 2702 means, they are below func_end. */ 2703 CORE_ADDR addr = func_end - 28; 2704 if (addr < func_addr + 4) 2705 addr = func_addr + 4; 2706 if (pc < addr) 2707 return 0; 2708 2709 /* First search forward until hitting an rts. */ 2710 while (addr < func_end 2711 && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order))) 2712 addr += 2; 2713 if (addr >= func_end) 2714 return 0; 2715 2716 /* At this point we should find a mov.l @r15+,r14 instruction, 2717 either before or after the rts. If not, then the function has 2718 probably no "normal" epilogue and we bail out here. */ 2719 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); 2720 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2, 2721 byte_order))) 2722 addr -= 2; 2723 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2, 2724 byte_order))) 2725 return 0; 2726 2727 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); 2728 2729 /* Step over possible lds.l @r15+,macl. */ 2730 if (IS_MACL_LDS (inst)) 2731 { 2732 addr -= 2; 2733 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); 2734 } 2735 2736 /* Step over possible lds.l @r15+,pr. */ 2737 if (IS_LDS (inst)) 2738 { 2739 addr -= 2; 2740 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); 2741 } 2742 2743 /* Step over possible mov r14,r15. */ 2744 if (IS_MOV_FP_SP (inst)) 2745 { 2746 addr -= 2; 2747 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); 2748 } 2749 2750 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14 2751 instructions. */ 2752 while (addr > func_addr + 4 2753 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst))) 2754 { 2755 addr -= 2; 2756 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); 2757 } 2758 2759 /* On SH2a check if the previous instruction was perhaps a MOVI20. 2760 That's allowed for the epilogue. */ 2761 if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a 2762 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu) 2763 && addr > func_addr + 6 2764 && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2, 2765 byte_order))) 2766 addr -= 4; 2767 2768 if (pc >= addr) 2769 return 1; 2770 } 2771 return 0; 2772} 2773 2774 2775/* Supply register REGNUM from the buffer specified by REGS and LEN 2776 in the register set REGSET to register cache REGCACHE. 2777 REGTABLE specifies where each register can be found in REGS. 2778 If REGNUM is -1, do this for all registers in REGSET. */ 2779 2780void 2781sh_corefile_supply_regset (const struct regset *regset, 2782 struct regcache *regcache, 2783 int regnum, const void *regs, size_t len) 2784{ 2785 struct gdbarch *gdbarch = get_regcache_arch (regcache); 2786 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2787 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset 2788 ? tdep->core_gregmap 2789 : tdep->core_fpregmap); 2790 int i; 2791 2792 for (i = 0; regmap[i].regnum != -1; i++) 2793 { 2794 if ((regnum == -1 || regnum == regmap[i].regnum) 2795 && regmap[i].offset + 4 <= len) 2796 regcache_raw_supply (regcache, regmap[i].regnum, 2797 (char *)regs + regmap[i].offset); 2798 } 2799} 2800 2801/* Collect register REGNUM in the register set REGSET from register cache 2802 REGCACHE into the buffer specified by REGS and LEN. 2803 REGTABLE specifies where each register can be found in REGS. 2804 If REGNUM is -1, do this for all registers in REGSET. */ 2805 2806void 2807sh_corefile_collect_regset (const struct regset *regset, 2808 const struct regcache *regcache, 2809 int regnum, void *regs, size_t len) 2810{ 2811 struct gdbarch *gdbarch = get_regcache_arch (regcache); 2812 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2813 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset 2814 ? tdep->core_gregmap 2815 : tdep->core_fpregmap); 2816 int i; 2817 2818 for (i = 0; regmap[i].regnum != -1; i++) 2819 { 2820 if ((regnum == -1 || regnum == regmap[i].regnum) 2821 && regmap[i].offset + 4 <= len) 2822 regcache_raw_collect (regcache, regmap[i].regnum, 2823 (char *)regs + regmap[i].offset); 2824 } 2825} 2826 2827/* The following two regsets have the same contents, so it is tempting to 2828 unify them, but they are distiguished by their address, so don't. */ 2829 2830struct regset sh_corefile_gregset = 2831{ 2832 NULL, 2833 sh_corefile_supply_regset, 2834 sh_corefile_collect_regset 2835}; 2836 2837static struct regset sh_corefile_fpregset = 2838{ 2839 NULL, 2840 sh_corefile_supply_regset, 2841 sh_corefile_collect_regset 2842}; 2843 2844static const struct regset * 2845sh_regset_from_core_section (struct gdbarch *gdbarch, const char *sect_name, 2846 size_t sect_size) 2847{ 2848 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2849 2850 if (tdep->core_gregmap && strcmp (sect_name, ".reg") == 0) 2851 return &sh_corefile_gregset; 2852 2853 if (tdep->core_fpregmap && strcmp (sect_name, ".reg2") == 0) 2854 return &sh_corefile_fpregset; 2855 2856 return NULL; 2857} 2858 2859 2860static struct gdbarch * 2861sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 2862{ 2863 struct gdbarch *gdbarch; 2864 struct gdbarch_tdep *tdep; 2865 2866 sh_show_regs = sh_generic_show_regs; 2867 switch (info.bfd_arch_info->mach) 2868 { 2869 case bfd_mach_sh2e: 2870 sh_show_regs = sh2e_show_regs; 2871 break; 2872 case bfd_mach_sh2a: 2873 sh_show_regs = sh2a_show_regs; 2874 break; 2875 case bfd_mach_sh2a_nofpu: 2876 sh_show_regs = sh2a_nofpu_show_regs; 2877 break; 2878 case bfd_mach_sh_dsp: 2879 sh_show_regs = sh_dsp_show_regs; 2880 break; 2881 2882 case bfd_mach_sh3: 2883 case bfd_mach_sh3_nommu: 2884 case bfd_mach_sh2a_nofpu_or_sh3_nommu: 2885 sh_show_regs = sh3_show_regs; 2886 break; 2887 2888 case bfd_mach_sh3e: 2889 case bfd_mach_sh2a_or_sh3e: 2890 sh_show_regs = sh3e_show_regs; 2891 break; 2892 2893 case bfd_mach_sh3_dsp: 2894 case bfd_mach_sh4al_dsp: 2895 sh_show_regs = sh3_dsp_show_regs; 2896 break; 2897 2898 case bfd_mach_sh4: 2899 case bfd_mach_sh4a: 2900 case bfd_mach_sh2a_or_sh4: 2901 sh_show_regs = sh4_show_regs; 2902 break; 2903 2904 case bfd_mach_sh4_nofpu: 2905 case bfd_mach_sh4_nommu_nofpu: 2906 case bfd_mach_sh4a_nofpu: 2907 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu: 2908 sh_show_regs = sh4_nofpu_show_regs; 2909 break; 2910 2911 case bfd_mach_sh5: 2912 sh_show_regs = sh64_show_regs; 2913 /* SH5 is handled entirely in sh64-tdep.c. */ 2914 return sh64_gdbarch_init (info, arches); 2915 } 2916 2917 /* If there is already a candidate, use it. */ 2918 arches = gdbarch_list_lookup_by_info (arches, &info); 2919 if (arches != NULL) 2920 return arches->gdbarch; 2921 2922 /* None found, create a new architecture from the information 2923 provided. */ 2924 tdep = XZALLOC (struct gdbarch_tdep); 2925 gdbarch = gdbarch_alloc (&info, tdep); 2926 2927 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); 2928 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2929 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2930 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); 2931 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2932 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); 2933 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); 2934 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2935 2936 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS); 2937 set_gdbarch_sp_regnum (gdbarch, 15); 2938 set_gdbarch_pc_regnum (gdbarch, 16); 2939 set_gdbarch_fp0_regnum (gdbarch, -1); 2940 set_gdbarch_num_pseudo_regs (gdbarch, 0); 2941 2942 set_gdbarch_register_type (gdbarch, sh_default_register_type); 2943 set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p); 2944 2945 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc); 2946 2947 set_gdbarch_print_insn (gdbarch, print_insn_sh); 2948 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); 2949 2950 set_gdbarch_return_value (gdbarch, sh_return_value_nofpu); 2951 2952 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); 2953 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 2954 2955 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); 2956 2957 set_gdbarch_believe_pcc_promotion (gdbarch, 1); 2958 2959 set_gdbarch_frame_align (gdbarch, sh_frame_align); 2960 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp); 2961 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc); 2962 set_gdbarch_dummy_id (gdbarch, sh_dummy_id); 2963 frame_base_set_default (gdbarch, &sh_frame_base); 2964 2965 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p); 2966 2967 dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg); 2968 2969 set_gdbarch_regset_from_core_section (gdbarch, sh_regset_from_core_section); 2970 2971 switch (info.bfd_arch_info->mach) 2972 { 2973 case bfd_mach_sh: 2974 set_gdbarch_register_name (gdbarch, sh_sh_register_name); 2975 break; 2976 2977 case bfd_mach_sh2: 2978 set_gdbarch_register_name (gdbarch, sh_sh_register_name); 2979 break; 2980 2981 case bfd_mach_sh2e: 2982 /* doubles on sh2e and sh3e are actually 4 byte. */ 2983 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2984 2985 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name); 2986 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); 2987 set_gdbarch_fp0_regnum (gdbarch, 25); 2988 set_gdbarch_return_value (gdbarch, sh_return_value_fpu); 2989 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); 2990 break; 2991 2992 case bfd_mach_sh2a: 2993 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name); 2994 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type); 2995 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); 2996 2997 set_gdbarch_fp0_regnum (gdbarch, 25); 2998 set_gdbarch_num_pseudo_regs (gdbarch, 9); 2999 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); 3000 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); 3001 set_gdbarch_return_value (gdbarch, sh_return_value_fpu); 3002 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); 3003 break; 3004 3005 case bfd_mach_sh2a_nofpu: 3006 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name); 3007 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); 3008 3009 set_gdbarch_num_pseudo_regs (gdbarch, 1); 3010 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); 3011 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); 3012 break; 3013 3014 case bfd_mach_sh_dsp: 3015 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name); 3016 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); 3017 break; 3018 3019 case bfd_mach_sh3: 3020 case bfd_mach_sh3_nommu: 3021 case bfd_mach_sh2a_nofpu_or_sh3_nommu: 3022 set_gdbarch_register_name (gdbarch, sh_sh3_register_name); 3023 break; 3024 3025 case bfd_mach_sh3e: 3026 case bfd_mach_sh2a_or_sh3e: 3027 /* doubles on sh2e and sh3e are actually 4 byte. */ 3028 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); 3029 3030 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name); 3031 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); 3032 set_gdbarch_fp0_regnum (gdbarch, 25); 3033 set_gdbarch_return_value (gdbarch, sh_return_value_fpu); 3034 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); 3035 break; 3036 3037 case bfd_mach_sh3_dsp: 3038 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name); 3039 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); 3040 break; 3041 3042 case bfd_mach_sh4: 3043 case bfd_mach_sh4a: 3044 case bfd_mach_sh2a_or_sh4: 3045 set_gdbarch_register_name (gdbarch, sh_sh4_register_name); 3046 set_gdbarch_register_type (gdbarch, sh_sh4_register_type); 3047 set_gdbarch_fp0_regnum (gdbarch, 25); 3048 set_gdbarch_num_pseudo_regs (gdbarch, 13); 3049 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); 3050 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); 3051 set_gdbarch_return_value (gdbarch, sh_return_value_fpu); 3052 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); 3053 break; 3054 3055 case bfd_mach_sh4_nofpu: 3056 case bfd_mach_sh4a_nofpu: 3057 case bfd_mach_sh4_nommu_nofpu: 3058 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu: 3059 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name); 3060 break; 3061 3062 case bfd_mach_sh4al_dsp: 3063 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name); 3064 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); 3065 break; 3066 3067 default: 3068 set_gdbarch_register_name (gdbarch, sh_sh_register_name); 3069 break; 3070 } 3071 3072 /* Hook in ABI-specific overrides, if they have been registered. */ 3073 gdbarch_init_osabi (info, gdbarch); 3074 3075 dwarf2_append_unwinders (gdbarch); 3076 frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind); 3077 3078 return gdbarch; 3079} 3080 3081static void 3082show_sh_command (char *args, int from_tty) 3083{ 3084 help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout); 3085} 3086 3087static void 3088set_sh_command (char *args, int from_tty) 3089{ 3090 printf_unfiltered 3091 ("\"set sh\" must be followed by an appropriate subcommand.\n"); 3092 help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout); 3093} 3094 3095extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */ 3096 3097void 3098_initialize_sh_tdep (void) 3099{ 3100 struct cmd_list_element *c; 3101 3102 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL); 3103 3104 add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers")); 3105 3106 add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.", 3107 &setshcmdlist, "set sh ", 0, &setlist); 3108 add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.", 3109 &showshcmdlist, "show sh ", 0, &showlist); 3110 3111 add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum, 3112 &sh_active_calling_convention, 3113 _("Set calling convention used when calling target " 3114 "functions from GDB."), 3115 _("Show calling convention used when calling target " 3116 "functions from GDB."), 3117 _("gcc - Use GCC calling convention (default).\n" 3118 "renesas - Enforce Renesas calling convention."), 3119 NULL, NULL, 3120 &setshcmdlist, &showshcmdlist); 3121} 3122