1/* Target-dependent code for the Toshiba MeP for GDB, the GNU debugger. 2 3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 4 2011 Free Software Foundation, Inc. 5 6 Contributed by Red Hat, Inc. 7 8 This file is part of GDB. 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 22 23#include "defs.h" 24#include "frame.h" 25#include "frame-unwind.h" 26#include "frame-base.h" 27#include "symtab.h" 28#include "gdbtypes.h" 29#include "gdbcmd.h" 30#include "gdbcore.h" 31#include "gdb_string.h" 32#include "value.h" 33#include "inferior.h" 34#include "dis-asm.h" 35#include "symfile.h" 36#include "objfiles.h" 37#include "language.h" 38#include "arch-utils.h" 39#include "regcache.h" 40#include "remote.h" 41#include "floatformat.h" 42#include "sim-regno.h" 43#include "disasm.h" 44#include "trad-frame.h" 45#include "reggroups.h" 46#include "elf-bfd.h" 47#include "elf/mep.h" 48#include "prologue-value.h" 49#include "cgen/bitset.h" 50#include "infcall.h" 51 52#include "gdb_assert.h" 53 54/* Get the user's customized MeP coprocessor register names from 55 libopcodes. */ 56#include "opcodes/mep-desc.h" 57#include "opcodes/mep-opc.h" 58 59 60/* The gdbarch_tdep structure. */ 61 62/* A quick recap for GDB hackers not familiar with the whole Toshiba 63 Media Processor story: 64 65 The MeP media engine is a configureable processor: users can design 66 their own coprocessors, implement custom instructions, adjust cache 67 sizes, select optional standard facilities like add-and-saturate 68 instructions, and so on. Then, they can build custom versions of 69 the GNU toolchain to support their customized chips. The 70 MeP-Integrator program (see utils/mep) takes a GNU toolchain source 71 tree, and a config file pointing to various files provided by the 72 user describing their customizations, and edits the source tree to 73 produce a compiler that can generate their custom instructions, an 74 assembler that can assemble them and recognize their custom 75 register names, and so on. 76 77 Furthermore, the user can actually specify several of these custom 78 configurations, called 'me_modules', and get a toolchain which can 79 produce code for any of them, given a compiler/assembler switch; 80 you say something like 'gcc -mconfig=mm_max' to generate code for 81 the me_module named 'mm_max'. 82 83 GDB, in particular, needs to: 84 85 - use the coprocessor control register names provided by the user 86 in their hardware description, in expressions, 'info register' 87 output, and disassembly, 88 89 - know the number, names, and types of the coprocessor's 90 general-purpose registers, adjust the 'info all-registers' output 91 accordingly, and print error messages if the user refers to one 92 that doesn't exist 93 94 - allow access to the control bus space only when the configuration 95 actually has a control bus, and recognize which regions of the 96 control bus space are actually populated, 97 98 - disassemble using the user's provided mnemonics for their custom 99 instructions, and 100 101 - recognize whether the $hi and $lo registers are present, and 102 allow access to them only when they are actually there. 103 104 There are three sources of information about what sort of me_module 105 we're actually dealing with: 106 107 - A MeP executable file indicates which me_module it was compiled 108 for, and libopcodes has tables describing each module. So, given 109 an executable file, we can find out about the processor it was 110 compiled for. 111 112 - There are SID command-line options to select a particular 113 me_module, overriding the one specified in the ELF file. SID 114 provides GDB with a fake read-only register, 'module', which 115 indicates which me_module GDB is communicating with an instance 116 of. 117 118 - There are SID command-line options to enable or disable certain 119 optional processor features, overriding the defaults for the 120 selected me_module. The MeP $OPT register indicates which 121 options are present on the current processor. */ 122 123 124struct gdbarch_tdep 125{ 126 /* A CGEN cpu descriptor for this BFD architecture and machine. 127 128 Note: this is *not* customized for any particular me_module; the 129 MeP libopcodes machinery actually puts off module-specific 130 customization until the last minute. So this contains 131 information about all supported me_modules. */ 132 CGEN_CPU_DESC cpu_desc; 133 134 /* The me_module index from the ELF file we used to select this 135 architecture, or CONFIG_NONE if there was none. 136 137 Note that we should prefer to use the me_module number available 138 via the 'module' register, whenever we're actually talking to a 139 real target. 140 141 In the absence of live information, we'd like to get the 142 me_module number from the ELF file. But which ELF file: the 143 executable file, the core file, ... ? The answer is, "the last 144 ELF file we used to set the current architecture". Thus, we 145 create a separate instance of the gdbarch structure for each 146 me_module value mep_gdbarch_init sees, and store the me_module 147 value from the ELF file here. */ 148 CONFIG_ATTR me_module; 149}; 150 151 152 153/* Getting me_module information from the CGEN tables. */ 154 155 156/* Find an entry in the DESC's hardware table whose name begins with 157 PREFIX, and whose ISA mask intersects COPRO_ISA_MASK, but does not 158 intersect with GENERIC_ISA_MASK. If there is no matching entry, 159 return zero. */ 160static const CGEN_HW_ENTRY * 161find_hw_entry_by_prefix_and_isa (CGEN_CPU_DESC desc, 162 const char *prefix, 163 CGEN_BITSET *copro_isa_mask, 164 CGEN_BITSET *generic_isa_mask) 165{ 166 int prefix_len = strlen (prefix); 167 int i; 168 169 for (i = 0; i < desc->hw_table.num_entries; i++) 170 { 171 const CGEN_HW_ENTRY *hw = desc->hw_table.entries[i]; 172 if (strncmp (prefix, hw->name, prefix_len) == 0) 173 { 174 CGEN_BITSET *hw_isa_mask 175 = ((CGEN_BITSET *) 176 &CGEN_ATTR_CGEN_HW_ISA_VALUE (CGEN_HW_ATTRS (hw))); 177 178 if (cgen_bitset_intersect_p (hw_isa_mask, copro_isa_mask) 179 && ! cgen_bitset_intersect_p (hw_isa_mask, generic_isa_mask)) 180 return hw; 181 } 182 } 183 184 return 0; 185} 186 187 188/* Find an entry in DESC's hardware table whose type is TYPE. Return 189 zero if there is none. */ 190static const CGEN_HW_ENTRY * 191find_hw_entry_by_type (CGEN_CPU_DESC desc, CGEN_HW_TYPE type) 192{ 193 int i; 194 195 for (i = 0; i < desc->hw_table.num_entries; i++) 196 { 197 const CGEN_HW_ENTRY *hw = desc->hw_table.entries[i]; 198 199 if (hw->type == type) 200 return hw; 201 } 202 203 return 0; 204} 205 206 207/* Return the CGEN hardware table entry for the coprocessor register 208 set for ME_MODULE, whose name prefix is PREFIX. If ME_MODULE has 209 no such register set, return zero. If ME_MODULE is the generic 210 me_module CONFIG_NONE, return the table entry for the register set 211 whose hardware type is GENERIC_TYPE. */ 212static const CGEN_HW_ENTRY * 213me_module_register_set (CONFIG_ATTR me_module, 214 const char *prefix, 215 CGEN_HW_TYPE generic_type) 216{ 217 /* This is kind of tricky, because the hardware table is constructed 218 in a way that isn't very helpful. Perhaps we can fix that, but 219 here's how it works at the moment: 220 221 The configuration map, `mep_config_map', is indexed by me_module 222 number, and indicates which coprocessor and core ISAs that 223 me_module supports. The 'core_isa' mask includes all the core 224 ISAs, and the 'cop_isa' mask includes all the coprocessor ISAs. 225 The entry for the generic me_module, CONFIG_NONE, has an empty 226 'cop_isa', and its 'core_isa' selects only the standard MeP 227 instruction set. 228 229 The CGEN CPU descriptor's hardware table, desc->hw_table, has 230 entries for all the register sets, for all me_modules. Each 231 entry has a mask indicating which ISAs use that register set. 232 So, if an me_module supports some coprocessor ISA, we can find 233 applicable register sets by scanning the hardware table for 234 register sets whose masks include (at least some of) those ISAs. 235 236 Each hardware table entry also has a name, whose prefix says 237 whether it's a general-purpose ("h-cr") or control ("h-ccr") 238 coprocessor register set. It might be nicer to have an attribute 239 indicating what sort of register set it was, that we could use 240 instead of pattern-matching on the name. 241 242 When there is no hardware table entry whose mask includes a 243 particular coprocessor ISA and whose name starts with a given 244 prefix, then that means that that coprocessor doesn't have any 245 registers of that type. In such cases, this function must return 246 a null pointer. 247 248 Coprocessor register sets' masks may or may not include the core 249 ISA for the me_module they belong to. Those generated by a2cgen 250 do, but the sample me_module included in the unconfigured tree, 251 'ccfx', does not. 252 253 There are generic coprocessor register sets, intended only for 254 use with the generic me_module. Unfortunately, their masks 255 include *all* ISAs --- even those for coprocessors that don't 256 have such register sets. This makes detecting the case where a 257 coprocessor lacks a particular register set more complicated. 258 259 So, here's the approach we take: 260 261 - For CONFIG_NONE, we return the generic coprocessor register set. 262 263 - For any other me_module, we search for a register set whose 264 mask contains any of the me_module's coprocessor ISAs, 265 specifically excluding the generic coprocessor register sets. */ 266 267 CGEN_CPU_DESC desc = gdbarch_tdep (target_gdbarch)->cpu_desc; 268 const CGEN_HW_ENTRY *hw; 269 270 if (me_module == CONFIG_NONE) 271 hw = find_hw_entry_by_type (desc, generic_type); 272 else 273 { 274 CGEN_BITSET *cop = &mep_config_map[me_module].cop_isa; 275 CGEN_BITSET *core = &mep_config_map[me_module].core_isa; 276 CGEN_BITSET *generic = &mep_config_map[CONFIG_NONE].core_isa; 277 CGEN_BITSET *cop_and_core; 278 279 /* The coprocessor ISAs include the ISA for the specific core which 280 has that coprocessor. */ 281 cop_and_core = cgen_bitset_copy (cop); 282 cgen_bitset_union (cop, core, cop_and_core); 283 hw = find_hw_entry_by_prefix_and_isa (desc, prefix, cop_and_core, generic); 284 } 285 286 return hw; 287} 288 289 290/* Given a hardware table entry HW representing a register set, return 291 a pointer to the keyword table with all the register names. If HW 292 is NULL, return NULL, to propage the "no such register set" info 293 along. */ 294static CGEN_KEYWORD * 295register_set_keyword_table (const CGEN_HW_ENTRY *hw) 296{ 297 if (! hw) 298 return NULL; 299 300 /* Check that HW is actually a keyword table. */ 301 gdb_assert (hw->asm_type == CGEN_ASM_KEYWORD); 302 303 /* The 'asm_data' field of a register set's hardware table entry 304 refers to a keyword table. */ 305 return (CGEN_KEYWORD *) hw->asm_data; 306} 307 308 309/* Given a keyword table KEYWORD and a register number REGNUM, return 310 the name of the register, or "" if KEYWORD contains no register 311 whose number is REGNUM. */ 312static char * 313register_name_from_keyword (CGEN_KEYWORD *keyword_table, int regnum) 314{ 315 const CGEN_KEYWORD_ENTRY *entry 316 = cgen_keyword_lookup_value (keyword_table, regnum); 317 318 if (entry) 319 { 320 char *name = entry->name; 321 322 /* The CGEN keyword entries for register names include the 323 leading $, which appears in MeP assembly as well as in GDB. 324 But we don't want to return that; GDB core code adds that 325 itself. */ 326 if (name[0] == '$') 327 name++; 328 329 return name; 330 } 331 else 332 return ""; 333} 334 335 336/* Masks for option bits in the OPT special-purpose register. */ 337enum { 338 MEP_OPT_DIV = 1 << 25, /* 32-bit divide instruction option */ 339 MEP_OPT_MUL = 1 << 24, /* 32-bit multiply instruction option */ 340 MEP_OPT_BIT = 1 << 23, /* bit manipulation instruction option */ 341 MEP_OPT_SAT = 1 << 22, /* saturation instruction option */ 342 MEP_OPT_CLP = 1 << 21, /* clip instruction option */ 343 MEP_OPT_MIN = 1 << 20, /* min/max instruction option */ 344 MEP_OPT_AVE = 1 << 19, /* average instruction option */ 345 MEP_OPT_ABS = 1 << 18, /* absolute difference instruction option */ 346 MEP_OPT_LDZ = 1 << 16, /* leading zero instruction option */ 347 MEP_OPT_VL64 = 1 << 6, /* 64-bit VLIW operation mode option */ 348 MEP_OPT_VL32 = 1 << 5, /* 32-bit VLIW operation mode option */ 349 MEP_OPT_COP = 1 << 4, /* coprocessor option */ 350 MEP_OPT_DSP = 1 << 2, /* DSP option */ 351 MEP_OPT_UCI = 1 << 1, /* UCI option */ 352 MEP_OPT_DBG = 1 << 0, /* DBG function option */ 353}; 354 355 356/* Given the option_mask value for a particular entry in 357 mep_config_map, produce the value the processor's OPT register 358 would use to represent the same set of options. */ 359static unsigned int 360opt_from_option_mask (unsigned int option_mask) 361{ 362 /* A table mapping OPT register bits onto CGEN config map option 363 bits. */ 364 struct { 365 unsigned int opt_bit, option_mask_bit; 366 } bits[] = { 367 { MEP_OPT_DIV, 1 << CGEN_INSN_OPTIONAL_DIV_INSN }, 368 { MEP_OPT_MUL, 1 << CGEN_INSN_OPTIONAL_MUL_INSN }, 369 { MEP_OPT_DIV, 1 << CGEN_INSN_OPTIONAL_DIV_INSN }, 370 { MEP_OPT_DBG, 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN }, 371 { MEP_OPT_LDZ, 1 << CGEN_INSN_OPTIONAL_LDZ_INSN }, 372 { MEP_OPT_ABS, 1 << CGEN_INSN_OPTIONAL_ABS_INSN }, 373 { MEP_OPT_AVE, 1 << CGEN_INSN_OPTIONAL_AVE_INSN }, 374 { MEP_OPT_MIN, 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN }, 375 { MEP_OPT_CLP, 1 << CGEN_INSN_OPTIONAL_CLIP_INSN }, 376 { MEP_OPT_SAT, 1 << CGEN_INSN_OPTIONAL_SAT_INSN }, 377 { MEP_OPT_UCI, 1 << CGEN_INSN_OPTIONAL_UCI_INSN }, 378 { MEP_OPT_DSP, 1 << CGEN_INSN_OPTIONAL_DSP_INSN }, 379 { MEP_OPT_COP, 1 << CGEN_INSN_OPTIONAL_CP_INSN }, 380 }; 381 382 int i; 383 unsigned int opt = 0; 384 385 for (i = 0; i < (sizeof (bits) / sizeof (bits[0])); i++) 386 if (option_mask & bits[i].option_mask_bit) 387 opt |= bits[i].opt_bit; 388 389 return opt; 390} 391 392 393/* Return the value the $OPT register would use to represent the set 394 of options for ME_MODULE. */ 395static unsigned int 396me_module_opt (CONFIG_ATTR me_module) 397{ 398 return opt_from_option_mask (mep_config_map[me_module].option_mask); 399} 400 401 402/* Return the width of ME_MODULE's coprocessor data bus, in bits. 403 This is either 32 or 64. */ 404static int 405me_module_cop_data_bus_width (CONFIG_ATTR me_module) 406{ 407 if (mep_config_map[me_module].option_mask 408 & (1 << CGEN_INSN_OPTIONAL_CP64_INSN)) 409 return 64; 410 else 411 return 32; 412} 413 414 415/* Return true if ME_MODULE is big-endian, false otherwise. */ 416static int 417me_module_big_endian (CONFIG_ATTR me_module) 418{ 419 return mep_config_map[me_module].big_endian; 420} 421 422 423/* Return the name of ME_MODULE, or NULL if it has no name. */ 424static const char * 425me_module_name (CONFIG_ATTR me_module) 426{ 427 /* The default me_module has "" as its name, but it's easier for our 428 callers to test for NULL. */ 429 if (! mep_config_map[me_module].name 430 || mep_config_map[me_module].name[0] == '\0') 431 return NULL; 432 else 433 return mep_config_map[me_module].name; 434} 435 436/* Register set. */ 437 438 439/* The MeP spec defines the following registers: 440 16 general purpose registers (r0-r15) 441 32 control/special registers (csr0-csr31) 442 32 coprocessor general-purpose registers (c0 -- c31) 443 64 coprocessor control registers (ccr0 -- ccr63) 444 445 For the raw registers, we assign numbers here explicitly, instead 446 of letting the enum assign them for us; the numbers are a matter of 447 external protocol, and shouldn't shift around as things are edited. 448 449 We access the control/special registers via pseudoregisters, to 450 enforce read-only portions that some registers have. 451 452 We access the coprocessor general purpose and control registers via 453 pseudoregisters, to make sure they appear in the proper order in 454 the 'info all-registers' command (which uses the register number 455 ordering), and also to allow them to be renamed and resized 456 depending on the me_module in use. 457 458 The MeP allows coprocessor general-purpose registers to be either 459 32 or 64 bits long, depending on the configuration. Since we don't 460 want the format of the 'g' packet to vary from one core to another, 461 the raw coprocessor GPRs are always 64 bits. GDB doesn't allow the 462 types of registers to change (see the implementation of 463 register_type), so we have four banks of pseudoregisters for the 464 coprocessor gprs --- 32-bit vs. 64-bit, and integer 465 vs. floating-point --- and we show or hide them depending on the 466 configuration. */ 467enum 468{ 469 MEP_FIRST_RAW_REGNUM = 0, 470 471 MEP_FIRST_GPR_REGNUM = 0, 472 MEP_R0_REGNUM = 0, 473 MEP_R1_REGNUM = 1, 474 MEP_R2_REGNUM = 2, 475 MEP_R3_REGNUM = 3, 476 MEP_R4_REGNUM = 4, 477 MEP_R5_REGNUM = 5, 478 MEP_R6_REGNUM = 6, 479 MEP_R7_REGNUM = 7, 480 MEP_R8_REGNUM = 8, 481 MEP_R9_REGNUM = 9, 482 MEP_R10_REGNUM = 10, 483 MEP_R11_REGNUM = 11, 484 MEP_R12_REGNUM = 12, 485 MEP_FP_REGNUM = MEP_R8_REGNUM, 486 MEP_R13_REGNUM = 13, 487 MEP_TP_REGNUM = MEP_R13_REGNUM, /* (r13) Tiny data pointer */ 488 MEP_R14_REGNUM = 14, 489 MEP_GP_REGNUM = MEP_R14_REGNUM, /* (r14) Global pointer */ 490 MEP_R15_REGNUM = 15, 491 MEP_SP_REGNUM = MEP_R15_REGNUM, /* (r15) Stack pointer */ 492 MEP_LAST_GPR_REGNUM = MEP_R15_REGNUM, 493 494 /* The raw control registers. These are the values as received via 495 the remote protocol, directly from the target; we only let user 496 code touch the via the pseudoregisters, which enforce read-only 497 bits. */ 498 MEP_FIRST_RAW_CSR_REGNUM = 16, 499 MEP_RAW_PC_REGNUM = 16, /* Program counter */ 500 MEP_RAW_LP_REGNUM = 17, /* Link pointer */ 501 MEP_RAW_SAR_REGNUM = 18, /* Raw shift amount */ 502 MEP_RAW_CSR3_REGNUM = 19, /* csr3: reserved */ 503 MEP_RAW_RPB_REGNUM = 20, /* Raw repeat begin address */ 504 MEP_RAW_RPE_REGNUM = 21, /* Repeat end address */ 505 MEP_RAW_RPC_REGNUM = 22, /* Repeat count */ 506 MEP_RAW_HI_REGNUM = 23, /* Upper 32 bits of result of 64 bit mult/div */ 507 MEP_RAW_LO_REGNUM = 24, /* Lower 32 bits of result of 64 bit mult/div */ 508 MEP_RAW_CSR9_REGNUM = 25, /* csr3: reserved */ 509 MEP_RAW_CSR10_REGNUM = 26, /* csr3: reserved */ 510 MEP_RAW_CSR11_REGNUM = 27, /* csr3: reserved */ 511 MEP_RAW_MB0_REGNUM = 28, /* Raw modulo begin address 0 */ 512 MEP_RAW_ME0_REGNUM = 29, /* Raw modulo end address 0 */ 513 MEP_RAW_MB1_REGNUM = 30, /* Raw modulo begin address 1 */ 514 MEP_RAW_ME1_REGNUM = 31, /* Raw modulo end address 1 */ 515 MEP_RAW_PSW_REGNUM = 32, /* Raw program status word */ 516 MEP_RAW_ID_REGNUM = 33, /* Raw processor ID/revision */ 517 MEP_RAW_TMP_REGNUM = 34, /* Temporary */ 518 MEP_RAW_EPC_REGNUM = 35, /* Exception program counter */ 519 MEP_RAW_EXC_REGNUM = 36, /* Raw exception cause */ 520 MEP_RAW_CFG_REGNUM = 37, /* Raw processor configuration*/ 521 MEP_RAW_CSR22_REGNUM = 38, /* csr3: reserved */ 522 MEP_RAW_NPC_REGNUM = 39, /* Nonmaskable interrupt PC */ 523 MEP_RAW_DBG_REGNUM = 40, /* Raw debug */ 524 MEP_RAW_DEPC_REGNUM = 41, /* Debug exception PC */ 525 MEP_RAW_OPT_REGNUM = 42, /* Raw options */ 526 MEP_RAW_RCFG_REGNUM = 43, /* Raw local ram config */ 527 MEP_RAW_CCFG_REGNUM = 44, /* Raw cache config */ 528 MEP_RAW_CSR29_REGNUM = 45, /* csr3: reserved */ 529 MEP_RAW_CSR30_REGNUM = 46, /* csr3: reserved */ 530 MEP_RAW_CSR31_REGNUM = 47, /* csr3: reserved */ 531 MEP_LAST_RAW_CSR_REGNUM = MEP_RAW_CSR31_REGNUM, 532 533 /* The raw coprocessor general-purpose registers. These are all 64 534 bits wide. */ 535 MEP_FIRST_RAW_CR_REGNUM = 48, 536 MEP_LAST_RAW_CR_REGNUM = MEP_FIRST_RAW_CR_REGNUM + 31, 537 538 MEP_FIRST_RAW_CCR_REGNUM = 80, 539 MEP_LAST_RAW_CCR_REGNUM = MEP_FIRST_RAW_CCR_REGNUM + 63, 540 541 /* The module number register. This is the index of the me_module 542 of which the current target is an instance. (This is not a real 543 MeP-specified register; it's provided by SID.) */ 544 MEP_MODULE_REGNUM, 545 546 MEP_LAST_RAW_REGNUM = MEP_MODULE_REGNUM, 547 548 MEP_NUM_RAW_REGS = MEP_LAST_RAW_REGNUM + 1, 549 550 /* Pseudoregisters. See mep_pseudo_register_read and 551 mep_pseudo_register_write. */ 552 MEP_FIRST_PSEUDO_REGNUM = MEP_NUM_RAW_REGS, 553 554 /* We have a pseudoregister for every control/special register, to 555 implement registers with read-only bits. */ 556 MEP_FIRST_CSR_REGNUM = MEP_FIRST_PSEUDO_REGNUM, 557 MEP_PC_REGNUM = MEP_FIRST_CSR_REGNUM, /* Program counter */ 558 MEP_LP_REGNUM, /* Link pointer */ 559 MEP_SAR_REGNUM, /* shift amount */ 560 MEP_CSR3_REGNUM, /* csr3: reserved */ 561 MEP_RPB_REGNUM, /* repeat begin address */ 562 MEP_RPE_REGNUM, /* Repeat end address */ 563 MEP_RPC_REGNUM, /* Repeat count */ 564 MEP_HI_REGNUM, /* Upper 32 bits of the result of 64 bit mult/div */ 565 MEP_LO_REGNUM, /* Lower 32 bits of the result of 64 bit mult/div */ 566 MEP_CSR9_REGNUM, /* csr3: reserved */ 567 MEP_CSR10_REGNUM, /* csr3: reserved */ 568 MEP_CSR11_REGNUM, /* csr3: reserved */ 569 MEP_MB0_REGNUM, /* modulo begin address 0 */ 570 MEP_ME0_REGNUM, /* modulo end address 0 */ 571 MEP_MB1_REGNUM, /* modulo begin address 1 */ 572 MEP_ME1_REGNUM, /* modulo end address 1 */ 573 MEP_PSW_REGNUM, /* program status word */ 574 MEP_ID_REGNUM, /* processor ID/revision */ 575 MEP_TMP_REGNUM, /* Temporary */ 576 MEP_EPC_REGNUM, /* Exception program counter */ 577 MEP_EXC_REGNUM, /* exception cause */ 578 MEP_CFG_REGNUM, /* processor configuration*/ 579 MEP_CSR22_REGNUM, /* csr3: reserved */ 580 MEP_NPC_REGNUM, /* Nonmaskable interrupt PC */ 581 MEP_DBG_REGNUM, /* debug */ 582 MEP_DEPC_REGNUM, /* Debug exception PC */ 583 MEP_OPT_REGNUM, /* options */ 584 MEP_RCFG_REGNUM, /* local ram config */ 585 MEP_CCFG_REGNUM, /* cache config */ 586 MEP_CSR29_REGNUM, /* csr3: reserved */ 587 MEP_CSR30_REGNUM, /* csr3: reserved */ 588 MEP_CSR31_REGNUM, /* csr3: reserved */ 589 MEP_LAST_CSR_REGNUM = MEP_CSR31_REGNUM, 590 591 /* The 32-bit integer view of the coprocessor GPR's. */ 592 MEP_FIRST_CR32_REGNUM, 593 MEP_LAST_CR32_REGNUM = MEP_FIRST_CR32_REGNUM + 31, 594 595 /* The 32-bit floating-point view of the coprocessor GPR's. */ 596 MEP_FIRST_FP_CR32_REGNUM, 597 MEP_LAST_FP_CR32_REGNUM = MEP_FIRST_FP_CR32_REGNUM + 31, 598 599 /* The 64-bit integer view of the coprocessor GPR's. */ 600 MEP_FIRST_CR64_REGNUM, 601 MEP_LAST_CR64_REGNUM = MEP_FIRST_CR64_REGNUM + 31, 602 603 /* The 64-bit floating-point view of the coprocessor GPR's. */ 604 MEP_FIRST_FP_CR64_REGNUM, 605 MEP_LAST_FP_CR64_REGNUM = MEP_FIRST_FP_CR64_REGNUM + 31, 606 607 MEP_FIRST_CCR_REGNUM, 608 MEP_LAST_CCR_REGNUM = MEP_FIRST_CCR_REGNUM + 63, 609 610 MEP_LAST_PSEUDO_REGNUM = MEP_LAST_CCR_REGNUM, 611 612 MEP_NUM_PSEUDO_REGS = (MEP_LAST_PSEUDO_REGNUM - MEP_LAST_RAW_REGNUM), 613 614 MEP_NUM_REGS = MEP_NUM_RAW_REGS + MEP_NUM_PSEUDO_REGS 615}; 616 617 618#define IN_SET(set, n) \ 619 (MEP_FIRST_ ## set ## _REGNUM <= (n) && (n) <= MEP_LAST_ ## set ## _REGNUM) 620 621#define IS_GPR_REGNUM(n) (IN_SET (GPR, (n))) 622#define IS_RAW_CSR_REGNUM(n) (IN_SET (RAW_CSR, (n))) 623#define IS_RAW_CR_REGNUM(n) (IN_SET (RAW_CR, (n))) 624#define IS_RAW_CCR_REGNUM(n) (IN_SET (RAW_CCR, (n))) 625 626#define IS_CSR_REGNUM(n) (IN_SET (CSR, (n))) 627#define IS_CR32_REGNUM(n) (IN_SET (CR32, (n))) 628#define IS_FP_CR32_REGNUM(n) (IN_SET (FP_CR32, (n))) 629#define IS_CR64_REGNUM(n) (IN_SET (CR64, (n))) 630#define IS_FP_CR64_REGNUM(n) (IN_SET (FP_CR64, (n))) 631#define IS_CR_REGNUM(n) (IS_CR32_REGNUM (n) || IS_FP_CR32_REGNUM (n) \ 632 || IS_CR64_REGNUM (n) || IS_FP_CR64_REGNUM (n)) 633#define IS_CCR_REGNUM(n) (IN_SET (CCR, (n))) 634 635#define IS_RAW_REGNUM(n) (IN_SET (RAW, (n))) 636#define IS_PSEUDO_REGNUM(n) (IN_SET (PSEUDO, (n))) 637 638#define NUM_REGS_IN_SET(set) \ 639 (MEP_LAST_ ## set ## _REGNUM - MEP_FIRST_ ## set ## _REGNUM + 1) 640 641#define MEP_GPR_SIZE (4) /* Size of a MeP general-purpose register. */ 642#define MEP_PSW_SIZE (4) /* Size of the PSW register. */ 643#define MEP_LP_SIZE (4) /* Size of the LP register. */ 644 645 646/* Many of the control/special registers contain bits that cannot be 647 written to; some are entirely read-only. So we present them all as 648 pseudoregisters. 649 650 The following table describes the special properties of each CSR. */ 651struct mep_csr_register 652{ 653 /* The number of this CSR's raw register. */ 654 int raw; 655 656 /* The number of this CSR's pseudoregister. */ 657 int pseudo; 658 659 /* A mask of the bits that are writeable: if a bit is set here, then 660 it can be modified; if the bit is clear, then it cannot. */ 661 LONGEST writeable_bits; 662}; 663 664 665/* mep_csr_registers[i] describes the i'th CSR. 666 We just list the register numbers here explicitly to help catch 667 typos. */ 668#define CSR(name) MEP_RAW_ ## name ## _REGNUM, MEP_ ## name ## _REGNUM 669struct mep_csr_register mep_csr_registers[] = { 670 { CSR(PC), 0xffffffff }, /* manual says r/o, but we can write it */ 671 { CSR(LP), 0xffffffff }, 672 { CSR(SAR), 0x0000003f }, 673 { CSR(CSR3), 0xffffffff }, 674 { CSR(RPB), 0xfffffffe }, 675 { CSR(RPE), 0xffffffff }, 676 { CSR(RPC), 0xffffffff }, 677 { CSR(HI), 0xffffffff }, 678 { CSR(LO), 0xffffffff }, 679 { CSR(CSR9), 0xffffffff }, 680 { CSR(CSR10), 0xffffffff }, 681 { CSR(CSR11), 0xffffffff }, 682 { CSR(MB0), 0x0000ffff }, 683 { CSR(ME0), 0x0000ffff }, 684 { CSR(MB1), 0x0000ffff }, 685 { CSR(ME1), 0x0000ffff }, 686 { CSR(PSW), 0x000003ff }, 687 { CSR(ID), 0x00000000 }, 688 { CSR(TMP), 0xffffffff }, 689 { CSR(EPC), 0xffffffff }, 690 { CSR(EXC), 0x000030f0 }, 691 { CSR(CFG), 0x00c0001b }, 692 { CSR(CSR22), 0xffffffff }, 693 { CSR(NPC), 0xffffffff }, 694 { CSR(DBG), 0x00000580 }, 695 { CSR(DEPC), 0xffffffff }, 696 { CSR(OPT), 0x00000000 }, 697 { CSR(RCFG), 0x00000000 }, 698 { CSR(CCFG), 0x00000000 }, 699 { CSR(CSR29), 0xffffffff }, 700 { CSR(CSR30), 0xffffffff }, 701 { CSR(CSR31), 0xffffffff }, 702}; 703 704 705/* If R is the number of a raw register, then mep_raw_to_pseudo[R] is 706 the number of the corresponding pseudoregister. Otherwise, 707 mep_raw_to_pseudo[R] == R. */ 708static int mep_raw_to_pseudo[MEP_NUM_REGS]; 709 710/* If R is the number of a pseudoregister, then mep_pseudo_to_raw[R] 711 is the number of the underlying raw register. Otherwise 712 mep_pseudo_to_raw[R] == R. */ 713static int mep_pseudo_to_raw[MEP_NUM_REGS]; 714 715static void 716mep_init_pseudoregister_maps (void) 717{ 718 int i; 719 720 /* Verify that mep_csr_registers covers all the CSRs, in order. */ 721 gdb_assert (ARRAY_SIZE (mep_csr_registers) == NUM_REGS_IN_SET (CSR)); 722 gdb_assert (ARRAY_SIZE (mep_csr_registers) == NUM_REGS_IN_SET (RAW_CSR)); 723 724 /* Verify that the raw and pseudo ranges have matching sizes. */ 725 gdb_assert (NUM_REGS_IN_SET (RAW_CSR) == NUM_REGS_IN_SET (CSR)); 726 gdb_assert (NUM_REGS_IN_SET (RAW_CR) == NUM_REGS_IN_SET (CR32)); 727 gdb_assert (NUM_REGS_IN_SET (RAW_CR) == NUM_REGS_IN_SET (CR64)); 728 gdb_assert (NUM_REGS_IN_SET (RAW_CCR) == NUM_REGS_IN_SET (CCR)); 729 730 for (i = 0; i < ARRAY_SIZE (mep_csr_registers); i++) 731 { 732 struct mep_csr_register *r = &mep_csr_registers[i]; 733 734 gdb_assert (r->pseudo == MEP_FIRST_CSR_REGNUM + i); 735 gdb_assert (r->raw == MEP_FIRST_RAW_CSR_REGNUM + i); 736 } 737 738 /* Set up the initial raw<->pseudo mappings. */ 739 for (i = 0; i < MEP_NUM_REGS; i++) 740 { 741 mep_raw_to_pseudo[i] = i; 742 mep_pseudo_to_raw[i] = i; 743 } 744 745 /* Add the CSR raw<->pseudo mappings. */ 746 for (i = 0; i < ARRAY_SIZE (mep_csr_registers); i++) 747 { 748 struct mep_csr_register *r = &mep_csr_registers[i]; 749 750 mep_raw_to_pseudo[r->raw] = r->pseudo; 751 mep_pseudo_to_raw[r->pseudo] = r->raw; 752 } 753 754 /* Add the CR raw<->pseudo mappings. */ 755 for (i = 0; i < NUM_REGS_IN_SET (RAW_CR); i++) 756 { 757 int raw = MEP_FIRST_RAW_CR_REGNUM + i; 758 int pseudo32 = MEP_FIRST_CR32_REGNUM + i; 759 int pseudofp32 = MEP_FIRST_FP_CR32_REGNUM + i; 760 int pseudo64 = MEP_FIRST_CR64_REGNUM + i; 761 int pseudofp64 = MEP_FIRST_FP_CR64_REGNUM + i; 762 763 /* Truly, the raw->pseudo mapping depends on the current module. 764 But we use the raw->pseudo mapping when we read the debugging 765 info; at that point, we don't know what module we'll actually 766 be running yet. So, we always supply the 64-bit register 767 numbers; GDB knows how to pick a smaller value out of a 768 larger register properly. */ 769 mep_raw_to_pseudo[raw] = pseudo64; 770 mep_pseudo_to_raw[pseudo32] = raw; 771 mep_pseudo_to_raw[pseudofp32] = raw; 772 mep_pseudo_to_raw[pseudo64] = raw; 773 mep_pseudo_to_raw[pseudofp64] = raw; 774 } 775 776 /* Add the CCR raw<->pseudo mappings. */ 777 for (i = 0; i < NUM_REGS_IN_SET (CCR); i++) 778 { 779 int raw = MEP_FIRST_RAW_CCR_REGNUM + i; 780 int pseudo = MEP_FIRST_CCR_REGNUM + i; 781 mep_raw_to_pseudo[raw] = pseudo; 782 mep_pseudo_to_raw[pseudo] = raw; 783 } 784} 785 786 787static int 788mep_debug_reg_to_regnum (struct gdbarch *gdbarch, int debug_reg) 789{ 790 /* The debug info uses the raw register numbers. */ 791 return mep_raw_to_pseudo[debug_reg]; 792} 793 794 795/* Return the size, in bits, of the coprocessor pseudoregister 796 numbered PSEUDO. */ 797static int 798mep_pseudo_cr_size (int pseudo) 799{ 800 if (IS_CR32_REGNUM (pseudo) 801 || IS_FP_CR32_REGNUM (pseudo)) 802 return 32; 803 else if (IS_CR64_REGNUM (pseudo) 804 || IS_FP_CR64_REGNUM (pseudo)) 805 return 64; 806 else 807 gdb_assert_not_reached ("unexpected coprocessor pseudo register"); 808} 809 810 811/* If the coprocessor pseudoregister numbered PSEUDO is a 812 floating-point register, return non-zero; if it is an integer 813 register, return zero. */ 814static int 815mep_pseudo_cr_is_float (int pseudo) 816{ 817 return (IS_FP_CR32_REGNUM (pseudo) 818 || IS_FP_CR64_REGNUM (pseudo)); 819} 820 821 822/* Given a coprocessor GPR pseudoregister number, return its index 823 within that register bank. */ 824static int 825mep_pseudo_cr_index (int pseudo) 826{ 827 if (IS_CR32_REGNUM (pseudo)) 828 return pseudo - MEP_FIRST_CR32_REGNUM; 829 else if (IS_FP_CR32_REGNUM (pseudo)) 830 return pseudo - MEP_FIRST_FP_CR32_REGNUM; 831 else if (IS_CR64_REGNUM (pseudo)) 832 return pseudo - MEP_FIRST_CR64_REGNUM; 833 else if (IS_FP_CR64_REGNUM (pseudo)) 834 return pseudo - MEP_FIRST_FP_CR64_REGNUM; 835 else 836 gdb_assert_not_reached ("unexpected coprocessor pseudo register"); 837} 838 839 840/* Return the me_module index describing the current target. 841 842 If the current target has registers (e.g., simulator, remote 843 target), then this uses the value of the 'module' register, raw 844 register MEP_MODULE_REGNUM. Otherwise, this retrieves the value 845 from the ELF header's e_flags field of the current executable 846 file. */ 847static CONFIG_ATTR 848current_me_module (void) 849{ 850 if (target_has_registers) 851 { 852 ULONGEST regval; 853 regcache_cooked_read_unsigned (get_current_regcache (), 854 MEP_MODULE_REGNUM, ®val); 855 return regval; 856 } 857 else 858 return gdbarch_tdep (target_gdbarch)->me_module; 859} 860 861 862/* Return the set of options for the current target, in the form that 863 the OPT register would use. 864 865 If the current target has registers (e.g., simulator, remote 866 target), then this is the actual value of the OPT register. If the 867 current target does not have registers (e.g., an executable file), 868 then use the 'module_opt' field we computed when we build the 869 gdbarch object for this module. */ 870static unsigned int 871current_options (void) 872{ 873 if (target_has_registers) 874 { 875 ULONGEST regval; 876 regcache_cooked_read_unsigned (get_current_regcache (), 877 MEP_OPT_REGNUM, ®val); 878 return regval; 879 } 880 else 881 return me_module_opt (current_me_module ()); 882} 883 884 885/* Return the width of the current me_module's coprocessor data bus, 886 in bits. This is either 32 or 64. */ 887static int 888current_cop_data_bus_width (void) 889{ 890 return me_module_cop_data_bus_width (current_me_module ()); 891} 892 893 894/* Return the keyword table of coprocessor general-purpose register 895 names appropriate for the me_module we're dealing with. */ 896static CGEN_KEYWORD * 897current_cr_names (void) 898{ 899 const CGEN_HW_ENTRY *hw 900 = me_module_register_set (current_me_module (), "h-cr-", HW_H_CR); 901 902 return register_set_keyword_table (hw); 903} 904 905 906/* Return non-zero if the coprocessor general-purpose registers are 907 floating-point values, zero otherwise. */ 908static int 909current_cr_is_float (void) 910{ 911 const CGEN_HW_ENTRY *hw 912 = me_module_register_set (current_me_module (), "h-cr-", HW_H_CR); 913 914 return CGEN_ATTR_CGEN_HW_IS_FLOAT_VALUE (CGEN_HW_ATTRS (hw)); 915} 916 917 918/* Return the keyword table of coprocessor control register names 919 appropriate for the me_module we're dealing with. */ 920static CGEN_KEYWORD * 921current_ccr_names (void) 922{ 923 const CGEN_HW_ENTRY *hw 924 = me_module_register_set (current_me_module (), "h-ccr-", HW_H_CCR); 925 926 return register_set_keyword_table (hw); 927} 928 929 930static const char * 931mep_register_name (struct gdbarch *gdbarch, int regnr) 932{ 933 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 934 935 /* General-purpose registers. */ 936 static const char *gpr_names[] = { 937 "r0", "r1", "r2", "r3", /* 0 */ 938 "r4", "r5", "r6", "r7", /* 4 */ 939 "fp", "r9", "r10", "r11", /* 8 */ 940 "r12", "tp", "gp", "sp" /* 12 */ 941 }; 942 943 /* Special-purpose registers. */ 944 static const char *csr_names[] = { 945 "pc", "lp", "sar", "", /* 0 csr3: reserved */ 946 "rpb", "rpe", "rpc", "hi", /* 4 */ 947 "lo", "", "", "", /* 8 csr9-csr11: reserved */ 948 "mb0", "me0", "mb1", "me1", /* 12 */ 949 950 "psw", "id", "tmp", "epc", /* 16 */ 951 "exc", "cfg", "", "npc", /* 20 csr22: reserved */ 952 "dbg", "depc", "opt", "rcfg", /* 24 */ 953 "ccfg", "", "", "" /* 28 csr29-csr31: reserved */ 954 }; 955 956 if (IS_GPR_REGNUM (regnr)) 957 return gpr_names[regnr - MEP_R0_REGNUM]; 958 else if (IS_CSR_REGNUM (regnr)) 959 { 960 /* The 'hi' and 'lo' registers are only present on processors 961 that have the 'MUL' or 'DIV' instructions enabled. */ 962 if ((regnr == MEP_HI_REGNUM || regnr == MEP_LO_REGNUM) 963 && (! (current_options () & (MEP_OPT_MUL | MEP_OPT_DIV)))) 964 return ""; 965 966 return csr_names[regnr - MEP_FIRST_CSR_REGNUM]; 967 } 968 else if (IS_CR_REGNUM (regnr)) 969 { 970 CGEN_KEYWORD *names; 971 int cr_size; 972 int cr_is_float; 973 974 /* Does this module have a coprocessor at all? */ 975 if (! (current_options () & MEP_OPT_COP)) 976 return ""; 977 978 names = current_cr_names (); 979 if (! names) 980 /* This module's coprocessor has no general-purpose registers. */ 981 return ""; 982 983 cr_size = current_cop_data_bus_width (); 984 if (cr_size != mep_pseudo_cr_size (regnr)) 985 /* This module's coprocessor's GPR's are of a different size. */ 986 return ""; 987 988 cr_is_float = current_cr_is_float (); 989 /* The extra ! operators ensure we get boolean equality, not 990 numeric equality. */ 991 if (! cr_is_float != ! mep_pseudo_cr_is_float (regnr)) 992 /* This module's coprocessor's GPR's are of a different type. */ 993 return ""; 994 995 return register_name_from_keyword (names, mep_pseudo_cr_index (regnr)); 996 } 997 else if (IS_CCR_REGNUM (regnr)) 998 { 999 /* Does this module have a coprocessor at all? */ 1000 if (! (current_options () & MEP_OPT_COP)) 1001 return ""; 1002 1003 { 1004 CGEN_KEYWORD *names = current_ccr_names (); 1005 1006 if (! names) 1007 /* This me_module's coprocessor has no control registers. */ 1008 return ""; 1009 1010 return register_name_from_keyword (names, regnr-MEP_FIRST_CCR_REGNUM); 1011 } 1012 } 1013 1014 /* It might be nice to give the 'module' register a name, but that 1015 would affect the output of 'info all-registers', which would 1016 disturb the test suites. So we leave it invisible. */ 1017 else 1018 return NULL; 1019} 1020 1021 1022/* Custom register groups for the MeP. */ 1023static struct reggroup *mep_csr_reggroup; /* control/special */ 1024static struct reggroup *mep_cr_reggroup; /* coprocessor general-purpose */ 1025static struct reggroup *mep_ccr_reggroup; /* coprocessor control */ 1026 1027 1028static int 1029mep_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 1030 struct reggroup *group) 1031{ 1032 /* Filter reserved or unused register numbers. */ 1033 { 1034 const char *name = mep_register_name (gdbarch, regnum); 1035 1036 if (! name || name[0] == '\0') 1037 return 0; 1038 } 1039 1040 /* We could separate the GPRs and the CSRs. Toshiba has approved of 1041 the existing behavior, so we'd want to run that by them. */ 1042 if (group == general_reggroup) 1043 return (IS_GPR_REGNUM (regnum) 1044 || IS_CSR_REGNUM (regnum)); 1045 1046 /* Everything is in the 'all' reggroup, except for the raw CSR's. */ 1047 else if (group == all_reggroup) 1048 return (IS_GPR_REGNUM (regnum) 1049 || IS_CSR_REGNUM (regnum) 1050 || IS_CR_REGNUM (regnum) 1051 || IS_CCR_REGNUM (regnum)); 1052 1053 /* All registers should be saved and restored, except for the raw 1054 CSR's. 1055 1056 This is probably right if the coprocessor is something like a 1057 floating-point unit, but would be wrong if the coprocessor is 1058 something that does I/O, where register accesses actually cause 1059 externally-visible actions. But I get the impression that the 1060 coprocessor isn't supposed to do things like that --- you'd use a 1061 hardware engine, perhaps. */ 1062 else if (group == save_reggroup || group == restore_reggroup) 1063 return (IS_GPR_REGNUM (regnum) 1064 || IS_CSR_REGNUM (regnum) 1065 || IS_CR_REGNUM (regnum) 1066 || IS_CCR_REGNUM (regnum)); 1067 1068 else if (group == mep_csr_reggroup) 1069 return IS_CSR_REGNUM (regnum); 1070 else if (group == mep_cr_reggroup) 1071 return IS_CR_REGNUM (regnum); 1072 else if (group == mep_ccr_reggroup) 1073 return IS_CCR_REGNUM (regnum); 1074 else 1075 return 0; 1076} 1077 1078 1079static struct type * 1080mep_register_type (struct gdbarch *gdbarch, int reg_nr) 1081{ 1082 /* Coprocessor general-purpose registers may be either 32 or 64 bits 1083 long. So for them, the raw registers are always 64 bits long (to 1084 keep the 'g' packet format fixed), and the pseudoregisters vary 1085 in length. */ 1086 if (IS_RAW_CR_REGNUM (reg_nr)) 1087 return builtin_type (gdbarch)->builtin_uint64; 1088 1089 /* Since GDB doesn't allow registers to change type, we have two 1090 banks of pseudoregisters for the coprocessor general-purpose 1091 registers: one that gives a 32-bit view, and one that gives a 1092 64-bit view. We hide or show one or the other depending on the 1093 current module. */ 1094 if (IS_CR_REGNUM (reg_nr)) 1095 { 1096 int size = mep_pseudo_cr_size (reg_nr); 1097 if (size == 32) 1098 { 1099 if (mep_pseudo_cr_is_float (reg_nr)) 1100 return builtin_type (gdbarch)->builtin_float; 1101 else 1102 return builtin_type (gdbarch)->builtin_uint32; 1103 } 1104 else if (size == 64) 1105 { 1106 if (mep_pseudo_cr_is_float (reg_nr)) 1107 return builtin_type (gdbarch)->builtin_double; 1108 else 1109 return builtin_type (gdbarch)->builtin_uint64; 1110 } 1111 else 1112 gdb_assert_not_reached ("unexpected cr size"); 1113 } 1114 1115 /* All other registers are 32 bits long. */ 1116 else 1117 return builtin_type (gdbarch)->builtin_uint32; 1118} 1119 1120 1121static CORE_ADDR 1122mep_read_pc (struct regcache *regcache) 1123{ 1124 ULONGEST pc; 1125 regcache_cooked_read_unsigned (regcache, MEP_PC_REGNUM, &pc); 1126 return pc; 1127} 1128 1129static void 1130mep_write_pc (struct regcache *regcache, CORE_ADDR pc) 1131{ 1132 regcache_cooked_write_unsigned (regcache, MEP_PC_REGNUM, pc); 1133} 1134 1135 1136static enum register_status 1137mep_pseudo_cr32_read (struct gdbarch *gdbarch, 1138 struct regcache *regcache, 1139 int cookednum, 1140 void *buf) 1141{ 1142 enum register_status status; 1143 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1144 /* Read the raw register into a 64-bit buffer, and then return the 1145 appropriate end of that buffer. */ 1146 int rawnum = mep_pseudo_to_raw[cookednum]; 1147 char buf64[8]; 1148 1149 gdb_assert (TYPE_LENGTH (register_type (gdbarch, rawnum)) == sizeof (buf64)); 1150 gdb_assert (TYPE_LENGTH (register_type (gdbarch, cookednum)) == 4); 1151 status = regcache_raw_read (regcache, rawnum, buf64); 1152 if (status == REG_VALID) 1153 { 1154 /* Slow, but legible. */ 1155 store_unsigned_integer (buf, 4, byte_order, 1156 extract_unsigned_integer (buf64, 8, byte_order)); 1157 } 1158 return status; 1159} 1160 1161 1162static enum register_status 1163mep_pseudo_cr64_read (struct gdbarch *gdbarch, 1164 struct regcache *regcache, 1165 int cookednum, 1166 void *buf) 1167{ 1168 return regcache_raw_read (regcache, mep_pseudo_to_raw[cookednum], buf); 1169} 1170 1171 1172static enum register_status 1173mep_pseudo_register_read (struct gdbarch *gdbarch, 1174 struct regcache *regcache, 1175 int cookednum, 1176 gdb_byte *buf) 1177{ 1178 if (IS_CSR_REGNUM (cookednum) 1179 || IS_CCR_REGNUM (cookednum)) 1180 return regcache_raw_read (regcache, mep_pseudo_to_raw[cookednum], buf); 1181 else if (IS_CR32_REGNUM (cookednum) 1182 || IS_FP_CR32_REGNUM (cookednum)) 1183 return mep_pseudo_cr32_read (gdbarch, regcache, cookednum, buf); 1184 else if (IS_CR64_REGNUM (cookednum) 1185 || IS_FP_CR64_REGNUM (cookednum)) 1186 return mep_pseudo_cr64_read (gdbarch, regcache, cookednum, buf); 1187 else 1188 gdb_assert_not_reached ("unexpected pseudo register"); 1189} 1190 1191 1192static void 1193mep_pseudo_csr_write (struct gdbarch *gdbarch, 1194 struct regcache *regcache, 1195 int cookednum, 1196 const void *buf) 1197{ 1198 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1199 int size = register_size (gdbarch, cookednum); 1200 struct mep_csr_register *r 1201 = &mep_csr_registers[cookednum - MEP_FIRST_CSR_REGNUM]; 1202 1203 if (r->writeable_bits == 0) 1204 /* A completely read-only register; avoid the read-modify- 1205 write cycle, and juts ignore the entire write. */ 1206 ; 1207 else 1208 { 1209 /* A partially writeable register; do a read-modify-write cycle. */ 1210 ULONGEST old_bits; 1211 ULONGEST new_bits; 1212 ULONGEST mixed_bits; 1213 1214 regcache_raw_read_unsigned (regcache, r->raw, &old_bits); 1215 new_bits = extract_unsigned_integer (buf, size, byte_order); 1216 mixed_bits = ((r->writeable_bits & new_bits) 1217 | (~r->writeable_bits & old_bits)); 1218 regcache_raw_write_unsigned (regcache, r->raw, mixed_bits); 1219 } 1220} 1221 1222 1223static void 1224mep_pseudo_cr32_write (struct gdbarch *gdbarch, 1225 struct regcache *regcache, 1226 int cookednum, 1227 const void *buf) 1228{ 1229 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1230 /* Expand the 32-bit value into a 64-bit value, and write that to 1231 the pseudoregister. */ 1232 int rawnum = mep_pseudo_to_raw[cookednum]; 1233 char buf64[8]; 1234 1235 gdb_assert (TYPE_LENGTH (register_type (gdbarch, rawnum)) == sizeof (buf64)); 1236 gdb_assert (TYPE_LENGTH (register_type (gdbarch, cookednum)) == 4); 1237 /* Slow, but legible. */ 1238 store_unsigned_integer (buf64, 8, byte_order, 1239 extract_unsigned_integer (buf, 4, byte_order)); 1240 regcache_raw_write (regcache, rawnum, buf64); 1241} 1242 1243 1244static void 1245mep_pseudo_cr64_write (struct gdbarch *gdbarch, 1246 struct regcache *regcache, 1247 int cookednum, 1248 const void *buf) 1249{ 1250 regcache_raw_write (regcache, mep_pseudo_to_raw[cookednum], buf); 1251} 1252 1253 1254static void 1255mep_pseudo_register_write (struct gdbarch *gdbarch, 1256 struct regcache *regcache, 1257 int cookednum, 1258 const gdb_byte *buf) 1259{ 1260 if (IS_CSR_REGNUM (cookednum)) 1261 mep_pseudo_csr_write (gdbarch, regcache, cookednum, buf); 1262 else if (IS_CR32_REGNUM (cookednum) 1263 || IS_FP_CR32_REGNUM (cookednum)) 1264 mep_pseudo_cr32_write (gdbarch, regcache, cookednum, buf); 1265 else if (IS_CR64_REGNUM (cookednum) 1266 || IS_FP_CR64_REGNUM (cookednum)) 1267 mep_pseudo_cr64_write (gdbarch, regcache, cookednum, buf); 1268 else if (IS_CCR_REGNUM (cookednum)) 1269 regcache_raw_write (regcache, mep_pseudo_to_raw[cookednum], buf); 1270 else 1271 gdb_assert_not_reached ("unexpected pseudo register"); 1272} 1273 1274 1275 1276/* Disassembly. */ 1277 1278/* The mep disassembler needs to know about the section in order to 1279 work correctly. */ 1280static int 1281mep_gdb_print_insn (bfd_vma pc, disassemble_info * info) 1282{ 1283 struct obj_section * s = find_pc_section (pc); 1284 1285 if (s) 1286 { 1287 /* The libopcodes disassembly code uses the section to find the 1288 BFD, the BFD to find the ELF header, the ELF header to find 1289 the me_module index, and the me_module index to select the 1290 right instructions to print. */ 1291 info->section = s->the_bfd_section; 1292 info->arch = bfd_arch_mep; 1293 1294 return print_insn_mep (pc, info); 1295 } 1296 1297 return 0; 1298} 1299 1300 1301/* Prologue analysis. */ 1302 1303 1304/* The MeP has two classes of instructions: "core" instructions, which 1305 are pretty normal RISC chip stuff, and "coprocessor" instructions, 1306 which are mostly concerned with moving data in and out of 1307 coprocessor registers, and branching on coprocessor condition 1308 codes. There's space in the instruction set for custom coprocessor 1309 instructions, too. 1310 1311 Instructions can be 16 or 32 bits long; the top two bits of the 1312 first byte indicate the length. The coprocessor instructions are 1313 mixed in with the core instructions, and there's no easy way to 1314 distinguish them; you have to completely decode them to tell one 1315 from the other. 1316 1317 The MeP also supports a "VLIW" operation mode, where instructions 1318 always occur in fixed-width bundles. The bundles are either 32 1319 bits or 64 bits long, depending on a fixed configuration flag. You 1320 decode the first part of the bundle as normal; if it's a core 1321 instruction, and there's any space left in the bundle, the 1322 remainder of the bundle is a coprocessor instruction, which will 1323 execute in parallel with the core instruction. If the first part 1324 of the bundle is a coprocessor instruction, it occupies the entire 1325 bundle. 1326 1327 So, here are all the cases: 1328 1329 - 32-bit VLIW mode: 1330 Every bundle is four bytes long, and naturally aligned, and can hold 1331 one or two instructions: 1332 - 16-bit core instruction; 16-bit coprocessor instruction 1333 These execute in parallel. 1334 - 32-bit core instruction 1335 - 32-bit coprocessor instruction 1336 1337 - 64-bit VLIW mode: 1338 Every bundle is eight bytes long, and naturally aligned, and can hold 1339 one or two instructions: 1340 - 16-bit core instruction; 48-bit (!) coprocessor instruction 1341 These execute in parallel. 1342 - 32-bit core instruction; 32-bit coprocessor instruction 1343 These execute in parallel. 1344 - 64-bit coprocessor instruction 1345 1346 Now, the MeP manual doesn't define any 48- or 64-bit coprocessor 1347 instruction, so I don't really know what's up there; perhaps these 1348 are always the user-defined coprocessor instructions. */ 1349 1350 1351/* Return non-zero if PC is in a VLIW code section, zero 1352 otherwise. */ 1353static int 1354mep_pc_in_vliw_section (CORE_ADDR pc) 1355{ 1356 struct obj_section *s = find_pc_section (pc); 1357 if (s) 1358 return (s->the_bfd_section->flags & SEC_MEP_VLIW); 1359 return 0; 1360} 1361 1362 1363/* Set *INSN to the next core instruction at PC, and return the 1364 address of the next instruction. 1365 1366 The MeP instruction encoding is endian-dependent. 16- and 32-bit 1367 instructions are encoded as one or two two-byte parts, and each 1368 part is byte-swapped independently. Thus: 1369 1370 void 1371 foo (void) 1372 { 1373 asm ("movu $1, 0x123456"); 1374 asm ("sb $1,0x5678($2)"); 1375 asm ("clip $1, 19"); 1376 } 1377 1378 compiles to this big-endian code: 1379 1380 0: d1 56 12 34 movu $1,0x123456 1381 4: c1 28 56 78 sb $1,22136($2) 1382 8: f1 01 10 98 clip $1,0x13 1383 c: 70 02 ret 1384 1385 and this little-endian code: 1386 1387 0: 56 d1 34 12 movu $1,0x123456 1388 4: 28 c1 78 56 sb $1,22136($2) 1389 8: 01 f1 98 10 clip $1,0x13 1390 c: 02 70 ret 1391 1392 Instructions are returned in *INSN in an endian-independent form: a 1393 given instruction always appears in *INSN the same way, regardless 1394 of whether the instruction stream is big-endian or little-endian. 1395 1396 *INSN's most significant 16 bits are the first (i.e., at lower 1397 addresses) 16 bit part of the instruction. Its least significant 1398 16 bits are the second (i.e., higher-addressed) 16 bit part of the 1399 instruction, or zero for a 16-bit instruction. Both 16-bit parts 1400 are fetched using the current endianness. 1401 1402 So, the *INSN values for the instruction sequence above would be 1403 the following, in either endianness: 1404 1405 0xd1561234 movu $1,0x123456 1406 0xc1285678 sb $1,22136($2) 1407 0xf1011098 clip $1,0x13 1408 0x70020000 ret 1409 1410 (In a sense, it would be more natural to return 16-bit instructions 1411 in the least significant 16 bits of *INSN, but that would be 1412 ambiguous. In order to tell whether you're looking at a 16- or a 1413 32-bit instruction, you have to consult the major opcode field --- 1414 the most significant four bits of the instruction's first 16-bit 1415 part. But if we put 16-bit instructions at the least significant 1416 end of *INSN, then you don't know where to find the major opcode 1417 field until you know if it's a 16- or a 32-bit instruction --- 1418 which is where we started.) 1419 1420 If PC points to a core / coprocessor bundle in a VLIW section, set 1421 *INSN to the core instruction, and return the address of the next 1422 bundle. This has the effect of skipping the bundled coprocessor 1423 instruction. That's okay, since coprocessor instructions aren't 1424 significant to prologue analysis --- for the time being, 1425 anyway. */ 1426 1427static CORE_ADDR 1428mep_get_insn (struct gdbarch *gdbarch, CORE_ADDR pc, long *insn) 1429{ 1430 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1431 int pc_in_vliw_section; 1432 int vliw_mode; 1433 int insn_len; 1434 char buf[2]; 1435 1436 *insn = 0; 1437 1438 /* Are we in a VLIW section? */ 1439 pc_in_vliw_section = mep_pc_in_vliw_section (pc); 1440 if (pc_in_vliw_section) 1441 { 1442 /* Yes, find out which bundle size. */ 1443 vliw_mode = current_options () & (MEP_OPT_VL32 | MEP_OPT_VL64); 1444 1445 /* If PC is in a VLIW section, but the current core doesn't say 1446 that it supports either VLIW mode, then we don't have enough 1447 information to parse the instruction stream it contains. 1448 Since the "undifferentiated" standard core doesn't have 1449 either VLIW mode bit set, this could happen. 1450 1451 But it shouldn't be an error to (say) set a breakpoint in a 1452 VLIW section, if you know you'll never reach it. (Perhaps 1453 you have a script that sets a bunch of standard breakpoints.) 1454 1455 So we'll just return zero here, and hope for the best. */ 1456 if (! (vliw_mode & (MEP_OPT_VL32 | MEP_OPT_VL64))) 1457 return 0; 1458 1459 /* If both VL32 and VL64 are set, that's bogus, too. */ 1460 if (vliw_mode == (MEP_OPT_VL32 | MEP_OPT_VL64)) 1461 return 0; 1462 } 1463 else 1464 vliw_mode = 0; 1465 1466 read_memory (pc, buf, sizeof (buf)); 1467 *insn = extract_unsigned_integer (buf, 2, byte_order) << 16; 1468 1469 /* The major opcode --- the top four bits of the first 16-bit 1470 part --- indicates whether this instruction is 16 or 32 bits 1471 long. All 32-bit instructions have a major opcode whose top 1472 two bits are 11; all the rest are 16-bit instructions. */ 1473 if ((*insn & 0xc0000000) == 0xc0000000) 1474 { 1475 /* Fetch the second 16-bit part of the instruction. */ 1476 read_memory (pc + 2, buf, sizeof (buf)); 1477 *insn = *insn | extract_unsigned_integer (buf, 2, byte_order); 1478 } 1479 1480 /* If we're in VLIW code, then the VLIW width determines the address 1481 of the next instruction. */ 1482 if (vliw_mode) 1483 { 1484 /* In 32-bit VLIW code, all bundles are 32 bits long. We ignore the 1485 coprocessor half of a core / copro bundle. */ 1486 if (vliw_mode == MEP_OPT_VL32) 1487 insn_len = 4; 1488 1489 /* In 64-bit VLIW code, all bundles are 64 bits long. We ignore the 1490 coprocessor half of a core / copro bundle. */ 1491 else if (vliw_mode == MEP_OPT_VL64) 1492 insn_len = 8; 1493 1494 /* We'd better be in either core, 32-bit VLIW, or 64-bit VLIW mode. */ 1495 else 1496 gdb_assert_not_reached ("unexpected vliw mode"); 1497 } 1498 1499 /* Otherwise, the top two bits of the major opcode are (again) what 1500 we need to check. */ 1501 else if ((*insn & 0xc0000000) == 0xc0000000) 1502 insn_len = 4; 1503 else 1504 insn_len = 2; 1505 1506 return pc + insn_len; 1507} 1508 1509 1510/* Sign-extend the LEN-bit value N. */ 1511#define SEXT(n, len) ((((int) (n)) ^ (1 << ((len) - 1))) - (1 << ((len) - 1))) 1512 1513/* Return the LEN-bit field at POS from I. */ 1514#define FIELD(i, pos, len) (((i) >> (pos)) & ((1 << (len)) - 1)) 1515 1516/* Like FIELD, but sign-extend the field's value. */ 1517#define SFIELD(i, pos, len) (SEXT (FIELD ((i), (pos), (len)), (len))) 1518 1519 1520/* Macros for decoding instructions. 1521 1522 Remember that 16-bit instructions are placed in bits 16..31 of i, 1523 not at the least significant end; this means that the major opcode 1524 field is always in the same place, regardless of the width of the 1525 instruction. As a reminder of this, we show the lower 16 bits of a 1526 16-bit instruction as xxxx_xxxx_xxxx_xxxx. */ 1527 1528/* SB Rn,(Rm) 0000_nnnn_mmmm_1000 */ 1529/* SH Rn,(Rm) 0000_nnnn_mmmm_1001 */ 1530/* SW Rn,(Rm) 0000_nnnn_mmmm_1010 */ 1531 1532/* SW Rn,disp16(Rm) 1100_nnnn_mmmm_1010 dddd_dddd_dddd_dddd */ 1533#define IS_SW(i) (((i) & 0xf00f0000) == 0xc00a0000) 1534/* SB Rn,disp16(Rm) 1100_nnnn_mmmm_1000 dddd_dddd_dddd_dddd */ 1535#define IS_SB(i) (((i) & 0xf00f0000) == 0xc0080000) 1536/* SH Rn,disp16(Rm) 1100_nnnn_mmmm_1001 dddd_dddd_dddd_dddd */ 1537#define IS_SH(i) (((i) & 0xf00f0000) == 0xc0090000) 1538#define SWBH_32_BASE(i) (FIELD (i, 20, 4)) 1539#define SWBH_32_SOURCE(i) (FIELD (i, 24, 4)) 1540#define SWBH_32_OFFSET(i) (SFIELD (i, 0, 16)) 1541 1542/* SW Rn,disp7.align4(SP) 0100_nnnn_0ddd_dd10 xxxx_xxxx_xxxx_xxxx */ 1543#define IS_SW_IMMD(i) (((i) & 0xf0830000) == 0x40020000) 1544#define SW_IMMD_SOURCE(i) (FIELD (i, 24, 4)) 1545#define SW_IMMD_OFFSET(i) (FIELD (i, 18, 5) << 2) 1546 1547/* SW Rn,(Rm) 0000_nnnn_mmmm_1010 xxxx_xxxx_xxxx_xxxx */ 1548#define IS_SW_REG(i) (((i) & 0xf00f0000) == 0x000a0000) 1549#define SW_REG_SOURCE(i) (FIELD (i, 24, 4)) 1550#define SW_REG_BASE(i) (FIELD (i, 20, 4)) 1551 1552/* ADD3 Rl,Rn,Rm 1001_nnnn_mmmm_llll xxxx_xxxx_xxxx_xxxx */ 1553#define IS_ADD3_16_REG(i) (((i) & 0xf0000000) == 0x90000000) 1554#define ADD3_16_REG_SRC1(i) (FIELD (i, 20, 4)) /* n */ 1555#define ADD3_16_REG_SRC2(i) (FIELD (i, 24, 4)) /* m */ 1556 1557/* ADD3 Rn,Rm,imm16 1100_nnnn_mmmm_0000 iiii_iiii_iiii_iiii */ 1558#define IS_ADD3_32(i) (((i) & 0xf00f0000) == 0xc0000000) 1559#define ADD3_32_TARGET(i) (FIELD (i, 24, 4)) 1560#define ADD3_32_SOURCE(i) (FIELD (i, 20, 4)) 1561#define ADD3_32_OFFSET(i) (SFIELD (i, 0, 16)) 1562 1563/* ADD3 Rn,SP,imm7.align4 0100_nnnn_0iii_ii00 xxxx_xxxx_xxxx_xxxx */ 1564#define IS_ADD3_16(i) (((i) & 0xf0830000) == 0x40000000) 1565#define ADD3_16_TARGET(i) (FIELD (i, 24, 4)) 1566#define ADD3_16_OFFSET(i) (FIELD (i, 18, 5) << 2) 1567 1568/* ADD Rn,imm6 0110_nnnn_iiii_ii00 xxxx_xxxx_xxxx_xxxx */ 1569#define IS_ADD(i) (((i) & 0xf0030000) == 0x60000000) 1570#define ADD_TARGET(i) (FIELD (i, 24, 4)) 1571#define ADD_OFFSET(i) (SFIELD (i, 18, 6)) 1572 1573/* LDC Rn,imm5 0111_nnnn_iiii_101I xxxx_xxxx_xxxx_xxxx 1574 imm5 = I||i[7:4] */ 1575#define IS_LDC(i) (((i) & 0xf00e0000) == 0x700a0000) 1576#define LDC_IMM(i) ((FIELD (i, 16, 1) << 4) | FIELD (i, 20, 4)) 1577#define LDC_TARGET(i) (FIELD (i, 24, 4)) 1578 1579/* LW Rn,disp16(Rm) 1100_nnnn_mmmm_1110 dddd_dddd_dddd_dddd */ 1580#define IS_LW(i) (((i) & 0xf00f0000) == 0xc00e0000) 1581#define LW_TARGET(i) (FIELD (i, 24, 4)) 1582#define LW_BASE(i) (FIELD (i, 20, 4)) 1583#define LW_OFFSET(i) (SFIELD (i, 0, 16)) 1584 1585/* MOV Rn,Rm 0000_nnnn_mmmm_0000 xxxx_xxxx_xxxx_xxxx */ 1586#define IS_MOV(i) (((i) & 0xf00f0000) == 0x00000000) 1587#define MOV_TARGET(i) (FIELD (i, 24, 4)) 1588#define MOV_SOURCE(i) (FIELD (i, 20, 4)) 1589 1590/* BRA disp12.align2 1011_dddd_dddd_ddd0 xxxx_xxxx_xxxx_xxxx */ 1591#define IS_BRA(i) (((i) & 0xf0010000) == 0xb0000000) 1592#define BRA_DISP(i) (SFIELD (i, 17, 11) << 1) 1593 1594 1595/* This structure holds the results of a prologue analysis. */ 1596struct mep_prologue 1597{ 1598 /* The architecture for which we generated this prologue info. */ 1599 struct gdbarch *gdbarch; 1600 1601 /* The offset from the frame base to the stack pointer --- always 1602 zero or negative. 1603 1604 Calling this a "size" is a bit misleading, but given that the 1605 stack grows downwards, using offsets for everything keeps one 1606 from going completely sign-crazy: you never change anything's 1607 sign for an ADD instruction; always change the second operand's 1608 sign for a SUB instruction; and everything takes care of 1609 itself. */ 1610 int frame_size; 1611 1612 /* Non-zero if this function has initialized the frame pointer from 1613 the stack pointer, zero otherwise. */ 1614 int has_frame_ptr; 1615 1616 /* If has_frame_ptr is non-zero, this is the offset from the frame 1617 base to where the frame pointer points. This is always zero or 1618 negative. */ 1619 int frame_ptr_offset; 1620 1621 /* The address of the first instruction at which the frame has been 1622 set up and the arguments are where the debug info says they are 1623 --- as best as we can tell. */ 1624 CORE_ADDR prologue_end; 1625 1626 /* reg_offset[R] is the offset from the CFA at which register R is 1627 saved, or 1 if register R has not been saved. (Real values are 1628 always zero or negative.) */ 1629 int reg_offset[MEP_NUM_REGS]; 1630}; 1631 1632/* Return non-zero if VALUE is an incoming argument register. */ 1633 1634static int 1635is_arg_reg (pv_t value) 1636{ 1637 return (value.kind == pvk_register 1638 && MEP_R1_REGNUM <= value.reg && value.reg <= MEP_R4_REGNUM 1639 && value.k == 0); 1640} 1641 1642/* Return non-zero if a store of REG's current value VALUE to ADDR is 1643 probably spilling an argument register to its stack slot in STACK. 1644 Such instructions should be included in the prologue, if possible. 1645 1646 The store is a spill if: 1647 - the value being stored is REG's original value; 1648 - the value has not already been stored somewhere in STACK; and 1649 - ADDR is a stack slot's address (e.g., relative to the original 1650 value of the SP). */ 1651static int 1652is_arg_spill (struct gdbarch *gdbarch, pv_t value, pv_t addr, 1653 struct pv_area *stack) 1654{ 1655 return (is_arg_reg (value) 1656 && pv_is_register (addr, MEP_SP_REGNUM) 1657 && ! pv_area_find_reg (stack, gdbarch, value.reg, 0)); 1658} 1659 1660 1661/* Function for finding saved registers in a 'struct pv_area'; we pass 1662 this to pv_area_scan. 1663 1664 If VALUE is a saved register, ADDR says it was saved at a constant 1665 offset from the frame base, and SIZE indicates that the whole 1666 register was saved, record its offset in RESULT_UNTYPED. */ 1667static void 1668check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size, pv_t value) 1669{ 1670 struct mep_prologue *result = (struct mep_prologue *) result_untyped; 1671 1672 if (value.kind == pvk_register 1673 && value.k == 0 1674 && pv_is_register (addr, MEP_SP_REGNUM) 1675 && size == register_size (result->gdbarch, value.reg)) 1676 result->reg_offset[value.reg] = addr.k; 1677} 1678 1679 1680/* Analyze a prologue starting at START_PC, going no further than 1681 LIMIT_PC. Fill in RESULT as appropriate. */ 1682static void 1683mep_analyze_prologue (struct gdbarch *gdbarch, 1684 CORE_ADDR start_pc, CORE_ADDR limit_pc, 1685 struct mep_prologue *result) 1686{ 1687 CORE_ADDR pc; 1688 unsigned long insn; 1689 int rn; 1690 int found_lp = 0; 1691 pv_t reg[MEP_NUM_REGS]; 1692 struct pv_area *stack; 1693 struct cleanup *back_to; 1694 CORE_ADDR after_last_frame_setup_insn = start_pc; 1695 1696 memset (result, 0, sizeof (*result)); 1697 result->gdbarch = gdbarch; 1698 1699 for (rn = 0; rn < MEP_NUM_REGS; rn++) 1700 { 1701 reg[rn] = pv_register (rn, 0); 1702 result->reg_offset[rn] = 1; 1703 } 1704 1705 stack = make_pv_area (MEP_SP_REGNUM, gdbarch_addr_bit (gdbarch)); 1706 back_to = make_cleanup_free_pv_area (stack); 1707 1708 pc = start_pc; 1709 while (pc < limit_pc) 1710 { 1711 CORE_ADDR next_pc; 1712 pv_t pre_insn_fp, pre_insn_sp; 1713 1714 next_pc = mep_get_insn (gdbarch, pc, &insn); 1715 1716 /* A zero return from mep_get_insn means that either we weren't 1717 able to read the instruction from memory, or that we don't 1718 have enough information to be able to reliably decode it. So 1719 we'll store here and hope for the best. */ 1720 if (! next_pc) 1721 break; 1722 1723 /* Note the current values of the SP and FP, so we can tell if 1724 this instruction changed them, below. */ 1725 pre_insn_fp = reg[MEP_FP_REGNUM]; 1726 pre_insn_sp = reg[MEP_SP_REGNUM]; 1727 1728 if (IS_ADD (insn)) 1729 { 1730 int rn = ADD_TARGET (insn); 1731 CORE_ADDR imm6 = ADD_OFFSET (insn); 1732 1733 reg[rn] = pv_add_constant (reg[rn], imm6); 1734 } 1735 else if (IS_ADD3_16 (insn)) 1736 { 1737 int rn = ADD3_16_TARGET (insn); 1738 int imm7 = ADD3_16_OFFSET (insn); 1739 1740 reg[rn] = pv_add_constant (reg[MEP_SP_REGNUM], imm7); 1741 } 1742 else if (IS_ADD3_32 (insn)) 1743 { 1744 int rn = ADD3_32_TARGET (insn); 1745 int rm = ADD3_32_SOURCE (insn); 1746 int imm16 = ADD3_32_OFFSET (insn); 1747 1748 reg[rn] = pv_add_constant (reg[rm], imm16); 1749 } 1750 else if (IS_SW_REG (insn)) 1751 { 1752 int rn = SW_REG_SOURCE (insn); 1753 int rm = SW_REG_BASE (insn); 1754 1755 /* If simulating this store would require us to forget 1756 everything we know about the stack frame in the name of 1757 accuracy, it would be better to just quit now. */ 1758 if (pv_area_store_would_trash (stack, reg[rm])) 1759 break; 1760 1761 if (is_arg_spill (gdbarch, reg[rn], reg[rm], stack)) 1762 after_last_frame_setup_insn = next_pc; 1763 1764 pv_area_store (stack, reg[rm], 4, reg[rn]); 1765 } 1766 else if (IS_SW_IMMD (insn)) 1767 { 1768 int rn = SW_IMMD_SOURCE (insn); 1769 int offset = SW_IMMD_OFFSET (insn); 1770 pv_t addr = pv_add_constant (reg[MEP_SP_REGNUM], offset); 1771 1772 /* If simulating this store would require us to forget 1773 everything we know about the stack frame in the name of 1774 accuracy, it would be better to just quit now. */ 1775 if (pv_area_store_would_trash (stack, addr)) 1776 break; 1777 1778 if (is_arg_spill (gdbarch, reg[rn], addr, stack)) 1779 after_last_frame_setup_insn = next_pc; 1780 1781 pv_area_store (stack, addr, 4, reg[rn]); 1782 } 1783 else if (IS_MOV (insn)) 1784 { 1785 int rn = MOV_TARGET (insn); 1786 int rm = MOV_SOURCE (insn); 1787 1788 reg[rn] = reg[rm]; 1789 1790 if (pv_is_register (reg[rm], rm) && is_arg_reg (reg[rm])) 1791 after_last_frame_setup_insn = next_pc; 1792 } 1793 else if (IS_SB (insn) || IS_SH (insn) || IS_SW (insn)) 1794 { 1795 int rn = SWBH_32_SOURCE (insn); 1796 int rm = SWBH_32_BASE (insn); 1797 int disp = SWBH_32_OFFSET (insn); 1798 int size = (IS_SB (insn) ? 1 1799 : IS_SH (insn) ? 2 1800 : (gdb_assert (IS_SW (insn)), 4)); 1801 pv_t addr = pv_add_constant (reg[rm], disp); 1802 1803 if (pv_area_store_would_trash (stack, addr)) 1804 break; 1805 1806 if (is_arg_spill (gdbarch, reg[rn], addr, stack)) 1807 after_last_frame_setup_insn = next_pc; 1808 1809 pv_area_store (stack, addr, size, reg[rn]); 1810 } 1811 else if (IS_LDC (insn)) 1812 { 1813 int rn = LDC_TARGET (insn); 1814 int cr = LDC_IMM (insn) + MEP_FIRST_CSR_REGNUM; 1815 1816 reg[rn] = reg[cr]; 1817 } 1818 else if (IS_LW (insn)) 1819 { 1820 int rn = LW_TARGET (insn); 1821 int rm = LW_BASE (insn); 1822 int offset = LW_OFFSET (insn); 1823 pv_t addr = pv_add_constant (reg[rm], offset); 1824 1825 reg[rn] = pv_area_fetch (stack, addr, 4); 1826 } 1827 else if (IS_BRA (insn) && BRA_DISP (insn) > 0) 1828 { 1829 /* When a loop appears as the first statement of a function 1830 body, gcc 4.x will use a BRA instruction to branch to the 1831 loop condition checking code. This BRA instruction is 1832 marked as part of the prologue. We therefore set next_pc 1833 to this branch target and also stop the prologue scan. 1834 The instructions at and beyond the branch target should 1835 no longer be associated with the prologue. 1836 1837 Note that we only consider forward branches here. We 1838 presume that a forward branch is being used to skip over 1839 a loop body. 1840 1841 A backwards branch is covered by the default case below. 1842 If we were to encounter a backwards branch, that would 1843 most likely mean that we've scanned through a loop body. 1844 We definitely want to stop the prologue scan when this 1845 happens and that is precisely what is done by the default 1846 case below. */ 1847 next_pc = pc + BRA_DISP (insn); 1848 after_last_frame_setup_insn = next_pc; 1849 break; 1850 } 1851 else 1852 /* We've hit some instruction we don't know how to simulate. 1853 Strictly speaking, we should set every value we're 1854 tracking to "unknown". But we'll be optimistic, assume 1855 that we have enough information already, and stop 1856 analysis here. */ 1857 break; 1858 1859 /* If this instruction changed the FP or decreased the SP (i.e., 1860 allocated more stack space), then this may be a good place to 1861 declare the prologue finished. However, there are some 1862 exceptions: 1863 1864 - If the instruction just changed the FP back to its original 1865 value, then that's probably a restore instruction. The 1866 prologue should definitely end before that. 1867 1868 - If the instruction increased the value of the SP (that is, 1869 shrunk the frame), then it's probably part of a frame 1870 teardown sequence, and the prologue should end before that. */ 1871 1872 if (! pv_is_identical (reg[MEP_FP_REGNUM], pre_insn_fp)) 1873 { 1874 if (! pv_is_register_k (reg[MEP_FP_REGNUM], MEP_FP_REGNUM, 0)) 1875 after_last_frame_setup_insn = next_pc; 1876 } 1877 else if (! pv_is_identical (reg[MEP_SP_REGNUM], pre_insn_sp)) 1878 { 1879 /* The comparison of constants looks odd, there, because .k 1880 is unsigned. All it really means is that the new value 1881 is lower than it was before the instruction. */ 1882 if (pv_is_register (pre_insn_sp, MEP_SP_REGNUM) 1883 && pv_is_register (reg[MEP_SP_REGNUM], MEP_SP_REGNUM) 1884 && ((pre_insn_sp.k - reg[MEP_SP_REGNUM].k) 1885 < (reg[MEP_SP_REGNUM].k - pre_insn_sp.k))) 1886 after_last_frame_setup_insn = next_pc; 1887 } 1888 1889 pc = next_pc; 1890 } 1891 1892 /* Is the frame size (offset, really) a known constant? */ 1893 if (pv_is_register (reg[MEP_SP_REGNUM], MEP_SP_REGNUM)) 1894 result->frame_size = reg[MEP_SP_REGNUM].k; 1895 1896 /* Was the frame pointer initialized? */ 1897 if (pv_is_register (reg[MEP_FP_REGNUM], MEP_SP_REGNUM)) 1898 { 1899 result->has_frame_ptr = 1; 1900 result->frame_ptr_offset = reg[MEP_FP_REGNUM].k; 1901 } 1902 1903 /* Record where all the registers were saved. */ 1904 pv_area_scan (stack, check_for_saved, (void *) result); 1905 1906 result->prologue_end = after_last_frame_setup_insn; 1907 1908 do_cleanups (back_to); 1909} 1910 1911 1912static CORE_ADDR 1913mep_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) 1914{ 1915 char *name; 1916 CORE_ADDR func_addr, func_end; 1917 struct mep_prologue p; 1918 1919 /* Try to find the extent of the function that contains PC. */ 1920 if (! find_pc_partial_function (pc, &name, &func_addr, &func_end)) 1921 return pc; 1922 1923 mep_analyze_prologue (gdbarch, pc, func_end, &p); 1924 return p.prologue_end; 1925} 1926 1927 1928 1929/* Breakpoints. */ 1930 1931static const unsigned char * 1932mep_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR * pcptr, int *lenptr) 1933{ 1934 static unsigned char breakpoint[] = { 0x70, 0x32 }; 1935 *lenptr = sizeof (breakpoint); 1936 return breakpoint; 1937} 1938 1939 1940 1941/* Frames and frame unwinding. */ 1942 1943 1944static struct mep_prologue * 1945mep_analyze_frame_prologue (struct frame_info *this_frame, 1946 void **this_prologue_cache) 1947{ 1948 if (! *this_prologue_cache) 1949 { 1950 CORE_ADDR func_start, stop_addr; 1951 1952 *this_prologue_cache 1953 = FRAME_OBSTACK_ZALLOC (struct mep_prologue); 1954 1955 func_start = get_frame_func (this_frame); 1956 stop_addr = get_frame_pc (this_frame); 1957 1958 /* If we couldn't find any function containing the PC, then 1959 just initialize the prologue cache, but don't do anything. */ 1960 if (! func_start) 1961 stop_addr = func_start; 1962 1963 mep_analyze_prologue (get_frame_arch (this_frame), 1964 func_start, stop_addr, *this_prologue_cache); 1965 } 1966 1967 return *this_prologue_cache; 1968} 1969 1970 1971/* Given the next frame and a prologue cache, return this frame's 1972 base. */ 1973static CORE_ADDR 1974mep_frame_base (struct frame_info *this_frame, 1975 void **this_prologue_cache) 1976{ 1977 struct mep_prologue *p 1978 = mep_analyze_frame_prologue (this_frame, this_prologue_cache); 1979 1980 /* In functions that use alloca, the distance between the stack 1981 pointer and the frame base varies dynamically, so we can't use 1982 the SP plus static information like prologue analysis to find the 1983 frame base. However, such functions must have a frame pointer, 1984 to be able to restore the SP on exit. So whenever we do have a 1985 frame pointer, use that to find the base. */ 1986 if (p->has_frame_ptr) 1987 { 1988 CORE_ADDR fp 1989 = get_frame_register_unsigned (this_frame, MEP_FP_REGNUM); 1990 return fp - p->frame_ptr_offset; 1991 } 1992 else 1993 { 1994 CORE_ADDR sp 1995 = get_frame_register_unsigned (this_frame, MEP_SP_REGNUM); 1996 return sp - p->frame_size; 1997 } 1998} 1999 2000 2001static void 2002mep_frame_this_id (struct frame_info *this_frame, 2003 void **this_prologue_cache, 2004 struct frame_id *this_id) 2005{ 2006 *this_id = frame_id_build (mep_frame_base (this_frame, this_prologue_cache), 2007 get_frame_func (this_frame)); 2008} 2009 2010 2011static struct value * 2012mep_frame_prev_register (struct frame_info *this_frame, 2013 void **this_prologue_cache, int regnum) 2014{ 2015 struct mep_prologue *p 2016 = mep_analyze_frame_prologue (this_frame, this_prologue_cache); 2017 2018 /* There are a number of complications in unwinding registers on the 2019 MeP, having to do with core functions calling VLIW functions and 2020 vice versa. 2021 2022 The least significant bit of the link register, LP.LTOM, is the 2023 VLIW mode toggle bit: it's set if a core function called a VLIW 2024 function, or vice versa, and clear when the caller and callee 2025 were both in the same mode. 2026 2027 So, if we're asked to unwind the PC, then we really want to 2028 unwind the LP and clear the least significant bit. (Real return 2029 addresses are always even.) And if we want to unwind the program 2030 status word (PSW), we need to toggle PSW.OM if LP.LTOM is set. 2031 2032 Tweaking the register values we return in this way means that the 2033 bits in BUFFERP[] are not the same as the bits you'd find at 2034 ADDRP in the inferior, so we make sure lvalp is not_lval when we 2035 do this. */ 2036 if (regnum == MEP_PC_REGNUM) 2037 { 2038 struct value *value; 2039 CORE_ADDR lp; 2040 value = mep_frame_prev_register (this_frame, this_prologue_cache, 2041 MEP_LP_REGNUM); 2042 lp = value_as_long (value); 2043 release_value (value); 2044 value_free (value); 2045 2046 return frame_unwind_got_constant (this_frame, regnum, lp & ~1); 2047 } 2048 else 2049 { 2050 CORE_ADDR frame_base = mep_frame_base (this_frame, this_prologue_cache); 2051 struct value *value; 2052 2053 /* Our caller's SP is our frame base. */ 2054 if (regnum == MEP_SP_REGNUM) 2055 return frame_unwind_got_constant (this_frame, regnum, frame_base); 2056 2057 /* If prologue analysis says we saved this register somewhere, 2058 return a description of the stack slot holding it. */ 2059 if (p->reg_offset[regnum] != 1) 2060 value = frame_unwind_got_memory (this_frame, regnum, 2061 frame_base + p->reg_offset[regnum]); 2062 2063 /* Otherwise, presume we haven't changed the value of this 2064 register, and get it from the next frame. */ 2065 else 2066 value = frame_unwind_got_register (this_frame, regnum, regnum); 2067 2068 /* If we need to toggle the operating mode, do so. */ 2069 if (regnum == MEP_PSW_REGNUM) 2070 { 2071 CORE_ADDR psw, lp; 2072 2073 psw = value_as_long (value); 2074 release_value (value); 2075 value_free (value); 2076 2077 /* Get the LP's value, too. */ 2078 value = get_frame_register_value (this_frame, MEP_LP_REGNUM); 2079 lp = value_as_long (value); 2080 release_value (value); 2081 value_free (value); 2082 2083 /* If LP.LTOM is set, then toggle PSW.OM. */ 2084 if (lp & 0x1) 2085 psw ^= 0x1000; 2086 2087 return frame_unwind_got_constant (this_frame, regnum, psw); 2088 } 2089 2090 return value; 2091 } 2092} 2093 2094 2095static const struct frame_unwind mep_frame_unwind = { 2096 NORMAL_FRAME, 2097 default_frame_unwind_stop_reason, 2098 mep_frame_this_id, 2099 mep_frame_prev_register, 2100 NULL, 2101 default_frame_sniffer 2102}; 2103 2104 2105/* Our general unwinding function can handle unwinding the PC. */ 2106static CORE_ADDR 2107mep_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 2108{ 2109 return frame_unwind_register_unsigned (next_frame, MEP_PC_REGNUM); 2110} 2111 2112 2113/* Our general unwinding function can handle unwinding the SP. */ 2114static CORE_ADDR 2115mep_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) 2116{ 2117 return frame_unwind_register_unsigned (next_frame, MEP_SP_REGNUM); 2118} 2119 2120 2121 2122/* Return values. */ 2123 2124 2125static int 2126mep_use_struct_convention (struct type *type) 2127{ 2128 return (TYPE_LENGTH (type) > MEP_GPR_SIZE); 2129} 2130 2131 2132static void 2133mep_extract_return_value (struct gdbarch *arch, 2134 struct type *type, 2135 struct regcache *regcache, 2136 gdb_byte *valbuf) 2137{ 2138 int byte_order = gdbarch_byte_order (arch); 2139 2140 /* Values that don't occupy a full register appear at the less 2141 significant end of the value. This is the offset to where the 2142 value starts. */ 2143 int offset; 2144 2145 /* Return values > MEP_GPR_SIZE bytes are returned in memory, 2146 pointed to by R0. */ 2147 gdb_assert (TYPE_LENGTH (type) <= MEP_GPR_SIZE); 2148 2149 if (byte_order == BFD_ENDIAN_BIG) 2150 offset = MEP_GPR_SIZE - TYPE_LENGTH (type); 2151 else 2152 offset = 0; 2153 2154 /* Return values that do fit in a single register are returned in R0. */ 2155 regcache_cooked_read_part (regcache, MEP_R0_REGNUM, 2156 offset, TYPE_LENGTH (type), 2157 valbuf); 2158} 2159 2160 2161static void 2162mep_store_return_value (struct gdbarch *arch, 2163 struct type *type, 2164 struct regcache *regcache, 2165 const gdb_byte *valbuf) 2166{ 2167 int byte_order = gdbarch_byte_order (arch); 2168 2169 /* Values that fit in a single register go in R0. */ 2170 if (TYPE_LENGTH (type) <= MEP_GPR_SIZE) 2171 { 2172 /* Values that don't occupy a full register appear at the least 2173 significant end of the value. This is the offset to where the 2174 value starts. */ 2175 int offset; 2176 2177 if (byte_order == BFD_ENDIAN_BIG) 2178 offset = MEP_GPR_SIZE - TYPE_LENGTH (type); 2179 else 2180 offset = 0; 2181 2182 regcache_cooked_write_part (regcache, MEP_R0_REGNUM, 2183 offset, TYPE_LENGTH (type), 2184 valbuf); 2185 } 2186 2187 /* Return values larger than a single register are returned in 2188 memory, pointed to by R0. Unfortunately, we can't count on R0 2189 pointing to the return buffer, so we raise an error here. */ 2190 else 2191 error (_("\ 2192GDB cannot set return values larger than four bytes; the Media Processor's\n\ 2193calling conventions do not provide enough information to do this.\n\ 2194Try using the 'return' command with no argument.")); 2195} 2196 2197static enum return_value_convention 2198mep_return_value (struct gdbarch *gdbarch, struct type *func_type, 2199 struct type *type, struct regcache *regcache, 2200 gdb_byte *readbuf, const gdb_byte *writebuf) 2201{ 2202 if (mep_use_struct_convention (type)) 2203 { 2204 if (readbuf) 2205 { 2206 ULONGEST addr; 2207 /* Although the address of the struct buffer gets passed in R1, it's 2208 returned in R0. Fetch R0's value and then read the memory 2209 at that address. */ 2210 regcache_raw_read_unsigned (regcache, MEP_R0_REGNUM, &addr); 2211 read_memory (addr, readbuf, TYPE_LENGTH (type)); 2212 } 2213 if (writebuf) 2214 { 2215 /* Return values larger than a single register are returned in 2216 memory, pointed to by R0. Unfortunately, we can't count on R0 2217 pointing to the return buffer, so we raise an error here. */ 2218 error (_("\ 2219GDB cannot set return values larger than four bytes; the Media Processor's\n\ 2220calling conventions do not provide enough information to do this.\n\ 2221Try using the 'return' command with no argument.")); 2222 } 2223 return RETURN_VALUE_ABI_RETURNS_ADDRESS; 2224 } 2225 2226 if (readbuf) 2227 mep_extract_return_value (gdbarch, type, regcache, readbuf); 2228 if (writebuf) 2229 mep_store_return_value (gdbarch, type, regcache, writebuf); 2230 2231 return RETURN_VALUE_REGISTER_CONVENTION; 2232} 2233 2234 2235/* Inferior calls. */ 2236 2237 2238static CORE_ADDR 2239mep_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 2240{ 2241 /* Require word alignment. */ 2242 return sp & -4; 2243} 2244 2245 2246/* From "lang_spec2.txt": 2247 2248 4.2 Calling conventions 2249 2250 4.2.1 Core register conventions 2251 2252 - Parameters should be evaluated from left to right, and they 2253 should be held in $1,$2,$3,$4 in order. The fifth parameter or 2254 after should be held in the stack. If the size is larger than 4 2255 bytes in the first four parameters, the pointer should be held in 2256 the registers instead. If the size is larger than 4 bytes in the 2257 fifth parameter or after, the pointer should be held in the stack. 2258 2259 - Return value of a function should be held in register $0. If the 2260 size of return value is larger than 4 bytes, $1 should hold the 2261 pointer pointing memory that would hold the return value. In this 2262 case, the first parameter should be held in $2, the second one in 2263 $3, and the third one in $4, and the forth parameter or after 2264 should be held in the stack. 2265 2266 [This doesn't say so, but arguments shorter than four bytes are 2267 passed in the least significant end of a four-byte word when 2268 they're passed on the stack.] */ 2269 2270 2271/* Traverse the list of ARGC arguments ARGV; for every ARGV[i] too 2272 large to fit in a register, save it on the stack, and place its 2273 address in COPY[i]. SP is the initial stack pointer; return the 2274 new stack pointer. */ 2275static CORE_ADDR 2276push_large_arguments (CORE_ADDR sp, int argc, struct value **argv, 2277 CORE_ADDR copy[]) 2278{ 2279 int i; 2280 2281 for (i = 0; i < argc; i++) 2282 { 2283 unsigned arg_len = TYPE_LENGTH (value_type (argv[i])); 2284 2285 if (arg_len > MEP_GPR_SIZE) 2286 { 2287 /* Reserve space for the copy, and then round the SP down, to 2288 make sure it's all aligned properly. */ 2289 sp = (sp - arg_len) & -4; 2290 write_memory (sp, value_contents (argv[i]), arg_len); 2291 copy[i] = sp; 2292 } 2293 } 2294 2295 return sp; 2296} 2297 2298 2299static CORE_ADDR 2300mep_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 2301 struct regcache *regcache, CORE_ADDR bp_addr, 2302 int argc, struct value **argv, CORE_ADDR sp, 2303 int struct_return, 2304 CORE_ADDR struct_addr) 2305{ 2306 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2307 CORE_ADDR *copy = (CORE_ADDR *) alloca (argc * sizeof (copy[0])); 2308 CORE_ADDR func_addr = find_function_addr (function, NULL); 2309 int i; 2310 2311 /* The number of the next register available to hold an argument. */ 2312 int arg_reg; 2313 2314 /* The address of the next stack slot available to hold an argument. */ 2315 CORE_ADDR arg_stack; 2316 2317 /* The address of the end of the stack area for arguments. This is 2318 just for error checking. */ 2319 CORE_ADDR arg_stack_end; 2320 2321 sp = push_large_arguments (sp, argc, argv, copy); 2322 2323 /* Reserve space for the stack arguments, if any. */ 2324 arg_stack_end = sp; 2325 if (argc + (struct_addr ? 1 : 0) > 4) 2326 sp -= ((argc + (struct_addr ? 1 : 0)) - 4) * MEP_GPR_SIZE; 2327 2328 arg_reg = MEP_R1_REGNUM; 2329 arg_stack = sp; 2330 2331 /* If we're returning a structure by value, push the pointer to the 2332 buffer as the first argument. */ 2333 if (struct_return) 2334 { 2335 regcache_cooked_write_unsigned (regcache, arg_reg, struct_addr); 2336 arg_reg++; 2337 } 2338 2339 for (i = 0; i < argc; i++) 2340 { 2341 unsigned arg_size = TYPE_LENGTH (value_type (argv[i])); 2342 ULONGEST value; 2343 2344 /* Arguments that fit in a GPR get expanded to fill the GPR. */ 2345 if (arg_size <= MEP_GPR_SIZE) 2346 value = extract_unsigned_integer (value_contents (argv[i]), 2347 TYPE_LENGTH (value_type (argv[i])), 2348 byte_order); 2349 2350 /* Arguments too large to fit in a GPR get copied to the stack, 2351 and we pass a pointer to the copy. */ 2352 else 2353 value = copy[i]; 2354 2355 /* We use $1 -- $4 for passing arguments, then use the stack. */ 2356 if (arg_reg <= MEP_R4_REGNUM) 2357 { 2358 regcache_cooked_write_unsigned (regcache, arg_reg, value); 2359 arg_reg++; 2360 } 2361 else 2362 { 2363 char buf[MEP_GPR_SIZE]; 2364 store_unsigned_integer (buf, MEP_GPR_SIZE, byte_order, value); 2365 write_memory (arg_stack, buf, MEP_GPR_SIZE); 2366 arg_stack += MEP_GPR_SIZE; 2367 } 2368 } 2369 2370 gdb_assert (arg_stack <= arg_stack_end); 2371 2372 /* Set the return address. */ 2373 regcache_cooked_write_unsigned (regcache, MEP_LP_REGNUM, bp_addr); 2374 2375 /* Update the stack pointer. */ 2376 regcache_cooked_write_unsigned (regcache, MEP_SP_REGNUM, sp); 2377 2378 return sp; 2379} 2380 2381 2382static struct frame_id 2383mep_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 2384{ 2385 CORE_ADDR sp = get_frame_register_unsigned (this_frame, MEP_SP_REGNUM); 2386 return frame_id_build (sp, get_frame_pc (this_frame)); 2387} 2388 2389 2390 2391/* Initialization. */ 2392 2393 2394static struct gdbarch * 2395mep_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 2396{ 2397 struct gdbarch *gdbarch; 2398 struct gdbarch_tdep *tdep; 2399 2400 /* Which me_module are we building a gdbarch object for? */ 2401 CONFIG_ATTR me_module; 2402 2403 /* If we have a BFD in hand, figure out which me_module it was built 2404 for. Otherwise, use the no-particular-me_module code. */ 2405 if (info.abfd) 2406 { 2407 /* The way to get the me_module code depends on the object file 2408 format. At the moment, we only know how to handle ELF. */ 2409 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) 2410 me_module = elf_elfheader (info.abfd)->e_flags & EF_MEP_INDEX_MASK; 2411 else 2412 me_module = CONFIG_NONE; 2413 } 2414 else 2415 me_module = CONFIG_NONE; 2416 2417 /* If we're setting the architecture from a file, check the 2418 endianness of the file against that of the me_module. */ 2419 if (info.abfd) 2420 { 2421 /* The negations on either side make the comparison treat all 2422 non-zero (true) values as equal. */ 2423 if (! bfd_big_endian (info.abfd) != ! me_module_big_endian (me_module)) 2424 { 2425 const char *module_name = me_module_name (me_module); 2426 const char *module_endianness 2427 = me_module_big_endian (me_module) ? "big" : "little"; 2428 const char *file_name = bfd_get_filename (info.abfd); 2429 const char *file_endianness 2430 = bfd_big_endian (info.abfd) ? "big" : "little"; 2431 2432 fputc_unfiltered ('\n', gdb_stderr); 2433 if (module_name) 2434 warning (_("the MeP module '%s' is %s-endian, but the executable\n" 2435 "%s is %s-endian."), 2436 module_name, module_endianness, 2437 file_name, file_endianness); 2438 else 2439 warning (_("the selected MeP module is %s-endian, but the " 2440 "executable\n" 2441 "%s is %s-endian."), 2442 module_endianness, file_name, file_endianness); 2443 } 2444 } 2445 2446 /* Find a candidate among the list of architectures we've created 2447 already. info->bfd_arch_info needs to match, but we also want 2448 the right me_module: the ELF header's e_flags field needs to 2449 match as well. */ 2450 for (arches = gdbarch_list_lookup_by_info (arches, &info); 2451 arches != NULL; 2452 arches = gdbarch_list_lookup_by_info (arches->next, &info)) 2453 if (gdbarch_tdep (arches->gdbarch)->me_module == me_module) 2454 return arches->gdbarch; 2455 2456 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); 2457 gdbarch = gdbarch_alloc (&info, tdep); 2458 2459 /* Get a CGEN CPU descriptor for this architecture. */ 2460 { 2461 const char *mach_name = info.bfd_arch_info->printable_name; 2462 enum cgen_endian endian = (info.byte_order == BFD_ENDIAN_BIG 2463 ? CGEN_ENDIAN_BIG 2464 : CGEN_ENDIAN_LITTLE); 2465 2466 tdep->cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, 2467 CGEN_CPU_OPEN_ENDIAN, endian, 2468 CGEN_CPU_OPEN_END); 2469 } 2470 2471 tdep->me_module = me_module; 2472 2473 /* Register set. */ 2474 set_gdbarch_read_pc (gdbarch, mep_read_pc); 2475 set_gdbarch_write_pc (gdbarch, mep_write_pc); 2476 set_gdbarch_num_regs (gdbarch, MEP_NUM_RAW_REGS); 2477 set_gdbarch_sp_regnum (gdbarch, MEP_SP_REGNUM); 2478 set_gdbarch_register_name (gdbarch, mep_register_name); 2479 set_gdbarch_register_type (gdbarch, mep_register_type); 2480 set_gdbarch_num_pseudo_regs (gdbarch, MEP_NUM_PSEUDO_REGS); 2481 set_gdbarch_pseudo_register_read (gdbarch, mep_pseudo_register_read); 2482 set_gdbarch_pseudo_register_write (gdbarch, mep_pseudo_register_write); 2483 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mep_debug_reg_to_regnum); 2484 set_gdbarch_stab_reg_to_regnum (gdbarch, mep_debug_reg_to_regnum); 2485 2486 set_gdbarch_register_reggroup_p (gdbarch, mep_register_reggroup_p); 2487 reggroup_add (gdbarch, all_reggroup); 2488 reggroup_add (gdbarch, general_reggroup); 2489 reggroup_add (gdbarch, save_reggroup); 2490 reggroup_add (gdbarch, restore_reggroup); 2491 reggroup_add (gdbarch, mep_csr_reggroup); 2492 reggroup_add (gdbarch, mep_cr_reggroup); 2493 reggroup_add (gdbarch, mep_ccr_reggroup); 2494 2495 /* Disassembly. */ 2496 set_gdbarch_print_insn (gdbarch, mep_gdb_print_insn); 2497 2498 /* Breakpoints. */ 2499 set_gdbarch_breakpoint_from_pc (gdbarch, mep_breakpoint_from_pc); 2500 set_gdbarch_decr_pc_after_break (gdbarch, 0); 2501 set_gdbarch_skip_prologue (gdbarch, mep_skip_prologue); 2502 2503 /* Frames and frame unwinding. */ 2504 frame_unwind_append_unwinder (gdbarch, &mep_frame_unwind); 2505 set_gdbarch_unwind_pc (gdbarch, mep_unwind_pc); 2506 set_gdbarch_unwind_sp (gdbarch, mep_unwind_sp); 2507 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 2508 set_gdbarch_frame_args_skip (gdbarch, 0); 2509 2510 /* Return values. */ 2511 set_gdbarch_return_value (gdbarch, mep_return_value); 2512 2513 /* Inferior function calls. */ 2514 set_gdbarch_frame_align (gdbarch, mep_frame_align); 2515 set_gdbarch_push_dummy_call (gdbarch, mep_push_dummy_call); 2516 set_gdbarch_dummy_id (gdbarch, mep_dummy_id); 2517 2518 return gdbarch; 2519} 2520 2521/* Provide a prototype to silence -Wmissing-prototypes. */ 2522extern initialize_file_ftype _initialize_mep_tdep; 2523 2524void 2525_initialize_mep_tdep (void) 2526{ 2527 mep_csr_reggroup = reggroup_new ("csr", USER_REGGROUP); 2528 mep_cr_reggroup = reggroup_new ("cr", USER_REGGROUP); 2529 mep_ccr_reggroup = reggroup_new ("ccr", USER_REGGROUP); 2530 2531 register_gdbarch_init (bfd_arch_mep, mep_gdbarch_init); 2532 2533 mep_init_pseudoregister_maps (); 2534} 2535