1/* Common target dependent code for GDB on ARM systems.
2   Copyright (C) 2002, 2003, 2007, 2008, 2009, 2010, 2011
3   Free Software Foundation, Inc.
4
5   This file is part of GDB.
6
7   This program is free software; you can redistribute it and/or modify
8   it under the terms of the GNU General Public License as published by
9   the Free Software Foundation; either version 3 of the License, or
10   (at your option) any later version.
11
12   This program is distributed in the hope that it will be useful,
13   but WITHOUT ANY WARRANTY; without even the implied warranty of
14   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15   GNU General Public License for more details.
16
17   You should have received a copy of the GNU General Public License
18   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
19
20#ifndef ARM_TDEP_H
21#define ARM_TDEP_H
22
23/* Forward declarations.  */
24struct gdbarch;
25struct regset;
26struct address_space;
27
28/* Register numbers of various important registers.  */
29
30enum gdb_regnum {
31  ARM_A1_REGNUM = 0,		/* first integer-like argument */
32  ARM_A4_REGNUM = 3,		/* last integer-like argument */
33  ARM_AP_REGNUM = 11,
34  ARM_IP_REGNUM = 12,
35  ARM_SP_REGNUM = 13,		/* Contains address of top of stack */
36  ARM_LR_REGNUM = 14,		/* address to return to from a function call */
37  ARM_PC_REGNUM = 15,		/* Contains program counter */
38  ARM_F0_REGNUM = 16,		/* first floating point register */
39  ARM_F3_REGNUM = 19,		/* last floating point argument register */
40  ARM_F7_REGNUM = 23, 		/* last floating point register */
41  ARM_FPS_REGNUM = 24,		/* floating point status register */
42  ARM_PS_REGNUM = 25,		/* Contains processor status */
43  ARM_WR0_REGNUM,		/* WMMX data registers.  */
44  ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
45  ARM_WC0_REGNUM,		/* WMMX control registers.  */
46  ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
47  ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
48  ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
49  ARM_WCGR0_REGNUM,		/* WMMX general purpose registers.  */
50  ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
51  ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
52  ARM_D0_REGNUM,		/* VFP double-precision registers.  */
53  ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
54  ARM_FPSCR_REGNUM,
55
56  ARM_NUM_REGS,
57
58  /* Other useful registers.  */
59  ARM_FP_REGNUM = 11,		/* Frame register in ARM code, if used.  */
60  THUMB_FP_REGNUM = 7,		/* Frame register in Thumb code, if used.  */
61  ARM_NUM_ARG_REGS = 4,
62  ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
63  ARM_NUM_FP_ARG_REGS = 4,
64  ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
65};
66
67/* Size of integer registers.  */
68#define INT_REGISTER_SIZE		4
69
70/* Say how long FP registers are.  Used for documentation purposes and
71   code readability in this header.  IEEE extended doubles are 80
72   bits.  DWORD aligned they use 96 bits.  */
73#define FP_REGISTER_SIZE	12
74
75/* Number of machine registers.  The only define actually required
76   is gdbarch_num_regs.  The other definitions are used for documentation
77   purposes and code readability.  */
78/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
79   (and called PS for processor status) so the status bits can be cleared
80   from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
81   in PS.  */
82#define NUM_FREGS	8	/* Number of floating point registers.  */
83#define NUM_SREGS	2	/* Number of status registers.  */
84#define NUM_GREGS	16	/* Number of general purpose registers.  */
85
86
87/* Instruction condition field values.  */
88#define INST_EQ		0x0
89#define INST_NE		0x1
90#define INST_CS		0x2
91#define INST_CC		0x3
92#define INST_MI		0x4
93#define INST_PL		0x5
94#define INST_VS		0x6
95#define INST_VC		0x7
96#define INST_HI		0x8
97#define INST_LS		0x9
98#define INST_GE		0xa
99#define INST_LT		0xb
100#define INST_GT		0xc
101#define INST_LE		0xd
102#define INST_AL		0xe
103#define INST_NV		0xf
104
105#define FLAG_N		0x80000000
106#define FLAG_Z		0x40000000
107#define FLAG_C		0x20000000
108#define FLAG_V		0x10000000
109
110#define CPSR_T		0x20
111
112#define XPSR_T		0x01000000
113
114/* Type of floating-point code in use by inferior.  There are really 3 models
115   that are traditionally supported (plus the endianness issue), but gcc can
116   only generate 2 of those.  The third is APCS_FLOAT, where arguments to
117   functions are passed in floating-point registers.
118
119   In addition to the traditional models, VFP adds two more.
120
121   If you update this enum, don't forget to update fp_model_strings in
122   arm-tdep.c.  */
123
124enum arm_float_model
125{
126  ARM_FLOAT_AUTO,	/* Automatic detection.  Do not set in tdep.  */
127  ARM_FLOAT_SOFT_FPA,	/* Traditional soft-float (mixed-endian on LE ARM).  */
128  ARM_FLOAT_FPA,	/* FPA co-processor.  GCC calling convention.  */
129  ARM_FLOAT_SOFT_VFP,	/* Soft-float with pure-endian doubles.  */
130  ARM_FLOAT_VFP,	/* Full VFP calling convention.  */
131  ARM_FLOAT_LAST	/* Keep at end.  */
132};
133
134/* ABI used by the inferior.  */
135enum arm_abi_kind
136{
137  ARM_ABI_AUTO,
138  ARM_ABI_APCS,
139  ARM_ABI_AAPCS,
140  ARM_ABI_LAST
141};
142
143/* Convention for returning structures.  */
144
145enum struct_return
146{
147  pcc_struct_return,		/* Return "short" structures in memory.  */
148  reg_struct_return		/* Return "short" structures in registers.  */
149};
150
151/* Target-dependent structure in gdbarch.  */
152struct gdbarch_tdep
153{
154  /* The ABI for this architecture.  It should never be set to
155     ARM_ABI_AUTO.  */
156  enum arm_abi_kind arm_abi;
157
158  enum arm_float_model fp_model; /* Floating point calling conventions.  */
159
160  int have_fpa_registers;	/* Does the target report the FPA registers?  */
161  int have_vfp_registers;	/* Does the target report the VFP registers?  */
162  int have_vfp_pseudos;		/* Are we synthesizing the single precision
163				   VFP registers?  */
164  int have_neon_pseudos;	/* Are we synthesizing the quad precision
165				   NEON registers?  Requires
166				   have_vfp_pseudos.  */
167  int have_neon;		/* Do we have a NEON unit?  */
168
169  int is_m;			/* Does the target follow the "M" profile.  */
170  CORE_ADDR lowest_pc;		/* Lowest address at which instructions
171				   will appear.  */
172
173  const char *arm_breakpoint;	/* Breakpoint pattern for an ARM insn.  */
174  int arm_breakpoint_size;	/* And its size.  */
175  const char *thumb_breakpoint;	/* Breakpoint pattern for a Thumb insn.  */
176  int thumb_breakpoint_size;	/* And its size.  */
177
178  /* If the Thumb breakpoint is an undefined instruction (which is
179     affected by IT blocks) rather than a BKPT instruction (which is
180     not), then we need a 32-bit Thumb breakpoint to preserve the
181     instruction count in IT blocks.  */
182  const char *thumb2_breakpoint;
183  int thumb2_breakpoint_size;
184
185  int jb_pc;			/* Offset to PC value in jump buffer.
186				   If this is negative, longjmp support
187				   will be disabled.  */
188  size_t jb_elt_size;		/* And the size of each entry in the buf.  */
189
190  /* Convention for returning structures.  */
191  enum struct_return struct_return;
192
193  /* Cached core file helpers.  */
194  struct regset *gregset, *fpregset;
195
196  /* ISA-specific data types.  */
197  struct type *arm_ext_type;
198  struct type *neon_double_type;
199  struct type *neon_quad_type;
200
201  /* Return the expected next PC if FRAME is stopped at a syscall
202     instruction.  */
203  CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
204};
205
206/* Structures used for displaced stepping.  */
207
208/* The maximum number of temporaries available for displaced instructions.  */
209#define DISPLACED_TEMPS			16
210/* The maximum number of modified instructions generated for one single-stepped
211   instruction, including the breakpoint (usually at the end of the instruction
212   sequence) and any scratch words, etc.  */
213#define DISPLACED_MODIFIED_INSNS	8
214
215struct displaced_step_closure
216{
217  ULONGEST tmp[DISPLACED_TEMPS];
218  int rd;
219  int wrote_to_pc;
220  union
221  {
222    struct
223    {
224      int xfersize;
225      int rn;			   /* Writeback register.  */
226      unsigned int immed : 1;      /* Offset is immediate.  */
227      unsigned int writeback : 1;  /* Perform base-register writeback.  */
228      unsigned int restore_r4 : 1; /* Used r4 as scratch.  */
229    } ldst;
230
231    struct
232    {
233      unsigned long dest;
234      unsigned int link : 1;
235      unsigned int exchange : 1;
236      unsigned int cond : 4;
237    } branch;
238
239    struct
240    {
241      unsigned int regmask;
242      int rn;
243      CORE_ADDR xfer_addr;
244      unsigned int load : 1;
245      unsigned int user : 1;
246      unsigned int increment : 1;
247      unsigned int before : 1;
248      unsigned int writeback : 1;
249      unsigned int cond : 4;
250    } block;
251
252    struct
253    {
254      unsigned int immed : 1;
255    } preload;
256
257    struct
258    {
259      /* If non-NULL, override generic SVC handling (e.g. for a particular
260         OS).  */
261      int (*copy_svc_os) (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
262			  struct regcache *regs,
263			  struct displaced_step_closure *dsc);
264    } svc;
265  } u;
266
267  /* The size of original instruction, 2 or 4.  */
268  unsigned int insn_size;
269  /* True if the original insn (and thus all replacement insns) are Thumb
270     instead of ARM.   */
271  unsigned int is_thumb;
272
273  /* The slots in the array is used in this way below,
274     - ARM instruction occupies one slot,
275     - Thumb 16 bit instruction occupies one slot,
276     - Thumb 32-bit instruction occupies *two* slots, one part for each.  */
277  unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
278  int numinsns;
279  CORE_ADDR insn_addr;
280  CORE_ADDR scratch_base;
281  void (*cleanup) (struct gdbarch *, struct regcache *,
282		   struct displaced_step_closure *);
283};
284
285/* Values for the WRITE_PC argument to displaced_write_reg.  If the register
286   write may write to the PC, specifies the way the CPSR T bit, etc. is
287   modified by the instruction.  */
288
289enum pc_write_style
290{
291  BRANCH_WRITE_PC,
292  BX_WRITE_PC,
293  LOAD_WRITE_PC,
294  ALU_WRITE_PC,
295  CANNOT_WRITE_PC
296};
297
298extern void
299  arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
300			      CORE_ADDR to, struct regcache *regs,
301			      struct displaced_step_closure *dsc);
302extern void
303  arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
304			      CORE_ADDR to, struct displaced_step_closure *dsc);
305extern ULONGEST
306  displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
307		      int regno);
308extern void
309  displaced_write_reg (struct regcache *regs,
310		       struct displaced_step_closure *dsc, int regno,
311		       ULONGEST val, enum pc_write_style write_pc);
312
313CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
314CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
315void arm_insert_single_step_breakpoint (struct gdbarch *,
316					struct address_space *, CORE_ADDR);
317int arm_software_single_step (struct frame_info *);
318int arm_frame_is_thumb (struct frame_info *frame);
319
320extern struct displaced_step_closure *
321  arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR,
322				struct regcache *);
323extern void arm_displaced_step_fixup (struct gdbarch *,
324				      struct displaced_step_closure *,
325				      CORE_ADDR, CORE_ADDR, struct regcache *);
326
327/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode.  */
328extern int arm_psr_thumb_bit (struct gdbarch *);
329
330/* Is the instruction at the given memory address a Thumb or ARM
331   instruction?  */
332extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
333
334/* Functions exported from armbsd-tdep.h.  */
335
336/* Return the appropriate register set for the core section identified
337   by SECT_NAME and SECT_SIZE.  */
338
339extern const struct regset *
340  armbsd_regset_from_core_section (struct gdbarch *gdbarch,
341				   const char *sect_name, size_t sect_size);
342
343#endif /* arm-tdep.h */
344