1/* { dg-do compile { target { powerpc_fprs && ilp32 } } } */ 2/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w" } */ 3/* { dg-final { scan-assembler-not "lfd" } } */ 4/* { dg-final { scan-assembler-not "sfd" } } */ 5/* { dg-final { scan-assembler "lfq" } } */ 6/* { dg-final { scan-assembler "stfq" } } */ 7 8register volatile double t1 __asm__("fr0"); 9register volatile double t2 __asm__("fr1"); 10register volatile double t3 __asm__("fr2"), t4 __asm__("fr3"); 11void t(double *a, double *b) 12{ 13 t1 = a[-1]; 14 t2 = a[0]; 15 t3 = a[1]; 16 t4 = a[2]; 17 b[-1] = t1; 18 b[0] = t2; 19 b[1] = t3; 20 b[2] = t4; 21} 22 23