1/* { dg-do compile { target { ilp32 } } } */ 2/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w -mhard-float" } */ 3/* This used to ICE as the peephole was not checking to see 4 if the register is a floating point one (I think this cannot 5 happen in real life except in this example). */ 6 7register volatile double t1 __asm__("r14"); 8register volatile double t2 __asm__("r15"); 9register volatile double t3 __asm__("r16"), t4 __asm__("r17"); 10void t(double *a, double *b) 11{ 12 t1 = a[-1]; 13 t2 = a[0]; 14 t3 = a[1]; 15 t4 = a[2]; 16 b[-1] = t1; 17 b[0] = t2; 18 b[1] = t3; 19 b[2] = t4; 20} 21 22