1/* 2 * Copyright (c) 2000-2012 Apple Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28/* 29 * @OSF_COPYRIGHT@ 30 */ 31#include <platforms.h> 32#include <vm/vm_page.h> 33#include <pexpert/pexpert.h> 34 35#include <i386/cpuid.h> 36 37static boolean_t cpuid_dbg 38#if DEBUG 39 = TRUE; 40#else 41 = FALSE; 42#endif 43#define DBG(x...) \ 44 do { \ 45 if (cpuid_dbg) \ 46 kprintf(x); \ 47 } while (0) \ 48 49#define min(a,b) ((a) < (b) ? (a) : (b)) 50#define quad(hi,lo) (((uint64_t)(hi)) << 32 | (lo)) 51 52/* Only for 32bit values */ 53#define bit32(n) (1U << (n)) 54#define bitmask32(h,l) ((bit32(h)|(bit32(h)-1)) & ~(bit32(l)-1)) 55#define bitfield32(x,h,l) ((((x) & bitmask32(h,l)) >> l)) 56 57/* 58 * Leaf 2 cache descriptor encodings. 59 */ 60typedef enum { 61 _NULL_, /* NULL (empty) descriptor */ 62 CACHE, /* Cache */ 63 TLB, /* TLB */ 64 STLB, /* Shared second-level unified TLB */ 65 PREFETCH /* Prefetch size */ 66} cpuid_leaf2_desc_type_t; 67 68typedef enum { 69 NA, /* Not Applicable */ 70 FULLY, /* Fully-associative */ 71 TRACE, /* Trace Cache (P4 only) */ 72 INST, /* Instruction TLB */ 73 DATA, /* Data TLB */ 74 DATA0, /* Data TLB, 1st level */ 75 DATA1, /* Data TLB, 2nd level */ 76 L1, /* L1 (unified) cache */ 77 L1_INST, /* L1 Instruction cache */ 78 L1_DATA, /* L1 Data cache */ 79 L2, /* L2 (unified) cache */ 80 L3, /* L3 (unified) cache */ 81 L2_2LINESECTOR, /* L2 (unified) cache with 2 lines per sector */ 82 L3_2LINESECTOR, /* L3(unified) cache with 2 lines per sector */ 83 SMALL, /* Small page TLB */ 84 LARGE, /* Large page TLB */ 85 BOTH /* Small and Large page TLB */ 86} cpuid_leaf2_qualifier_t; 87 88typedef struct cpuid_cache_descriptor { 89 uint8_t value; /* descriptor code */ 90 uint8_t type; /* cpuid_leaf2_desc_type_t */ 91 uint8_t level; /* level of cache/TLB hierachy */ 92 uint8_t ways; /* wayness of cache */ 93 uint16_t size; /* cachesize or TLB pagesize */ 94 uint16_t entries; /* number of TLB entries or linesize */ 95} cpuid_cache_descriptor_t; 96 97/* 98 * These multipliers are used to encode 1*K .. 64*M in a 16 bit size field 99 */ 100#define K (1) 101#define M (1024) 102 103/* 104 * Intel cache descriptor table: 105 */ 106static cpuid_cache_descriptor_t intel_cpuid_leaf2_descriptor_table[] = { 107// ------------------------------------------------------- 108// value type level ways size entries 109// ------------------------------------------------------- 110 { 0x00, _NULL_, NA, NA, NA, NA }, 111 { 0x01, TLB, INST, 4, SMALL, 32 }, 112 { 0x02, TLB, INST, FULLY, LARGE, 2 }, 113 { 0x03, TLB, DATA, 4, SMALL, 64 }, 114 { 0x04, TLB, DATA, 4, LARGE, 8 }, 115 { 0x05, TLB, DATA1, 4, LARGE, 32 }, 116 { 0x06, CACHE, L1_INST, 4, 8*K, 32 }, 117 { 0x08, CACHE, L1_INST, 4, 16*K, 32 }, 118 { 0x09, CACHE, L1_INST, 4, 32*K, 64 }, 119 { 0x0A, CACHE, L1_DATA, 2, 8*K, 32 }, 120 { 0x0B, TLB, INST, 4, LARGE, 4 }, 121 { 0x0C, CACHE, L1_DATA, 4, 16*K, 32 }, 122 { 0x0D, CACHE, L1_DATA, 4, 16*K, 64 }, 123 { 0x0E, CACHE, L1_DATA, 6, 24*K, 64 }, 124 { 0x21, CACHE, L2, 8, 256*K, 64 }, 125 { 0x22, CACHE, L3_2LINESECTOR, 4, 512*K, 64 }, 126 { 0x23, CACHE, L3_2LINESECTOR, 8, 1*M, 64 }, 127 { 0x25, CACHE, L3_2LINESECTOR, 8, 2*M, 64 }, 128 { 0x29, CACHE, L3_2LINESECTOR, 8, 4*M, 64 }, 129 { 0x2C, CACHE, L1_DATA, 8, 32*K, 64 }, 130 { 0x30, CACHE, L1_INST, 8, 32*K, 64 }, 131 { 0x40, CACHE, L2, NA, 0, NA }, 132 { 0x41, CACHE, L2, 4, 128*K, 32 }, 133 { 0x42, CACHE, L2, 4, 256*K, 32 }, 134 { 0x43, CACHE, L2, 4, 512*K, 32 }, 135 { 0x44, CACHE, L2, 4, 1*M, 32 }, 136 { 0x45, CACHE, L2, 4, 2*M, 32 }, 137 { 0x46, CACHE, L3, 4, 4*M, 64 }, 138 { 0x47, CACHE, L3, 8, 8*M, 64 }, 139 { 0x48, CACHE, L2, 12, 3*M, 64 }, 140 { 0x49, CACHE, L2, 16, 4*M, 64 }, 141 { 0x4A, CACHE, L3, 12, 6*M, 64 }, 142 { 0x4B, CACHE, L3, 16, 8*M, 64 }, 143 { 0x4C, CACHE, L3, 12, 12*M, 64 }, 144 { 0x4D, CACHE, L3, 16, 16*M, 64 }, 145 { 0x4E, CACHE, L2, 24, 6*M, 64 }, 146 { 0x4F, TLB, INST, NA, SMALL, 32 }, 147 { 0x50, TLB, INST, NA, BOTH, 64 }, 148 { 0x51, TLB, INST, NA, BOTH, 128 }, 149 { 0x52, TLB, INST, NA, BOTH, 256 }, 150 { 0x55, TLB, INST, FULLY, BOTH, 7 }, 151 { 0x56, TLB, DATA0, 4, LARGE, 16 }, 152 { 0x57, TLB, DATA0, 4, SMALL, 16 }, 153 { 0x59, TLB, DATA0, FULLY, SMALL, 16 }, 154 { 0x5A, TLB, DATA0, 4, LARGE, 32 }, 155 { 0x5B, TLB, DATA, NA, BOTH, 64 }, 156 { 0x5C, TLB, DATA, NA, BOTH, 128 }, 157 { 0x5D, TLB, DATA, NA, BOTH, 256 }, 158 { 0x60, CACHE, L1, 16*K, 8, 64 }, 159 { 0x61, CACHE, L1, 4, 8*K, 64 }, 160 { 0x62, CACHE, L1, 4, 16*K, 64 }, 161 { 0x63, CACHE, L1, 4, 32*K, 64 }, 162 { 0x70, CACHE, TRACE, 8, 12*K, NA }, 163 { 0x71, CACHE, TRACE, 8, 16*K, NA }, 164 { 0x72, CACHE, TRACE, 8, 32*K, NA }, 165 { 0x76, TLB, INST, NA, BOTH, 8 }, 166 { 0x78, CACHE, L2, 4, 1*M, 64 }, 167 { 0x79, CACHE, L2_2LINESECTOR, 8, 128*K, 64 }, 168 { 0x7A, CACHE, L2_2LINESECTOR, 8, 256*K, 64 }, 169 { 0x7B, CACHE, L2_2LINESECTOR, 8, 512*K, 64 }, 170 { 0x7C, CACHE, L2_2LINESECTOR, 8, 1*M, 64 }, 171 { 0x7D, CACHE, L2, 8, 2*M, 64 }, 172 { 0x7F, CACHE, L2, 2, 512*K, 64 }, 173 { 0x80, CACHE, L2, 8, 512*K, 64 }, 174 { 0x82, CACHE, L2, 8, 256*K, 32 }, 175 { 0x83, CACHE, L2, 8, 512*K, 32 }, 176 { 0x84, CACHE, L2, 8, 1*M, 32 }, 177 { 0x85, CACHE, L2, 8, 2*M, 32 }, 178 { 0x86, CACHE, L2, 4, 512*K, 64 }, 179 { 0x87, CACHE, L2, 8, 1*M, 64 }, 180 { 0xB0, TLB, INST, 4, SMALL, 128 }, 181 { 0xB1, TLB, INST, 4, LARGE, 8 }, 182 { 0xB2, TLB, INST, 4, SMALL, 64 }, 183 { 0xB3, TLB, DATA, 4, SMALL, 128 }, 184 { 0xB4, TLB, DATA1, 4, SMALL, 256 }, 185 { 0xB5, TLB, DATA1, 8, SMALL, 64 }, 186 { 0xB6, TLB, DATA1, 8, SMALL, 128 }, 187 { 0xBA, TLB, DATA1, 4, BOTH, 64 }, 188 { 0xC1, STLB, DATA1, 8, SMALL, 1024}, 189 { 0xCA, STLB, DATA1, 4, SMALL, 512 }, 190 { 0xD0, CACHE, L3, 4, 512*K, 64 }, 191 { 0xD1, CACHE, L3, 4, 1*M, 64 }, 192 { 0xD2, CACHE, L3, 4, 2*M, 64 }, 193 { 0xD3, CACHE, L3, 4, 4*M, 64 }, 194 { 0xD4, CACHE, L3, 4, 8*M, 64 }, 195 { 0xD6, CACHE, L3, 8, 1*M, 64 }, 196 { 0xD7, CACHE, L3, 8, 2*M, 64 }, 197 { 0xD8, CACHE, L3, 8, 4*M, 64 }, 198 { 0xD9, CACHE, L3, 8, 8*M, 64 }, 199 { 0xDA, CACHE, L3, 8, 12*M, 64 }, 200 { 0xDC, CACHE, L3, 12, 1536*K, 64 }, 201 { 0xDD, CACHE, L3, 12, 3*M, 64 }, 202 { 0xDE, CACHE, L3, 12, 6*M, 64 }, 203 { 0xDF, CACHE, L3, 12, 12*M, 64 }, 204 { 0xE0, CACHE, L3, 12, 18*M, 64 }, 205 { 0xE2, CACHE, L3, 16, 2*M, 64 }, 206 { 0xE3, CACHE, L3, 16, 4*M, 64 }, 207 { 0xE4, CACHE, L3, 16, 8*M, 64 }, 208 { 0xE5, CACHE, L3, 16, 16*M, 64 }, 209 { 0xE6, CACHE, L3, 16, 24*M, 64 }, 210 { 0xF0, PREFETCH, NA, NA, 64, NA }, 211 { 0xF1, PREFETCH, NA, NA, 128, NA }, 212 { 0xFF, CACHE, NA, NA, 0, NA } 213}; 214#define INTEL_LEAF2_DESC_NUM (sizeof(intel_cpuid_leaf2_descriptor_table) / \ 215 sizeof(cpuid_cache_descriptor_t)) 216 217static inline cpuid_cache_descriptor_t * 218cpuid_leaf2_find(uint8_t value) 219{ 220 unsigned int i; 221 222 for (i = 0; i < INTEL_LEAF2_DESC_NUM; i++) 223 if (intel_cpuid_leaf2_descriptor_table[i].value == value) 224 return &intel_cpuid_leaf2_descriptor_table[i]; 225 return NULL; 226} 227 228/* 229 * CPU identification routines. 230 */ 231 232static i386_cpu_info_t cpuid_cpu_info; 233static i386_cpu_info_t *cpuid_cpu_infop = NULL; 234 235static void cpuid_fn(uint32_t selector, uint32_t *result) 236{ 237 do_cpuid(selector, result); 238 DBG("cpuid_fn(0x%08x) eax:0x%08x ebx:0x%08x ecx:0x%08x edx:0x%08x\n", 239 selector, result[0], result[1], result[2], result[3]); 240} 241 242static const char *cache_type_str[LCACHE_MAX] = { 243 "Lnone", "L1I", "L1D", "L2U", "L3U" 244}; 245 246/* this function is Intel-specific */ 247static void 248cpuid_set_cache_info( i386_cpu_info_t * info_p ) 249{ 250 uint32_t cpuid_result[4]; 251 uint32_t reg[4]; 252 uint32_t index; 253 uint32_t linesizes[LCACHE_MAX]; 254 unsigned int i; 255 unsigned int j; 256 boolean_t cpuid_deterministic_supported = FALSE; 257 258 DBG("cpuid_set_cache_info(%p)\n", info_p); 259 260 bzero( linesizes, sizeof(linesizes) ); 261 262 /* Get processor cache descriptor info using leaf 2. We don't use 263 * this internally, but must publish it for KEXTs. 264 */ 265 cpuid_fn(2, cpuid_result); 266 for (j = 0; j < 4; j++) { 267 if ((cpuid_result[j] >> 31) == 1) /* bit31 is validity */ 268 continue; 269 ((uint32_t *) info_p->cache_info)[j] = cpuid_result[j]; 270 } 271 /* first byte gives number of cpuid calls to get all descriptors */ 272 for (i = 1; i < info_p->cache_info[0]; i++) { 273 if (i*16 > sizeof(info_p->cache_info)) 274 break; 275 cpuid_fn(2, cpuid_result); 276 for (j = 0; j < 4; j++) { 277 if ((cpuid_result[j] >> 31) == 1) 278 continue; 279 ((uint32_t *) info_p->cache_info)[4*i+j] = 280 cpuid_result[j]; 281 } 282 } 283 284 /* 285 * Get cache info using leaf 4, the "deterministic cache parameters." 286 * Most processors Mac OS X supports implement this flavor of CPUID. 287 * Loop over each cache on the processor. 288 */ 289 cpuid_fn(0, cpuid_result); 290 if (cpuid_result[eax] >= 4) 291 cpuid_deterministic_supported = TRUE; 292 293 for (index = 0; cpuid_deterministic_supported; index++) { 294 cache_type_t type = Lnone; 295 uint32_t cache_type; 296 uint32_t cache_level; 297 uint32_t cache_sharing; 298 uint32_t cache_linesize; 299 uint32_t cache_sets; 300 uint32_t cache_associativity; 301 uint32_t cache_size; 302 uint32_t cache_partitions; 303 uint32_t colors; 304 305 reg[eax] = 4; /* cpuid request 4 */ 306 reg[ecx] = index; /* index starting at 0 */ 307 cpuid(reg); 308 DBG("cpuid(4) index=%d eax=0x%x\n", index, reg[eax]); 309 cache_type = bitfield32(reg[eax], 4, 0); 310 if (cache_type == 0) 311 break; /* no more caches */ 312 cache_level = bitfield32(reg[eax], 7, 5); 313 cache_sharing = bitfield32(reg[eax], 25, 14) + 1; 314 info_p->cpuid_cores_per_package 315 = bitfield32(reg[eax], 31, 26) + 1; 316 cache_linesize = bitfield32(reg[ebx], 11, 0) + 1; 317 cache_partitions = bitfield32(reg[ebx], 21, 12) + 1; 318 cache_associativity = bitfield32(reg[ebx], 31, 22) + 1; 319 cache_sets = bitfield32(reg[ecx], 31, 0) + 1; 320 321 /* Map type/levels returned by CPUID into cache_type_t */ 322 switch (cache_level) { 323 case 1: 324 type = cache_type == 1 ? L1D : 325 cache_type == 2 ? L1I : 326 Lnone; 327 break; 328 case 2: 329 type = cache_type == 3 ? L2U : 330 Lnone; 331 break; 332 case 3: 333 type = cache_type == 3 ? L3U : 334 Lnone; 335 break; 336 default: 337 type = Lnone; 338 } 339 340 /* The total size of a cache is: 341 * ( linesize * sets * associativity * partitions ) 342 */ 343 if (type != Lnone) { 344 cache_size = cache_linesize * cache_sets * 345 cache_associativity * cache_partitions; 346 info_p->cache_size[type] = cache_size; 347 info_p->cache_sharing[type] = cache_sharing; 348 info_p->cache_partitions[type] = cache_partitions; 349 linesizes[type] = cache_linesize; 350 351 DBG(" cache_size[%s] : %d\n", 352 cache_type_str[type], cache_size); 353 DBG(" cache_sharing[%s] : %d\n", 354 cache_type_str[type], cache_sharing); 355 DBG(" cache_partitions[%s]: %d\n", 356 cache_type_str[type], cache_partitions); 357 358 /* 359 * Overwrite associativity determined via 360 * CPUID.0x80000006 -- this leaf is more 361 * accurate 362 */ 363 if (type == L2U) 364 info_p->cpuid_cache_L2_associativity = cache_associativity; 365 366 /* Compute the number of page colors for this cache, 367 * which is: 368 * ( linesize * sets ) / page_size 369 * 370 * To help visualize this, consider two views of a 371 * physical address. To the cache, it is composed 372 * of a line offset, a set selector, and a tag. 373 * To VM, it is composed of a page offset, a page 374 * color, and other bits in the pageframe number: 375 * 376 * +-----------------+---------+--------+ 377 * cache: | tag | set | offset | 378 * +-----------------+---------+--------+ 379 * 380 * +-----------------+-------+----------+ 381 * VM: | don't care | color | pg offset| 382 * +-----------------+-------+----------+ 383 * 384 * The color is those bits in (set+offset) not covered 385 * by the page offset. 386 */ 387 colors = ( cache_linesize * cache_sets ) >> 12; 388 389 if ( colors > vm_cache_geometry_colors ) 390 vm_cache_geometry_colors = colors; 391 } 392 } 393 DBG(" vm_cache_geometry_colors: %d\n", vm_cache_geometry_colors); 394 395 /* 396 * If deterministic cache parameters are not available, use 397 * something else 398 */ 399 if (info_p->cpuid_cores_per_package == 0) { 400 info_p->cpuid_cores_per_package = 1; 401 402 /* cpuid define in 1024 quantities */ 403 info_p->cache_size[L2U] = info_p->cpuid_cache_size * 1024; 404 info_p->cache_sharing[L2U] = 1; 405 info_p->cache_partitions[L2U] = 1; 406 407 linesizes[L2U] = info_p->cpuid_cache_linesize; 408 409 DBG(" cache_size[L2U] : %d\n", 410 info_p->cache_size[L2U]); 411 DBG(" cache_sharing[L2U] : 1\n"); 412 DBG(" cache_partitions[L2U]: 1\n"); 413 DBG(" linesizes[L2U] : %d\n", 414 info_p->cpuid_cache_linesize); 415 } 416 417 /* 418 * What linesize to publish? We use the L2 linesize if any, 419 * else the L1D. 420 */ 421 if ( linesizes[L2U] ) 422 info_p->cache_linesize = linesizes[L2U]; 423 else if (linesizes[L1D]) 424 info_p->cache_linesize = linesizes[L1D]; 425 else panic("no linesize"); 426 DBG(" cache_linesize : %d\n", info_p->cache_linesize); 427 428 /* 429 * Extract and publish TLB information from Leaf 2 descriptors. 430 */ 431 DBG(" %ld leaf2 descriptors:\n", sizeof(info_p->cache_info)); 432 for (i = 1; i < sizeof(info_p->cache_info); i++) { 433 cpuid_cache_descriptor_t *descp; 434 int id; 435 int level; 436 int page; 437 438 DBG(" 0x%02x", info_p->cache_info[i]); 439 descp = cpuid_leaf2_find(info_p->cache_info[i]); 440 if (descp == NULL) 441 continue; 442 443 switch (descp->type) { 444 case TLB: 445 page = (descp->size == SMALL) ? TLB_SMALL : TLB_LARGE; 446 /* determine I or D: */ 447 switch (descp->level) { 448 case INST: 449 id = TLB_INST; 450 break; 451 case DATA: 452 case DATA0: 453 case DATA1: 454 id = TLB_DATA; 455 break; 456 default: 457 continue; 458 } 459 /* determine level: */ 460 switch (descp->level) { 461 case DATA1: 462 level = 1; 463 break; 464 default: 465 level = 0; 466 } 467 info_p->cpuid_tlb[id][page][level] = descp->entries; 468 break; 469 case STLB: 470 info_p->cpuid_stlb = descp->entries; 471 } 472 } 473 DBG("\n"); 474} 475 476static void 477cpuid_set_generic_info(i386_cpu_info_t *info_p) 478{ 479 uint32_t reg[4]; 480 char str[128], *p; 481 482 DBG("cpuid_set_generic_info(%p)\n", info_p); 483 484 /* do cpuid 0 to get vendor */ 485 cpuid_fn(0, reg); 486 info_p->cpuid_max_basic = reg[eax]; 487 bcopy((char *)®[ebx], &info_p->cpuid_vendor[0], 4); /* ug */ 488 bcopy((char *)®[ecx], &info_p->cpuid_vendor[8], 4); 489 bcopy((char *)®[edx], &info_p->cpuid_vendor[4], 4); 490 info_p->cpuid_vendor[12] = 0; 491 492 /* get extended cpuid results */ 493 cpuid_fn(0x80000000, reg); 494 info_p->cpuid_max_ext = reg[eax]; 495 496 /* check to see if we can get brand string */ 497 if (info_p->cpuid_max_ext >= 0x80000004) { 498 /* 499 * The brand string 48 bytes (max), guaranteed to 500 * be NUL terminated. 501 */ 502 cpuid_fn(0x80000002, reg); 503 bcopy((char *)reg, &str[0], 16); 504 cpuid_fn(0x80000003, reg); 505 bcopy((char *)reg, &str[16], 16); 506 cpuid_fn(0x80000004, reg); 507 bcopy((char *)reg, &str[32], 16); 508 for (p = str; *p != '\0'; p++) { 509 if (*p != ' ') break; 510 } 511 strlcpy(info_p->cpuid_brand_string, 512 p, sizeof(info_p->cpuid_brand_string)); 513 514 if (!strncmp(info_p->cpuid_brand_string, CPUID_STRING_UNKNOWN, 515 min(sizeof(info_p->cpuid_brand_string), 516 strlen(CPUID_STRING_UNKNOWN) + 1))) { 517 /* 518 * This string means we have a firmware-programmable brand string, 519 * and the firmware couldn't figure out what sort of CPU we have. 520 */ 521 info_p->cpuid_brand_string[0] = '\0'; 522 } 523 } 524 525 /* Get cache and addressing info. */ 526 if (info_p->cpuid_max_ext >= 0x80000006) { 527 uint32_t assoc; 528 cpuid_fn(0x80000006, reg); 529 info_p->cpuid_cache_linesize = bitfield32(reg[ecx], 7, 0); 530 assoc = bitfield32(reg[ecx],15,12); 531 /* 532 * L2 associativity is encoded, though in an insufficiently 533 * descriptive fashion, e.g. 24-way is mapped to 16-way. 534 * Represent a fully associative cache as 0xFFFF. 535 * Overwritten by associativity as determined via CPUID.4 536 * if available. 537 */ 538 if (assoc == 6) 539 assoc = 8; 540 else if (assoc == 8) 541 assoc = 16; 542 else if (assoc == 0xF) 543 assoc = 0xFFFF; 544 info_p->cpuid_cache_L2_associativity = assoc; 545 info_p->cpuid_cache_size = bitfield32(reg[ecx],31,16); 546 cpuid_fn(0x80000008, reg); 547 info_p->cpuid_address_bits_physical = 548 bitfield32(reg[eax], 7, 0); 549 info_p->cpuid_address_bits_virtual = 550 bitfield32(reg[eax],15, 8); 551 } 552 553 /* 554 * Get processor signature and decode 555 * and bracket this with the approved procedure for reading the 556 * the microcode version number a.k.a. signature a.k.a. BIOS ID 557 */ 558 wrmsr64(MSR_IA32_BIOS_SIGN_ID, 0); 559 cpuid_fn(1, reg); 560 info_p->cpuid_microcode_version = 561 (uint32_t) (rdmsr64(MSR_IA32_BIOS_SIGN_ID) >> 32); 562 info_p->cpuid_signature = reg[eax]; 563 info_p->cpuid_stepping = bitfield32(reg[eax], 3, 0); 564 info_p->cpuid_model = bitfield32(reg[eax], 7, 4); 565 info_p->cpuid_family = bitfield32(reg[eax], 11, 8); 566 info_p->cpuid_type = bitfield32(reg[eax], 13, 12); 567 info_p->cpuid_extmodel = bitfield32(reg[eax], 19, 16); 568 info_p->cpuid_extfamily = bitfield32(reg[eax], 27, 20); 569 info_p->cpuid_brand = bitfield32(reg[ebx], 7, 0); 570 info_p->cpuid_features = quad(reg[ecx], reg[edx]); 571 572 /* Get "processor flag"; necessary for microcode update matching */ 573 info_p->cpuid_processor_flag = (rdmsr64(MSR_IA32_PLATFORM_ID)>> 50) & 0x7; 574 575 /* Fold extensions into family/model */ 576 if (info_p->cpuid_family == 0x0f) 577 info_p->cpuid_family += info_p->cpuid_extfamily; 578 if (info_p->cpuid_family == 0x0f || info_p->cpuid_family == 0x06) 579 info_p->cpuid_model += (info_p->cpuid_extmodel << 4); 580 581 if (info_p->cpuid_features & CPUID_FEATURE_HTT) 582 info_p->cpuid_logical_per_package = 583 bitfield32(reg[ebx], 23, 16); 584 else 585 info_p->cpuid_logical_per_package = 1; 586 587 if (info_p->cpuid_max_ext >= 0x80000001) { 588 cpuid_fn(0x80000001, reg); 589 info_p->cpuid_extfeatures = 590 quad(reg[ecx], reg[edx]); 591 } 592 593 DBG(" max_basic : %d\n", info_p->cpuid_max_basic); 594 DBG(" max_ext : 0x%08x\n", info_p->cpuid_max_ext); 595 DBG(" vendor : %s\n", info_p->cpuid_vendor); 596 DBG(" brand_string : %s\n", info_p->cpuid_brand_string); 597 DBG(" signature : 0x%08x\n", info_p->cpuid_signature); 598 DBG(" stepping : %d\n", info_p->cpuid_stepping); 599 DBG(" model : %d\n", info_p->cpuid_model); 600 DBG(" family : %d\n", info_p->cpuid_family); 601 DBG(" type : %d\n", info_p->cpuid_type); 602 DBG(" extmodel : %d\n", info_p->cpuid_extmodel); 603 DBG(" extfamily : %d\n", info_p->cpuid_extfamily); 604 DBG(" brand : %d\n", info_p->cpuid_brand); 605 DBG(" features : 0x%016llx\n", info_p->cpuid_features); 606 DBG(" extfeatures : 0x%016llx\n", info_p->cpuid_extfeatures); 607 DBG(" logical_per_package : %d\n", info_p->cpuid_logical_per_package); 608 DBG(" microcode_version : 0x%08x\n", info_p->cpuid_microcode_version); 609 610 /* Fold in the Invariant TSC feature bit, if present */ 611 if (info_p->cpuid_max_ext >= 0x80000007) { 612 cpuid_fn(0x80000007, reg); 613 info_p->cpuid_extfeatures |= 614 reg[edx] & (uint32_t)CPUID_EXTFEATURE_TSCI; 615 DBG(" extfeatures : 0x%016llx\n", 616 info_p->cpuid_extfeatures); 617 } 618 619 if (info_p->cpuid_max_basic >= 0x5) { 620 cpuid_mwait_leaf_t *cmp = &info_p->cpuid_mwait_leaf; 621 622 /* 623 * Extract the Monitor/Mwait Leaf info: 624 */ 625 cpuid_fn(5, reg); 626 cmp->linesize_min = reg[eax]; 627 cmp->linesize_max = reg[ebx]; 628 cmp->extensions = reg[ecx]; 629 cmp->sub_Cstates = reg[edx]; 630 info_p->cpuid_mwait_leafp = cmp; 631 632 DBG(" Monitor/Mwait Leaf:\n"); 633 DBG(" linesize_min : %d\n", cmp->linesize_min); 634 DBG(" linesize_max : %d\n", cmp->linesize_max); 635 DBG(" extensions : %d\n", cmp->extensions); 636 DBG(" sub_Cstates : 0x%08x\n", cmp->sub_Cstates); 637 } 638 639 if (info_p->cpuid_max_basic >= 0x6) { 640 cpuid_thermal_leaf_t *ctp = &info_p->cpuid_thermal_leaf; 641 642 /* 643 * The thermal and Power Leaf: 644 */ 645 cpuid_fn(6, reg); 646 ctp->sensor = bitfield32(reg[eax], 0, 0); 647 ctp->dynamic_acceleration = bitfield32(reg[eax], 1, 1); 648 ctp->invariant_APIC_timer = bitfield32(reg[eax], 2, 2); 649 ctp->core_power_limits = bitfield32(reg[eax], 4, 4); 650 ctp->fine_grain_clock_mod = bitfield32(reg[eax], 5, 5); 651 ctp->package_thermal_intr = bitfield32(reg[eax], 6, 6); 652 ctp->thresholds = bitfield32(reg[ebx], 3, 0); 653 ctp->ACNT_MCNT = bitfield32(reg[ecx], 0, 0); 654 ctp->hardware_feedback = bitfield32(reg[ecx], 1, 1); 655 ctp->energy_policy = bitfield32(reg[ecx], 3, 3); 656 info_p->cpuid_thermal_leafp = ctp; 657 658 DBG(" Thermal/Power Leaf:\n"); 659 DBG(" sensor : %d\n", ctp->sensor); 660 DBG(" dynamic_acceleration : %d\n", ctp->dynamic_acceleration); 661 DBG(" invariant_APIC_timer : %d\n", ctp->invariant_APIC_timer); 662 DBG(" core_power_limits : %d\n", ctp->core_power_limits); 663 DBG(" fine_grain_clock_mod : %d\n", ctp->fine_grain_clock_mod); 664 DBG(" package_thermal_intr : %d\n", ctp->package_thermal_intr); 665 DBG(" thresholds : %d\n", ctp->thresholds); 666 DBG(" ACNT_MCNT : %d\n", ctp->ACNT_MCNT); 667 DBG(" ACNT2 : %d\n", ctp->hardware_feedback); 668 DBG(" energy_policy : %d\n", ctp->energy_policy); 669 } 670 671 if (info_p->cpuid_max_basic >= 0xa) { 672 cpuid_arch_perf_leaf_t *capp = &info_p->cpuid_arch_perf_leaf; 673 674 /* 675 * Architectural Performance Monitoring Leaf: 676 */ 677 cpuid_fn(0xa, reg); 678 capp->version = bitfield32(reg[eax], 7, 0); 679 capp->number = bitfield32(reg[eax], 15, 8); 680 capp->width = bitfield32(reg[eax], 23, 16); 681 capp->events_number = bitfield32(reg[eax], 31, 24); 682 capp->events = reg[ebx]; 683 capp->fixed_number = bitfield32(reg[edx], 4, 0); 684 capp->fixed_width = bitfield32(reg[edx], 12, 5); 685 info_p->cpuid_arch_perf_leafp = capp; 686 687 DBG(" Architectural Performance Monitoring Leaf:\n"); 688 DBG(" version : %d\n", capp->version); 689 DBG(" number : %d\n", capp->number); 690 DBG(" width : %d\n", capp->width); 691 DBG(" events_number : %d\n", capp->events_number); 692 DBG(" events : %d\n", capp->events); 693 DBG(" fixed_number : %d\n", capp->fixed_number); 694 DBG(" fixed_width : %d\n", capp->fixed_width); 695 } 696 697 if (info_p->cpuid_max_basic >= 0xd) { 698 cpuid_xsave_leaf_t *xsp = &info_p->cpuid_xsave_leaf; 699 /* 700 * XSAVE Features: 701 */ 702 cpuid_fn(0xd, info_p->cpuid_xsave_leaf.extended_state); 703 info_p->cpuid_xsave_leafp = xsp; 704 705 DBG(" XSAVE Leaf:\n"); 706 DBG(" EAX : 0x%x\n", xsp->extended_state[eax]); 707 DBG(" EBX : 0x%x\n", xsp->extended_state[ebx]); 708 DBG(" ECX : 0x%x\n", xsp->extended_state[ecx]); 709 DBG(" EDX : 0x%x\n", xsp->extended_state[edx]); 710 } 711 712 if (info_p->cpuid_model >= CPUID_MODEL_IVYBRIDGE) { 713 /* 714 * Leaf7 Features: 715 */ 716 cpuid_fn(0x7, reg); 717 info_p->cpuid_leaf7_features = reg[ebx]; 718 719 DBG(" Feature Leaf7:\n"); 720 DBG(" EBX : 0x%x\n", reg[ebx]); 721 } 722 723 return; 724} 725 726static uint32_t 727cpuid_set_cpufamily(i386_cpu_info_t *info_p) 728{ 729 uint32_t cpufamily = CPUFAMILY_UNKNOWN; 730 731 switch (info_p->cpuid_family) { 732 case 6: 733 switch (info_p->cpuid_model) { 734 case 15: 735 cpufamily = CPUFAMILY_INTEL_MEROM; 736 break; 737 case 23: 738 cpufamily = CPUFAMILY_INTEL_PENRYN; 739 break; 740 case CPUID_MODEL_NEHALEM: 741 case CPUID_MODEL_FIELDS: 742 case CPUID_MODEL_DALES: 743 case CPUID_MODEL_NEHALEM_EX: 744 cpufamily = CPUFAMILY_INTEL_NEHALEM; 745 break; 746 case CPUID_MODEL_DALES_32NM: 747 case CPUID_MODEL_WESTMERE: 748 case CPUID_MODEL_WESTMERE_EX: 749 cpufamily = CPUFAMILY_INTEL_WESTMERE; 750 break; 751 case CPUID_MODEL_SANDYBRIDGE: 752 case CPUID_MODEL_JAKETOWN: 753 cpufamily = CPUFAMILY_INTEL_SANDYBRIDGE; 754 break; 755 case CPUID_MODEL_IVYBRIDGE: 756 case CPUID_MODEL_IVYBRIDGE_EP: 757 cpufamily = CPUFAMILY_INTEL_IVYBRIDGE; 758 break; 759 case CPUID_MODEL_HASWELL: 760 case CPUID_MODEL_HASWELL_ULT: 761 case CPUID_MODEL_CRYSTALWELL: 762 cpufamily = CPUFAMILY_INTEL_HASWELL; 763 break; 764 } 765 break; 766 } 767 768 info_p->cpuid_cpufamily = cpufamily; 769 DBG("cpuid_set_cpufamily(%p) returning 0x%x\n", info_p, cpufamily); 770 return cpufamily; 771} 772/* 773 * Must be invoked either when executing single threaded, or with 774 * independent synchronization. 775 */ 776void 777cpuid_set_info(void) 778{ 779 i386_cpu_info_t *info_p = &cpuid_cpu_info; 780 781 cpuid_set_generic_info(info_p); 782 783 /* verify we are running on a supported CPU */ 784 if ((strncmp(CPUID_VID_INTEL, info_p->cpuid_vendor, 785 min(strlen(CPUID_STRING_UNKNOWN) + 1, 786 sizeof(info_p->cpuid_vendor)))) || 787 (cpuid_set_cpufamily(info_p) == CPUFAMILY_UNKNOWN)) 788 panic("Unsupported CPU"); 789 790 info_p->cpuid_cpu_type = CPU_TYPE_X86; 791 info_p->cpuid_cpu_subtype = CPU_SUBTYPE_X86_ARCH1; 792 /* Must be invoked after set_generic_info */ 793 cpuid_set_cache_info(info_p); 794 795 /* 796 * Find the number of enabled cores and threads 797 * (which determines whether SMT/Hyperthreading is active). 798 */ 799 switch (info_p->cpuid_cpufamily) { 800 case CPUFAMILY_INTEL_WESTMERE: { 801 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT); 802 info_p->core_count = bitfield32((uint32_t)msr, 19, 16); 803 info_p->thread_count = bitfield32((uint32_t)msr, 15, 0); 804 break; 805 } 806 case CPUFAMILY_INTEL_HASWELL: 807 case CPUFAMILY_INTEL_IVYBRIDGE: 808 case CPUFAMILY_INTEL_SANDYBRIDGE: 809 case CPUFAMILY_INTEL_NEHALEM: { 810 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT); 811 info_p->core_count = bitfield32((uint32_t)msr, 31, 16); 812 info_p->thread_count = bitfield32((uint32_t)msr, 15, 0); 813 break; 814 } 815 } 816 if (info_p->core_count == 0) { 817 info_p->core_count = info_p->cpuid_cores_per_package; 818 info_p->thread_count = info_p->cpuid_logical_per_package; 819 } 820 DBG("cpuid_set_info():\n"); 821 DBG(" core_count : %d\n", info_p->core_count); 822 DBG(" thread_count : %d\n", info_p->thread_count); 823 824 info_p->cpuid_model_string = ""; /* deprecated */ 825} 826 827static struct table { 828 uint64_t mask; 829 const char *name; 830} feature_map[] = { 831 {CPUID_FEATURE_FPU, "FPU"}, 832 {CPUID_FEATURE_VME, "VME"}, 833 {CPUID_FEATURE_DE, "DE"}, 834 {CPUID_FEATURE_PSE, "PSE"}, 835 {CPUID_FEATURE_TSC, "TSC"}, 836 {CPUID_FEATURE_MSR, "MSR"}, 837 {CPUID_FEATURE_PAE, "PAE"}, 838 {CPUID_FEATURE_MCE, "MCE"}, 839 {CPUID_FEATURE_CX8, "CX8"}, 840 {CPUID_FEATURE_APIC, "APIC"}, 841 {CPUID_FEATURE_SEP, "SEP"}, 842 {CPUID_FEATURE_MTRR, "MTRR"}, 843 {CPUID_FEATURE_PGE, "PGE"}, 844 {CPUID_FEATURE_MCA, "MCA"}, 845 {CPUID_FEATURE_CMOV, "CMOV"}, 846 {CPUID_FEATURE_PAT, "PAT"}, 847 {CPUID_FEATURE_PSE36, "PSE36"}, 848 {CPUID_FEATURE_PSN, "PSN"}, 849 {CPUID_FEATURE_CLFSH, "CLFSH"}, 850 {CPUID_FEATURE_DS, "DS"}, 851 {CPUID_FEATURE_ACPI, "ACPI"}, 852 {CPUID_FEATURE_MMX, "MMX"}, 853 {CPUID_FEATURE_FXSR, "FXSR"}, 854 {CPUID_FEATURE_SSE, "SSE"}, 855 {CPUID_FEATURE_SSE2, "SSE2"}, 856 {CPUID_FEATURE_SS, "SS"}, 857 {CPUID_FEATURE_HTT, "HTT"}, 858 {CPUID_FEATURE_TM, "TM"}, 859 {CPUID_FEATURE_PBE, "PBE"}, 860 {CPUID_FEATURE_SSE3, "SSE3"}, 861 {CPUID_FEATURE_PCLMULQDQ, "PCLMULQDQ"}, 862 {CPUID_FEATURE_DTES64, "DTES64"}, 863 {CPUID_FEATURE_MONITOR, "MON"}, 864 {CPUID_FEATURE_DSCPL, "DSCPL"}, 865 {CPUID_FEATURE_VMX, "VMX"}, 866 {CPUID_FEATURE_SMX, "SMX"}, 867 {CPUID_FEATURE_EST, "EST"}, 868 {CPUID_FEATURE_TM2, "TM2"}, 869 {CPUID_FEATURE_SSSE3, "SSSE3"}, 870 {CPUID_FEATURE_CID, "CID"}, 871 {CPUID_FEATURE_FMA, "FMA"}, 872 {CPUID_FEATURE_CX16, "CX16"}, 873 {CPUID_FEATURE_xTPR, "TPR"}, 874 {CPUID_FEATURE_PDCM, "PDCM"}, 875 {CPUID_FEATURE_SSE4_1, "SSE4.1"}, 876 {CPUID_FEATURE_SSE4_2, "SSE4.2"}, 877 {CPUID_FEATURE_x2APIC, "x2APIC"}, 878 {CPUID_FEATURE_MOVBE, "MOVBE"}, 879 {CPUID_FEATURE_POPCNT, "POPCNT"}, 880 {CPUID_FEATURE_AES, "AES"}, 881 {CPUID_FEATURE_VMM, "VMM"}, 882 {CPUID_FEATURE_PCID, "PCID"}, 883 {CPUID_FEATURE_XSAVE, "XSAVE"}, 884 {CPUID_FEATURE_OSXSAVE, "OSXSAVE"}, 885 {CPUID_FEATURE_SEGLIM64, "SEGLIM64"}, 886 {CPUID_FEATURE_TSCTMR, "TSCTMR"}, 887 {CPUID_FEATURE_AVX1_0, "AVX1.0"}, 888 {CPUID_FEATURE_RDRAND, "RDRAND"}, 889 {CPUID_FEATURE_F16C, "F16C"}, 890 {0, 0} 891}, 892extfeature_map[] = { 893 {CPUID_EXTFEATURE_SYSCALL, "SYSCALL"}, 894 {CPUID_EXTFEATURE_XD, "XD"}, 895 {CPUID_EXTFEATURE_1GBPAGE, "1GBPAGE"}, 896 {CPUID_EXTFEATURE_EM64T, "EM64T"}, 897 {CPUID_EXTFEATURE_LAHF, "LAHF"}, 898 {CPUID_EXTFEATURE_RDTSCP, "RDTSCP"}, 899 {CPUID_EXTFEATURE_TSCI, "TSCI"}, 900 {0, 0} 901 902}, 903leaf7_feature_map[] = { 904 {CPUID_LEAF7_FEATURE_SMEP, "SMEP"}, 905 {CPUID_LEAF7_FEATURE_ENFSTRG, "ENFSTRG"}, 906 {CPUID_LEAF7_FEATURE_RDWRFSGS, "RDWRFSGS"}, 907 {CPUID_LEAF7_FEATURE_TSCOFF, "TSC_THREAD_OFFSET"}, 908 {CPUID_LEAF7_FEATURE_BMI1, "BMI1"}, 909 {CPUID_LEAF7_FEATURE_HLE, "HLE"}, 910 {CPUID_LEAF7_FEATURE_AVX2, "AVX2"}, 911 {CPUID_LEAF7_FEATURE_BMI2, "BMI2"}, 912 {CPUID_LEAF7_FEATURE_INVPCID, "INVPCID"}, 913 {CPUID_LEAF7_FEATURE_RTM, "RTM"}, 914 {0, 0} 915}; 916 917static char * 918cpuid_get_names(struct table *map, uint64_t bits, char *buf, unsigned buf_len) 919{ 920 size_t len = 0; 921 char *p = buf; 922 int i; 923 924 for (i = 0; map[i].mask != 0; i++) { 925 if ((bits & map[i].mask) == 0) 926 continue; 927 if (len && ((size_t) (p - buf) < (buf_len - 1))) 928 *p++ = ' '; 929 len = min(strlen(map[i].name), (size_t)((buf_len-1)-(p-buf))); 930 if (len == 0) 931 break; 932 bcopy(map[i].name, p, len); 933 p += len; 934 } 935 *p = '\0'; 936 return buf; 937} 938 939i386_cpu_info_t * 940cpuid_info(void) 941{ 942 /* Set-up the cpuid_info stucture lazily */ 943 if (cpuid_cpu_infop == NULL) { 944 PE_parse_boot_argn("-cpuid", &cpuid_dbg, sizeof(cpuid_dbg)); 945 cpuid_set_info(); 946 cpuid_cpu_infop = &cpuid_cpu_info; 947 } 948 return cpuid_cpu_infop; 949} 950 951char * 952cpuid_get_feature_names(uint64_t features, char *buf, unsigned buf_len) 953{ 954 return cpuid_get_names(feature_map, features, buf, buf_len); 955} 956 957char * 958cpuid_get_extfeature_names(uint64_t extfeatures, char *buf, unsigned buf_len) 959{ 960 return cpuid_get_names(extfeature_map, extfeatures, buf, buf_len); 961} 962 963char * 964cpuid_get_leaf7_feature_names(uint64_t features, char *buf, unsigned buf_len) 965{ 966 return cpuid_get_names(leaf7_feature_map, features, buf, buf_len); 967} 968 969void 970cpuid_feature_display( 971 const char *header) 972{ 973 char buf[256]; 974 975 kprintf("%s: %s", header, 976 cpuid_get_feature_names(cpuid_features(), buf, sizeof(buf))); 977 if (cpuid_leaf7_features()) 978 kprintf(" %s", cpuid_get_leaf7_feature_names( 979 cpuid_leaf7_features(), buf, sizeof(buf))); 980 kprintf("\n"); 981 if (cpuid_features() & CPUID_FEATURE_HTT) { 982#define s_if_plural(n) ((n > 1) ? "s" : "") 983 kprintf(" HTT: %d core%s per package;" 984 " %d logical cpu%s per package\n", 985 cpuid_cpu_infop->cpuid_cores_per_package, 986 s_if_plural(cpuid_cpu_infop->cpuid_cores_per_package), 987 cpuid_cpu_infop->cpuid_logical_per_package, 988 s_if_plural(cpuid_cpu_infop->cpuid_logical_per_package)); 989 } 990} 991 992void 993cpuid_extfeature_display( 994 const char *header) 995{ 996 char buf[256]; 997 998 kprintf("%s: %s\n", header, 999 cpuid_get_extfeature_names(cpuid_extfeatures(), 1000 buf, sizeof(buf))); 1001} 1002 1003void 1004cpuid_cpu_display( 1005 const char *header) 1006{ 1007 if (cpuid_cpu_infop->cpuid_brand_string[0] != '\0') { 1008 kprintf("%s: %s\n", header, cpuid_cpu_infop->cpuid_brand_string); 1009 } 1010} 1011 1012unsigned int 1013cpuid_family(void) 1014{ 1015 return cpuid_info()->cpuid_family; 1016} 1017 1018uint32_t 1019cpuid_cpufamily(void) 1020{ 1021 return cpuid_info()->cpuid_cpufamily; 1022} 1023 1024cpu_type_t 1025cpuid_cputype(void) 1026{ 1027 return cpuid_info()->cpuid_cpu_type; 1028} 1029 1030cpu_subtype_t 1031cpuid_cpusubtype(void) 1032{ 1033 return cpuid_info()->cpuid_cpu_subtype; 1034} 1035 1036uint64_t 1037cpuid_features(void) 1038{ 1039 static int checked = 0; 1040 char fpu_arg[20] = { 0 }; 1041 1042 (void) cpuid_info(); 1043 if (!checked) { 1044 /* check for boot-time fpu limitations */ 1045 if (PE_parse_boot_argn("_fpu", &fpu_arg[0], sizeof (fpu_arg))) { 1046 printf("limiting fpu features to: %s\n", fpu_arg); 1047 if (!strncmp("387", fpu_arg, sizeof("387")) || !strncmp("mmx", fpu_arg, sizeof("mmx"))) { 1048 printf("no sse or sse2\n"); 1049 cpuid_cpu_infop->cpuid_features &= ~(CPUID_FEATURE_SSE | CPUID_FEATURE_SSE2 | CPUID_FEATURE_FXSR); 1050 } else if (!strncmp("sse", fpu_arg, sizeof("sse"))) { 1051 printf("no sse2\n"); 1052 cpuid_cpu_infop->cpuid_features &= ~(CPUID_FEATURE_SSE2); 1053 } 1054 } 1055 checked = 1; 1056 } 1057 return cpuid_cpu_infop->cpuid_features; 1058} 1059 1060uint64_t 1061cpuid_extfeatures(void) 1062{ 1063 return cpuid_info()->cpuid_extfeatures; 1064} 1065 1066uint64_t 1067cpuid_leaf7_features(void) 1068{ 1069 return cpuid_info()->cpuid_leaf7_features; 1070} 1071 1072static i386_vmm_info_t *_cpuid_vmm_infop = NULL; 1073static i386_vmm_info_t _cpuid_vmm_info; 1074 1075static void 1076cpuid_init_vmm_info(i386_vmm_info_t *info_p) 1077{ 1078 uint32_t reg[4]; 1079 uint32_t max_vmm_leaf; 1080 1081 bzero(info_p, sizeof(*info_p)); 1082 1083 if (!cpuid_vmm_present()) 1084 return; 1085 1086 DBG("cpuid_init_vmm_info(%p)\n", info_p); 1087 1088 /* do cpuid 0x40000000 to get VMM vendor */ 1089 cpuid_fn(0x40000000, reg); 1090 max_vmm_leaf = reg[eax]; 1091 bcopy((char *)®[ebx], &info_p->cpuid_vmm_vendor[0], 4); 1092 bcopy((char *)®[ecx], &info_p->cpuid_vmm_vendor[4], 4); 1093 bcopy((char *)®[edx], &info_p->cpuid_vmm_vendor[8], 4); 1094 info_p->cpuid_vmm_vendor[12] = '\0'; 1095 1096 if (0 == strcmp(info_p->cpuid_vmm_vendor, CPUID_VMM_ID_VMWARE)) { 1097 /* VMware identification string: kb.vmware.com/kb/1009458 */ 1098 info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_VMWARE; 1099 } else { 1100 info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_UNKNOWN; 1101 } 1102 1103 /* VMM generic leaves: https://lkml.org/lkml/2008/10/1/246 */ 1104 if (max_vmm_leaf >= 0x40000010) { 1105 cpuid_fn(0x40000010, reg); 1106 1107 info_p->cpuid_vmm_tsc_frequency = reg[eax]; 1108 info_p->cpuid_vmm_bus_frequency = reg[ebx]; 1109 } 1110 1111 DBG(" vmm_vendor : %s\n", info_p->cpuid_vmm_vendor); 1112 DBG(" vmm_family : %u\n", info_p->cpuid_vmm_family); 1113 DBG(" vmm_bus_frequency : %u\n", info_p->cpuid_vmm_bus_frequency); 1114 DBG(" vmm_tsc_frequency : %u\n", info_p->cpuid_vmm_tsc_frequency); 1115} 1116 1117boolean_t 1118cpuid_vmm_present(void) 1119{ 1120 return (cpuid_features() & CPUID_FEATURE_VMM) ? TRUE : FALSE; 1121} 1122 1123i386_vmm_info_t * 1124cpuid_vmm_info(void) 1125{ 1126 if (_cpuid_vmm_infop == NULL) { 1127 cpuid_init_vmm_info(&_cpuid_vmm_info); 1128 _cpuid_vmm_infop = &_cpuid_vmm_info; 1129 } 1130 return _cpuid_vmm_infop; 1131} 1132 1133uint32_t 1134cpuid_vmm_family(void) 1135{ 1136 return cpuid_vmm_info()->cpuid_vmm_family; 1137} 1138 1139