1//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This is a target description file for the Intel i386 architecture, referred 11// to here as the "X86" architecture. 12// 13//===----------------------------------------------------------------------===// 14 15// Get the target-independent interfaces which we are implementing... 16// 17include "llvm/Target/Target.td" 18 19//===----------------------------------------------------------------------===// 20// X86 Subtarget state 21// 22 23def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true", 24 "64-bit mode (x86_64)">; 25 26//===----------------------------------------------------------------------===// 27// X86 Subtarget features 28//===----------------------------------------------------------------------===// 29 30def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true", 31 "Enable conditional move instructions">; 32 33def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true", 34 "Support POPCNT instruction">; 35 36 37def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX", 38 "Enable MMX instructions">; 39def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", 40 "Enable SSE instructions", 41 // SSE codegen depends on cmovs, and all 42 // SSE1+ processors support them. 43 [FeatureMMX, FeatureCMOV]>; 44def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", 45 "Enable SSE2 instructions", 46 [FeatureSSE1]>; 47def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3", 48 "Enable SSE3 instructions", 49 [FeatureSSE2]>; 50def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3", 51 "Enable SSSE3 instructions", 52 [FeatureSSE3]>; 53def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41", 54 "Enable SSE 4.1 instructions", 55 [FeatureSSSE3]>; 56def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42", 57 "Enable SSE 4.2 instructions", 58 [FeatureSSE41]>; 59def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", 60 "Enable 3DNow! instructions", 61 [FeatureMMX]>; 62def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", 63 "Enable 3DNow! Athlon instructions", 64 [Feature3DNow]>; 65// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied 66// feature, because SSE2 can be disabled (e.g. for compiling OS kernels) 67// without disabling 64-bit mode. 68def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", 69 "Support 64-bit instructions", 70 [FeatureCMOV]>; 71def FeatureCMPXCHG16B : SubtargetFeature<"cmpxchg16b", "HasCmpxchg16b", "true", 72 "64-bit with cmpxchg16b", 73 [Feature64Bit]>; 74def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true", 75 "Bit testing of memory is slow">; 76def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem", 77 "IsUAMemFast", "true", 78 "Fast unaligned memory access">; 79def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true", 80 "Support SSE 4a instructions", 81 [FeatureSSE3]>; 82 83def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX", 84 "Enable AVX instructions", 85 [FeatureSSE42]>; 86def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2", 87 "Enable AVX2 instructions", 88 [FeatureAVX]>; 89def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true", 90 "Enable packed carry-less multiplication instructions", 91 [FeatureSSE2]>; 92def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true", 93 "Enable three-operand fused multiple-add", 94 [FeatureAVX]>; 95def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", 96 "Enable four-operand fused multiple-add", 97 [FeatureAVX, FeatureSSE4A]>; 98def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true", 99 "Enable XOP instructions", 100 [FeatureFMA4]>; 101def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem", 102 "HasVectorUAMem", "true", 103 "Allow unaligned memory operands on vector/SIMD instructions">; 104def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", 105 "Enable AES instructions", 106 [FeatureSSE2]>; 107def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true", 108 "Support MOVBE instruction">; 109def FeatureRDRAND : SubtargetFeature<"rdrand", "HasRDRAND", "true", 110 "Support RDRAND instruction">; 111def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true", 112 "Support 16-bit floating point conversion instructions">; 113def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true", 114 "Support FS/GS Base instructions">; 115def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true", 116 "Support LZCNT instruction">; 117def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true", 118 "Support BMI instructions">; 119def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true", 120 "Support BMI2 instructions">; 121def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true", 122 "Use LEA for adjusting the stack pointer">; 123def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb", 124 "HasSlowDivide", "true", 125 "Use small divide for positive values less than 256">; 126 127//===----------------------------------------------------------------------===// 128// X86 processors supported. 129//===----------------------------------------------------------------------===// 130 131include "X86Schedule.td" 132 133def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom", 134 "Intel Atom processors">; 135 136class Proc<string Name, list<SubtargetFeature> Features> 137 : ProcessorModel<Name, GenericModel, Features>; 138 139class AtomProc<string Name, list<SubtargetFeature> Features> 140 : ProcessorModel<Name, AtomModel, Features>; 141 142def : Proc<"generic", []>; 143def : Proc<"i386", []>; 144def : Proc<"i486", []>; 145def : Proc<"i586", []>; 146def : Proc<"pentium", []>; 147def : Proc<"pentium-mmx", [FeatureMMX]>; 148def : Proc<"i686", []>; 149def : Proc<"pentiumpro", [FeatureCMOV]>; 150def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>; 151def : Proc<"pentium3", [FeatureSSE1]>; 152def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>; 153def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>; 154def : Proc<"pentium4", [FeatureSSE2]>; 155def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>; 156def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>; 157def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>; 158def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>; 159def : Proc<"nocona", [FeatureSSE3, FeatureCMPXCHG16B, 160 FeatureSlowBTMem]>; 161def : Proc<"core2", [FeatureSSSE3, FeatureCMPXCHG16B, 162 FeatureSlowBTMem]>; 163def : Proc<"penryn", [FeatureSSE41, FeatureCMPXCHG16B, 164 FeatureSlowBTMem]>; 165def : AtomProc<"atom", [ProcIntelAtom, FeatureSSE3, FeatureCMPXCHG16B, 166 FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP, 167 FeatureSlowDivide]>; 168// "Arrandale" along with corei3 and corei5 169def : Proc<"corei7", [FeatureSSE42, FeatureCMPXCHG16B, 170 FeatureSlowBTMem, FeatureFastUAMem, 171 FeaturePOPCNT, FeatureAES]>; 172def : Proc<"nehalem", [FeatureSSE42, FeatureCMPXCHG16B, 173 FeatureSlowBTMem, FeatureFastUAMem, 174 FeaturePOPCNT]>; 175// Westmere is a similar machine to nehalem with some additional features. 176// Westmere is the corei3/i5/i7 path from nehalem to sandybridge 177def : Proc<"westmere", [FeatureSSE42, FeatureCMPXCHG16B, 178 FeatureSlowBTMem, FeatureFastUAMem, 179 FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>; 180// Sandy Bridge 181// SSE is not listed here since llvm treats AVX as a reimplementation of SSE, 182// rather than a superset. 183def : Proc<"corei7-avx", [FeatureAVX, FeatureCMPXCHG16B, FeaturePOPCNT, 184 FeatureAES, FeaturePCLMUL]>; 185// Ivy Bridge 186def : Proc<"core-avx-i", [FeatureAVX, FeatureCMPXCHG16B, FeaturePOPCNT, 187 FeatureAES, FeaturePCLMUL, 188 FeatureRDRAND, FeatureF16C, FeatureFSGSBase]>; 189 190// Haswell 191def : Proc<"core-avx2", [FeatureAVX2, FeatureCMPXCHG16B, FeaturePOPCNT, 192 FeatureAES, FeaturePCLMUL, FeatureRDRAND, 193 FeatureF16C, FeatureFSGSBase, 194 FeatureMOVBE, FeatureLZCNT, FeatureBMI, 195 FeatureBMI2, FeatureFMA]>; 196 197def : Proc<"k6", [FeatureMMX]>; 198def : Proc<"k6-2", [Feature3DNow]>; 199def : Proc<"k6-3", [Feature3DNow]>; 200def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem]>; 201def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem]>; 202def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; 203def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; 204def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; 205def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit, 206 FeatureSlowBTMem]>; 207def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit, 208 FeatureSlowBTMem]>; 209def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit, 210 FeatureSlowBTMem]>; 211def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit, 212 FeatureSlowBTMem]>; 213def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B, 214 FeatureSlowBTMem]>; 215def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B, 216 FeatureSlowBTMem]>; 217def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B, 218 FeatureSlowBTMem]>; 219def : Proc<"amdfam10", [FeatureSSE4A, 220 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT, 221 FeaturePOPCNT, FeatureSlowBTMem]>; 222// Bobcat 223def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B, 224 FeatureLZCNT, FeaturePOPCNT]>; 225// Bulldozer 226def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B, 227 FeatureAES, FeaturePCLMUL, 228 FeatureLZCNT, FeaturePOPCNT]>; 229// Enhanced Bulldozer 230def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B, 231 FeatureAES, FeaturePCLMUL, 232 FeatureF16C, FeatureLZCNT, 233 FeaturePOPCNT, FeatureBMI, FeatureFMA]>; 234def : Proc<"geode", [Feature3DNowA]>; 235 236def : Proc<"winchip-c6", [FeatureMMX]>; 237def : Proc<"winchip2", [Feature3DNow]>; 238def : Proc<"c3", [Feature3DNow]>; 239def : Proc<"c3-2", [FeatureSSE1]>; 240 241//===----------------------------------------------------------------------===// 242// Register File Description 243//===----------------------------------------------------------------------===// 244 245include "X86RegisterInfo.td" 246 247//===----------------------------------------------------------------------===// 248// Instruction Descriptions 249//===----------------------------------------------------------------------===// 250 251include "X86InstrInfo.td" 252 253def X86InstrInfo : InstrInfo; 254 255//===----------------------------------------------------------------------===// 256// Calling Conventions 257//===----------------------------------------------------------------------===// 258 259include "X86CallingConv.td" 260 261 262//===----------------------------------------------------------------------===// 263// Assembly Parser 264//===----------------------------------------------------------------------===// 265 266def ATTAsmParser : AsmParser { 267 string AsmParserClassName = "AsmParser"; 268} 269 270def ATTAsmParserVariant : AsmParserVariant { 271 int Variant = 0; 272 273 // Discard comments in assembly strings. 274 string CommentDelimiter = "#"; 275 276 // Recognize hard coded registers. 277 string RegisterPrefix = "%"; 278} 279 280def IntelAsmParserVariant : AsmParserVariant { 281 int Variant = 1; 282 283 // Discard comments in assembly strings. 284 string CommentDelimiter = ";"; 285 286 // Recognize hard coded registers. 287 string RegisterPrefix = ""; 288} 289 290//===----------------------------------------------------------------------===// 291// Assembly Printers 292//===----------------------------------------------------------------------===// 293 294// The X86 target supports two different syntaxes for emitting machine code. 295// This is controlled by the -x86-asm-syntax={att|intel} 296def ATTAsmWriter : AsmWriter { 297 string AsmWriterClassName = "ATTInstPrinter"; 298 int Variant = 0; 299 bit isMCAsmWriter = 1; 300} 301def IntelAsmWriter : AsmWriter { 302 string AsmWriterClassName = "IntelInstPrinter"; 303 int Variant = 1; 304 bit isMCAsmWriter = 1; 305} 306 307def X86 : Target { 308 // Information about the instructions... 309 let InstructionSet = X86InstrInfo; 310 let AssemblyParsers = [ATTAsmParser]; 311 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant]; 312 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter]; 313} 314