1/* 2 * Copyright (c) 2004, Apple Computer, Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. Neither the name of Apple Computer, Inc. ("Apple") nor the names of 13 * its contributors may be used to endorse or promote products derived 14 * from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY APPLE AND ITS CONTRIBUTORS "AS IS" AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL APPLE OR ITS CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28/* @(#)reg.h 1.16 92/04/28 SMI */ 29 30/* 31 * Copyright (c) 1985 by Sun Microsystems, Inc. 32 */ 33 34#ifndef _sparc_reg_h 35#define _sparc_reg_h 36 37/* 38 * Location of the users' stored 39 * registers relative to R0. 40 * Usage is u.u_ar0[XX]. 41 */ 42#define PSR (0) 43#define PC (1) 44#define nPC (2) 45#define SPARC_Y (3) 46#define G1 (4) 47#define G2 (5) 48#define G3 (6) 49#define G4 (7) 50#define G5 (8) 51#define G6 (9) 52#define G7 (10) 53#define O0 (11) 54#define O1 (12) 55#define O2 (13) 56#define O3 (14) 57#define O4 (15) 58#define O5 (16) 59#define O6 (17) 60#define O7 (18) 61 62/* the following defines are for portability */ 63#define PS PSR 64#define SP O6 65#define R0 O0 66#define R1 O1 67 68/* 69 * And now for something completely the same... 70 */ 71#ifndef __ASSEMBLER__ 72struct regs { 73 int r_psr; /* processor status register */ 74 int r_pc; /* program counter */ 75 int r_npc; /* next program counter */ 76 int r_y; /* the y register */ 77 int r_g1; /* user global regs */ 78 int r_g2; 79 int r_g3; 80 int r_g4; 81 int r_g5; 82 int r_g6; 83 int r_g7; 84 int r_o0; 85 int r_o1; 86 int r_o2; 87 int r_o3; 88 int r_o4; 89 int r_o5; 90 int r_o6; 91 int r_o7; 92}; 93 94#define r_ps r_psr /* for portablility */ 95#define r_r0 r_o0 96#define r_sp r_o6 97 98#endif /* !__ASSEMBLER__ */ 99 100/* 101 * Floating point definitions. 102 */ 103 104#define FPU /* we have an external float unit */ 105 106#ifndef __ASSEMBLER__ 107 108#define FQ_DEPTH 16 /* maximum instuctions in FQ */ 109 110/* 111 * struct fpu_status is the floating point processor state 112 * struct fpu is the sum total of all possible floating point state 113 * which includes the state of external floating point hardware, 114 * fpa registers, etc..., if it exists. 115 */ 116struct fpq { 117 unsigned int *addr; /* address */ 118 unsigned int instr; /* instruction */ 119}; 120struct fq { 121 union { /* FPU inst/addr queue */ 122 double whole; 123 struct fpq fpq; 124 } FQu; 125}; 126 127 128#define FPU_REGS_TYPE unsigned 129#define FPU_FSR_TYPE unsigned 130 131struct fpu { 132 union { /* FPU floating point regs */ 133 FPU_REGS_TYPE Fpu_regs[32]; /* 32 singles */ 134 double Fpu_dregs[16]; /* 16 doubles */ 135 } fpu_fr; 136 FPU_FSR_TYPE Fpu_fsr; /* FPU status register */ 137 unsigned Fpu_flags; /* control flags */ 138 unsigned Fpu_extra; /* extra word */ 139 unsigned Fpu_qcnt; /* count of valid entries in fps_q */ 140 struct fq Fpu_q[FQ_DEPTH]; /* FPU instruction address queue */ 141}; 142 143#define fpu_regs fpu_fr.Fpu_regs 144#define fpu_dregs fpu_fr.Fpu_dregs 145#define fpu_fsr Fpu_fsr 146#define fpu_flags Fpu_flags 147#define fpu_extra Fpu_extra 148#define fpu_q Fpu_q 149#define fpu_qcnt Fpu_qcnt 150 151#endif /* !__ASSEMBLER__ */ 152 153 154/* 155 * Definition of bits in the Sun-4 FSR (Floating-point Status Register) 156 * ________________________________________________________________________ 157 * | RD | RP | TEM | NS | res | vers | FTT | QNE | PR | FCC | AEXC | CEXC | 158 * |-----|---- |-----|----|-----|------|-----|-----|----|-----|------|------| 159 * 31 30 29 28 27 23 22 21 20 19 17 16 14 13 12 11 10 9 5 4 0 160 */ 161#define FSR_CEXC 0x0000001f /* Current Exception */ 162#define FSR_AEXC 0x000003e0 /* ieee accrued exceptions */ 163#define FSR_FCC 0x00000c00 /* Floating-point Condition Codes */ 164#define FSR_PR 0x00001000 /* Partial Remainder */ 165#define FSR_QNE 0x00002000 /* Queue not empty */ 166#define FSR_FTT 0x0001c000 /* Floating-point Trap Type */ 167#define FSR_VERS 0x000e0000 /* version field */ 168#define FSR_RESV 0x00300000 /* reserved */ 169#define FSR_NS 0x00400000 /* non-standard fp */ 170#define FSR_TEM 0x0f800000 /* ieee Trap Enable Mask */ 171#define FSR_RP 0x30000000 /* Rounding Precision */ 172#define FSR_RD 0xc0000000 /* Rounding Direction */ 173 174#define FSR_VERS_SHIFT (17) /* amount to shift version field */ 175 176/* 177 * Definition of CEXC (Current EXCeption) bit field of fsr 178 */ 179#define FSR_CEXC_NX 0x00000001 /* inexact */ 180#define FSR_CEXC_DZ 0x00000002 /* divide-by-zero */ 181#define FSR_CEXC_UF 0x00000004 /* underflow */. 182#define FSR_CEXC_OF 0x00000008 /* overflow */ 183#define FSR_CEXC_NV 0x00000010 /* invalid */ 184 185/* 186 * Definition of AEXC (Accrued EXCeption) bit field of fsr 187 */ 188#define FSR_AEXC_NX (0x1 << 5) /* inexact */ 189#define FSR_AEXC_DZ (0x2 << 5) /* divide-by-zero */ 190#define FSR_AEXC_UF (0x4 << 5) /* underflow */. 191#define FSR_AEXC_OF (0x8 << 5) /* overflow */ 192#define FSR_AEXC_NV (0x10 << 5) /* invalid */ 193 194/* 195 * Defintion of FTT (Floating-point Trap Type) field within the FSR 196 */ 197#define FTT_NONE 0 /* no excepitons */ 198#define FTT_IEEE 1 /* IEEE exception */ 199#define FTT_UNFIN 2 /* unfinished fpop */ 200#define FTT_UNIMP 3 /* unimplemented fpop */ 201#define FTT_SEQ 4 /* sequence error */ 202#define FTT_ALIGN 5 /* alignment, by software convention */ 203#define FTT_DFAULT 6 /* data fault, by software convention */ 204#define FSR_FTT_SHIFT 14 /* shift needed to justfy ftt field */ 205#define FSR_FTT_IEEE (FTT_IEEE << FSR_FTT_SHIFT) 206#define FSR_FTT_UNFIN (FTT_UNFIN << FSR_FTT_SHIFT) 207#define FSR_FTT_UNIMP (FTT_UNIMP << FSR_FTT_SHIFT) 208#define FSR_FTT_SEQ (FTT_SEQ << FSR_FTT_SHIFT) 209#define FSR_FTT_ALIGN (FTT_ALIGN << FSR_FTT_SHIFT) 210#define FSR_FTT_DFAULT (FTT_DFAULT << FSR_FTT_SHIFT) 211 212/* 213 * Values of VERS (version) field within the FSR 214 * NOTE: these values are overloaded; the cpu type must be used to 215 * further discriminate amongst these. For that reason, no #defines are 216 * provided. 217 * 218 * Version cpu = 21-22, 51-54 cpu = 23-24, 55-57 219 * 0 Weitek 1164/5 (FAB 1-4) TI 8847 220 * 1 Weitek 1164/5 (FAB 5-6) LSI L64814 221 * 2 TI 8847 TI TMS390C602A 222 * 3 Weitek 3170 Weitek 3171 223 * 4 Meiko ? 224 * 5 ? ? 225 * 6 ? ? 226 * 7 No FP Hardware No FP Hardware 227 */ 228 229 230/* 231 * Definition of TEM (Trap Enable Mask) bit field of fsr 232 */ 233#define FSR_TEM_NX (0x1 << 23) /* inexact */ 234#define FSR_TEM_DZ (0x2 << 23) /* divide-by-zero */ 235#define FSR_TEM_UF (0x4 << 23) /* underflow */. 236#define FSR_TEM_OF (0x8 << 23) /* overflow */ 237#define FSR_TEM_NV (0x10 << 23) /* invalid */ 238 239/* 240 * Definition of RP (Rounding Precision) field of fsr 241 */ 242#define RP_DBLEXT 0 /* double-extended */ 243#define RP_SINGLE 1 /* single */ 244#define RP_DOUBLE 2 /* double */ 245#define RP_RESERVED 3 /* unused and reserved */ 246 247/* 248 * Defintion of RD (Rounding Direction) field of fsr 249 */ 250#define RD_NEAR 0 /* nearest or even if tie */ 251#define RD_ZER0 1 /* to zero */ 252#define RD_POSINF 2 /* positive infinity */ 253#define RD_NEGINF 3 /* negative infinity */ 254 255/* 256 * Definition of the FP enable flags of the pcb struct 257 * Normal operation, all flags are zero 258 */ 259#define FP_UNINITIALIZED 1 260#define FP_STARTSIG 2 261#define FP_DISABLE 4 262#define FP_ENABLE 8 263 264#ifndef __ASSEMBLER__ 265/* 266 * How a register window looks on the stack. 267 */ 268struct rwindow { 269 int rw_local[8]; /* locals */ 270 int rw_in[8]; /* ins */ 271}; 272 273#define rw_fp rw_in[6] /* frame pointer */ 274#define rw_rtn rw_in[7] /* return address */ 275 276#endif /* !__ASSEMBLER__ */ 277 278 279/* 280 * Definition of bits in the Sun-4 PSR (Processor Status Register) 281 * ____________________________________________________________________ 282 * | IMPL | VER | ICC | res | EC | EF | PIL | S | PS | ET | CWP | 283 * |-----------|-----|------|-----|----|----|-------|---|----|----|-----| 284 * 31 28 27 24 23 20 19 14 13 12 11 8 7 6 5 4 0 285 */ 286 287 288struct p_status { 289 union { 290 unsigned int psr; 291 struct { 292 unsigned int 293 impl:4, 294 ver:4, 295 icc:4, 296 reserved:6, 297 ec:1, 298 ef:1, 299 pil:4, 300 s:1, 301 ps:1, 302 et:1, 303 cwp:5; 304 } psr_bits; 305 } PSRREG; 306}; 307 308struct f_status { 309 union { 310 FPU_FSR_TYPE Fpu_fsr; /* FPU status register */ 311 struct { 312 unsigned int 313 rd:2, 314 rp:2, 315 tem:5, 316 res:6, 317 ftt:3, 318 qne:1, 319 pr:1, 320 fcc:2, 321 aexc:5, 322 cexc:5; 323 } Fpu_fsr_bits; 324 } FPUREG; 325}; 326 327#endif /*!_sparc_reg_h*/ 328