1/* i386.h -- Header file for i386.c 2 Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002, 2003, 2004 4 Free Software Foundation, Inc. 5 6 This file is part of GAS, the GNU Assembler. 7 8 GAS is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2, or (at your option) 11 any later version. 12 13 GAS is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GAS; see the file COPYING. If not, write to the Free 20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 21 02111-1307, USA. */ 22 23#include "write_object.h" 24 25#define PARAMS(ARGS) ARGS 26 27#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0 28 29#define LOCAL_LABELS_FB 1 30 31extern const char extra_symbol_chars[]; 32#define tc_symbol_chars extra_symbol_chars 33 34#define MAX_OPERANDS 3 /* max operands per insn */ 35#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */ 36#define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */ 37 38/* Prefixes will be emitted in the order defined below. 39 WAIT_PREFIX must be the first prefix since FWAIT is really is an 40 instruction, and so must come before any prefixes. */ 41#define WAIT_PREFIX 0 42#define LOCKREP_PREFIX 1 43#define ADDR_PREFIX 2 44#define DATA_PREFIX 3 45#define SEG_PREFIX 4 46#define MAN_PREFIX 5 /* 0xf2,0xf3,etc "mandatory" prefix, not REPs */ 47#define REX_PREFIX 6 /* must come last. */ 48#define MAX_PREFIXES 7 /* max prefixes per opcode */ 49 50/* we define the syntax here (modulo base,index,scale syntax) */ 51#define REGISTER_PREFIX '%' 52#define IMMEDIATE_PREFIX '$' 53#define ABSOLUTE_PREFIX '*' 54 55#define TWO_BYTE_OPCODE_ESCAPE 0x0f 56#define NOP_OPCODE (char) 0x90 57 58/* register numbers */ 59#define EBP_REG_NUM 5 60#define ESP_REG_NUM 4 61 62/* modrm_byte.regmem for twobyte escape */ 63#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM 64/* index_base_byte.index for no index register addressing */ 65#define NO_INDEX_REGISTER ESP_REG_NUM 66/* index_base_byte.base for no base register addressing */ 67#define NO_BASE_REGISTER EBP_REG_NUM 68#define NO_BASE_REGISTER_16 6 69 70/* these are the instruction mnemonic suffixes. */ 71#define WORD_MNEM_SUFFIX 'w' 72#define BYTE_MNEM_SUFFIX 'b' 73#define SHORT_MNEM_SUFFIX 's' 74#define LONG_MNEM_SUFFIX 'l' 75#define QWORD_MNEM_SUFFIX 'q' 76/* Intel Syntax */ 77#define LONG_DOUBLE_MNEM_SUFFIX 'x' 78 79/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ 80#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ 81#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) 82 83#define END_OF_INSN '\0' 84 85typedef struct 86{ 87 /* instruction name sans width suffix ("mov" for movl insns) */ 88 char *name; 89 90 /* how many operands */ 91 unsigned int operands; 92 93 /* base_opcode is the fundamental opcode byte without optional 94 prefix(es). */ 95 unsigned int base_opcode; 96 97 /* extension_opcode is the 3 bit extension for group <n> insns. 98 This field is also used to store the 8-bit opcode suffix for the 99 AMD 3DNow! instructions. 100 If this template has no extension opcode (the usual case) use None */ 101 unsigned int extension_opcode; 102#define None 0xffff /* If no extension_opcode is possible. */ 103 104 /* cpu feature flags */ 105 unsigned int cpu_flags; 106#define Cpu086 0x1 /* Any old cpu will do, 0 does the same */ 107#define Cpu186 0x2 /* i186 or better required */ 108#define Cpu286 0x4 /* i286 or better required */ 109#define Cpu386 0x8 /* i386 or better required */ 110#define Cpu486 0x10 /* i486 or better required */ 111#define Cpu586 0x20 /* i585 or better required */ 112#define Cpu686 0x40 /* i686 or better required */ 113#define CpuP4 0x80 /* Pentium4 or better required */ 114#define CpuK6 0x100 /* AMD K6 or better required*/ 115#define CpuAthlon 0x200 /* AMD Athlon or better required*/ 116#define CpuSledgehammer 0x400 /* Sledgehammer or better required */ 117#define CpuMMX 0x800 /* MMX support required */ 118#define CpuMMX2 0x1000 /* extended MMX support (with SSE or 3DNow!Ext) required */ 119#define CpuSSE 0x2000 /* Streaming SIMD extensions required */ 120#define CpuSSE2 0x4000 /* Streaming SIMD extensions 2 required */ 121#define Cpu3dnow 0x8000 /* 3dnow! support required */ 122#define Cpu3dnowA 0x10000 /* 3dnow!Extensions support required */ 123#define CpuPNI 0x20000 /* Prescott New Instructions required */ 124#define CpuPadLock 0x40000 /* VIA PadLock required */ 125#ifdef NeXT_MOD 126#define CpuMNI 0x80000 /* Merom New Instructions required */ 127#endif 128#define CpuVMX 0x100000 /* VMX Instructions required */ 129#define CpuSSE4 0x200000 /* Streaming SIMD extensions 4 required */ 130 131 /* These flags are set by gas depending on the flag_code. */ 132#define Cpu64 0x4000000 /* 64bit support required */ 133#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */ 134 135 /* The default value for unknown CPUs - enable all features to avoid problems. */ 136#ifdef NeXT_MOD 137#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX|Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock|CpuMNI|CpuSSE4) 138#else 139#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX|Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock) 140#endif 141 142 /* the bits in opcode_modifier are used to generate the final opcode from 143 the base_opcode. These bits also are used to detect alternate forms of 144 the same instruction */ 145 unsigned int opcode_modifier; 146 147 /* opcode_modifier bits: */ 148#define W 0x1 /* set if operands can be words or dwords 149 encoded the canonical way */ 150#define D 0x2 /* D = 0 if Reg --> Regmem; 151 D = 1 if Regmem --> Reg: MUST BE 0x2 */ 152#define Modrm 0x4 153#define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */ 154#define ShortForm 0x10 /* register is in low 3 bits of opcode */ 155#define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */ 156#define Jump 0x40 /* special case for jump insns. */ 157#define JumpDword 0x80 /* call and jump */ 158#define JumpByte 0x100 /* loop and jecxz */ 159#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */ 160#define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */ 161#define Seg2ShortForm 0x800 /* encoding of load segment reg insns */ 162#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */ 163#define Size16 0x2000 /* needs size prefix if in 32-bit mode */ 164#define Size32 0x4000 /* needs size prefix if in 16-bit mode */ 165#define Size64 0x8000 /* needs size prefix if in 16-bit mode */ 166#define IgnoreSize 0x10000 /* instruction ignores operand size prefix */ 167#define DefaultSize 0x20000 /* default insn size depends on mode */ 168#define No_bSuf 0x40000 /* b suffix on instruction illegal */ 169#define No_wSuf 0x80000 /* w suffix on instruction illegal */ 170#define No_lSuf 0x100000 /* l suffix on instruction illegal */ 171#define No_sSuf 0x200000 /* s suffix on instruction illegal */ 172#define No_qSuf 0x400000 /* q suffix on instruction illegal */ 173#define No_xSuf 0x800000 /* x suffix on instruction illegal */ 174#define FWait 0x1000000 /* instruction needs FWAIT */ 175#define IsString 0x2000000 /* quick test for string instructions */ 176#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */ 177#define IsPrefix 0x8000000 /* opcode is a prefix */ 178#define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */ 179#define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */ 180#define Rex64 0x40000000 /* instruction require Rex64 prefix. */ 181#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */ 182 183 /* operand_types[i] describes the type of operand i. This is made 184 by OR'ing together all of the possible type masks. (e.g. 185 'operand_types[i] = Reg|Imm' specifies that operand i can be 186 either a register or an immediate operand. */ 187 unsigned int operand_types[3]; 188 189 /* operand_types[i] bits */ 190 /* register */ 191#define Reg8 0x1 /* 8 bit reg */ 192#define Reg16 0x2 /* 16 bit reg */ 193#define Reg32 0x4 /* 32 bit reg */ 194#define Reg64 0x8 /* 64 bit reg */ 195 /* immediate */ 196#define Imm8 0x10 /* 8 bit immediate */ 197#define Imm8S 0x20 /* 8 bit immediate sign extended */ 198#define Imm16 0x40 /* 16 bit immediate */ 199#define Imm32 0x80 /* 32 bit immediate */ 200#define Imm32S 0x100 /* 32 bit immediate sign extended */ 201#define Imm64 0x200 /* 64 bit immediate */ 202#define Imm1 0x400 /* 1 bit immediate */ 203 /* memory */ 204#define BaseIndex 0x800 205 /* Disp8,16,32 are used in different ways, depending on the 206 instruction. For jumps, they specify the size of the PC relative 207 displacement, for baseindex type instructions, they specify the 208 size of the offset relative to the base register, and for memory 209 offset instructions such as `mov 1234,%al' they specify the size of 210 the offset relative to the segment base. */ 211#define Disp8 0x1000 /* 8 bit displacement */ 212#define Disp16 0x2000 /* 16 bit displacement */ 213#define Disp32 0x4000 /* 32 bit displacement */ 214#define Disp32S 0x8000 /* 32 bit signed displacement */ 215#define Disp64 0x10000 /* 64 bit displacement */ 216 /* specials */ 217#define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */ 218#define ShiftCount 0x40000 /* register to hold shift cound = cl */ 219#define Control 0x80000 /* Control register */ 220#define Debug 0x100000 /* Debug register */ 221#define Test 0x200000 /* Test register */ 222#define FloatReg 0x400000 /* Float register */ 223#define FloatAcc 0x800000 /* Float stack top %st(0) */ 224#define SReg2 0x1000000 /* 2 bit segment register */ 225#define SReg3 0x2000000 /* 3 bit segment register */ 226#define Acc 0x4000000 /* Accumulator %al or %ax or %eax */ 227#define JumpAbsolute 0x8000000 228#define RegMMX 0x10000000 /* MMX register */ 229#define RegXMM 0x20000000 /* XMM registers in PIII */ 230#define EsSeg 0x40000000 /* String insn operand with fixed es segment */ 231 232 /* InvMem is for instructions with a modrm byte that only allow a 233 general register encoding in the i.tm.mode and i.tm.regmem fields, 234 eg. control reg moves. They really ought to support a memory form, 235 but don't, so we add an InvMem flag to the register operand to 236 indicate that it should be encoded in the i.tm.regmem field. */ 237#define InvMem 0x80000000 238 239#define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */ 240#define WordReg (Reg16|Reg32|Reg64) 241#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc) 242#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */ 243#define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */ 244#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */ 245#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */ 246 /* The following aliases are defined because the opcode table 247 carefully specifies the allowed memory types for each instruction. 248 At the moment we can only tell a memory reference size by the 249 instruction suffix, so there's not much point in defining Mem8, 250 Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use 251 the suffix directly to check memory operands. */ 252#define LLongMem AnyMem /* 64 bits (or more) */ 253#define LongMem AnyMem /* 32 bit memory ref */ 254#define ShortMem AnyMem /* 16 bit memory ref */ 255#define WordMem AnyMem /* 16 or 32 bit memory ref */ 256#define ByteMem AnyMem /* 8 bit memory ref */ 257} 258template; 259 260/* 261 'templates' is for grouping together 'template' structures for opcodes 262 of the same name. This is only used for storing the insns in the grand 263 ole hash table of insns. 264 The templates themselves start at START and range up to (but not including) 265 END. 266 */ 267typedef struct 268{ 269 const template *start; 270 const template *end; 271} 272templates; 273 274/* these are for register name --> number & type hash lookup */ 275typedef struct 276{ 277 char *reg_name; 278 unsigned int reg_type; 279 unsigned int reg_flags; 280#define RegRex 0x1 /* Extended register. */ 281#define RegRex64 0x2 /* Extended 8 bit register. */ 282 unsigned int reg_num; 283} 284reg_entry; 285 286typedef struct 287{ 288 char *seg_name; 289 unsigned int seg_prefix; 290} 291seg_entry; 292 293/* 386 operand encoding bytes: see 386 book for details of this. */ 294typedef struct 295{ 296 unsigned int regmem; /* codes register or memory operand */ 297 unsigned int reg; /* codes register operand (or extended opcode) */ 298 unsigned int mode; /* how to interpret regmem & reg */ 299} 300modrm_byte; 301 302/* x86-64 extension prefix. */ 303typedef int rex_byte; 304#define REX_OPCODE 0x40 305 306/* Indicates 64 bit operand size. */ 307#define REX_MODE64 8 308/* High extension to reg field of modrm byte. */ 309#define REX_EXTX 4 310/* High extension to SIB index field. */ 311#define REX_EXTY 2 312/* High extension to base field of modrm or SIB, or reg field of opcode. */ 313#define REX_EXTZ 1 314 315/* 386 opcode byte to code indirect addressing. */ 316typedef struct 317{ 318 unsigned base; 319 unsigned index; 320 unsigned scale; 321} 322sib_byte; 323 324/* x86 arch names and features */ 325typedef struct 326{ 327 const char *name; /* arch name */ 328 unsigned int flags; /* cpu feature flags */ 329} 330arch_entry; 331 332/* The name of the global offset table generated by the compiler. Allow 333 this to be overridden if need be. */ 334#ifndef GLOBAL_OFFSET_TABLE_NAME 335#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_" 336#endif 337 338#ifndef LEX_AT 339#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES) 340#ifdef NeXT_MOD 341extern segT x86_cons PARAMS ((expressionS *, int)); 342#else 343extern void x86_cons PARAMS ((expressionS *, int)); 344#endif 345 346#if !NeXT_MOD || ARCH64 347#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP) 348extern void x86_cons_fix_new 349 PARAMS ((fragS *, unsigned int, unsigned int, expressionS *)); 350#endif 351#endif 352 353#ifdef TE_PE 354#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_pe_cons_fix_new(FRAG, OFF, LEN, EXP) 355extern void x86_pe_cons_fix_new 356 PARAMS ((fragS *, unsigned int, unsigned int, expressionS *)); 357#endif 358 359#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */ 360 361#ifdef NeXT_MOD 362int is_local_symbol(struct symbol *sym); 363#endif 364 365void i386_validate_fix PARAMS ((struct fix *)); 366#define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) i386_validate_fix(FIX) 367 368#ifdef NeXT_MOD 369#if ARCH64 370int32_t x86_64_fixup_symbol PARAMS ((fixS *, int, struct symbol **)); 371#define TC_FIXUP_SYMBOL(FIX, SECT, SYM) x86_64_fixup_symbol(FIX, SECT, SYM) 372#endif 373#endif 374 375#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X) 376extern int tc_i386_fix_adjustable PARAMS ((struct fix *)); 377 378/* Values passed to md_apply_fix3 don't include the symbol value. */ 379#define MD_APPLY_SYM_VALUE(FIX) 0 380 381/* ELF wants external syms kept, as does PE COFF. */ 382#if defined (TE_PE) && defined (STRICT_PE_FORMAT) 383#define EXTERN_FORCE_RELOC \ 384 (OUTPUT_FLAVOR == bfd_target_elf_flavour \ 385 || OUTPUT_FLAVOR == bfd_target_coff_flavour) 386#else 387#define EXTERN_FORCE_RELOC \ 388 (OUTPUT_FLAVOR == bfd_target_elf_flavour) 389#endif 390 391/* This expression evaluates to true if the relocation is for a local 392 object for which we still want to do the relocation at runtime. 393 False if we are willing to perform this relocation while building 394 the .o file. GOTOFF does not need to be checked here because it is 395 not pcrel. I am not sure if some of the others are ever used with 396 pcrel, but it is easier to be safe than sorry. */ 397 398#define TC_FORCE_RELOCATION_LOCAL(FIX) \ 399 (!(FIX)->fx_pcrel \ 400 || (FIX)->fx_plt \ 401 || (FIX)->fx_r_type == BFD_RELOC_386_PLT32 \ 402 || (FIX)->fx_r_type == BFD_RELOC_386_GOT32 \ 403 || (FIX)->fx_r_type == BFD_RELOC_386_GOTPC \ 404 || TC_FORCE_RELOCATION (FIX)) 405 406#define md_operand(x) 407 408extern const struct relax_type md_relax_table[]; 409#define TC_GENERIC_RELAX_TABLE md_relax_table 410 411extern int optimize_align_code; 412 413#define md_do_align(n, fill, len, max, around) \ 414if ((n) \ 415 && !need_pass_2 \ 416 && optimize_align_code \ 417 && (!(fill) \ 418 || ((char)*(fill) == (char)0x90 && (len) == 1)) \ 419 && subseg_text_p (now_seg)) \ 420 { \ 421 frag_align_code ((n), (max)); \ 422 goto around; \ 423 } 424 425#define MAX_MEM_FOR_RS_ALIGN_CODE 15 426 427extern void i386_align_code PARAMS ((fragS *, int)); 428 429#define HANDLE_ALIGN(fragP) \ 430if (fragP->fr_type == rs_align_code) \ 431 i386_align_code (fragP, (fragP->fr_next->fr_address \ 432 - fragP->fr_address \ 433 - fragP->fr_fix)); 434 435void i386_print_statistics PARAMS ((FILE *)); 436#define tc_print_statistics i386_print_statistics 437 438#ifndef NeXT_MOD 439inline void md_number_to_chars (char *buf, signed_expr_t val, int n) { 440 number_to_chars_littleendian(buf, val, n); 441} 442#endif 443 444#ifdef SCO_ELF 445#define tc_init_after_args() sco_id () 446extern void sco_id PARAMS ((void)); 447#endif 448 449/* We want .cfi_* pseudo-ops for generating unwind info. */ 450#define TARGET_USE_CFIPOP 1 451 452extern unsigned int x86_dwarf2_return_column; 453#define DWARF2_DEFAULT_RETURN_COLUMN x86_dwarf2_return_column 454 455extern int x86_cie_data_alignment; 456#define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment 457 458#define tc_regname_to_dw2regnum tc_x86_regname_to_dw2regnum 459extern int tc_x86_regname_to_dw2regnum PARAMS ((const char *regname)); 460 461#define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions 462extern void tc_x86_frame_initial_instructions PARAMS ((void)); 463 464#define md_elf_section_type(str,len) i386_elf_section_type (str, len) 465extern int i386_elf_section_type PARAMS ((const char *, size_t len)); 466 467#ifdef TE_PE 468 469#define O_secrel O_md1 470 471#define TC_DWARF2_EMIT_OFFSET tc_pe_dwarf2_emit_offset 472void tc_pe_dwarf2_emit_offset (symbolS *, unsigned int); 473 474#endif /* TE_PE */ 475