1/* hppa-opcode.h */ 2/* Table of opcodes for the hppa. 3 Copyright (C) 1990 Free Software Foundation, Inc. 4 5This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. 6 7GAS/GDB is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 1, or (at your option) 10any later version. 11 12GAS/GDB is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with GAS or GDB; see the file COPYING. If not, write to 19the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ 20 21/* 22 HP PA-RISC support was contributed by the Center for Software Science 23 at the University of Utah. 24 */ 25 26/* HP-PA support for Mach-O ... USV */ 27 28#ifndef HPPA_OPCODE_INCLUDED 29#define HPPA_OPCODE_INCLUDED 30 31#include <stdint.h> 32 33#if !defined(__STDC__) && !defined(const) 34#define const 35#endif 36 37/* bug #41317 .... umeshv@NeXT.com Mon May 2 17:53:29 PDT 1994 */ 38/* The masks for 2 bits at 20 */ 39 40#define NO_CACHE_CONTROL_HINT (uint32_t)0x0U 41#define BC_OR_CO_CACHE_CONTROL_HINT (uint32_t)0x400U 42 43/************************************************************************ 44 * The parsing characters used in the opcode table are listed in ASCII 45 * order. This is updated list as of Wed Jul 27 14:15:09 PDT 1994 46 * --- Umesh. 47 ***************** Begin List ******************************************* 48 ! negated or non-negated add conditions (used only by 'addb' and 'addib' pseudo-instructions) 49 & logical instruction conditions 50 + non-negated add conditions 51 - compare/subtract conditions 52 0 10 bit Special Function Unit operation split between 5 bits at 20 and 5 bits at 31 53 1 15 bit Special Function Unit operation split between 10 bits at 20 and 5 bits at 31 54 2 22 bit Special Function Unit operation split between 17 bits at 20 and 5 bits at 31 55 3 Store Instruction Cache Control Hint (Table 5-8) with Indexed load completers (Table 5-10) 56 4 a variation of the 'b' operand type for 'fmpyadd' and 'fmpysub' 57 5 5 bit immediate at 15. 58 6 a variation of the 'x' operand type for 'fmpyadd' and 'fmpysub' 59 7 a variation of the 't' operand type for 'fmpyadd' and 'fmpysub' 60 8 5 bit register field at 20 (used in 'fmpyadd' and 'fmpysub') 61 9 5 bit register field at 25 (used in 'fmpyadd' and 'fmpysub') 62 < non-negated compare/subtract conditions. 63 > shift/extract/deposit conditions. 64 ? negated or non-negated compare/subtract conditions (used only by 'comb' and 'comib' pseudo-instructions) 65 @ 17 bit branch displacement --- JBSR 66 A 13 bit immediate at 18 (to support the BREAK instruction) 67 B either s,b or b where 's' 2 bit space specifier at 17 and 'b' register field at 10. 68 C short load and store completer. 69 D 26 bit immediate at 31 (to support the DIAG instruction) 70 E a 'b' operand type extended to handle L/R register halves. 71 F Source Floating Point Operand Format Completer encoded 2 bits at 20 72 G Destination Floating Point Operand Format Completer encoded 2 bits at 18 73 H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub' (very similar to 'F') 74 L Load and Clear Word Cache Control Hint with Indexed load completers 75 M Floating-Point Compare Conditions (encoded as 5 bits at 31) 76 O 20 bit Special Function Unit operation split between 15 bits at 20 and 5 bits at 31 77 P 5 bit bit position at 26 78 Q 5 bit immediate value at 10 (a bit position specified in the bb instruction. It's the same as r above, except the value is in a different location) 79 R 5 bit immediate value at 15 (for the ssm, rsm instruction) (same as r above, except the value is in a different location) 80 S 3 bit space specifier at 18. 81 T 5 bit field length at 31 (encoded as 32-T) 82 U unit instruction conditions 83 V 5 bit immediate value at 31 84 W 17 bit branch displacement (pc-rel for BL and GATE) 85 X an 'x' operand type extended to handle L/R register halves. 86 Y Store Bytes Short completer with cache control hints 87 Z System Control Completer (to support LDA, LHA, etc.) 88 a Load and Clear Word Cache Control Hint with Short displacement load and store completers 89 b register field at 10. 90 c indexed load completer. 91 f 3 bit Special Function Unit identifier at 25 92 i 11 bit immediate value at 31 93 j 14 bit immediate value at 31 94 k 21 bit immediate value at 31 95 l Store Instruction Cache Control Hint with Short displacement load and store completers 96 n nullification for branch instructions 97 o 15 bit Special Function Unit operation at 20 98 p 5 bit shift count at 26 (to support the SHD instruction) encoded as (31-p) 99 r 5 bit immediate value at 31 (for the break instruction) (very similar to V above, except the value is unsigned instead of low_sign_ext) 100 s 2 bit space specifier at 17. 101 t register field at 31. 102 u 3 bit coprocessor unit identifier at 25 103 v a 't' operand type extended to handle L/R register halves. 104 w 12 bit branch displacement 105 x register field at 15. 106 y nullification at 26 107 z 17 bit branch displacement (not pc-rel) 108 ~ bvb,bb conditions 109 ***************** End List ******************************************* 110 * The following characters are available for use later. If used in future 111 * please delete from this list and add to the list above (in order). 112 113 " # $ % ' * . / : ; = I J K N [ \ ] ^ _ ` d e g h m q { | } 114 115 ************************************************************************/ 116 117/* 118 * Structure of an opcode table entry. 119 */ 120 121/* There are two kinds of delay slot nullification: normal which is 122 * controled by the nullification bit, and conditional, which depends 123 * on the direction of the branch and its success or failure. 124 */ 125enum delay_type {NONE, NORMAL, CONDITIONAL}; 126struct pa_opcode 127{ 128 const char *name; 129 uint32_t match; /* Bits that must be set... */ 130 uint32_t mask; /* ... in these bits. */ 131 char *args; 132 /* Nonzero if this is a delayed branch instruction. */ 133 char delayed; 134}; 135 136/* 137 All hppa opcodes are 32 bits. 138 139 The match component is a mask saying which bits must match a 140 particular opcode in order for an instruction to be an instance 141 of that opcode. 142 143 The args component is a string containing one character 144 for each operand of the instruction. 145 146 Bit positions in this description follow HP usage of lsb = 31, 147 "at" is lsb of field. 148 149Kinds of operands: 150 x register field at 15. 151 b register field at 10. 152 t register field at 31. 153 5 5 bit immediate at 15. 154 s 2 bit space specifier at 17. 155 S 3 bit space specifier at 18. 156 c indexed load completer. 157 C short load and store completer. 158 Y Store Bytes Short completer 159 < non-negated compare/subtract conditions. 160 - compare/subtract conditions 161 + non-negated add conditions 162 & logical instruction conditions 163 U unit instruction conditions 164 > shift/extract/deposit conditions. 165 ~ bvb,bb conditions 166 V 5 bit immediate value at 31 167 i 11 bit immediate value at 31 168 j 14 bit immediate value at 31 169 k 21 bit immediate value at 31 170 n nullification for branch instructions 171 w 12 bit branch displacement 172 W 17 bit branch displacement (pc-rel for BL and GATE) 173 z 17 bit branch displacement (not pc-rel) 174 175Also these (PJH): 176 177 B either s,b or b where 178 179 s 2 bit space specifier at 17. 180 b register field at 10. 181 182 p 5 bit shift count at 26 (to support the SHD instruction) encoded as 183 31-p 184 P 5 bit bit position at 26 185 T 5 bit field length at 31 (encoded as 32-T) 186 A 13 bit immediate at 18 (to support the BREAK instruction) 187 Z System Control Completer (to support LDA, LHA, etc.) 188 D 26 bit immediate at 31 (to support the DIAG instruction) 189 190 f 3 bit Special Function Unit identifier at 25 191 O 20 bit Special Function Unit operation split between 15 bits at 20 192 and 5 bits at 31 193 o 15 bit Special Function Unit operation at 20 194 2 22 bit Special Function Unit operation split between 17 bits at 20 195 and 5 bits at 31 196 1 15 bit Special Function Unit operation split between 10 bits at 20 197 and 5 bits at 31 198 0 10 bit Special Function Unit operation split between 5 bits at 20 199 and 5 bits at 31 200 u 3 bit coprocessor unit identifier at 25 201 F Source Floating Point Operand Format Completer encoded 2 bits at 20 202 G Destination Floating Point Operand Format Completer encoded 2 bits at 18 203 M Floating-Point Compare Conditions (encoded as 5 bits at 31) 204 ? negated or non-negated compare/subtract conditions 205 (used only by 'comb' and 'comib' pseudo-instructions) 206 ! negated or non-negated add conditions 207 (used only by 'addb' and 'addib' pseudo-instructions) 208 r 5 bit immediate value at 31 (for the break instruction) 209 (very similar to V above, except the value is unsigned instead of 210 low_sign_ext) 211 R 5 bit immediate value at 15 (for the ssm, rsm instruction) 212 (same as r above, except the value is in a different location) 213 Q 5 bit immediate value at 10 (a bit position specified in 214 the bb instruction. It's the same as r above, except the 215 value is in a different location) 216 217And these (PJH) for PA-89 F.P. registers and instructions: 218 219 v a 't' operand type extended to handle L/R register halves. 220 E a 'b' operand type extended to handle L/R register halves. 221 X an 'x' operand type extended to handle L/R register halves. 222 4 a variation of the 'b' operand type for 'fmpyadd' and 'fmpysub' 223 6 a variation of the 'x' operand type for 'fmpyadd' and 'fmpysub' 224 7 a variation of the 't' operand type for 'fmpyadd' and 'fmpysub' 225 8 5 bit register field at 20 (used in 'fmpyadd' and 'fmpysub') 226 9 5 bit register field at 25 (used in 'fmpyadd' and 'fmpysub') 227 H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub' 228 (very similar to 'F') 229 230*/ 231 232/* bug #41317 .... umeshv@NeXT.com Mon May 2 17:53:29 PDT 1994 233 234 These are for 'cache control hints' 235 236 l Store Instruction Cache Control Hint (Table 5-8) with 237 Short displacement load and store completers (Table 5-11) 238 239 L Load and Clear Word Cache Control Hint (Table 5-9) with 240 Indexed load completers (Table 5-10) 241 242 3 Store Instruction Cache Control Hint (Table 5-8) with 243 Indexed load completers (Table 5-10) 244 245 a Load and Clear Word Cache Control Hint (Table 5-9) with 246 Short displacement load and store completers (Table 5-11) 247 248 These parse ",cc" and encode "cc" in 2 bits at 20, 249 where "cc" encoding is as given in Tables 5-8, 5-9. 250 Refer to 'PA-RISC 1.1 Architecture and Instruction Set Reference 251 Manual, Second Edition' for the tables. 252*/ 253 254/* The order of the opcodes in this table is significant: 255 256 * The assembler requires that all instances of the same mnemonic must be 257 consecutive. If they aren't, the assembler will bomb at runtime. 258 259 * The disassembler should not care about the order of the opcodes. */ 260 261static struct pa_opcode pa_opcodes[] = 262{ 263 264/* pseudo-instructions (first so otool matches them) */ 265 266{ "b", 0xe8000000, 0xffe0e000, "nW", NORMAL}, 267{ "ldi", 0x34000000, 0xffe0c000, "j,x"}, /* j by a */ 268{ "comib", 0x84000000, 0xfc000000, "?n5,b,w", CONDITIONAL}, 269{ "comb", 0x80000000, 0xfc000000, "?nx,b,w", CONDITIONAL}, 270{ "addb", 0xa0000000, 0xfc000000, "!nx,b,w", CONDITIONAL}, 271{ "addib", 0xa4000000, 0xfc000000, "!n5,b,w", CONDITIONAL}, 272{ "nop", 0x08000240, 0xffffffff, ""}, /* NOP <=> OR 0,0,0 */ 273{ "copy", 0x08000240, 0xffe0ffe0, "x,t"}, /* COPY <=> OR r,0,t */ 274 275/* real instructions */ 276{ "ldw", 0x48000000, 0xfc000000, "j(B),x"}, 277{ "ldh", 0x44000000, 0xfc000000, "j(B),x"}, 278{ "ldb", 0x40000000, 0xfc000000, "j(B),x"}, 279{ "stw", 0x68000000, 0xfc000000, "x,j(B)"}, 280{ "sth", 0x64000000, 0xfc000000, "x,j(B)"}, 281{ "stb", 0x60000000, 0xfc000000, "x,j(B)"}, 282{ "ldwm", 0x4c000000, 0xfc000000, "j(B),x"}, 283{ "stwm", 0x6c000000, 0xfc000000, "x,j(B)"}, 284{ "ldwx", 0x0c000080, 0xfc001fc0, "cx(B),t"}, 285{ "ldhx", 0x0c000040, 0xfc001fc0, "cx(B),t"}, 286{ "ldbx", 0x0c000000, 0xfc001fc0, "cx(B),t"}, 287{ "ldwax", 0x0c000180, 0xfc00dfc0, "cx(b),t"}, 288{ "ldcwx", 0x0c0001c0, 0xfc001bc0, "Lx(B),t"}, /* #41317 */ 289{ "ldws", 0x0c001080, 0xfc001fc0, "C5(B),t"}, 290{ "ldhs", 0x0c001040, 0xfc001fc0, "C5(B),t"}, 291{ "ldbs", 0x0c001000, 0xfc001fc0, "C5(B),t"}, 292{ "ldwas", 0x0c001180, 0xfc00dfc0, "C5(b),t"}, 293{ "ldcws", 0x0c0011c0, 0xfc001bc0, "a5(B),t"}, /* #41317 was "CL5(B),t" */ 294{ "stws", 0x0c001280, 0xfc001bc0, "lx,V(B)"}, /* #41317 */ 295{ "sths", 0x0c001240, 0xfc001bc0, "lx,V(B)"}, /* #41317 */ 296{ "stbs", 0x0c001200, 0xfc001bc0, "lx,V(B)"}, /* #41317 */ 297{ "stwas", 0x0c001380, 0xfc00dbc0, "lx,V(b)"}, /* #41317 */ 298{ "stbys", 0x0c001300, 0xfc001bc0, "Yx,V(B)"}, /* #41317 */ 299{ "ldo", 0x34000000, 0xfc00c000, "j(b),x"}, 300{ "ldil", 0x20000000, 0xfc000000, "k,b"}, 301{ "addil", 0x28000000, 0xfc000000, "k,b"}, 302{ "bl", 0xe8000000, 0xfc00e000, "nW,b", NORMAL}, 303{ "gate", 0xe8002000, 0xfc00e000, "nW,b", NORMAL}, 304{ "blr", 0xe8004000, 0xfc00e001, "nx,b", NORMAL}, 305{ "bv", 0xe800c000, 0xfc00e001, "nx(b)", NORMAL}, 306{ "be", 0xe0000000, 0xfc000000, "nz(S,b)", NORMAL}, 307{ "ble", 0xe4000000, 0xfc000000, "nz(S,b)", NORMAL}, 308{ "movb", 0xc8000000, 0xfc000000, ">nx,b,w", CONDITIONAL}, 309{ "movib", 0xcc000000, 0xfc000000, ">n5,b,w", CONDITIONAL}, 310{ "combt", 0x80000000, 0xfc000000, "<nx,b,w", CONDITIONAL}, 311{ "combf", 0x88000000, 0xfc000000, "<nx,b,w", CONDITIONAL}, 312{ "comibt", 0x84000000, 0xfc000000, "<n5,b,w", CONDITIONAL}, 313{ "comibf", 0x8c000000, 0xfc000000, "<n5,b,w", CONDITIONAL}, 314{ "addbt", 0xa0000000, 0xfc000000, "+nx,b,w", CONDITIONAL}, 315{ "addbf", 0xa8000000, 0xfc000000, "+nx,b,w", CONDITIONAL}, 316{ "addibt", 0xa4000000, 0xfc000000, "+n5,b,w", CONDITIONAL}, 317{ "addibf", 0xac000000, 0xfc000000, "+n5,b,w", CONDITIONAL}, 318{ "bvb", 0xc0000000, 0xffe00000, "~nx,w", CONDITIONAL}, 319{ "bb", 0xc4000000, 0xfc000000, "~nx,Q,w", CONDITIONAL}, /* maybe */ 320 321/* Computation Instructions */ 322 323{ "add", 0x08000600, 0xfc000fe0, "+x,b,t", CONDITIONAL}, 324{ "addl", 0x08000a00, 0xfc000fe0, "+x,b,t", CONDITIONAL}, 325{ "addo", 0x08000e00, 0xfc000fe0, "+x,b,t", CONDITIONAL}, 326{ "addc", 0x08000700, 0xfc000fe0, "+x,b,t", CONDITIONAL}, 327{ "addco", 0x08000f00, 0xfc000fe0, "+x,b,t", CONDITIONAL}, 328{ "sh1add", 0x08000640, 0xfc000fe0, "+x,b,t", CONDITIONAL}, 329{ "sh1addl", 0x08000a40, 0xfc000fe0, "+x,b,t", CONDITIONAL}, 330{ "sh1addo", 0x08000e40, 0xfc000fe0, "+x,b,t", CONDITIONAL}, 331{ "sh2add", 0x08000680, 0xfc000fe0, "+x,b,t", CONDITIONAL}, 332{ "sh2addl", 0x08000a80, 0xfc000fe0, "+x,b,t", CONDITIONAL}, 333{ "sh2addo", 0x08000e80, 0xfc000fe0, "+x,b,t", CONDITIONAL}, 334{ "sh3add", 0x080006c0, 0xfc000fe0, "+x,b,t", CONDITIONAL}, 335{ "sh3addl", 0x08000ac0, 0xfc000fe0, "+x,b,t", CONDITIONAL}, 336{ "sh3addo", 0x08000ec0, 0xfc000fe0, "+x,b,t", CONDITIONAL}, 337{ "sub", 0x08000400, 0xfc000fe0, "-x,b,t", CONDITIONAL}, 338{ "subo", 0x08000c00, 0xfc000fe0, "-x,b,t", CONDITIONAL}, 339{ "subb", 0x08000500, 0xfc000fe0, "-x,b,t", CONDITIONAL}, 340{ "subbo", 0x08000d00, 0xfc000fe0, "-x,b,t", CONDITIONAL}, 341{ "subt", 0x080004c0, 0xfc000fe0, "-x,b,t", CONDITIONAL}, 342{ "subto", 0x08000cc0, 0xfc000fe0, "-x,b,t", CONDITIONAL}, 343{ "ds", 0x08000440, 0xfc000fe0, "-x,b,t", CONDITIONAL}, 344{ "comclr", 0x08000880, 0xfc000fe0, "-x,b,t", CONDITIONAL}, 345{ "or", 0x08000240, 0xfc000fe0, "&x,b,t", CONDITIONAL}, 346{ "xor", 0x08000280, 0xfc000fe0, "&x,b,t", CONDITIONAL}, 347{ "and", 0x08000200, 0xfc000fe0, "&x,b,t", CONDITIONAL}, 348{ "andcm", 0x08000000, 0xfc000fe0, "&x,b,t", CONDITIONAL}, 349{ "uxor", 0x08000380, 0xfc000fe0, "Ux,b,t", CONDITIONAL}, 350{ "uaddcm", 0x08000980, 0xfc000fe0, "Ux,b,t", CONDITIONAL}, 351{ "uaddcmt", 0x080009c0, 0xfc000fe0, "Ux,b,t", CONDITIONAL}, 352{ "dcor", 0x08000b80, 0xfc1f0fe0, "Ub,t", CONDITIONAL}, 353{ "idcor", 0x08000bc0, 0xfc1f0fe0, "Ub,t", CONDITIONAL}, 354{ "addi", 0xb4000000, 0xfc000800, "+i,b,x", CONDITIONAL}, 355{ "addio", 0xb4000800, 0xfc000800, "+i,b,x", CONDITIONAL}, 356{ "addit", 0xb0000000, 0xfc000800, "+i,b,x", CONDITIONAL}, 357{ "addito", 0xb0000800, 0xfc000800, "+i,b,x", CONDITIONAL}, 358{ "subi", 0x94000000, 0xfc000800, "-i,b,x", CONDITIONAL}, 359{ "subio", 0x94000800, 0xfc000800, "-i,b,x", CONDITIONAL}, 360{ "comiclr", 0x90000000, 0xfc000800, "-i,b,x", CONDITIONAL}, 361{ "vshd", 0xd0000000, 0xfc001fe0, ">x,b,t", CONDITIONAL}, 362{ "shd", 0xd0000800, 0xfc001c00, ">x,b,p,t", CONDITIONAL}, 363{ "vextru", 0xd0001000, 0xfc001fe0, ">b,T,x", CONDITIONAL}, 364{ "vextrs", 0xd0001400, 0xfc001fe0, ">b,T,x", CONDITIONAL}, 365{ "extru", 0xd0001800, 0xfc001c00, ">b,P,T,x", CONDITIONAL}, 366{ "extrs", 0xd0001c00, 0xfc001c00, ">b,P,T,x", CONDITIONAL}, 367{ "vdep", 0xd4000400, 0xfc001fe0, ">x,T,b", CONDITIONAL}, 368{ "dep", 0xd4000c00, 0xfc001c00, ">x,p,T,b", CONDITIONAL}, 369{ "vdepi", 0xd4001400, 0xfc001fe0, ">5,T,b", CONDITIONAL}, 370{ "depi", 0xd4001c00, 0xfc001c00, ">5,p,T,b", CONDITIONAL}, 371{ "zvdep", 0xd4000000, 0xfc001fe0, ">x,T,b", CONDITIONAL}, 372{ "zdep", 0xd4000800, 0xfc001c00, ">x,p,T,b", CONDITIONAL}, 373{ "zvdepi", 0xd4001000, 0xfc001fe0, ">5,T,b", CONDITIONAL}, 374{ "zdepi", 0xd4001800, 0xfc001c00, ">5,p,T,b", CONDITIONAL}, 375 376/* System Control Instructions */ 377 378{ "break", 0x00000000, 0xfc001fe0, "r,A"}, 379{ "rfi", 0x00000c00, 0xffffffff, ""}, 380{ "rfir", 0x00000ca0, 0xffffffff, ""}, 381{ "ssm", 0x00000d60, 0xffe0ffe0, "R,t"}, 382{ "rsm", 0x00000e60, 0xffe0ffe0, "R,t"}, 383{ "mtsm", 0x00001860, 0xffe0ffff, "x"}, 384{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(B),t"}, 385{ "mtsp", 0x00001820, 0xffe01fff, "x,S"}, 386{ "mtctl", 0x00001840, 0xfc00ffff, "x,b"}, 387{ "mfsp", 0x000004a0, 0xffff1fe0, "S,t"}, 388{ "mfctl", 0x000008a0, 0xfc1fffe0, "b,t"}, 389{ "sync", 0x00000400, 0xffffffff, ""}, 390{ "prober", 0x04001180, 0xfc003fe0, "(B),x,t"}, 391{ "proberi", 0x04003180, 0xfc003fe0, "(B),5,t"}, 392{ "probew", 0x040011c0, 0xfc003fe0, "(B),x,t"}, 393{ "probewi", 0x040031c0, 0xfc003fe0, "(B),5,t"}, 394{ "lpa", 0x04001340, 0xfc003fc0, "Zx(B),t"}, 395{ "lha", 0x04001300, 0xfc003fc0, "Zx(B),t"}, 396{ "pdtlb", 0x04001200, 0xfc003fdf, "Zx(B)"}, 397{ "pitlb", 0x04000200, 0xfc001fdf, "Zx(S,b)"}, 398{ "pdtlbe", 0x04001240, 0xfc003fdf, "Zx(B)"}, 399{ "pitlbe", 0x04000240, 0xfc003fdf, "Zx(B)"}, 400{ "idtlba", 0x04001040, 0xfc003fff, "x,(B)"}, 401{ "iitlba", 0x04000040, 0xfc001fff, "x,(S,b)"}, 402{ "idtlbp", 0x04001000, 0xfc003fff, "x,(B)"}, 403{ "iitlbp", 0x04000000, 0xfc001fff, "x,(S,b)"}, 404{ "pdc", 0x04001380, 0xfc003fdf, "Zx(B)"}, 405{ "fdc", 0x04001280, 0xfc003fdf, "Zx(B)"}, 406{ "fic", 0x04000280, 0xfc001fdf, "Zx(S,b)"}, 407{ "fdce", 0x040012c0, 0xfc003fdf, "Zx(B)"}, 408{ "fice", 0x040002c0, 0xfc001fdf, "Zx(S,b)"}, 409{ "diag", 0x14000000, 0xfc000000, "D"}, 410{ "gfw", 0x04001680, 0xfc003fdf, "Zx(B)"}, /* variant of fdc */ 411{ "gfr", 0x04001a80, 0xfc003fdf, "Zx(B)"}, /* variant of fdc */ 412 413/* Floating Point Coprocessor Instructions */ 414 415{ "fldwx", 0x24000000, 0xfc001f80, "cx(B),v"}, /* PJH: v used to be t */ 416 /* and 0xfc001f80 used to be 0xfc001fc0 */ 417{ "flddx", 0x2c000000, 0xfc001fc0, "cx(B),t"}, 418{ "fstwx", 0x24000200, 0xfc001fc0, "cv,x(B)"}, /* PJH: v used to be t */ 419{ "fstdx", 0x2c000200, 0xfc001bc0, "3t,x(B)"}, /* #41317 was "clt,x(B)" */ 420{ "fldws", 0x24001000, 0xfc001fc0, "C5(B),v"}, /* PJH: v used to be t */ 421{ "fldds", 0x2c001000, 0xfc001fc0, "C5(B),t"}, 422{ "fstws", 0x24001200, 0xfc001bc0, "lv,5(B)"}, /* #41317 */ 423{ "fstds", 0x2c001200, 0xfc001bc0, "lt,5(B)"}, /* #41317 */ 424{ "fadd", 0x30000600, 0xf400e720, "FE,X,v"}, /* PJH: operands were "Fb,x,t" */ 425{ "fsub", 0x30002600, 0xf400e720, "FE,X,v"}, /* PJH: operands were "Fb,x,t" */ 426{ "fmpy", 0x30004600, 0xf400e720, "FE,X,v"}, /* PJH: operands were "Fb,x,t" */ 427{ "fdiv", 0x30006600, 0xf400e720, "FE,X,v"}, /* PJH: operands were "Fb,x,t" */ 428{ "fsqrt", 0x30008000, 0xf41fe720, "FE,v"}, /* PJH: operands were "Fb,t" */ 429{ "fabs", 0x30006000, 0xf41fe720, "FE,v"}, /* PJH: operands were "Fb,t" */ 430{ "frem", 0x30008600, 0xf400e720, "FE,X,v"}, /* PJH: operands were "Fb,x,t" */ 431{ "frnd", 0x3000a000, 0xf41fe720, "FE,v"}, /* PJH: operands were "Fb,t" */ 432{ "fcpy", 0x30004000, 0xf41fe720, "FE,v"}, /* PJH: operands were "Fb,t" */ 433{ "fcnvff", 0x30000200, 0xf41f8720, "FGE,v"}, /* PJH: operands were "FGb,t" */ 434{ "fcnvxf", 0x30008200, 0xf41f8720, "FGE,v"}, /* PJH: operands were "FGb,t" */ 435{ "fcnvfx", 0x30010200, 0xf41f8720, "FGE,v"}, /* PJH: operands were "FGb,t" */ 436{ "fcnvfxt", 0x30018200, 0xf41f8720, "FGE,v"}, /* PJH: operands were "FGb,t" */ 437{ "fcmp", 0x30000400, 0xf400e760, "FME,X"}, /* PJH: operands were "FMb,x" */ 438{ "ftest", 0x30002420, 0xffffffff, ""}, 439 440/* PA-89 only instructions */ 441 442{ "xmpyu", 0x38004700, 0xfc00e720, "FE,X,v"}, 443{ "fmpyadd", 0x18000000, 0xfc000000, "H4,6,7,9,8"}, 444{ "fmpysub", 0x98000000, 0xfc000000, "H4,6,7,9,8"}, 445 446/* Assist Instructions */ 447 448/* { "spop0", 0x10000000, 0xfc000600, ",f,On", NORMAL}, */ 449/* { "spop1", 0x10000200, 0xfc000600, ",f,ont", NORMAL}, */ 450/* { "spop2", 0x10000400, 0xfc000600, ",f,1nb", NORMAL}, */ 451/* { "spop3", 0x10000600, 0xfc000600, ",f,0nx,b", NORMAL}, */ 452/* { "copr", 0x30000000, 0xfc000000, ",u,2n", NORMAL}, */ 453{ "spop0", 0x10000000, 0xfc000600, ",f,Oy", NORMAL}, 454{ "spop1", 0x10000200, 0xfc000600, ",f,oyt", NORMAL}, 455{ "spop2", 0x10000400, 0xfc000600, ",f,1yb", NORMAL}, 456{ "spop3", 0x10000600, 0xfc000600, ",f,0yx,b", NORMAL}, 457{ "copr", 0x30000000, 0xfc000000, ",u,2y", NORMAL}, 458{ "cldwx", 0x24000000, 0xfc001e00, ",u,Zx(B),t"}, 459{ "clddx", 0x2c000000, 0xfc001e00, ",u,Zx(B),t"}, 460{ "cstwx", 0x24000200, 0xfc001a00, ",u,3t,x(B)"}, /* #41317 */ 461{ "cstdx", 0x2c000200, 0xfc001200, ",u,3t,x(B)"}, /* #41317 */ 462{ "cldws", 0x24001000, 0xfc001e00, ",u,Z5(B),t"}, 463{ "cldds", 0x2c001000, 0xfc001e00, ",u,Z5(B),t"}, 464{ "cstws", 0x24001200, 0xfc001e00, ",u,Zt,5(B)"}, 465{ "cstds", 0x2c001200, 0xfc001a00, ",u,3t,5(B)"}, /* #41317 */ 466{ "mtsar", 0x01601840, 0xffe0ffff, "x"}, 467 468/* 469 * This pseudo-instruction must be at the end so otool will dissassemble using 470 * it over a bl. 471 */ 472 473/* Gets translated to BL,n W,b (NeXT procedure call) and */ 474/* creates a relocation entry for @ .. USV */ 475 476{ "jbsr", 0xe8000000, 0xfc00e000, "n@,b,W", NORMAL}, 477}; 478 479#define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0])) 480 481#endif /* HPPA_OPCODE_INCLUDED */ 482 483/* end hppa-opcode.h */ 484