1/*
2 * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28
29#include <sys/appleapiopts.h>
30#include <ppc/asm.h>					// EXT, LEXT
31#include <machine/cpu_capabilities.h>
32#include <machine/commpage.h>
33
34        .text
35        .align	2
36
37
38// *********************************************
39// * C O M M P A G E _ F L U S H _ D C A C H E *
40// *********************************************
41//
42// Note that this routine is called both in 32 and 64-bit mode.
43//
44//	r3 = ptr to 1st byte to flush
45//	r4 = length to flush (may be 0)
46
47commpage_flush_dcache:
48        mr.     r4,r4           // test length for 0 in mode-independent way
49        lhz		r5,_COMM_PAGE_CACHE_LINESIZE(0)
50        subi	r9,r5,1			// get (linesize-1)
51        and		r0,r3,r9		// get offset within line of 1st byte
52        add		r4,r4,r0		// adjust length so we flush them all
53        add		r4,r4,r9		// round length up...
54        andc	r4,r4,r9		// ...to multiple of cache lines
55        beqlr--					// length was 0, so exit
561:
57        sub.	r4,r4,r5		// more to go?
58        dcbf	0,r3			// flush another line
59        add		r3,r3,r5
60        bne		1b
61        sync					// make sure lines are flushed before we return
62        blr
63
64	COMMPAGE_DESCRIPTOR(commpage_flush_dcache,_COMM_PAGE_FLUSH_DCACHE,0,0,kCommPageBoth)
65
66
67// *********************************************
68// * C O M M P A G E _ F L U S H _ I C A C H E *
69// *********************************************
70//
71// Note that this routine is called both in 32 and 64-bit mode.
72//
73//	r3 = ptr to 1st byte to flush
74//	r4 = length to flush (may be 0)
75
76commpage_flush_icache:
77        mr.     r4,r4           // test length for 0 in mode-independent way
78        lhz		r5,_COMM_PAGE_CACHE_LINESIZE(0)
79        subi	r9,r5,1			// get (linesize-1)
80        and		r0,r3,r9		// get offset within line of 1st byte
81        add		r4,r4,r0		// adjust length so we flush them all
82        mr		r7,r3			// copy ptr
83        add		r4,r4,r9		// round length up...
84        andc	r4,r4,r9		// ...to multiple of cache lines
85        mr		r6,r4			// copy length
86        beqlr--					// length was 0, so exit
871:
88        sub.	r4,r4,r5		// more to go?
89        dcbf	0,r3			// flush another line
90        add		r3,r3,r5
91        bne		1b
92        sync					// make sure lines are flushed
932:
94        sub.	r6,r6,r5		// more to go?
95        icbi	0,r7
96        add		r7,r7,r5
97        bne		2b
98
99        // The following sync is only needed on MP machines, probably only on
100        // 7400-family MP machines.  But because we're not certain of this, and
101        // this isn't a speed critical routine, we are conservative and always sync.
102
103        sync					// wait until other processors see the icbi's
104        isync					// make sure we haven't prefetched old instructions
105
106        blr
107
108	COMMPAGE_DESCRIPTOR(commpage_flush_icache,_COMM_PAGE_FLUSH_ICACHE,0,0,kCommPageBoth)
109
110
111