1/* 2 * Copyright (c) 2003-2006 Apple Computer, Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28 29#include <machine/cpu_capabilities.h> 30#include <machine/commpage.h> 31 32 .text 33 .align 2, 0x90 34 35// void sysFlushDcache( void *p, size_t len ); 36// 32-bit version 37 38Lsys_flush_dcache: 39 movl 8(%esp),%ecx // get length 40 movl 4(%esp),%edx // get ptr 41 testl %ecx,%ecx // length 0? 42 jz 2f // yes 43 mfence // ensure previous stores make it to memory 44 clflush -1(%edx,%ecx) // make sure last line is flushed 451: 46 clflush (%edx) // flush a line 47 addl $64,%edx 48 subl $64,%ecx 49 ja 1b 50 mfence // make sure memory is updated before we return 512: 52 ret 53 54 COMMPAGE_DESCRIPTOR(sys_flush_dcache,_COMM_PAGE_FLUSH_DCACHE,kCache64,0) 55 56 57// void sysFlushDcache( void *p, size_t len ); 58// 64-bit version 59 .code64 60Lsys_flush_dcache_64: // %rdi = ptr, %rsi = length 61 testq %rsi,%rsi // length 0? 62 jz 2f // yes 63 mfence // ensure previous stores make it to memory 64 clflush -1(%rdi,%rsi) // make sure last line is flushed 651: 66 clflush (%rdi) // flush a line 67 addq $64,%rdi 68 subq $64,%rsi 69 ja 1b 70 mfence // make sure memory is updated before we return 712: 72 ret 73 .code32 74 COMMPAGE_DESCRIPTOR(sys_flush_dcache_64,_COMM_PAGE_FLUSH_DCACHE,kCache64,0) 75 76 77// void sysIcacheInvalidate( void *p, size_t len ); 78 79Lsys_icache_invalidate: 80 // This is a NOP on intel processors, since the intent of the API 81 // is to make data executable, and Intel L1Is are coherent with L1D. 82 // We can use same routine both in 32 and 64-bit mode, since it is 83 // just a RET instruction. 84 ret 85 86 COMMPAGE_DESCRIPTOR(sys_icache_invalidate,_COMM_PAGE_FLUSH_ICACHE,0,0) 87