1//===-- X86RegisterInfo.cpp - X86 Register Information --------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetRegisterInfo class. 11// This file is responsible for the frame pointer elimination optimization 12// on X86. 13// 14//===----------------------------------------------------------------------===// 15 16#include "X86RegisterInfo.h" 17#include "X86.h" 18#include "X86InstrBuilder.h" 19#include "X86MachineFunctionInfo.h" 20#include "X86Subtarget.h" 21#include "X86TargetMachine.h" 22#include "llvm/Constants.h" 23#include "llvm/Function.h" 24#include "llvm/Type.h" 25#include "llvm/CodeGen/ValueTypes.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineFunction.h" 28#include "llvm/CodeGen/MachineFunctionPass.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineModuleInfo.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/MC/MCAsmInfo.h" 33#include "llvm/Target/TargetFrameLowering.h" 34#include "llvm/Target/TargetInstrInfo.h" 35#include "llvm/Target/TargetMachine.h" 36#include "llvm/Target/TargetOptions.h" 37#include "llvm/ADT/BitVector.h" 38#include "llvm/ADT/STLExtras.h" 39#include "llvm/Support/ErrorHandling.h" 40#include "llvm/Support/CommandLine.h" 41 42#define GET_REGINFO_TARGET_DESC 43#include "X86GenRegisterInfo.inc" 44 45using namespace llvm; 46 47cl::opt<bool> 48ForceStackAlign("force-align-stack", 49 cl::desc("Force align the stack to the minimum alignment" 50 " needed for the function."), 51 cl::init(false), cl::Hidden); 52 53cl::opt<bool> 54EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true), 55 cl::desc("Enable use of a base pointer for complex stack frames")); 56 57X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm, 58 const TargetInstrInfo &tii) 59 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() 60 ? X86::RIP : X86::EIP, 61 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false), 62 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true)), 63 TM(tm), TII(tii) { 64 X86_MC::InitLLVM2SEHRegisterMapping(this); 65 66 // Cache some information. 67 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 68 Is64Bit = Subtarget->is64Bit(); 69 IsWin64 = Subtarget->isTargetWin64(); 70 71 if (Is64Bit) { 72 SlotSize = 8; 73 StackPtr = X86::RSP; 74 FramePtr = X86::RBP; 75 } else { 76 SlotSize = 4; 77 StackPtr = X86::ESP; 78 FramePtr = X86::EBP; 79 } 80 // Use a callee-saved register as the base pointer. These registers must 81 // not conflict with any ABI requirements. For example, in 32-bit mode PIC 82 // requires GOT in the EBX register before function calls via PLT GOT pointer. 83 BasePtr = Is64Bit ? X86::RBX : X86::ESI; 84} 85 86/// getCompactUnwindRegNum - This function maps the register to the number for 87/// compact unwind encoding. Return -1 if the register isn't valid. 88int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const { 89 switch (getLLVMRegNum(RegNum, isEH)) { 90 case X86::EBX: case X86::RBX: return 1; 91 case X86::ECX: case X86::R12: return 2; 92 case X86::EDX: case X86::R13: return 3; 93 case X86::EDI: case X86::R14: return 4; 94 case X86::ESI: case X86::R15: return 5; 95 case X86::EBP: case X86::RBP: return 6; 96 } 97 98 return -1; 99} 100 101bool 102X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 103 // Only enable when post-RA scheduling is enabled and this is needed. 104 return TM.getSubtargetImpl()->postRAScheduler(); 105} 106 107int 108X86RegisterInfo::getSEHRegNum(unsigned i) const { 109 int reg = X86_MC::getX86RegNum(i); 110 switch (i) { 111 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: 112 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: 113 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: 114 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B: 115 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B: 116 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: 117 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: 118 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: 119 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: 120 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: 121 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11: 122 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15: 123 reg += 8; 124 } 125 return reg; 126} 127 128const TargetRegisterClass * 129X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, 130 unsigned Idx) const { 131 // The sub_8bit sub-register index is more constrained in 32-bit mode. 132 // It behaves just like the sub_8bit_hi index. 133 if (!Is64Bit && Idx == X86::sub_8bit) 134 Idx = X86::sub_8bit_hi; 135 136 // Forward to TableGen's default version. 137 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx); 138} 139 140const TargetRegisterClass * 141X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 142 const TargetRegisterClass *B, 143 unsigned SubIdx) const { 144 // The sub_8bit sub-register index is more constrained in 32-bit mode. 145 if (!Is64Bit && SubIdx == X86::sub_8bit) { 146 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi); 147 if (!A) 148 return 0; 149 } 150 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx); 151} 152 153const TargetRegisterClass* 154X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{ 155 // Don't allow super-classes of GR8_NOREX. This class is only used after 156 // extrating sub_8bit_hi sub-registers. The H sub-registers cannot be copied 157 // to the full GR8 register class in 64-bit mode, so we cannot allow the 158 // reigster class inflation. 159 // 160 // The GR8_NOREX class is always used in a way that won't be constrained to a 161 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the 162 // full GR8 class. 163 if (RC == &X86::GR8_NOREXRegClass) 164 return RC; 165 166 const TargetRegisterClass *Super = RC; 167 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 168 do { 169 switch (Super->getID()) { 170 case X86::GR8RegClassID: 171 case X86::GR16RegClassID: 172 case X86::GR32RegClassID: 173 case X86::GR64RegClassID: 174 case X86::FR32RegClassID: 175 case X86::FR64RegClassID: 176 case X86::RFP32RegClassID: 177 case X86::RFP64RegClassID: 178 case X86::RFP80RegClassID: 179 case X86::VR128RegClassID: 180 case X86::VR256RegClassID: 181 // Don't return a super-class that would shrink the spill size. 182 // That can happen with the vector and float classes. 183 if (Super->getSize() == RC->getSize()) 184 return Super; 185 } 186 Super = *I++; 187 } while (Super); 188 return RC; 189} 190 191const TargetRegisterClass * 192X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 193 const { 194 switch (Kind) { 195 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!"); 196 case 0: // Normal GPRs. 197 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 198 return &X86::GR64RegClass; 199 return &X86::GR32RegClass; 200 case 1: // Normal GPRs except the stack pointer (for encoding reasons). 201 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 202 return &X86::GR64_NOSPRegClass; 203 return &X86::GR32_NOSPRegClass; 204 case 2: // Available for tailcall (not callee-saved GPRs). 205 if (TM.getSubtarget<X86Subtarget>().isTargetWin64()) 206 return &X86::GR64_TCW64RegClass; 207 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 208 return &X86::GR64_TCRegClass; 209 return &X86::GR32_TCRegClass; 210 } 211} 212 213const TargetRegisterClass * 214X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 215 if (RC == &X86::CCRRegClass) { 216 if (Is64Bit) 217 return &X86::GR64RegClass; 218 else 219 return &X86::GR32RegClass; 220 } 221 return RC; 222} 223 224unsigned 225X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 226 MachineFunction &MF) const { 227 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 228 229 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0; 230 switch (RC->getID()) { 231 default: 232 return 0; 233 case X86::GR32RegClassID: 234 return 4 - FPDiff; 235 case X86::GR64RegClassID: 236 return 12 - FPDiff; 237 case X86::VR128RegClassID: 238 return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4; 239 case X86::VR64RegClassID: 240 return 4; 241 } 242} 243 244const uint16_t * 245X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 246 bool callsEHReturn = false; 247 bool ghcCall = false; 248 bool oclBiCall = false; 249 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 250 251 if (MF) { 252 callsEHReturn = MF->getMMI().callsEHReturn(); 253 const Function *F = MF->getFunction(); 254 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false); 255 oclBiCall = (F ? F->getCallingConv() == CallingConv::Intel_OCL_BI : false); 256 } 257 258 if (ghcCall) 259 return CSR_NoRegs_SaveList; 260 if (oclBiCall) { 261 if (HasAVX && IsWin64) 262 return CSR_Win64_Intel_OCL_BI_AVX_SaveList; 263 if (HasAVX && Is64Bit) 264 return CSR_64_Intel_OCL_BI_AVX_SaveList; 265 if (!HasAVX && !IsWin64 && Is64Bit) 266 return CSR_64_Intel_OCL_BI_SaveList; 267 } 268 if (Is64Bit) { 269 if (IsWin64) 270 return CSR_Win64_SaveList; 271 if (callsEHReturn) 272 return CSR_64EHRet_SaveList; 273 return CSR_64_SaveList; 274 } 275 if (callsEHReturn) 276 return CSR_32EHRet_SaveList; 277 return CSR_32_SaveList; 278} 279 280const uint32_t* 281X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 282 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 283 284 if (CC == CallingConv::Intel_OCL_BI) { 285 if (IsWin64 && HasAVX) 286 return CSR_Win64_Intel_OCL_BI_AVX_RegMask; 287 if (Is64Bit && HasAVX) 288 return CSR_64_Intel_OCL_BI_AVX_RegMask; 289 if (!HasAVX && !IsWin64 && Is64Bit) 290 return CSR_64_Intel_OCL_BI_RegMask; 291 } 292 if (CC == CallingConv::GHC) 293 return CSR_NoRegs_RegMask; 294 if (!Is64Bit) 295 return CSR_32_RegMask; 296 if (IsWin64) 297 return CSR_Win64_RegMask; 298 return CSR_64_RegMask; 299} 300 301BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const { 302 BitVector Reserved(getNumRegs()); 303 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 304 305 // Set the stack-pointer register and its aliases as reserved. 306 Reserved.set(X86::RSP); 307 for (MCSubRegIterator I(X86::RSP, this); I.isValid(); ++I) 308 Reserved.set(*I); 309 310 // Set the instruction pointer register and its aliases as reserved. 311 Reserved.set(X86::RIP); 312 for (MCSubRegIterator I(X86::RIP, this); I.isValid(); ++I) 313 Reserved.set(*I); 314 315 // Set the frame-pointer register and its aliases as reserved if needed. 316 if (TFI->hasFP(MF)) { 317 Reserved.set(X86::RBP); 318 for (MCSubRegIterator I(X86::RBP, this); I.isValid(); ++I) 319 Reserved.set(*I); 320 } 321 322 // Set the base-pointer register and its aliases as reserved if needed. 323 if (hasBasePointer(MF)) { 324 CallingConv::ID CC = MF.getFunction()->getCallingConv(); 325 const uint32_t* RegMask = getCallPreservedMask(CC); 326 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister())) 327 report_fatal_error( 328 "Stack realignment in presence of dynamic allocas is not supported with" 329 "this calling convention."); 330 331 Reserved.set(getBaseRegister()); 332 for (MCSubRegIterator I(getBaseRegister(), this); I.isValid(); ++I) 333 Reserved.set(*I); 334 } 335 336 // Mark the segment registers as reserved. 337 Reserved.set(X86::CS); 338 Reserved.set(X86::SS); 339 Reserved.set(X86::DS); 340 Reserved.set(X86::ES); 341 Reserved.set(X86::FS); 342 Reserved.set(X86::GS); 343 344 // Mark the floating point stack registers as reserved. 345 Reserved.set(X86::ST0); 346 Reserved.set(X86::ST1); 347 Reserved.set(X86::ST2); 348 Reserved.set(X86::ST3); 349 Reserved.set(X86::ST4); 350 Reserved.set(X86::ST5); 351 Reserved.set(X86::ST6); 352 Reserved.set(X86::ST7); 353 354 // Reserve the registers that only exist in 64-bit mode. 355 if (!Is64Bit) { 356 // These 8-bit registers are part of the x86-64 extension even though their 357 // super-registers are old 32-bits. 358 Reserved.set(X86::SIL); 359 Reserved.set(X86::DIL); 360 Reserved.set(X86::BPL); 361 Reserved.set(X86::SPL); 362 363 for (unsigned n = 0; n != 8; ++n) { 364 // R8, R9, ... 365 static const uint16_t GPR64[] = { 366 X86::R8, X86::R9, X86::R10, X86::R11, 367 X86::R12, X86::R13, X86::R14, X86::R15 368 }; 369 for (MCRegAliasIterator AI(GPR64[n], this, true); AI.isValid(); ++AI) 370 Reserved.set(*AI); 371 372 // XMM8, XMM9, ... 373 assert(X86::XMM15 == X86::XMM8+7); 374 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI) 375 Reserved.set(*AI); 376 } 377 } 378 379 return Reserved; 380} 381 382//===----------------------------------------------------------------------===// 383// Stack Frame Processing methods 384//===----------------------------------------------------------------------===// 385 386bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const { 387 const MachineFrameInfo *MFI = MF.getFrameInfo(); 388 389 if (!EnableBasePointer) 390 return false; 391 392 // When we need stack realignment and there are dynamic allocas, we can't 393 // reference off of the stack pointer, so we reserve a base pointer. 394 if (needsStackRealignment(MF) && MFI->hasVarSizedObjects()) 395 return true; 396 397 return false; 398} 399 400bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const { 401 const MachineFrameInfo *MFI = MF.getFrameInfo(); 402 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 403 if (!MF.getTarget().Options.RealignStack) 404 return false; 405 406 // Stack realignment requires a frame pointer. If we already started 407 // register allocation with frame pointer elimination, it is too late now. 408 if (!MRI->canReserveReg(FramePtr)) 409 return false; 410 411 // If a base pointer is necessary. Check that it isn't too late to reserve 412 // it. 413 if (MFI->hasVarSizedObjects()) 414 return MRI->canReserveReg(BasePtr); 415 return true; 416} 417 418bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const { 419 const MachineFrameInfo *MFI = MF.getFrameInfo(); 420 const Function *F = MF.getFunction(); 421 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 422 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || 423 F->getFnAttributes().hasStackAlignmentAttr()); 424 425 // If we've requested that we force align the stack do so now. 426 if (ForceStackAlign) 427 return canRealignStack(MF); 428 429 return requiresRealignment && canRealignStack(MF); 430} 431 432bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 433 unsigned Reg, int &FrameIdx) const { 434 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 435 436 if (Reg == FramePtr && TFI->hasFP(MF)) { 437 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin(); 438 return true; 439 } 440 return false; 441} 442 443static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) { 444 if (is64Bit) { 445 if (isInt<8>(Imm)) 446 return X86::SUB64ri8; 447 return X86::SUB64ri32; 448 } else { 449 if (isInt<8>(Imm)) 450 return X86::SUB32ri8; 451 return X86::SUB32ri; 452 } 453} 454 455static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) { 456 if (is64Bit) { 457 if (isInt<8>(Imm)) 458 return X86::ADD64ri8; 459 return X86::ADD64ri32; 460 } else { 461 if (isInt<8>(Imm)) 462 return X86::ADD32ri8; 463 return X86::ADD32ri; 464 } 465} 466 467void X86RegisterInfo:: 468eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 469 MachineBasicBlock::iterator I) const { 470 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 471 bool reseveCallFrame = TFI->hasReservedCallFrame(MF); 472 int Opcode = I->getOpcode(); 473 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode(); 474 DebugLoc DL = I->getDebugLoc(); 475 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0; 476 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0; 477 I = MBB.erase(I); 478 479 if (!reseveCallFrame) { 480 // If the stack pointer can be changed after prologue, turn the 481 // adjcallstackup instruction into a 'sub ESP, <amt>' and the 482 // adjcallstackdown instruction into 'add ESP, <amt>' 483 // TODO: consider using push / pop instead of sub + store / add 484 if (Amount == 0) 485 return; 486 487 // We need to keep the stack aligned properly. To do this, we round the 488 // amount of space needed for the outgoing arguments up to the next 489 // alignment boundary. 490 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 491 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign; 492 493 MachineInstr *New = 0; 494 if (Opcode == TII.getCallFrameSetupOpcode()) { 495 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)), 496 StackPtr) 497 .addReg(StackPtr) 498 .addImm(Amount); 499 } else { 500 assert(Opcode == TII.getCallFrameDestroyOpcode()); 501 502 // Factor out the amount the callee already popped. 503 Amount -= CalleeAmt; 504 505 if (Amount) { 506 unsigned Opc = getADDriOpcode(Is64Bit, Amount); 507 New = BuildMI(MF, DL, TII.get(Opc), StackPtr) 508 .addReg(StackPtr).addImm(Amount); 509 } 510 } 511 512 if (New) { 513 // The EFLAGS implicit def is dead. 514 New->getOperand(3).setIsDead(); 515 516 // Replace the pseudo instruction with a new instruction. 517 MBB.insert(I, New); 518 } 519 520 return; 521 } 522 523 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) { 524 // If we are performing frame pointer elimination and if the callee pops 525 // something off the stack pointer, add it back. We do this until we have 526 // more advanced stack pointer tracking ability. 527 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt); 528 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr) 529 .addReg(StackPtr).addImm(CalleeAmt); 530 531 // The EFLAGS implicit def is dead. 532 New->getOperand(3).setIsDead(); 533 534 // We are not tracking the stack pointer adjustment by the callee, so make 535 // sure we restore the stack pointer immediately after the call, there may 536 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions. 537 MachineBasicBlock::iterator B = MBB.begin(); 538 while (I != B && !llvm::prior(I)->isCall()) 539 --I; 540 MBB.insert(I, New); 541 } 542} 543 544void 545X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 546 int SPAdj, RegScavenger *RS) const { 547 assert(SPAdj == 0 && "Unexpected"); 548 549 unsigned i = 0; 550 MachineInstr &MI = *II; 551 MachineFunction &MF = *MI.getParent()->getParent(); 552 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 553 554 while (!MI.getOperand(i).isFI()) { 555 ++i; 556 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 557 } 558 559 int FrameIndex = MI.getOperand(i).getIndex(); 560 unsigned BasePtr; 561 562 unsigned Opc = MI.getOpcode(); 563 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm; 564 if (hasBasePointer(MF)) 565 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister()); 566 else if (needsStackRealignment(MF)) 567 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr); 568 else if (AfterFPPop) 569 BasePtr = StackPtr; 570 else 571 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr); 572 573 // This must be part of a four operand memory reference. Replace the 574 // FrameIndex with base register with EBP. Add an offset to the offset. 575 MI.getOperand(i).ChangeToRegister(BasePtr, false); 576 577 // Now add the frame object offset to the offset from EBP. 578 int FIOffset; 579 if (AfterFPPop) { 580 // Tail call jmp happens after FP is popped. 581 const MachineFrameInfo *MFI = MF.getFrameInfo(); 582 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea(); 583 } else 584 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex); 585 586 if (MI.getOperand(i+3).isImm()) { 587 // Offset is a 32-bit integer. 588 int Imm = (int)(MI.getOperand(i + 3).getImm()); 589 int Offset = FIOffset + Imm; 590 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) && 591 "Requesting 64-bit offset in 32-bit immediate!"); 592 MI.getOperand(i + 3).ChangeToImmediate(Offset); 593 } else { 594 // Offset is symbolic. This is extremely rare. 595 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset(); 596 MI.getOperand(i+3).setOffset(Offset); 597 } 598} 599 600unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const { 601 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 602 return TFI->hasFP(MF) ? FramePtr : StackPtr; 603} 604 605unsigned X86RegisterInfo::getEHExceptionRegister() const { 606 llvm_unreachable("What is the exception register"); 607} 608 609unsigned X86RegisterInfo::getEHHandlerRegister() const { 610 llvm_unreachable("What is the exception handler register"); 611} 612 613namespace llvm { 614unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT, 615 bool High) { 616 switch (VT) { 617 default: llvm_unreachable("Unexpected VT"); 618 case MVT::i8: 619 if (High) { 620 switch (Reg) { 621 default: return getX86SubSuperRegister(Reg, MVT::i64, High); 622 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 623 return X86::AH; 624 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 625 return X86::DH; 626 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 627 return X86::CH; 628 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 629 return X86::BH; 630 } 631 } else { 632 switch (Reg) { 633 default: llvm_unreachable("Unexpected register"); 634 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 635 return X86::AL; 636 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 637 return X86::DL; 638 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 639 return X86::CL; 640 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 641 return X86::BL; 642 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 643 return X86::SIL; 644 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 645 return X86::DIL; 646 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 647 return X86::BPL; 648 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 649 return X86::SPL; 650 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 651 return X86::R8B; 652 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 653 return X86::R9B; 654 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 655 return X86::R10B; 656 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 657 return X86::R11B; 658 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 659 return X86::R12B; 660 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 661 return X86::R13B; 662 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 663 return X86::R14B; 664 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 665 return X86::R15B; 666 } 667 } 668 case MVT::i16: 669 switch (Reg) { 670 default: llvm_unreachable("Unexpected register"); 671 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 672 return X86::AX; 673 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 674 return X86::DX; 675 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 676 return X86::CX; 677 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 678 return X86::BX; 679 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 680 return X86::SI; 681 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 682 return X86::DI; 683 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 684 return X86::BP; 685 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 686 return X86::SP; 687 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 688 return X86::R8W; 689 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 690 return X86::R9W; 691 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 692 return X86::R10W; 693 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 694 return X86::R11W; 695 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 696 return X86::R12W; 697 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 698 return X86::R13W; 699 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 700 return X86::R14W; 701 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 702 return X86::R15W; 703 } 704 case MVT::i32: 705 switch (Reg) { 706 default: llvm_unreachable("Unexpected register"); 707 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 708 return X86::EAX; 709 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 710 return X86::EDX; 711 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 712 return X86::ECX; 713 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 714 return X86::EBX; 715 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 716 return X86::ESI; 717 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 718 return X86::EDI; 719 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 720 return X86::EBP; 721 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 722 return X86::ESP; 723 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 724 return X86::R8D; 725 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 726 return X86::R9D; 727 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 728 return X86::R10D; 729 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 730 return X86::R11D; 731 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 732 return X86::R12D; 733 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 734 return X86::R13D; 735 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 736 return X86::R14D; 737 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 738 return X86::R15D; 739 } 740 case MVT::i64: 741 // For 64-bit mode if we've requested a "high" register and the 742 // Q or r constraints we want one of these high registers or 743 // just the register name otherwise. 744 if (High) { 745 switch (Reg) { 746 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 747 return X86::SI; 748 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 749 return X86::DI; 750 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 751 return X86::BP; 752 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 753 return X86::SP; 754 // Fallthrough. 755 } 756 } 757 switch (Reg) { 758 default: llvm_unreachable("Unexpected register"); 759 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 760 return X86::RAX; 761 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 762 return X86::RDX; 763 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 764 return X86::RCX; 765 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 766 return X86::RBX; 767 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 768 return X86::RSI; 769 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 770 return X86::RDI; 771 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 772 return X86::RBP; 773 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 774 return X86::RSP; 775 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 776 return X86::R8; 777 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 778 return X86::R9; 779 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 780 return X86::R10; 781 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 782 return X86::R11; 783 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 784 return X86::R12; 785 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 786 return X86::R13; 787 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 788 return X86::R14; 789 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 790 return X86::R15; 791 } 792 } 793} 794} 795 796namespace { 797 struct MSAH : public MachineFunctionPass { 798 static char ID; 799 MSAH() : MachineFunctionPass(ID) {} 800 801 virtual bool runOnMachineFunction(MachineFunction &MF) { 802 const X86TargetMachine *TM = 803 static_cast<const X86TargetMachine *>(&MF.getTarget()); 804 const TargetFrameLowering *TFI = TM->getFrameLowering(); 805 MachineRegisterInfo &RI = MF.getRegInfo(); 806 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 807 unsigned StackAlignment = TFI->getStackAlignment(); 808 809 // Be over-conservative: scan over all vreg defs and find whether vector 810 // registers are used. If yes, there is a possibility that vector register 811 // will be spilled and thus require dynamic stack realignment. 812 for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) { 813 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 814 if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) { 815 FuncInfo->setForceFramePointer(true); 816 return true; 817 } 818 } 819 // Nothing to do 820 return false; 821 } 822 823 virtual const char *getPassName() const { 824 return "X86 Maximal Stack Alignment Check"; 825 } 826 827 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 828 AU.setPreservesCFG(); 829 MachineFunctionPass::getAnalysisUsage(AU); 830 } 831 }; 832 833 char MSAH::ID = 0; 834} 835 836FunctionPass* 837llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); } 838