1//===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of TargetFrameLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "X86FrameLowering.h" 15#include "X86InstrBuilder.h" 16#include "X86InstrInfo.h" 17#include "X86MachineFunctionInfo.h" 18#include "X86Subtarget.h" 19#include "X86TargetMachine.h" 20#include "llvm/Function.h" 21#include "llvm/CodeGen/MachineFrameInfo.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineInstrBuilder.h" 24#include "llvm/CodeGen/MachineModuleInfo.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/MC/MCAsmInfo.h" 27#include "llvm/MC/MCSymbol.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetOptions.h" 30#include "llvm/Support/CommandLine.h" 31#include "llvm/ADT/SmallSet.h" 32 33using namespace llvm; 34 35// FIXME: completely move here. 36extern cl::opt<bool> ForceStackAlign; 37 38bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { 39 return !MF.getFrameInfo()->hasVarSizedObjects(); 40} 41 42/// hasFP - Return true if the specified function should have a dedicated frame 43/// pointer register. This is true if the function has variable sized allocas 44/// or if frame pointer elimination is disabled. 45bool X86FrameLowering::hasFP(const MachineFunction &MF) const { 46 const MachineFrameInfo *MFI = MF.getFrameInfo(); 47 const MachineModuleInfo &MMI = MF.getMMI(); 48 const TargetRegisterInfo *RegInfo = TM.getRegisterInfo(); 49 50 return (MF.getTarget().Options.DisableFramePointerElim(MF) || 51 RegInfo->needsStackRealignment(MF) || 52 MFI->hasVarSizedObjects() || 53 MFI->isFrameAddressTaken() || 54 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() || 55 MMI.callsUnwindInit() || MMI.callsEHReturn()); 56} 57 58static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) { 59 if (is64Bit) { 60 if (isInt<8>(Imm)) 61 return X86::SUB64ri8; 62 return X86::SUB64ri32; 63 } else { 64 if (isInt<8>(Imm)) 65 return X86::SUB32ri8; 66 return X86::SUB32ri; 67 } 68} 69 70static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) { 71 if (is64Bit) { 72 if (isInt<8>(Imm)) 73 return X86::ADD64ri8; 74 return X86::ADD64ri32; 75 } else { 76 if (isInt<8>(Imm)) 77 return X86::ADD32ri8; 78 return X86::ADD32ri; 79 } 80} 81 82static unsigned getLEArOpcode(unsigned is64Bit) { 83 return is64Bit ? X86::LEA64r : X86::LEA32r; 84} 85 86/// findDeadCallerSavedReg - Return a caller-saved register that isn't live 87/// when it reaches the "return" instruction. We can then pop a stack object 88/// to this register without worry about clobbering it. 89static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, 90 MachineBasicBlock::iterator &MBBI, 91 const TargetRegisterInfo &TRI, 92 bool Is64Bit) { 93 const MachineFunction *MF = MBB.getParent(); 94 const Function *F = MF->getFunction(); 95 if (!F || MF->getMMI().callsEHReturn()) 96 return 0; 97 98 static const uint16_t CallerSavedRegs32Bit[] = { 99 X86::EAX, X86::EDX, X86::ECX, 0 100 }; 101 102 static const uint16_t CallerSavedRegs64Bit[] = { 103 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI, 104 X86::R8, X86::R9, X86::R10, X86::R11, 0 105 }; 106 107 unsigned Opc = MBBI->getOpcode(); 108 switch (Opc) { 109 default: return 0; 110 case X86::RET: 111 case X86::RETI: 112 case X86::TCRETURNdi: 113 case X86::TCRETURNri: 114 case X86::TCRETURNmi: 115 case X86::TCRETURNdi64: 116 case X86::TCRETURNri64: 117 case X86::TCRETURNmi64: 118 case X86::EH_RETURN: 119 case X86::EH_RETURN64: { 120 SmallSet<uint16_t, 8> Uses; 121 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) { 122 MachineOperand &MO = MBBI->getOperand(i); 123 if (!MO.isReg() || MO.isDef()) 124 continue; 125 unsigned Reg = MO.getReg(); 126 if (!Reg) 127 continue; 128 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI) 129 Uses.insert(*AI); 130 } 131 132 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit; 133 for (; *CS; ++CS) 134 if (!Uses.count(*CS)) 135 return *CS; 136 } 137 } 138 139 return 0; 140} 141 142 143/// emitSPUpdate - Emit a series of instructions to increment / decrement the 144/// stack pointer by a constant value. 145static 146void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 147 unsigned StackPtr, int64_t NumBytes, 148 bool Is64Bit, bool UseLEA, 149 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) { 150 bool isSub = NumBytes < 0; 151 uint64_t Offset = isSub ? -NumBytes : NumBytes; 152 unsigned Opc; 153 if (UseLEA) 154 Opc = getLEArOpcode(Is64Bit); 155 else 156 Opc = isSub 157 ? getSUBriOpcode(Is64Bit, Offset) 158 : getADDriOpcode(Is64Bit, Offset); 159 160 uint64_t Chunk = (1LL << 31) - 1; 161 DebugLoc DL = MBB.findDebugLoc(MBBI); 162 163 while (Offset) { 164 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset; 165 if (ThisVal == (Is64Bit ? 8 : 4)) { 166 // Use push / pop instead. 167 unsigned Reg = isSub 168 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX) 169 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit); 170 if (Reg) { 171 Opc = isSub 172 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r) 173 : (Is64Bit ? X86::POP64r : X86::POP32r); 174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc)) 175 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)); 176 if (isSub) 177 MI->setFlag(MachineInstr::FrameSetup); 178 Offset -= ThisVal; 179 continue; 180 } 181 } 182 183 MachineInstr *MI = NULL; 184 185 if (UseLEA) { 186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr), 187 StackPtr, false, isSub ? -ThisVal : ThisVal); 188 } else { 189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) 190 .addReg(StackPtr) 191 .addImm(ThisVal); 192 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead. 193 } 194 195 if (isSub) 196 MI->setFlag(MachineInstr::FrameSetup); 197 198 Offset -= ThisVal; 199 } 200} 201 202/// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator. 203static 204void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 205 unsigned StackPtr, uint64_t *NumBytes = NULL) { 206 if (MBBI == MBB.begin()) return; 207 208 MachineBasicBlock::iterator PI = prior(MBBI); 209 unsigned Opc = PI->getOpcode(); 210 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || 211 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 || 212 Opc == X86::LEA32r || Opc == X86::LEA64_32r) && 213 PI->getOperand(0).getReg() == StackPtr) { 214 if (NumBytes) 215 *NumBytes += PI->getOperand(2).getImm(); 216 MBB.erase(PI); 217 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || 218 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && 219 PI->getOperand(0).getReg() == StackPtr) { 220 if (NumBytes) 221 *NumBytes -= PI->getOperand(2).getImm(); 222 MBB.erase(PI); 223 } 224} 225 226/// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower iterator. 227static 228void mergeSPUpdatesDown(MachineBasicBlock &MBB, 229 MachineBasicBlock::iterator &MBBI, 230 unsigned StackPtr, uint64_t *NumBytes = NULL) { 231 // FIXME: THIS ISN'T RUN!!! 232 return; 233 234 if (MBBI == MBB.end()) return; 235 236 MachineBasicBlock::iterator NI = llvm::next(MBBI); 237 if (NI == MBB.end()) return; 238 239 unsigned Opc = NI->getOpcode(); 240 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || 241 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) && 242 NI->getOperand(0).getReg() == StackPtr) { 243 if (NumBytes) 244 *NumBytes -= NI->getOperand(2).getImm(); 245 MBB.erase(NI); 246 MBBI = NI; 247 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || 248 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && 249 NI->getOperand(0).getReg() == StackPtr) { 250 if (NumBytes) 251 *NumBytes += NI->getOperand(2).getImm(); 252 MBB.erase(NI); 253 MBBI = NI; 254 } 255} 256 257/// mergeSPUpdates - Checks the instruction before/after the passed 258/// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and the 259/// stack adjustment is returned as a positive value for ADD/LEA and a negative for 260/// SUB. 261static int mergeSPUpdates(MachineBasicBlock &MBB, 262 MachineBasicBlock::iterator &MBBI, 263 unsigned StackPtr, 264 bool doMergeWithPrevious) { 265 if ((doMergeWithPrevious && MBBI == MBB.begin()) || 266 (!doMergeWithPrevious && MBBI == MBB.end())) 267 return 0; 268 269 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI; 270 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI); 271 unsigned Opc = PI->getOpcode(); 272 int Offset = 0; 273 274 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || 275 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 || 276 Opc == X86::LEA32r || Opc == X86::LEA64_32r) && 277 PI->getOperand(0).getReg() == StackPtr){ 278 Offset += PI->getOperand(2).getImm(); 279 MBB.erase(PI); 280 if (!doMergeWithPrevious) MBBI = NI; 281 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || 282 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && 283 PI->getOperand(0).getReg() == StackPtr) { 284 Offset -= PI->getOperand(2).getImm(); 285 MBB.erase(PI); 286 if (!doMergeWithPrevious) MBBI = NI; 287 } 288 289 return Offset; 290} 291 292static bool isEAXLiveIn(MachineFunction &MF) { 293 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(), 294 EE = MF.getRegInfo().livein_end(); II != EE; ++II) { 295 unsigned Reg = II->first; 296 297 if (Reg == X86::EAX || Reg == X86::AX || 298 Reg == X86::AH || Reg == X86::AL) 299 return true; 300 } 301 302 return false; 303} 304 305void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF, 306 MCSymbol *Label, 307 unsigned FramePtr) const { 308 MachineFrameInfo *MFI = MF.getFrameInfo(); 309 MachineModuleInfo &MMI = MF.getMMI(); 310 311 // Add callee saved registers to move list. 312 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 313 if (CSI.empty()) return; 314 315 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 316 const TargetData *TD = TM.getTargetData(); 317 bool HasFP = hasFP(MF); 318 319 // Calculate amount of bytes used for return address storing. 320 int stackGrowth = -TD->getPointerSize(); 321 322 // FIXME: This is dirty hack. The code itself is pretty mess right now. 323 // It should be rewritten from scratch and generalized sometimes. 324 325 // Determine maximum offset (minimum due to stack growth). 326 int64_t MaxOffset = 0; 327 for (std::vector<CalleeSavedInfo>::const_iterator 328 I = CSI.begin(), E = CSI.end(); I != E; ++I) 329 MaxOffset = std::min(MaxOffset, 330 MFI->getObjectOffset(I->getFrameIdx())); 331 332 // Calculate offsets. 333 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth; 334 for (std::vector<CalleeSavedInfo>::const_iterator 335 I = CSI.begin(), E = CSI.end(); I != E; ++I) { 336 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx()); 337 unsigned Reg = I->getReg(); 338 Offset = MaxOffset - Offset + saveAreaOffset; 339 340 // Don't output a new machine move if we're re-saving the frame 341 // pointer. This happens when the PrologEpilogInserter has inserted an extra 342 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically 343 // generates one when frame pointers are used. If we generate a "machine 344 // move" for this extra "PUSH", the linker will lose track of the fact that 345 // the frame pointer should have the value of the first "PUSH" when it's 346 // trying to unwind. 347 // 348 // FIXME: This looks inelegant. It's possibly correct, but it's covering up 349 // another bug. I.e., one where we generate a prolog like this: 350 // 351 // pushl %ebp 352 // movl %esp, %ebp 353 // pushl %ebp 354 // pushl %esi 355 // ... 356 // 357 // The immediate re-push of EBP is unnecessary. At the least, it's an 358 // optimization bug. EBP can be used as a scratch register in certain 359 // cases, but probably not when we have a frame pointer. 360 if (HasFP && FramePtr == Reg) 361 continue; 362 363 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 364 MachineLocation CSSrc(Reg); 365 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 366 } 367} 368 369/// getCompactUnwindRegNum - Get the compact unwind number for a given 370/// register. The number corresponds to the enum lists in 371/// compact_unwind_encoding.h. 372static int getCompactUnwindRegNum(const uint16_t *CURegs, unsigned Reg) { 373 for (int Idx = 1; *CURegs; ++CURegs, ++Idx) 374 if (*CURegs == Reg) 375 return Idx; 376 377 return -1; 378} 379 380// Number of registers that can be saved in a compact unwind encoding. 381#define CU_NUM_SAVED_REGS 6 382 383/// encodeCompactUnwindRegistersWithoutFrame - Create the permutation encoding 384/// used with frameless stacks. It is passed the number of registers to be saved 385/// and an array of the registers saved. 386static uint32_t 387encodeCompactUnwindRegistersWithoutFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS], 388 unsigned RegCount, bool Is64Bit) { 389 // The saved registers are numbered from 1 to 6. In order to encode the order 390 // in which they were saved, we re-number them according to their place in the 391 // register order. The re-numbering is relative to the last re-numbered 392 // register. E.g., if we have registers {6, 2, 4, 5} saved in that order: 393 // 394 // Orig Re-Num 395 // ---- ------ 396 // 6 6 397 // 2 2 398 // 4 3 399 // 5 3 400 // 401 static const uint16_t CU32BitRegs[] = { 402 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0 403 }; 404 static const uint16_t CU64BitRegs[] = { 405 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 406 }; 407 const uint16_t *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs); 408 409 for (unsigned i = 0; i != CU_NUM_SAVED_REGS; ++i) { 410 int CUReg = getCompactUnwindRegNum(CURegs, SavedRegs[i]); 411 if (CUReg == -1) return ~0U; 412 SavedRegs[i] = CUReg; 413 } 414 415 // Reverse the list. 416 std::swap(SavedRegs[0], SavedRegs[5]); 417 std::swap(SavedRegs[1], SavedRegs[4]); 418 std::swap(SavedRegs[2], SavedRegs[3]); 419 420 uint32_t RenumRegs[CU_NUM_SAVED_REGS]; 421 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i) { 422 unsigned Countless = 0; 423 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j) 424 if (SavedRegs[j] < SavedRegs[i]) 425 ++Countless; 426 427 RenumRegs[i] = SavedRegs[i] - Countless - 1; 428 } 429 430 // Take the renumbered values and encode them into a 10-bit number. 431 uint32_t permutationEncoding = 0; 432 switch (RegCount) { 433 case 6: 434 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1] 435 + 6 * RenumRegs[2] + 2 * RenumRegs[3] 436 + RenumRegs[4]; 437 break; 438 case 5: 439 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2] 440 + 6 * RenumRegs[3] + 2 * RenumRegs[4] 441 + RenumRegs[5]; 442 break; 443 case 4: 444 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3] 445 + 3 * RenumRegs[4] + RenumRegs[5]; 446 break; 447 case 3: 448 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4] 449 + RenumRegs[5]; 450 break; 451 case 2: 452 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5]; 453 break; 454 case 1: 455 permutationEncoding |= RenumRegs[5]; 456 break; 457 } 458 459 assert((permutationEncoding & 0x3FF) == permutationEncoding && 460 "Invalid compact register encoding!"); 461 return permutationEncoding; 462} 463 464/// encodeCompactUnwindRegistersWithFrame - Return the registers encoded for a 465/// compact encoding with a frame pointer. 466static uint32_t 467encodeCompactUnwindRegistersWithFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS], 468 bool Is64Bit) { 469 static const uint16_t CU32BitRegs[] = { 470 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0 471 }; 472 static const uint16_t CU64BitRegs[] = { 473 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 474 }; 475 const uint16_t *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs); 476 477 // Encode the registers in the order they were saved, 3-bits per register. The 478 // registers are numbered from 1 to CU_NUM_SAVED_REGS. 479 uint32_t RegEnc = 0; 480 for (int I = CU_NUM_SAVED_REGS - 1, Idx = 0; I != -1; --I) { 481 unsigned Reg = SavedRegs[I]; 482 if (Reg == 0) continue; 483 484 int CURegNum = getCompactUnwindRegNum(CURegs, Reg); 485 if (CURegNum == -1) return ~0U; 486 487 // Encode the 3-bit register number in order, skipping over 3-bits for each 488 // register. 489 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3); 490 } 491 492 assert((RegEnc & 0x3FFFF) == RegEnc && "Invalid compact register encoding!"); 493 return RegEnc; 494} 495 496uint32_t X86FrameLowering::getCompactUnwindEncoding(MachineFunction &MF) const { 497 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 498 unsigned FramePtr = RegInfo->getFrameRegister(MF); 499 unsigned StackPtr = RegInfo->getStackRegister(); 500 501 bool Is64Bit = STI.is64Bit(); 502 bool HasFP = hasFP(MF); 503 504 unsigned SavedRegs[CU_NUM_SAVED_REGS] = { 0, 0, 0, 0, 0, 0 }; 505 unsigned SavedRegIdx = 0; 506 507 unsigned OffsetSize = (Is64Bit ? 8 : 4); 508 509 unsigned PushInstr = (Is64Bit ? X86::PUSH64r : X86::PUSH32r); 510 unsigned PushInstrSize = 1; 511 unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr); 512 unsigned MoveInstrSize = (Is64Bit ? 3 : 2); 513 unsigned SubtractInstrIdx = (Is64Bit ? 3 : 2); 514 515 unsigned StackDivide = (Is64Bit ? 8 : 4); 516 517 unsigned InstrOffset = 0; 518 unsigned StackAdjust = 0; 519 unsigned StackSize = 0; 520 521 MachineBasicBlock &MBB = MF.front(); // Prologue is in entry BB. 522 bool ExpectEnd = false; 523 for (MachineBasicBlock::iterator 524 MBBI = MBB.begin(), MBBE = MBB.end(); MBBI != MBBE; ++MBBI) { 525 MachineInstr &MI = *MBBI; 526 unsigned Opc = MI.getOpcode(); 527 if (Opc == X86::PROLOG_LABEL) continue; 528 if (!MI.getFlag(MachineInstr::FrameSetup)) break; 529 530 // We don't exect any more prolog instructions. 531 if (ExpectEnd) return 0; 532 533 if (Opc == PushInstr) { 534 // If there are too many saved registers, we cannot use compact encoding. 535 if (SavedRegIdx >= CU_NUM_SAVED_REGS) return 0; 536 537 SavedRegs[SavedRegIdx++] = MI.getOperand(0).getReg(); 538 StackAdjust += OffsetSize; 539 InstrOffset += PushInstrSize; 540 } else if (Opc == MoveInstr) { 541 unsigned SrcReg = MI.getOperand(1).getReg(); 542 unsigned DstReg = MI.getOperand(0).getReg(); 543 544 if (DstReg != FramePtr || SrcReg != StackPtr) 545 return 0; 546 547 StackAdjust = 0; 548 memset(SavedRegs, 0, sizeof(SavedRegs)); 549 SavedRegIdx = 0; 550 InstrOffset += MoveInstrSize; 551 } else if (Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || 552 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) { 553 if (StackSize) 554 // We already have a stack size. 555 return 0; 556 557 if (!MI.getOperand(0).isReg() || 558 MI.getOperand(0).getReg() != MI.getOperand(1).getReg() || 559 MI.getOperand(0).getReg() != StackPtr || !MI.getOperand(2).isImm()) 560 // We need this to be a stack adjustment pointer. Something like: 561 // 562 // %RSP<def> = SUB64ri8 %RSP, 48 563 return 0; 564 565 StackSize = MI.getOperand(2).getImm() / StackDivide; 566 SubtractInstrIdx += InstrOffset; 567 ExpectEnd = true; 568 } 569 } 570 571 // Encode that we are using EBP/RBP as the frame pointer. 572 uint32_t CompactUnwindEncoding = 0; 573 StackAdjust /= StackDivide; 574 if (HasFP) { 575 if ((StackAdjust & 0xFF) != StackAdjust) 576 // Offset was too big for compact encoding. 577 return 0; 578 579 // Get the encoding of the saved registers when we have a frame pointer. 580 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(SavedRegs, Is64Bit); 581 if (RegEnc == ~0U) return 0; 582 583 CompactUnwindEncoding |= 0x01000000; 584 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16; 585 CompactUnwindEncoding |= RegEnc & 0x7FFF; 586 } else { 587 ++StackAdjust; 588 uint32_t TotalStackSize = StackAdjust + StackSize; 589 if ((TotalStackSize & 0xFF) == TotalStackSize) { 590 // Frameless stack with a small stack size. 591 CompactUnwindEncoding |= 0x02000000; 592 593 // Encode the stack size. 594 CompactUnwindEncoding |= (TotalStackSize & 0xFF) << 16; 595 } else { 596 if ((StackAdjust & 0x7) != StackAdjust) 597 // The extra stack adjustments are too big for us to handle. 598 return 0; 599 600 // Frameless stack with an offset too large for us to encode compactly. 601 CompactUnwindEncoding |= 0x03000000; 602 603 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP' 604 // instruction. 605 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16; 606 607 // Encode any extra stack stack adjustments (done via push instructions). 608 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13; 609 } 610 611 // Encode the number of registers saved. 612 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10; 613 614 // Get the encoding of the saved registers when we don't have a frame 615 // pointer. 616 uint32_t RegEnc = 617 encodeCompactUnwindRegistersWithoutFrame(SavedRegs, SavedRegIdx, 618 Is64Bit); 619 if (RegEnc == ~0U) return 0; 620 621 // Encode the register encoding. 622 CompactUnwindEncoding |= RegEnc & 0x3FF; 623 } 624 625 return CompactUnwindEncoding; 626} 627 628/// emitPrologue - Push callee-saved registers onto the stack, which 629/// automatically adjust the stack pointer. Adjust the stack pointer to allocate 630/// space for local variables. Also emit labels used by the exception handler to 631/// generate the exception handling frames. 632void X86FrameLowering::emitPrologue(MachineFunction &MF) const { 633 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB. 634 MachineBasicBlock::iterator MBBI = MBB.begin(); 635 MachineFrameInfo *MFI = MF.getFrameInfo(); 636 const Function *Fn = MF.getFunction(); 637 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 638 const X86InstrInfo &TII = *TM.getInstrInfo(); 639 MachineModuleInfo &MMI = MF.getMMI(); 640 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 641 bool needsFrameMoves = MMI.hasDebugInfo() || 642 Fn->needsUnwindTableEntry(); 643 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment. 644 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate. 645 bool HasFP = hasFP(MF); 646 bool Is64Bit = STI.is64Bit(); 647 bool IsWin64 = STI.isTargetWin64(); 648 bool UseLEA = STI.useLeaForSP(); 649 unsigned StackAlign = getStackAlignment(); 650 unsigned SlotSize = RegInfo->getSlotSize(); 651 unsigned FramePtr = RegInfo->getFrameRegister(MF); 652 unsigned StackPtr = RegInfo->getStackRegister(); 653 unsigned BasePtr = RegInfo->getBaseRegister(); 654 DebugLoc DL; 655 656 // If we're forcing a stack realignment we can't rely on just the frame 657 // info, we need to know the ABI stack alignment as well in case we 658 // have a call out. Otherwise just make sure we have some alignment - we'll 659 // go with the minimum SlotSize. 660 if (ForceStackAlign) { 661 if (MFI->hasCalls()) 662 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign; 663 else if (MaxAlign < SlotSize) 664 MaxAlign = SlotSize; 665 } 666 667 // Add RETADDR move area to callee saved frame size. 668 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); 669 if (TailCallReturnAddrDelta < 0) 670 X86FI->setCalleeSavedFrameSize( 671 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta); 672 673 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf 674 // function, and use up to 128 bytes of stack space, don't have a frame 675 // pointer, calls, or dynamic alloca then we do not need to adjust the 676 // stack pointer (we fit in the Red Zone). 677 if (Is64Bit && !Fn->getFnAttributes().hasNoRedZoneAttr() && 678 !RegInfo->needsStackRealignment(MF) && 679 !MFI->hasVarSizedObjects() && // No dynamic alloca. 680 !MFI->adjustsStack() && // No calls. 681 !IsWin64 && // Win64 has no Red Zone 682 !MF.getTarget().Options.EnableSegmentedStacks) { // Regular stack 683 uint64_t MinSize = X86FI->getCalleeSavedFrameSize(); 684 if (HasFP) MinSize += SlotSize; 685 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0); 686 MFI->setStackSize(StackSize); 687 } 688 689 // Insert stack pointer adjustment for later moving of return addr. Only 690 // applies to tail call optimized functions where the callee argument stack 691 // size is bigger than the callers. 692 if (TailCallReturnAddrDelta < 0) { 693 MachineInstr *MI = 694 BuildMI(MBB, MBBI, DL, 695 TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)), 696 StackPtr) 697 .addReg(StackPtr) 698 .addImm(-TailCallReturnAddrDelta) 699 .setMIFlag(MachineInstr::FrameSetup); 700 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead. 701 } 702 703 // Mapping for machine moves: 704 // 705 // DST: VirtualFP AND 706 // SRC: VirtualFP => DW_CFA_def_cfa_offset 707 // ELSE => DW_CFA_def_cfa 708 // 709 // SRC: VirtualFP AND 710 // DST: Register => DW_CFA_def_cfa_register 711 // 712 // ELSE 713 // OFFSET < 0 => DW_CFA_offset_extended_sf 714 // REG < 64 => DW_CFA_offset + Reg 715 // ELSE => DW_CFA_offset_extended 716 717 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 718 const TargetData *TD = MF.getTarget().getTargetData(); 719 uint64_t NumBytes = 0; 720 int stackGrowth = -TD->getPointerSize(); 721 722 if (HasFP) { 723 // Calculate required stack adjustment. 724 uint64_t FrameSize = StackSize - SlotSize; 725 if (RegInfo->needsStackRealignment(MF)) { 726 // Callee-saved registers are pushed on stack before the stack 727 // is realigned. 728 FrameSize -= X86FI->getCalleeSavedFrameSize(); 729 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign; 730 } else { 731 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize(); 732 } 733 734 // Get the offset of the stack slot for the EBP register, which is 735 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. 736 // Update the frame offset adjustment. 737 MFI->setOffsetAdjustment(-NumBytes); 738 739 // Save EBP/RBP into the appropriate stack slot. 740 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) 741 .addReg(FramePtr, RegState::Kill) 742 .setMIFlag(MachineInstr::FrameSetup); 743 744 if (needsFrameMoves) { 745 // Mark the place where EBP/RBP was saved. 746 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol(); 747 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)) 748 .addSym(FrameLabel); 749 750 // Define the current CFA rule to use the provided offset. 751 if (StackSize) { 752 MachineLocation SPDst(MachineLocation::VirtualFP); 753 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth); 754 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 755 } else { 756 MachineLocation SPDst(StackPtr); 757 MachineLocation SPSrc(StackPtr, stackGrowth); 758 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 759 } 760 761 // Change the rule for the FramePtr to be an "offset" rule. 762 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth); 763 MachineLocation FPSrc(FramePtr); 764 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 765 } 766 767 // Update EBP with the new base value. 768 BuildMI(MBB, MBBI, DL, 769 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) 770 .addReg(StackPtr) 771 .setMIFlag(MachineInstr::FrameSetup); 772 773 if (needsFrameMoves) { 774 // Mark effective beginning of when frame pointer becomes valid. 775 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol(); 776 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)) 777 .addSym(FrameLabel); 778 779 // Define the current CFA to use the EBP/RBP register. 780 MachineLocation FPDst(FramePtr); 781 MachineLocation FPSrc(MachineLocation::VirtualFP); 782 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 783 } 784 785 // Mark the FramePtr as live-in in every block except the entry. 786 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end(); 787 I != E; ++I) 788 I->addLiveIn(FramePtr); 789 } else { 790 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize(); 791 } 792 793 // Skip the callee-saved push instructions. 794 bool PushedRegs = false; 795 int StackOffset = 2 * stackGrowth; 796 797 while (MBBI != MBB.end() && 798 (MBBI->getOpcode() == X86::PUSH32r || 799 MBBI->getOpcode() == X86::PUSH64r)) { 800 PushedRegs = true; 801 MBBI->setFlag(MachineInstr::FrameSetup); 802 ++MBBI; 803 804 if (!HasFP && needsFrameMoves) { 805 // Mark callee-saved push instruction. 806 MCSymbol *Label = MMI.getContext().CreateTempSymbol(); 807 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label); 808 809 // Define the current CFA rule to use the provided offset. 810 unsigned Ptr = StackSize ? MachineLocation::VirtualFP : StackPtr; 811 MachineLocation SPDst(Ptr); 812 MachineLocation SPSrc(Ptr, StackOffset); 813 Moves.push_back(MachineMove(Label, SPDst, SPSrc)); 814 StackOffset += stackGrowth; 815 } 816 } 817 818 // Realign stack after we pushed callee-saved registers (so that we'll be 819 // able to calculate their offsets from the frame pointer). 820 821 // NOTE: We push the registers before realigning the stack, so 822 // vector callee-saved (xmm) registers may be saved w/o proper 823 // alignment in this way. However, currently these regs are saved in 824 // stack slots (see X86FrameLowering::spillCalleeSavedRegisters()), so 825 // this shouldn't be a problem. 826 if (RegInfo->needsStackRealignment(MF)) { 827 assert(HasFP && "There should be a frame pointer if stack is realigned."); 828 MachineInstr *MI = 829 BuildMI(MBB, MBBI, DL, 830 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr) 831 .addReg(StackPtr) 832 .addImm(-MaxAlign) 833 .setMIFlag(MachineInstr::FrameSetup); 834 835 // The EFLAGS implicit def is dead. 836 MI->getOperand(3).setIsDead(); 837 } 838 839 DL = MBB.findDebugLoc(MBBI); 840 841 // If there is an SUB32ri of ESP immediately before this instruction, merge 842 // the two. This can be the case when tail call elimination is enabled and 843 // the callee has more arguments then the caller. 844 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true); 845 846 // If there is an ADD32ri or SUB32ri of ESP immediately after this 847 // instruction, merge the two instructions. 848 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes); 849 850 // Adjust stack pointer: ESP -= numbytes. 851 852 // Windows and cygwin/mingw require a prologue helper routine when allocating 853 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw 854 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the 855 // stack and adjust the stack pointer in one go. The 64-bit version of 856 // __chkstk is only responsible for probing the stack. The 64-bit prologue is 857 // responsible for adjusting the stack pointer. Touching the stack at 4K 858 // increments is necessary to ensure that the guard pages used by the OS 859 // virtual memory manager are allocated in correct sequence. 860 if (NumBytes >= 4096 && STI.isTargetCOFF() && !STI.isTargetEnvMacho()) { 861 const char *StackProbeSymbol; 862 bool isSPUpdateNeeded = false; 863 864 if (Is64Bit) { 865 if (STI.isTargetCygMing()) 866 StackProbeSymbol = "___chkstk"; 867 else { 868 StackProbeSymbol = "__chkstk"; 869 isSPUpdateNeeded = true; 870 } 871 } else if (STI.isTargetCygMing()) 872 StackProbeSymbol = "_alloca"; 873 else 874 StackProbeSymbol = "_chkstk"; 875 876 // Check whether EAX is livein for this function. 877 bool isEAXAlive = isEAXLiveIn(MF); 878 879 if (isEAXAlive) { 880 // Sanity check that EAX is not livein for this function. 881 // It should not be, so throw an assert. 882 assert(!Is64Bit && "EAX is livein in x64 case!"); 883 884 // Save EAX 885 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r)) 886 .addReg(X86::EAX, RegState::Kill) 887 .setMIFlag(MachineInstr::FrameSetup); 888 } 889 890 if (Is64Bit) { 891 // Handle the 64-bit Windows ABI case where we need to call __chkstk. 892 // Function prologue is responsible for adjusting the stack pointer. 893 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX) 894 .addImm(NumBytes) 895 .setMIFlag(MachineInstr::FrameSetup); 896 } else { 897 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive. 898 // We'll also use 4 already allocated bytes for EAX. 899 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX) 900 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes) 901 .setMIFlag(MachineInstr::FrameSetup); 902 } 903 904 BuildMI(MBB, MBBI, DL, 905 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32)) 906 .addExternalSymbol(StackProbeSymbol) 907 .addReg(StackPtr, RegState::Define | RegState::Implicit) 908 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit) 909 .setMIFlag(MachineInstr::FrameSetup); 910 911 // MSVC x64's __chkstk needs to adjust %rsp. 912 // FIXME: %rax preserves the offset and should be available. 913 if (isSPUpdateNeeded) 914 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, 915 UseLEA, TII, *RegInfo); 916 917 if (isEAXAlive) { 918 // Restore EAX 919 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), 920 X86::EAX), 921 StackPtr, false, NumBytes - 4); 922 MI->setFlag(MachineInstr::FrameSetup); 923 MBB.insert(MBBI, MI); 924 } 925 } else if (NumBytes) 926 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, 927 UseLEA, TII, *RegInfo); 928 929 // If we need a base pointer, set it up here. It's whatever the value 930 // of the stack pointer is at this point. Any variable size objects 931 // will be allocated after this, so we can still use the base pointer 932 // to reference locals. 933 if (RegInfo->hasBasePointer(MF)) { 934 // Update the frame pointer with the current stack pointer. 935 unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr; 936 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr) 937 .addReg(StackPtr) 938 .setMIFlag(MachineInstr::FrameSetup); 939 } 940 941 if (( (!HasFP && NumBytes) || PushedRegs) && needsFrameMoves) { 942 // Mark end of stack pointer adjustment. 943 MCSymbol *Label = MMI.getContext().CreateTempSymbol(); 944 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)) 945 .addSym(Label); 946 947 if (!HasFP && NumBytes) { 948 // Define the current CFA rule to use the provided offset. 949 if (StackSize) { 950 MachineLocation SPDst(MachineLocation::VirtualFP); 951 MachineLocation SPSrc(MachineLocation::VirtualFP, 952 -StackSize + stackGrowth); 953 Moves.push_back(MachineMove(Label, SPDst, SPSrc)); 954 } else { 955 MachineLocation SPDst(StackPtr); 956 MachineLocation SPSrc(StackPtr, stackGrowth); 957 Moves.push_back(MachineMove(Label, SPDst, SPSrc)); 958 } 959 } 960 961 // Emit DWARF info specifying the offsets of the callee-saved registers. 962 if (PushedRegs) 963 emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr); 964 } 965 966 // Darwin 10.7 and greater has support for compact unwind encoding. 967 if (STI.getTargetTriple().isMacOSX() && 968 !STI.getTargetTriple().isMacOSXVersionLT(10, 7)) 969 MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF)); 970} 971 972void X86FrameLowering::emitEpilogue(MachineFunction &MF, 973 MachineBasicBlock &MBB) const { 974 const MachineFrameInfo *MFI = MF.getFrameInfo(); 975 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 976 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 977 const X86InstrInfo &TII = *TM.getInstrInfo(); 978 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 979 assert(MBBI != MBB.end() && "Returning block has no instructions"); 980 unsigned RetOpcode = MBBI->getOpcode(); 981 DebugLoc DL = MBBI->getDebugLoc(); 982 bool Is64Bit = STI.is64Bit(); 983 bool UseLEA = STI.useLeaForSP(); 984 unsigned StackAlign = getStackAlignment(); 985 unsigned SlotSize = RegInfo->getSlotSize(); 986 unsigned FramePtr = RegInfo->getFrameRegister(MF); 987 unsigned StackPtr = RegInfo->getStackRegister(); 988 989 switch (RetOpcode) { 990 default: 991 llvm_unreachable("Can only insert epilog into returning blocks"); 992 case X86::RET: 993 case X86::RETI: 994 case X86::TCRETURNdi: 995 case X86::TCRETURNri: 996 case X86::TCRETURNmi: 997 case X86::TCRETURNdi64: 998 case X86::TCRETURNri64: 999 case X86::TCRETURNmi64: 1000 case X86::EH_RETURN: 1001 case X86::EH_RETURN64: 1002 break; // These are ok 1003 } 1004 1005 // Get the number of bytes to allocate from the FrameInfo. 1006 uint64_t StackSize = MFI->getStackSize(); 1007 uint64_t MaxAlign = MFI->getMaxAlignment(); 1008 unsigned CSSize = X86FI->getCalleeSavedFrameSize(); 1009 uint64_t NumBytes = 0; 1010 1011 // If we're forcing a stack realignment we can't rely on just the frame 1012 // info, we need to know the ABI stack alignment as well in case we 1013 // have a call out. Otherwise just make sure we have some alignment - we'll 1014 // go with the minimum. 1015 if (ForceStackAlign) { 1016 if (MFI->hasCalls()) 1017 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign; 1018 else 1019 MaxAlign = MaxAlign ? MaxAlign : 4; 1020 } 1021 1022 if (hasFP(MF)) { 1023 // Calculate required stack adjustment. 1024 uint64_t FrameSize = StackSize - SlotSize; 1025 if (RegInfo->needsStackRealignment(MF)) { 1026 // Callee-saved registers were pushed on stack before the stack 1027 // was realigned. 1028 FrameSize -= CSSize; 1029 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign; 1030 } else { 1031 NumBytes = FrameSize - CSSize; 1032 } 1033 1034 // Pop EBP. 1035 BuildMI(MBB, MBBI, DL, 1036 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr); 1037 } else { 1038 NumBytes = StackSize - CSSize; 1039 } 1040 1041 // Skip the callee-saved pop instructions. 1042 while (MBBI != MBB.begin()) { 1043 MachineBasicBlock::iterator PI = prior(MBBI); 1044 unsigned Opc = PI->getOpcode(); 1045 1046 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE && 1047 !PI->isTerminator()) 1048 break; 1049 1050 --MBBI; 1051 } 1052 MachineBasicBlock::iterator FirstCSPop = MBBI; 1053 1054 DL = MBBI->getDebugLoc(); 1055 1056 // If there is an ADD32ri or SUB32ri of ESP immediately before this 1057 // instruction, merge the two instructions. 1058 if (NumBytes || MFI->hasVarSizedObjects()) 1059 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes); 1060 1061 // If dynamic alloca is used, then reset esp to point to the last callee-saved 1062 // slot before popping them off! Same applies for the case, when stack was 1063 // realigned. 1064 if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) { 1065 if (RegInfo->needsStackRealignment(MF)) 1066 MBBI = FirstCSPop; 1067 if (CSSize != 0) { 1068 unsigned Opc = getLEArOpcode(Is64Bit); 1069 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr), 1070 FramePtr, false, -CSSize); 1071 } else { 1072 unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr); 1073 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) 1074 .addReg(FramePtr); 1075 } 1076 } else if (NumBytes) { 1077 // Adjust stack pointer back: ESP += numbytes. 1078 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, UseLEA, TII, *RegInfo); 1079 } 1080 1081 // We're returning from function via eh_return. 1082 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) { 1083 MBBI = MBB.getLastNonDebugInstr(); 1084 MachineOperand &DestAddr = MBBI->getOperand(0); 1085 assert(DestAddr.isReg() && "Offset should be in register!"); 1086 BuildMI(MBB, MBBI, DL, 1087 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), 1088 StackPtr).addReg(DestAddr.getReg()); 1089 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi || 1090 RetOpcode == X86::TCRETURNmi || 1091 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 || 1092 RetOpcode == X86::TCRETURNmi64) { 1093 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64; 1094 // Tail call return: adjust the stack pointer and jump to callee. 1095 MBBI = MBB.getLastNonDebugInstr(); 1096 MachineOperand &JumpTarget = MBBI->getOperand(0); 1097 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1); 1098 assert(StackAdjust.isImm() && "Expecting immediate value."); 1099 1100 // Adjust stack pointer. 1101 int StackAdj = StackAdjust.getImm(); 1102 int MaxTCDelta = X86FI->getTCReturnAddrDelta(); 1103 int Offset = 0; 1104 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive"); 1105 1106 // Incoporate the retaddr area. 1107 Offset = StackAdj-MaxTCDelta; 1108 assert(Offset >= 0 && "Offset should never be negative"); 1109 1110 if (Offset) { 1111 // Check for possible merge with preceding ADD instruction. 1112 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true); 1113 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, UseLEA, TII, *RegInfo); 1114 } 1115 1116 // Jump to label or value in register. 1117 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) { 1118 MachineInstrBuilder MIB = 1119 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi) 1120 ? X86::TAILJMPd : X86::TAILJMPd64)); 1121 if (JumpTarget.isGlobal()) 1122 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 1123 JumpTarget.getTargetFlags()); 1124 else { 1125 assert(JumpTarget.isSymbol()); 1126 MIB.addExternalSymbol(JumpTarget.getSymbolName(), 1127 JumpTarget.getTargetFlags()); 1128 } 1129 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) { 1130 MachineInstrBuilder MIB = 1131 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi) 1132 ? X86::TAILJMPm : X86::TAILJMPm64)); 1133 for (unsigned i = 0; i != 5; ++i) 1134 MIB.addOperand(MBBI->getOperand(i)); 1135 } else if (RetOpcode == X86::TCRETURNri64) { 1136 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)). 1137 addReg(JumpTarget.getReg(), RegState::Kill); 1138 } else { 1139 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)). 1140 addReg(JumpTarget.getReg(), RegState::Kill); 1141 } 1142 1143 MachineInstr *NewMI = prior(MBBI); 1144 NewMI->copyImplicitOps(MBBI); 1145 1146 // Delete the pseudo instruction TCRETURN. 1147 MBB.erase(MBBI); 1148 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) && 1149 (X86FI->getTCReturnAddrDelta() < 0)) { 1150 // Add the return addr area delta back since we are not tail calling. 1151 int delta = -1*X86FI->getTCReturnAddrDelta(); 1152 MBBI = MBB.getLastNonDebugInstr(); 1153 1154 // Check for possible merge with preceding ADD instruction. 1155 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true); 1156 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, UseLEA, TII, *RegInfo); 1157 } 1158} 1159 1160int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const { 1161 const X86RegisterInfo *RegInfo = 1162 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo()); 1163 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1164 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea(); 1165 uint64_t StackSize = MFI->getStackSize(); 1166 1167 if (RegInfo->hasBasePointer(MF)) { 1168 assert (hasFP(MF) && "VLAs and dynamic stack realign, but no FP?!"); 1169 if (FI < 0) { 1170 // Skip the saved EBP. 1171 return Offset + RegInfo->getSlotSize(); 1172 } else { 1173 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0); 1174 return Offset + StackSize; 1175 } 1176 } else if (RegInfo->needsStackRealignment(MF)) { 1177 if (FI < 0) { 1178 // Skip the saved EBP. 1179 return Offset + RegInfo->getSlotSize(); 1180 } else { 1181 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0); 1182 return Offset + StackSize; 1183 } 1184 // FIXME: Support tail calls 1185 } else { 1186 if (!hasFP(MF)) 1187 return Offset + StackSize; 1188 1189 // Skip the saved EBP. 1190 Offset += RegInfo->getSlotSize(); 1191 1192 // Skip the RETADDR move area 1193 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 1194 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); 1195 if (TailCallReturnAddrDelta < 0) 1196 Offset -= TailCallReturnAddrDelta; 1197 } 1198 1199 return Offset; 1200} 1201 1202int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, 1203 unsigned &FrameReg) const { 1204 const X86RegisterInfo *RegInfo = 1205 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo()); 1206 // We can't calculate offset from frame pointer if the stack is realigned, 1207 // so enforce usage of stack/base pointer. The base pointer is used when we 1208 // have dynamic allocas in addition to dynamic realignment. 1209 if (RegInfo->hasBasePointer(MF)) 1210 FrameReg = RegInfo->getBaseRegister(); 1211 else if (RegInfo->needsStackRealignment(MF)) 1212 FrameReg = RegInfo->getStackRegister(); 1213 else 1214 FrameReg = RegInfo->getFrameRegister(MF); 1215 return getFrameIndexOffset(MF, FI); 1216} 1217 1218bool X86FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1219 MachineBasicBlock::iterator MI, 1220 const std::vector<CalleeSavedInfo> &CSI, 1221 const TargetRegisterInfo *TRI) const { 1222 if (CSI.empty()) 1223 return false; 1224 1225 DebugLoc DL = MBB.findDebugLoc(MI); 1226 1227 MachineFunction &MF = *MBB.getParent(); 1228 1229 unsigned SlotSize = STI.is64Bit() ? 8 : 4; 1230 unsigned FPReg = TRI->getFrameRegister(MF); 1231 unsigned CalleeFrameSize = 0; 1232 1233 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 1234 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 1235 1236 // Push GPRs. It increases frame size. 1237 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r; 1238 for (unsigned i = CSI.size(); i != 0; --i) { 1239 unsigned Reg = CSI[i-1].getReg(); 1240 if (!X86::GR64RegClass.contains(Reg) && 1241 !X86::GR32RegClass.contains(Reg)) 1242 continue; 1243 // Add the callee-saved register as live-in. It's killed at the spill. 1244 MBB.addLiveIn(Reg); 1245 if (Reg == FPReg) 1246 // X86RegisterInfo::emitPrologue will handle spilling of frame register. 1247 continue; 1248 CalleeFrameSize += SlotSize; 1249 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill) 1250 .setMIFlag(MachineInstr::FrameSetup); 1251 } 1252 1253 X86FI->setCalleeSavedFrameSize(CalleeFrameSize); 1254 1255 // Make XMM regs spilled. X86 does not have ability of push/pop XMM. 1256 // It can be done by spilling XMMs to stack frame. 1257 // Note that only Win64 ABI might spill XMMs. 1258 for (unsigned i = CSI.size(); i != 0; --i) { 1259 unsigned Reg = CSI[i-1].getReg(); 1260 if (X86::GR64RegClass.contains(Reg) || 1261 X86::GR32RegClass.contains(Reg)) 1262 continue; 1263 // Add the callee-saved register as live-in. It's killed at the spill. 1264 MBB.addLiveIn(Reg); 1265 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1266 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), 1267 RC, TRI); 1268 } 1269 1270 return true; 1271} 1272 1273bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1274 MachineBasicBlock::iterator MI, 1275 const std::vector<CalleeSavedInfo> &CSI, 1276 const TargetRegisterInfo *TRI) const { 1277 if (CSI.empty()) 1278 return false; 1279 1280 DebugLoc DL = MBB.findDebugLoc(MI); 1281 1282 MachineFunction &MF = *MBB.getParent(); 1283 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 1284 1285 // Reload XMMs from stack frame. 1286 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1287 unsigned Reg = CSI[i].getReg(); 1288 if (X86::GR64RegClass.contains(Reg) || 1289 X86::GR32RegClass.contains(Reg)) 1290 continue; 1291 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1292 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), 1293 RC, TRI); 1294 } 1295 1296 // POP GPRs. 1297 unsigned FPReg = TRI->getFrameRegister(MF); 1298 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r; 1299 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1300 unsigned Reg = CSI[i].getReg(); 1301 if (!X86::GR64RegClass.contains(Reg) && 1302 !X86::GR32RegClass.contains(Reg)) 1303 continue; 1304 if (Reg == FPReg) 1305 // X86RegisterInfo::emitEpilogue will handle restoring of frame register. 1306 continue; 1307 BuildMI(MBB, MI, DL, TII.get(Opc), Reg); 1308 } 1309 return true; 1310} 1311 1312void 1313X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 1314 RegScavenger *RS) const { 1315 MachineFrameInfo *MFI = MF.getFrameInfo(); 1316 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 1317 unsigned SlotSize = RegInfo->getSlotSize(); 1318 1319 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 1320 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); 1321 1322 if (TailCallReturnAddrDelta < 0) { 1323 // create RETURNADDR area 1324 // arg 1325 // arg 1326 // RETADDR 1327 // { ... 1328 // RETADDR area 1329 // ... 1330 // } 1331 // [EBP] 1332 MFI->CreateFixedObject(-TailCallReturnAddrDelta, 1333 (-1U*SlotSize)+TailCallReturnAddrDelta, true); 1334 } 1335 1336 if (hasFP(MF)) { 1337 assert((TailCallReturnAddrDelta <= 0) && 1338 "The Delta should always be zero or negative"); 1339 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering(); 1340 1341 // Create a frame entry for the EBP register that must be saved. 1342 int FrameIdx = MFI->CreateFixedObject(SlotSize, 1343 -(int)SlotSize + 1344 TFI.getOffsetOfLocalArea() + 1345 TailCallReturnAddrDelta, 1346 true); 1347 assert(FrameIdx == MFI->getObjectIndexBegin() && 1348 "Slot for EBP register must be last in order to be found!"); 1349 (void)FrameIdx; 1350 } 1351 1352 // Spill the BasePtr if it's used. 1353 if (RegInfo->hasBasePointer(MF)) 1354 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister()); 1355} 1356 1357static bool 1358HasNestArgument(const MachineFunction *MF) { 1359 const Function *F = MF->getFunction(); 1360 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 1361 I != E; I++) { 1362 if (I->hasNestAttr()) 1363 return true; 1364 } 1365 return false; 1366} 1367 1368 1369/// GetScratchRegister - Get a register for performing work in the segmented 1370/// stack prologue. Depending on platform and the properties of the function 1371/// either one or two registers will be needed. Set primary to true for 1372/// the first register, false for the second. 1373static unsigned 1374GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) { 1375 if (Is64Bit) 1376 return Primary ? X86::R11 : X86::R12; 1377 1378 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv(); 1379 bool IsNested = HasNestArgument(&MF); 1380 1381 if (CallingConvention == CallingConv::X86_FastCall || 1382 CallingConvention == CallingConv::Fast) { 1383 if (IsNested) 1384 report_fatal_error("Segmented stacks does not support fastcall with " 1385 "nested function."); 1386 return Primary ? X86::EAX : X86::ECX; 1387 } 1388 if (IsNested) 1389 return Primary ? X86::EDX : X86::EAX; 1390 return Primary ? X86::ECX : X86::EAX; 1391} 1392 1393// The stack limit in the TCB is set to this many bytes above the actual stack 1394// limit. 1395static const uint64_t kSplitStackAvailable = 256; 1396 1397void 1398X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const { 1399 MachineBasicBlock &prologueMBB = MF.front(); 1400 MachineFrameInfo *MFI = MF.getFrameInfo(); 1401 const X86InstrInfo &TII = *TM.getInstrInfo(); 1402 uint64_t StackSize; 1403 bool Is64Bit = STI.is64Bit(); 1404 unsigned TlsReg, TlsOffset; 1405 DebugLoc DL; 1406 const X86Subtarget *ST = &MF.getTarget().getSubtarget<X86Subtarget>(); 1407 1408 unsigned ScratchReg = GetScratchRegister(Is64Bit, MF, true); 1409 assert(!MF.getRegInfo().isLiveIn(ScratchReg) && 1410 "Scratch register is live-in"); 1411 1412 if (MF.getFunction()->isVarArg()) 1413 report_fatal_error("Segmented stacks do not support vararg functions."); 1414 if (!ST->isTargetLinux() && !ST->isTargetDarwin() && 1415 !ST->isTargetWin32() && !ST->isTargetFreeBSD()) 1416 report_fatal_error("Segmented stacks not supported on this platform."); 1417 1418 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock(); 1419 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock(); 1420 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 1421 bool IsNested = false; 1422 1423 // We need to know if the function has a nest argument only in 64 bit mode. 1424 if (Is64Bit) 1425 IsNested = HasNestArgument(&MF); 1426 1427 // The MOV R10, RAX needs to be in a different block, since the RET we emit in 1428 // allocMBB needs to be last (terminating) instruction. 1429 1430 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(), 1431 e = prologueMBB.livein_end(); i != e; i++) { 1432 allocMBB->addLiveIn(*i); 1433 checkMBB->addLiveIn(*i); 1434 } 1435 1436 if (IsNested) 1437 allocMBB->addLiveIn(X86::R10); 1438 1439 MF.push_front(allocMBB); 1440 MF.push_front(checkMBB); 1441 1442 // Eventually StackSize will be calculated by a link-time pass; which will 1443 // also decide whether checking code needs to be injected into this particular 1444 // prologue. 1445 StackSize = MFI->getStackSize(); 1446 1447 // When the frame size is less than 256 we just compare the stack 1448 // boundary directly to the value of the stack pointer, per gcc. 1449 bool CompareStackPointer = StackSize < kSplitStackAvailable; 1450 1451 // Read the limit off the current stacklet off the stack_guard location. 1452 if (Is64Bit) { 1453 if (ST->isTargetLinux()) { 1454 TlsReg = X86::FS; 1455 TlsOffset = 0x70; 1456 } else if (ST->isTargetDarwin()) { 1457 TlsReg = X86::GS; 1458 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90. 1459 } else if (ST->isTargetFreeBSD()) { 1460 TlsReg = X86::FS; 1461 TlsOffset = 0x18; 1462 } else { 1463 report_fatal_error("Segmented stacks not supported on this platform."); 1464 } 1465 1466 if (CompareStackPointer) 1467 ScratchReg = X86::RSP; 1468 else 1469 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP) 1470 .addImm(1).addReg(0).addImm(-StackSize).addReg(0); 1471 1472 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg) 1473 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg); 1474 } else { 1475 if (ST->isTargetLinux()) { 1476 TlsReg = X86::GS; 1477 TlsOffset = 0x30; 1478 } else if (ST->isTargetDarwin()) { 1479 TlsReg = X86::GS; 1480 TlsOffset = 0x48 + 90*4; 1481 } else if (ST->isTargetWin32()) { 1482 TlsReg = X86::FS; 1483 TlsOffset = 0x14; // pvArbitrary, reserved for application use 1484 } else if (ST->isTargetFreeBSD()) { 1485 report_fatal_error("Segmented stacks not supported on FreeBSD i386."); 1486 } else { 1487 report_fatal_error("Segmented stacks not supported on this platform."); 1488 } 1489 1490 if (CompareStackPointer) 1491 ScratchReg = X86::ESP; 1492 else 1493 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP) 1494 .addImm(1).addReg(0).addImm(-StackSize).addReg(0); 1495 1496 if (ST->isTargetLinux() || ST->isTargetWin32()) { 1497 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg) 1498 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg); 1499 } else if (ST->isTargetDarwin()) { 1500 1501 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register 1502 unsigned ScratchReg2; 1503 bool SaveScratch2; 1504 if (CompareStackPointer) { 1505 // The primary scratch register is available for holding the TLS offset 1506 ScratchReg2 = GetScratchRegister(Is64Bit, MF, true); 1507 SaveScratch2 = false; 1508 } else { 1509 // Need to use a second register to hold the TLS offset 1510 ScratchReg2 = GetScratchRegister(Is64Bit, MF, false); 1511 1512 // Unfortunately, with fastcc the second scratch register may hold an arg 1513 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2); 1514 } 1515 1516 // If Scratch2 is live-in then it needs to be saved 1517 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) && 1518 "Scratch register is live-in and not saved"); 1519 1520 if (SaveScratch2) 1521 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r)) 1522 .addReg(ScratchReg2, RegState::Kill); 1523 1524 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2) 1525 .addImm(TlsOffset); 1526 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)) 1527 .addReg(ScratchReg) 1528 .addReg(ScratchReg2).addImm(1).addReg(0) 1529 .addImm(0) 1530 .addReg(TlsReg); 1531 1532 if (SaveScratch2) 1533 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2); 1534 } 1535 } 1536 1537 // This jump is taken if SP >= (Stacklet Limit + Stack Space required). 1538 // It jumps to normal execution of the function body. 1539 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB); 1540 1541 // On 32 bit we first push the arguments size and then the frame size. On 64 1542 // bit, we pass the stack frame size in r10 and the argument size in r11. 1543 if (Is64Bit) { 1544 // Functions with nested arguments use R10, so it needs to be saved across 1545 // the call to _morestack 1546 1547 if (IsNested) 1548 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10); 1549 1550 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10) 1551 .addImm(StackSize); 1552 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11) 1553 .addImm(X86FI->getArgumentStackSize()); 1554 MF.getRegInfo().setPhysRegUsed(X86::R10); 1555 MF.getRegInfo().setPhysRegUsed(X86::R11); 1556 } else { 1557 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32)) 1558 .addImm(X86FI->getArgumentStackSize()); 1559 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32)) 1560 .addImm(StackSize); 1561 } 1562 1563 // __morestack is in libgcc 1564 if (Is64Bit) 1565 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32)) 1566 .addExternalSymbol("__morestack"); 1567 else 1568 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32)) 1569 .addExternalSymbol("__morestack"); 1570 1571 if (IsNested) 1572 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10)); 1573 else 1574 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET)); 1575 1576 allocMBB->addSuccessor(&prologueMBB); 1577 1578 checkMBB->addSuccessor(allocMBB); 1579 checkMBB->addSuccessor(&prologueMBB); 1580 1581#ifdef XDEBUG 1582 MF.verify(); 1583#endif 1584} 1585