1//===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file provides X86 specific target descriptions. 11// 12//===----------------------------------------------------------------------===// 13 14#include "X86MCTargetDesc.h" 15#include "X86MCAsmInfo.h" 16#include "InstPrinter/X86ATTInstPrinter.h" 17#include "InstPrinter/X86IntelInstPrinter.h" 18#include "llvm/MC/MachineLocation.h" 19#include "llvm/MC/MCCodeGenInfo.h" 20#include "llvm/MC/MCInstrAnalysis.h" 21#include "llvm/MC/MCInstrInfo.h" 22#include "llvm/MC/MCRegisterInfo.h" 23#include "llvm/MC/MCStreamer.h" 24#include "llvm/MC/MCSubtargetInfo.h" 25#include "llvm/ADT/Triple.h" 26#include "llvm/Support/Host.h" 27#include "llvm/Support/ErrorHandling.h" 28#include "llvm/Support/TargetRegistry.h" 29 30#define GET_REGINFO_MC_DESC 31#include "X86GenRegisterInfo.inc" 32 33#define GET_INSTRINFO_MC_DESC 34#include "X86GenInstrInfo.inc" 35 36#define GET_SUBTARGETINFO_MC_DESC 37#include "X86GenSubtargetInfo.inc" 38 39#if _MSC_VER 40#include <intrin.h> 41#endif 42 43using namespace llvm; 44 45 46std::string X86_MC::ParseX86Triple(StringRef TT) { 47 Triple TheTriple(TT); 48 std::string FS; 49 if (TheTriple.getArch() == Triple::x86_64) 50 FS = "+64bit-mode"; 51 else 52 FS = "-64bit-mode"; 53 return FS; 54} 55 56/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the 57/// specified arguments. If we can't run cpuid on the host, return true. 58bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, 59 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) { 60#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) 61 #if defined(__GNUC__) 62 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. 63 asm ("movq\t%%rbx, %%rsi\n\t" 64 "cpuid\n\t" 65 "xchgq\t%%rbx, %%rsi\n\t" 66 : "=a" (*rEAX), 67 "=S" (*rEBX), 68 "=c" (*rECX), 69 "=d" (*rEDX) 70 : "a" (value)); 71 return false; 72 #elif defined(_MSC_VER) 73 int registers[4]; 74 __cpuid(registers, value); 75 *rEAX = registers[0]; 76 *rEBX = registers[1]; 77 *rECX = registers[2]; 78 *rEDX = registers[3]; 79 return false; 80 #else 81 return true; 82 #endif 83#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) 84 #if defined(__GNUC__) 85 asm ("movl\t%%ebx, %%esi\n\t" 86 "cpuid\n\t" 87 "xchgl\t%%ebx, %%esi\n\t" 88 : "=a" (*rEAX), 89 "=S" (*rEBX), 90 "=c" (*rECX), 91 "=d" (*rEDX) 92 : "a" (value)); 93 return false; 94 #elif defined(_MSC_VER) 95 __asm { 96 mov eax,value 97 cpuid 98 mov esi,rEAX 99 mov dword ptr [esi],eax 100 mov esi,rEBX 101 mov dword ptr [esi],ebx 102 mov esi,rECX 103 mov dword ptr [esi],ecx 104 mov esi,rEDX 105 mov dword ptr [esi],edx 106 } 107 return false; 108 #else 109 return true; 110 #endif 111#else 112 return true; 113#endif 114} 115 116/// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the 117/// 4 values in the specified arguments. If we can't run cpuid on the host, 118/// return true. 119bool X86_MC::GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX, 120 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) { 121#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) 122 #if defined(__GNUC__) 123 // gcc desn't know cpuid would clobber ebx/rbx. Preseve it manually. 124 asm ("movq\t%%rbx, %%rsi\n\t" 125 "cpuid\n\t" 126 "xchgq\t%%rbx, %%rsi\n\t" 127 : "=a" (*rEAX), 128 "=S" (*rEBX), 129 "=c" (*rECX), 130 "=d" (*rEDX) 131 : "a" (value), 132 "c" (subleaf)); 133 return false; 134 #elif defined(_MSC_VER) 135 // __cpuidex was added in MSVC++ 9.0 SP1 136 #if (_MSC_VER > 1500) || (_MSC_VER == 1500 && _MSC_FULL_VER >= 150030729) 137 int registers[4]; 138 __cpuidex(registers, value, subleaf); 139 *rEAX = registers[0]; 140 *rEBX = registers[1]; 141 *rECX = registers[2]; 142 *rEDX = registers[3]; 143 return false; 144 #else 145 return true; 146 #endif 147 #else 148 return true; 149 #endif 150#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) 151 #if defined(__GNUC__) 152 asm ("movl\t%%ebx, %%esi\n\t" 153 "cpuid\n\t" 154 "xchgl\t%%ebx, %%esi\n\t" 155 : "=a" (*rEAX), 156 "=S" (*rEBX), 157 "=c" (*rECX), 158 "=d" (*rEDX) 159 : "a" (value), 160 "c" (subleaf)); 161 return false; 162 #elif defined(_MSC_VER) 163 __asm { 164 mov eax,value 165 mov ecx,subleaf 166 cpuid 167 mov esi,rEAX 168 mov dword ptr [esi],eax 169 mov esi,rEBX 170 mov dword ptr [esi],ebx 171 mov esi,rECX 172 mov dword ptr [esi],ecx 173 mov esi,rEDX 174 mov dword ptr [esi],edx 175 } 176 return false; 177 #else 178 return true; 179 #endif 180#else 181 return true; 182#endif 183} 184 185void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family, 186 unsigned &Model) { 187 Family = (EAX >> 8) & 0xf; // Bits 8 - 11 188 Model = (EAX >> 4) & 0xf; // Bits 4 - 7 189 if (Family == 6 || Family == 0xf) { 190 if (Family == 0xf) 191 // Examine extended family ID if family ID is F. 192 Family += (EAX >> 20) & 0xff; // Bits 20 - 27 193 // Examine extended model ID if family ID is 6 or F. 194 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 195 } 196} 197 198unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) { 199 Triple TheTriple(TT); 200 if (TheTriple.getArch() == Triple::x86_64) 201 return DWARFFlavour::X86_64; 202 203 if (TheTriple.isOSDarwin()) 204 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic; 205 if (TheTriple.getOS() == Triple::MinGW32 || 206 TheTriple.getOS() == Triple::Cygwin) 207 // Unsupported by now, just quick fallback 208 return DWARFFlavour::X86_32_Generic; 209 return DWARFFlavour::X86_32_Generic; 210} 211 212/// getX86RegNum - This function maps LLVM register identifiers to their X86 213/// specific numbering, which is used in various places encoding instructions. 214unsigned X86_MC::getX86RegNum(unsigned RegNo) { 215 switch(RegNo) { 216 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX; 217 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX; 218 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX; 219 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX; 220 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH: 221 return N86::ESP; 222 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH: 223 return N86::EBP; 224 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH: 225 return N86::ESI; 226 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH: 227 return N86::EDI; 228 229 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: 230 return N86::EAX; 231 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: 232 return N86::ECX; 233 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: 234 return N86::EDX; 235 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B: 236 return N86::EBX; 237 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B: 238 return N86::ESP; 239 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: 240 return N86::EBP; 241 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: 242 return N86::ESI; 243 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: 244 return N86::EDI; 245 246 case X86::ST0: return 0; 247 case X86::ST1: return 1; 248 case X86::ST2: return 2; 249 case X86::ST3: return 3; 250 case X86::ST4: return 4; 251 case X86::ST5: return 5; 252 case X86::ST6: return 6; 253 case X86::ST7: return 7; 254 255 case X86::XMM0: case X86::XMM8: 256 case X86::YMM0: case X86::YMM8: case X86::MM0: 257 return 0; 258 case X86::XMM1: case X86::XMM9: 259 case X86::YMM1: case X86::YMM9: case X86::MM1: 260 return 1; 261 case X86::XMM2: case X86::XMM10: 262 case X86::YMM2: case X86::YMM10: case X86::MM2: 263 return 2; 264 case X86::XMM3: case X86::XMM11: 265 case X86::YMM3: case X86::YMM11: case X86::MM3: 266 return 3; 267 case X86::XMM4: case X86::XMM12: 268 case X86::YMM4: case X86::YMM12: case X86::MM4: 269 return 4; 270 case X86::XMM5: case X86::XMM13: 271 case X86::YMM5: case X86::YMM13: case X86::MM5: 272 return 5; 273 case X86::XMM6: case X86::XMM14: 274 case X86::YMM6: case X86::YMM14: case X86::MM6: 275 return 6; 276 case X86::XMM7: case X86::XMM15: 277 case X86::YMM7: case X86::YMM15: case X86::MM7: 278 return 7; 279 280 case X86::ES: return 0; 281 case X86::CS: return 1; 282 case X86::SS: return 2; 283 case X86::DS: return 3; 284 case X86::FS: return 4; 285 case X86::GS: return 5; 286 287 case X86::CR0: case X86::CR8 : case X86::DR0: return 0; 288 case X86::CR1: case X86::CR9 : case X86::DR1: return 1; 289 case X86::CR2: case X86::CR10: case X86::DR2: return 2; 290 case X86::CR3: case X86::CR11: case X86::DR3: return 3; 291 case X86::CR4: case X86::CR12: case X86::DR4: return 4; 292 case X86::CR5: case X86::CR13: case X86::DR5: return 5; 293 case X86::CR6: case X86::CR14: case X86::DR6: return 6; 294 case X86::CR7: case X86::CR15: case X86::DR7: return 7; 295 296 // Pseudo index registers are equivalent to a "none" 297 // scaled index (See Intel Manual 2A, table 2-3) 298 case X86::EIZ: 299 case X86::RIZ: 300 return 4; 301 302 default: 303 assert((int(RegNo) > 0) && "Unknown physical register!"); 304 return 0; 305 } 306} 307 308void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) { 309 // FIXME: TableGen these. 310 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) { 311 int SEH = X86_MC::getX86RegNum(Reg); 312 switch (Reg) { 313 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: 314 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: 315 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: 316 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B: 317 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B: 318 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: 319 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: 320 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: 321 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: 322 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: 323 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11: 324 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15: 325 SEH += 8; 326 break; 327 } 328 MRI->mapLLVMRegToSEHReg(Reg, SEH); 329 } 330} 331 332MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU, 333 StringRef FS) { 334 std::string ArchFS = X86_MC::ParseX86Triple(TT); 335 if (!FS.empty()) { 336 if (!ArchFS.empty()) 337 ArchFS = ArchFS + "," + FS.str(); 338 else 339 ArchFS = FS; 340 } 341 342 std::string CPUName = CPU; 343 if (CPUName.empty()) { 344#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\ 345 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) 346 CPUName = sys::getHostCPUName(); 347#else 348 CPUName = "generic"; 349#endif 350 } 351 352 MCSubtargetInfo *X = new MCSubtargetInfo(); 353 InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS); 354 return X; 355} 356 357static MCInstrInfo *createX86MCInstrInfo() { 358 MCInstrInfo *X = new MCInstrInfo(); 359 InitX86MCInstrInfo(X); 360 return X; 361} 362 363static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) { 364 Triple TheTriple(TT); 365 unsigned RA = (TheTriple.getArch() == Triple::x86_64) 366 ? X86::RIP // Should have dwarf #16. 367 : X86::EIP; // Should have dwarf #8. 368 369 MCRegisterInfo *X = new MCRegisterInfo(); 370 InitX86MCRegisterInfo(X, RA, 371 X86_MC::getDwarfRegFlavour(TT, false), 372 X86_MC::getDwarfRegFlavour(TT, true)); 373 X86_MC::InitLLVM2SEHRegisterMapping(X); 374 return X; 375} 376 377static MCAsmInfo *createX86MCAsmInfo(const Target &T, StringRef TT) { 378 Triple TheTriple(TT); 379 bool is64Bit = TheTriple.getArch() == Triple::x86_64; 380 381 MCAsmInfo *MAI; 382 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) { 383 if (is64Bit) 384 MAI = new X86_64MCAsmInfoDarwin(TheTriple); 385 else 386 MAI = new X86MCAsmInfoDarwin(TheTriple); 387 } else if (TheTriple.getOS() == Triple::Win32) { 388 MAI = new X86MCAsmInfoMicrosoft(TheTriple); 389 } else if (TheTriple.getOS() == Triple::MinGW32 || TheTriple.getOS() == Triple::Cygwin) { 390 MAI = new X86MCAsmInfoGNUCOFF(TheTriple); 391 } else { 392 MAI = new X86ELFMCAsmInfo(TheTriple); 393 } 394 395 // Initialize initial frame state. 396 // Calculate amount of bytes used for return address storing 397 int stackGrowth = is64Bit ? -8 : -4; 398 399 // Initial state of the frame pointer is esp+stackGrowth. 400 MachineLocation Dst(MachineLocation::VirtualFP); 401 MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth); 402 MAI->addInitialFrameState(0, Dst, Src); 403 404 // Add return address to move list 405 MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth); 406 MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP); 407 MAI->addInitialFrameState(0, CSDst, CSSrc); 408 409 return MAI; 410} 411 412static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM, 413 CodeModel::Model CM, 414 CodeGenOpt::Level OL) { 415 MCCodeGenInfo *X = new MCCodeGenInfo(); 416 417 Triple T(TT); 418 bool is64Bit = T.getArch() == Triple::x86_64; 419 420 if (RM == Reloc::Default) { 421 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode. 422 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we 423 // use static relocation model by default. 424 if (T.isOSDarwin()) { 425 if (is64Bit) 426 RM = Reloc::PIC_; 427 else 428 RM = Reloc::DynamicNoPIC; 429 } else if (T.isOSWindows() && is64Bit) 430 RM = Reloc::PIC_; 431 else 432 RM = Reloc::Static; 433 } 434 435 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC 436 // is defined as a model for code which may be used in static or dynamic 437 // executables but not necessarily a shared library. On X86-32 we just 438 // compile in -static mode, in x86-64 we use PIC. 439 if (RM == Reloc::DynamicNoPIC) { 440 if (is64Bit) 441 RM = Reloc::PIC_; 442 else if (!T.isOSDarwin()) 443 RM = Reloc::Static; 444 } 445 446 // If we are on Darwin, disallow static relocation model in X86-64 mode, since 447 // the Mach-O file format doesn't support it. 448 if (RM == Reloc::Static && T.isOSDarwin() && is64Bit) 449 RM = Reloc::PIC_; 450 451 // For static codegen, if we're not already set, use Small codegen. 452 if (CM == CodeModel::Default) 453 CM = CodeModel::Small; 454 else if (CM == CodeModel::JITDefault) 455 // 64-bit JIT places everything in the same buffer except external funcs. 456 CM = is64Bit ? CodeModel::Large : CodeModel::Small; 457 458 X->InitMCCodeGenInfo(RM, CM, OL); 459 return X; 460} 461 462static MCStreamer *createMCStreamer(const Target &T, StringRef TT, 463 MCContext &Ctx, MCAsmBackend &MAB, 464 raw_ostream &_OS, 465 MCCodeEmitter *_Emitter, 466 bool RelaxAll, 467 bool NoExecStack) { 468 Triple TheTriple(TT); 469 470 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) 471 return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll); 472 473 if (TheTriple.isOSWindows()) 474 return createWinCOFFStreamer(Ctx, MAB, *_Emitter, _OS, RelaxAll); 475 476 return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack); 477} 478 479static MCInstPrinter *createX86MCInstPrinter(const Target &T, 480 unsigned SyntaxVariant, 481 const MCAsmInfo &MAI, 482 const MCInstrInfo &MII, 483 const MCRegisterInfo &MRI, 484 const MCSubtargetInfo &STI) { 485 if (SyntaxVariant == 0) 486 return new X86ATTInstPrinter(MAI, MII, MRI); 487 if (SyntaxVariant == 1) 488 return new X86IntelInstPrinter(MAI, MII, MRI); 489 return 0; 490} 491 492static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) { 493 return new MCInstrAnalysis(Info); 494} 495 496// Force static initialization. 497extern "C" void LLVMInitializeX86TargetMC() { 498 // Register the MC asm info. 499 RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo); 500 RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo); 501 502 // Register the MC codegen info. 503 RegisterMCCodeGenInfoFn C(TheX86_32Target, createX86MCCodeGenInfo); 504 RegisterMCCodeGenInfoFn D(TheX86_64Target, createX86MCCodeGenInfo); 505 506 // Register the MC instruction info. 507 TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo); 508 TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo); 509 510 // Register the MC register info. 511 TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo); 512 TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo); 513 514 // Register the MC subtarget info. 515 TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target, 516 X86_MC::createX86MCSubtargetInfo); 517 TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target, 518 X86_MC::createX86MCSubtargetInfo); 519 520 // Register the MC instruction analyzer. 521 TargetRegistry::RegisterMCInstrAnalysis(TheX86_32Target, 522 createX86MCInstrAnalysis); 523 TargetRegistry::RegisterMCInstrAnalysis(TheX86_64Target, 524 createX86MCInstrAnalysis); 525 526 // Register the code emitter. 527 TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target, 528 createX86MCCodeEmitter); 529 TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target, 530 createX86MCCodeEmitter); 531 532 // Register the asm backend. 533 TargetRegistry::RegisterMCAsmBackend(TheX86_32Target, 534 createX86_32AsmBackend); 535 TargetRegistry::RegisterMCAsmBackend(TheX86_64Target, 536 createX86_64AsmBackend); 537 538 // Register the object streamer. 539 TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target, 540 createMCStreamer); 541 TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target, 542 createMCStreamer); 543 544 // Register the MCInstPrinter. 545 TargetRegistry::RegisterMCInstPrinter(TheX86_32Target, 546 createX86MCInstPrinter); 547 TargetRegistry::RegisterMCInstPrinter(TheX86_64Target, 548 createX86MCInstPrinter); 549} 550