1//===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Pass to verify generated machine code. The following is checked: 11// 12// Operand counts: All explicit operands must be present. 13// 14// Register classes: All physical and virtual register operands must be 15// compatible with the register class required by the instruction descriptor. 16// 17// Register live intervals: Registers must be defined only once, and must be 18// defined before use. 19// 20// The machine code verifier is enabled from LLVMTargetMachine.cpp with the 21// command-line option -verify-machineinstrs, or by defining the environment 22// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive 23// the verifier errors. 24//===----------------------------------------------------------------------===// 25 26#include "llvm/BasicBlock.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/CodeGen/LiveIntervalAnalysis.h" 30#include "llvm/CodeGen/LiveVariables.h" 31#include "llvm/CodeGen/LiveStackAnalysis.h" 32#include "llvm/CodeGen/MachineInstrBundle.h" 33#include "llvm/CodeGen/MachineFunctionPass.h" 34#include "llvm/CodeGen/MachineFrameInfo.h" 35#include "llvm/CodeGen/MachineMemOperand.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/Passes.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/Target/TargetMachine.h" 40#include "llvm/Target/TargetRegisterInfo.h" 41#include "llvm/Target/TargetInstrInfo.h" 42#include "llvm/ADT/DenseSet.h" 43#include "llvm/ADT/SetOperations.h" 44#include "llvm/ADT/SmallVector.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/ErrorHandling.h" 47#include "llvm/Support/raw_ostream.h" 48using namespace llvm; 49 50namespace { 51 struct MachineVerifier { 52 53 MachineVerifier(Pass *pass, const char *b) : 54 PASS(pass), 55 Banner(b), 56 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS")) 57 {} 58 59 bool runOnMachineFunction(MachineFunction &MF); 60 61 Pass *const PASS; 62 const char *Banner; 63 const char *const OutFileName; 64 raw_ostream *OS; 65 const MachineFunction *MF; 66 const TargetMachine *TM; 67 const TargetInstrInfo *TII; 68 const TargetRegisterInfo *TRI; 69 const MachineRegisterInfo *MRI; 70 71 unsigned foundErrors; 72 73 typedef SmallVector<unsigned, 16> RegVector; 74 typedef SmallVector<const uint32_t*, 4> RegMaskVector; 75 typedef DenseSet<unsigned> RegSet; 76 typedef DenseMap<unsigned, const MachineInstr*> RegMap; 77 typedef SmallPtrSet<const MachineBasicBlock*, 8> BlockSet; 78 79 const MachineInstr *FirstTerminator; 80 BlockSet FunctionBlocks; 81 82 BitVector regsReserved; 83 BitVector regsAllocatable; 84 RegSet regsLive; 85 RegVector regsDefined, regsDead, regsKilled; 86 RegMaskVector regMasks; 87 RegSet regsLiveInButUnused; 88 89 SlotIndex lastIndex; 90 91 // Add Reg and any sub-registers to RV 92 void addRegWithSubRegs(RegVector &RV, unsigned Reg) { 93 RV.push_back(Reg); 94 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 95 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) 96 RV.push_back(*SubRegs); 97 } 98 99 struct BBInfo { 100 // Is this MBB reachable from the MF entry point? 101 bool reachable; 102 103 // Vregs that must be live in because they are used without being 104 // defined. Map value is the user. 105 RegMap vregsLiveIn; 106 107 // Regs killed in MBB. They may be defined again, and will then be in both 108 // regsKilled and regsLiveOut. 109 RegSet regsKilled; 110 111 // Regs defined in MBB and live out. Note that vregs passing through may 112 // be live out without being mentioned here. 113 RegSet regsLiveOut; 114 115 // Vregs that pass through MBB untouched. This set is disjoint from 116 // regsKilled and regsLiveOut. 117 RegSet vregsPassed; 118 119 // Vregs that must pass through MBB because they are needed by a successor 120 // block. This set is disjoint from regsLiveOut. 121 RegSet vregsRequired; 122 123 // Set versions of block's predecessor and successor lists. 124 BlockSet Preds, Succs; 125 126 BBInfo() : reachable(false) {} 127 128 // Add register to vregsPassed if it belongs there. Return true if 129 // anything changed. 130 bool addPassed(unsigned Reg) { 131 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 132 return false; 133 if (regsKilled.count(Reg) || regsLiveOut.count(Reg)) 134 return false; 135 return vregsPassed.insert(Reg).second; 136 } 137 138 // Same for a full set. 139 bool addPassed(const RegSet &RS) { 140 bool changed = false; 141 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I) 142 if (addPassed(*I)) 143 changed = true; 144 return changed; 145 } 146 147 // Add register to vregsRequired if it belongs there. Return true if 148 // anything changed. 149 bool addRequired(unsigned Reg) { 150 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 151 return false; 152 if (regsLiveOut.count(Reg)) 153 return false; 154 return vregsRequired.insert(Reg).second; 155 } 156 157 // Same for a full set. 158 bool addRequired(const RegSet &RS) { 159 bool changed = false; 160 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I) 161 if (addRequired(*I)) 162 changed = true; 163 return changed; 164 } 165 166 // Same for a full map. 167 bool addRequired(const RegMap &RM) { 168 bool changed = false; 169 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I) 170 if (addRequired(I->first)) 171 changed = true; 172 return changed; 173 } 174 175 // Live-out registers are either in regsLiveOut or vregsPassed. 176 bool isLiveOut(unsigned Reg) const { 177 return regsLiveOut.count(Reg) || vregsPassed.count(Reg); 178 } 179 }; 180 181 // Extra register info per MBB. 182 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap; 183 184 bool isReserved(unsigned Reg) { 185 return Reg < regsReserved.size() && regsReserved.test(Reg); 186 } 187 188 bool isAllocatable(unsigned Reg) { 189 return Reg < regsAllocatable.size() && regsAllocatable.test(Reg); 190 } 191 192 // Analysis information if available 193 LiveVariables *LiveVars; 194 LiveIntervals *LiveInts; 195 LiveStacks *LiveStks; 196 SlotIndexes *Indexes; 197 198 void visitMachineFunctionBefore(); 199 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB); 200 void visitMachineBundleBefore(const MachineInstr *MI); 201 void visitMachineInstrBefore(const MachineInstr *MI); 202 void visitMachineOperand(const MachineOperand *MO, unsigned MONum); 203 void visitMachineInstrAfter(const MachineInstr *MI); 204 void visitMachineBundleAfter(const MachineInstr *MI); 205 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB); 206 void visitMachineFunctionAfter(); 207 208 void report(const char *msg, const MachineFunction *MF); 209 void report(const char *msg, const MachineBasicBlock *MBB); 210 void report(const char *msg, const MachineInstr *MI); 211 void report(const char *msg, const MachineOperand *MO, unsigned MONum); 212 void report(const char *msg, const MachineFunction *MF, 213 const LiveInterval &LI); 214 void report(const char *msg, const MachineBasicBlock *MBB, 215 const LiveInterval &LI); 216 217 void verifyInlineAsm(const MachineInstr *MI); 218 219 void checkLiveness(const MachineOperand *MO, unsigned MONum); 220 void markReachable(const MachineBasicBlock *MBB); 221 void calcRegsPassed(); 222 void checkPHIOps(const MachineBasicBlock *MBB); 223 224 void calcRegsRequired(); 225 void verifyLiveVariables(); 226 void verifyLiveIntervals(); 227 void verifyLiveInterval(const LiveInterval&); 228 void verifyLiveIntervalValue(const LiveInterval&, VNInfo*); 229 void verifyLiveIntervalSegment(const LiveInterval&, 230 LiveInterval::const_iterator); 231 }; 232 233 struct MachineVerifierPass : public MachineFunctionPass { 234 static char ID; // Pass ID, replacement for typeid 235 const char *const Banner; 236 237 MachineVerifierPass(const char *b = 0) 238 : MachineFunctionPass(ID), Banner(b) { 239 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry()); 240 } 241 242 void getAnalysisUsage(AnalysisUsage &AU) const { 243 AU.setPreservesAll(); 244 MachineFunctionPass::getAnalysisUsage(AU); 245 } 246 247 bool runOnMachineFunction(MachineFunction &MF) { 248 MF.verify(this, Banner); 249 return false; 250 } 251 }; 252 253} 254 255char MachineVerifierPass::ID = 0; 256INITIALIZE_PASS(MachineVerifierPass, "machineverifier", 257 "Verify generated machine code", false, false) 258 259FunctionPass *llvm::createMachineVerifierPass(const char *Banner) { 260 return new MachineVerifierPass(Banner); 261} 262 263void MachineFunction::verify(Pass *p, const char *Banner) const { 264 MachineVerifier(p, Banner) 265 .runOnMachineFunction(const_cast<MachineFunction&>(*this)); 266} 267 268bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) { 269 raw_ostream *OutFile = 0; 270 if (OutFileName) { 271 std::string ErrorInfo; 272 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo, 273 raw_fd_ostream::F_Append); 274 if (!ErrorInfo.empty()) { 275 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n'; 276 exit(1); 277 } 278 279 OS = OutFile; 280 } else { 281 OS = &errs(); 282 } 283 284 foundErrors = 0; 285 286 this->MF = &MF; 287 TM = &MF.getTarget(); 288 TII = TM->getInstrInfo(); 289 TRI = TM->getRegisterInfo(); 290 MRI = &MF.getRegInfo(); 291 292 LiveVars = NULL; 293 LiveInts = NULL; 294 LiveStks = NULL; 295 Indexes = NULL; 296 if (PASS) { 297 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>(); 298 // We don't want to verify LiveVariables if LiveIntervals is available. 299 if (!LiveInts) 300 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>(); 301 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>(); 302 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>(); 303 } 304 305 visitMachineFunctionBefore(); 306 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end(); 307 MFI!=MFE; ++MFI) { 308 visitMachineBasicBlockBefore(MFI); 309 // Keep track of the current bundle header. 310 const MachineInstr *CurBundle = 0; 311 for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(), 312 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) { 313 if (MBBI->getParent() != MFI) { 314 report("Bad instruction parent pointer", MFI); 315 *OS << "Instruction: " << *MBBI; 316 continue; 317 } 318 // Is this a bundle header? 319 if (!MBBI->isInsideBundle()) { 320 if (CurBundle) 321 visitMachineBundleAfter(CurBundle); 322 CurBundle = MBBI; 323 visitMachineBundleBefore(CurBundle); 324 } else if (!CurBundle) 325 report("No bundle header", MBBI); 326 visitMachineInstrBefore(MBBI); 327 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) 328 visitMachineOperand(&MBBI->getOperand(I), I); 329 visitMachineInstrAfter(MBBI); 330 } 331 if (CurBundle) 332 visitMachineBundleAfter(CurBundle); 333 visitMachineBasicBlockAfter(MFI); 334 } 335 visitMachineFunctionAfter(); 336 337 if (OutFile) 338 delete OutFile; 339 else if (foundErrors) 340 report_fatal_error("Found "+Twine(foundErrors)+" machine code errors."); 341 342 // Clean up. 343 regsLive.clear(); 344 regsDefined.clear(); 345 regsDead.clear(); 346 regsKilled.clear(); 347 regMasks.clear(); 348 regsLiveInButUnused.clear(); 349 MBBInfoMap.clear(); 350 351 return false; // no changes 352} 353 354void MachineVerifier::report(const char *msg, const MachineFunction *MF) { 355 assert(MF); 356 *OS << '\n'; 357 if (!foundErrors++) { 358 if (Banner) 359 *OS << "# " << Banner << '\n'; 360 MF->print(*OS, Indexes); 361 } 362 *OS << "*** Bad machine code: " << msg << " ***\n" 363 << "- function: " << MF->getName() << "\n"; 364} 365 366void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) { 367 assert(MBB); 368 report(msg, MBB->getParent()); 369 *OS << "- basic block: BB#" << MBB->getNumber() 370 << ' ' << MBB->getName() 371 << " (" << (const void*)MBB << ')'; 372 if (Indexes) 373 *OS << " [" << Indexes->getMBBStartIdx(MBB) 374 << ';' << Indexes->getMBBEndIdx(MBB) << ')'; 375 *OS << '\n'; 376} 377 378void MachineVerifier::report(const char *msg, const MachineInstr *MI) { 379 assert(MI); 380 report(msg, MI->getParent()); 381 *OS << "- instruction: "; 382 if (Indexes && Indexes->hasIndex(MI)) 383 *OS << Indexes->getInstructionIndex(MI) << '\t'; 384 MI->print(*OS, TM); 385} 386 387void MachineVerifier::report(const char *msg, 388 const MachineOperand *MO, unsigned MONum) { 389 assert(MO); 390 report(msg, MO->getParent()); 391 *OS << "- operand " << MONum << ": "; 392 MO->print(*OS, TM); 393 *OS << "\n"; 394} 395 396void MachineVerifier::report(const char *msg, const MachineFunction *MF, 397 const LiveInterval &LI) { 398 report(msg, MF); 399 *OS << "- interval: "; 400 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) 401 *OS << PrintReg(LI.reg, TRI); 402 else 403 *OS << PrintRegUnit(LI.reg, TRI); 404 *OS << ' ' << LI << '\n'; 405} 406 407void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB, 408 const LiveInterval &LI) { 409 report(msg, MBB); 410 *OS << "- interval: "; 411 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) 412 *OS << PrintReg(LI.reg, TRI); 413 else 414 *OS << PrintRegUnit(LI.reg, TRI); 415 *OS << ' ' << LI << '\n'; 416} 417 418void MachineVerifier::markReachable(const MachineBasicBlock *MBB) { 419 BBInfo &MInfo = MBBInfoMap[MBB]; 420 if (!MInfo.reachable) { 421 MInfo.reachable = true; 422 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(), 423 SuE = MBB->succ_end(); SuI != SuE; ++SuI) 424 markReachable(*SuI); 425 } 426} 427 428void MachineVerifier::visitMachineFunctionBefore() { 429 lastIndex = SlotIndex(); 430 regsReserved = MRI->getReservedRegs(); 431 432 // A sub-register of a reserved register is also reserved 433 for (int Reg = regsReserved.find_first(); Reg>=0; 434 Reg = regsReserved.find_next(Reg)) { 435 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { 436 // FIXME: This should probably be: 437 // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register"); 438 regsReserved.set(*SubRegs); 439 } 440 } 441 442 regsAllocatable = TRI->getAllocatableSet(*MF); 443 444 markReachable(&MF->front()); 445 446 // Build a set of the basic blocks in the function. 447 FunctionBlocks.clear(); 448 for (MachineFunction::const_iterator 449 I = MF->begin(), E = MF->end(); I != E; ++I) { 450 FunctionBlocks.insert(I); 451 BBInfo &MInfo = MBBInfoMap[I]; 452 453 MInfo.Preds.insert(I->pred_begin(), I->pred_end()); 454 if (MInfo.Preds.size() != I->pred_size()) 455 report("MBB has duplicate entries in its predecessor list.", I); 456 457 MInfo.Succs.insert(I->succ_begin(), I->succ_end()); 458 if (MInfo.Succs.size() != I->succ_size()) 459 report("MBB has duplicate entries in its successor list.", I); 460 } 461} 462 463// Does iterator point to a and b as the first two elements? 464static bool matchPair(MachineBasicBlock::const_succ_iterator i, 465 const MachineBasicBlock *a, const MachineBasicBlock *b) { 466 if (*i == a) 467 return *++i == b; 468 if (*i == b) 469 return *++i == a; 470 return false; 471} 472 473void 474MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) { 475 FirstTerminator = 0; 476 477 if (MRI->isSSA()) { 478 // If this block has allocatable physical registers live-in, check that 479 // it is an entry block or landing pad. 480 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(), 481 LE = MBB->livein_end(); 482 LI != LE; ++LI) { 483 unsigned reg = *LI; 484 if (isAllocatable(reg) && !MBB->isLandingPad() && 485 MBB != MBB->getParent()->begin()) { 486 report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB); 487 } 488 } 489 } 490 491 // Count the number of landing pad successors. 492 SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs; 493 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(), 494 E = MBB->succ_end(); I != E; ++I) { 495 if ((*I)->isLandingPad()) 496 LandingPadSuccs.insert(*I); 497 if (!FunctionBlocks.count(*I)) 498 report("MBB has successor that isn't part of the function.", MBB); 499 if (!MBBInfoMap[*I].Preds.count(MBB)) { 500 report("Inconsistent CFG", MBB); 501 *OS << "MBB is not in the predecessor list of the successor BB#" 502 << (*I)->getNumber() << ".\n"; 503 } 504 } 505 506 // Check the predecessor list. 507 for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(), 508 E = MBB->pred_end(); I != E; ++I) { 509 if (!FunctionBlocks.count(*I)) 510 report("MBB has predecessor that isn't part of the function.", MBB); 511 if (!MBBInfoMap[*I].Succs.count(MBB)) { 512 report("Inconsistent CFG", MBB); 513 *OS << "MBB is not in the successor list of the predecessor BB#" 514 << (*I)->getNumber() << ".\n"; 515 } 516 } 517 518 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo(); 519 const BasicBlock *BB = MBB->getBasicBlock(); 520 if (LandingPadSuccs.size() > 1 && 521 !(AsmInfo && 522 AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj && 523 BB && isa<SwitchInst>(BB->getTerminator()))) 524 report("MBB has more than one landing pad successor", MBB); 525 526 // Call AnalyzeBranch. If it succeeds, there several more conditions to check. 527 MachineBasicBlock *TBB = 0, *FBB = 0; 528 SmallVector<MachineOperand, 4> Cond; 529 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB), 530 TBB, FBB, Cond)) { 531 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's 532 // check whether its answers match up with reality. 533 if (!TBB && !FBB) { 534 // Block falls through to its successor. 535 MachineFunction::const_iterator MBBI = MBB; 536 ++MBBI; 537 if (MBBI == MF->end()) { 538 // It's possible that the block legitimately ends with a noreturn 539 // call or an unreachable, in which case it won't actually fall 540 // out the bottom of the function. 541 } else if (MBB->succ_size() == LandingPadSuccs.size()) { 542 // It's possible that the block legitimately ends with a noreturn 543 // call or an unreachable, in which case it won't actuall fall 544 // out of the block. 545 } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) { 546 report("MBB exits via unconditional fall-through but doesn't have " 547 "exactly one CFG successor!", MBB); 548 } else if (!MBB->isSuccessor(MBBI)) { 549 report("MBB exits via unconditional fall-through but its successor " 550 "differs from its CFG successor!", MBB); 551 } 552 if (!MBB->empty() && getBundleStart(&MBB->back())->isBarrier() && 553 !TII->isPredicated(getBundleStart(&MBB->back()))) { 554 report("MBB exits via unconditional fall-through but ends with a " 555 "barrier instruction!", MBB); 556 } 557 if (!Cond.empty()) { 558 report("MBB exits via unconditional fall-through but has a condition!", 559 MBB); 560 } 561 } else if (TBB && !FBB && Cond.empty()) { 562 // Block unconditionally branches somewhere. 563 if (MBB->succ_size() != 1+LandingPadSuccs.size()) { 564 report("MBB exits via unconditional branch but doesn't have " 565 "exactly one CFG successor!", MBB); 566 } else if (!MBB->isSuccessor(TBB)) { 567 report("MBB exits via unconditional branch but the CFG " 568 "successor doesn't match the actual successor!", MBB); 569 } 570 if (MBB->empty()) { 571 report("MBB exits via unconditional branch but doesn't contain " 572 "any instructions!", MBB); 573 } else if (!getBundleStart(&MBB->back())->isBarrier()) { 574 report("MBB exits via unconditional branch but doesn't end with a " 575 "barrier instruction!", MBB); 576 } else if (!getBundleStart(&MBB->back())->isTerminator()) { 577 report("MBB exits via unconditional branch but the branch isn't a " 578 "terminator instruction!", MBB); 579 } 580 } else if (TBB && !FBB && !Cond.empty()) { 581 // Block conditionally branches somewhere, otherwise falls through. 582 MachineFunction::const_iterator MBBI = MBB; 583 ++MBBI; 584 if (MBBI == MF->end()) { 585 report("MBB conditionally falls through out of function!", MBB); 586 } if (MBB->succ_size() == 1) { 587 // A conditional branch with only one successor is weird, but allowed. 588 if (&*MBBI != TBB) 589 report("MBB exits via conditional branch/fall-through but only has " 590 "one CFG successor!", MBB); 591 else if (TBB != *MBB->succ_begin()) 592 report("MBB exits via conditional branch/fall-through but the CFG " 593 "successor don't match the actual successor!", MBB); 594 } else if (MBB->succ_size() != 2) { 595 report("MBB exits via conditional branch/fall-through but doesn't have " 596 "exactly two CFG successors!", MBB); 597 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) { 598 report("MBB exits via conditional branch/fall-through but the CFG " 599 "successors don't match the actual successors!", MBB); 600 } 601 if (MBB->empty()) { 602 report("MBB exits via conditional branch/fall-through but doesn't " 603 "contain any instructions!", MBB); 604 } else if (getBundleStart(&MBB->back())->isBarrier()) { 605 report("MBB exits via conditional branch/fall-through but ends with a " 606 "barrier instruction!", MBB); 607 } else if (!getBundleStart(&MBB->back())->isTerminator()) { 608 report("MBB exits via conditional branch/fall-through but the branch " 609 "isn't a terminator instruction!", MBB); 610 } 611 } else if (TBB && FBB) { 612 // Block conditionally branches somewhere, otherwise branches 613 // somewhere else. 614 if (MBB->succ_size() == 1) { 615 // A conditional branch with only one successor is weird, but allowed. 616 if (FBB != TBB) 617 report("MBB exits via conditional branch/branch through but only has " 618 "one CFG successor!", MBB); 619 else if (TBB != *MBB->succ_begin()) 620 report("MBB exits via conditional branch/branch through but the CFG " 621 "successor don't match the actual successor!", MBB); 622 } else if (MBB->succ_size() != 2) { 623 report("MBB exits via conditional branch/branch but doesn't have " 624 "exactly two CFG successors!", MBB); 625 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) { 626 report("MBB exits via conditional branch/branch but the CFG " 627 "successors don't match the actual successors!", MBB); 628 } 629 if (MBB->empty()) { 630 report("MBB exits via conditional branch/branch but doesn't " 631 "contain any instructions!", MBB); 632 } else if (!getBundleStart(&MBB->back())->isBarrier()) { 633 report("MBB exits via conditional branch/branch but doesn't end with a " 634 "barrier instruction!", MBB); 635 } else if (!getBundleStart(&MBB->back())->isTerminator()) { 636 report("MBB exits via conditional branch/branch but the branch " 637 "isn't a terminator instruction!", MBB); 638 } 639 if (Cond.empty()) { 640 report("MBB exits via conditinal branch/branch but there's no " 641 "condition!", MBB); 642 } 643 } else { 644 report("AnalyzeBranch returned invalid data!", MBB); 645 } 646 } 647 648 regsLive.clear(); 649 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(), 650 E = MBB->livein_end(); I != E; ++I) { 651 if (!TargetRegisterInfo::isPhysicalRegister(*I)) { 652 report("MBB live-in list contains non-physical register", MBB); 653 continue; 654 } 655 regsLive.insert(*I); 656 for (MCSubRegIterator SubRegs(*I, TRI); SubRegs.isValid(); ++SubRegs) 657 regsLive.insert(*SubRegs); 658 } 659 regsLiveInButUnused = regsLive; 660 661 const MachineFrameInfo *MFI = MF->getFrameInfo(); 662 assert(MFI && "Function has no frame info"); 663 BitVector PR = MFI->getPristineRegs(MBB); 664 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) { 665 regsLive.insert(I); 666 for (MCSubRegIterator SubRegs(I, TRI); SubRegs.isValid(); ++SubRegs) 667 regsLive.insert(*SubRegs); 668 } 669 670 regsKilled.clear(); 671 regsDefined.clear(); 672 673 if (Indexes) 674 lastIndex = Indexes->getMBBStartIdx(MBB); 675} 676 677// This function gets called for all bundle headers, including normal 678// stand-alone unbundled instructions. 679void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) { 680 if (Indexes && Indexes->hasIndex(MI)) { 681 SlotIndex idx = Indexes->getInstructionIndex(MI); 682 if (!(idx > lastIndex)) { 683 report("Instruction index out of order", MI); 684 *OS << "Last instruction was at " << lastIndex << '\n'; 685 } 686 lastIndex = idx; 687 } 688 689 // Ensure non-terminators don't follow terminators. 690 // Ignore predicated terminators formed by if conversion. 691 // FIXME: If conversion shouldn't need to violate this rule. 692 if (MI->isTerminator() && !TII->isPredicated(MI)) { 693 if (!FirstTerminator) 694 FirstTerminator = MI; 695 } else if (FirstTerminator) { 696 report("Non-terminator instruction after the first terminator", MI); 697 *OS << "First terminator was:\t" << *FirstTerminator; 698 } 699} 700 701// The operands on an INLINEASM instruction must follow a template. 702// Verify that the flag operands make sense. 703void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) { 704 // The first two operands on INLINEASM are the asm string and global flags. 705 if (MI->getNumOperands() < 2) { 706 report("Too few operands on inline asm", MI); 707 return; 708 } 709 if (!MI->getOperand(0).isSymbol()) 710 report("Asm string must be an external symbol", MI); 711 if (!MI->getOperand(1).isImm()) 712 report("Asm flags must be an immediate", MI); 713 // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2, 714 // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16. 715 if (!isUInt<5>(MI->getOperand(1).getImm())) 716 report("Unknown asm flags", &MI->getOperand(1), 1); 717 718 assert(InlineAsm::MIOp_FirstOperand == 2 && "Asm format changed"); 719 720 unsigned OpNo = InlineAsm::MIOp_FirstOperand; 721 unsigned NumOps; 722 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) { 723 const MachineOperand &MO = MI->getOperand(OpNo); 724 // There may be implicit ops after the fixed operands. 725 if (!MO.isImm()) 726 break; 727 NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm()); 728 } 729 730 if (OpNo > MI->getNumOperands()) 731 report("Missing operands in last group", MI); 732 733 // An optional MDNode follows the groups. 734 if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata()) 735 ++OpNo; 736 737 // All trailing operands must be implicit registers. 738 for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) { 739 const MachineOperand &MO = MI->getOperand(OpNo); 740 if (!MO.isReg() || !MO.isImplicit()) 741 report("Expected implicit register after groups", &MO, OpNo); 742 } 743} 744 745void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) { 746 const MCInstrDesc &MCID = MI->getDesc(); 747 if (MI->getNumOperands() < MCID.getNumOperands()) { 748 report("Too few operands", MI); 749 *OS << MCID.getNumOperands() << " operands expected, but " 750 << MI->getNumExplicitOperands() << " given.\n"; 751 } 752 753 // Check the tied operands. 754 if (MI->isInlineAsm()) 755 verifyInlineAsm(MI); 756 757 // Check the MachineMemOperands for basic consistency. 758 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(), 759 E = MI->memoperands_end(); I != E; ++I) { 760 if ((*I)->isLoad() && !MI->mayLoad()) 761 report("Missing mayLoad flag", MI); 762 if ((*I)->isStore() && !MI->mayStore()) 763 report("Missing mayStore flag", MI); 764 } 765 766 // Debug values must not have a slot index. 767 // Other instructions must have one, unless they are inside a bundle. 768 if (LiveInts) { 769 bool mapped = !LiveInts->isNotInMIMap(MI); 770 if (MI->isDebugValue()) { 771 if (mapped) 772 report("Debug instruction has a slot index", MI); 773 } else if (MI->isInsideBundle()) { 774 if (mapped) 775 report("Instruction inside bundle has a slot index", MI); 776 } else { 777 if (!mapped) 778 report("Missing slot index", MI); 779 } 780 } 781 782 StringRef ErrorInfo; 783 if (!TII->verifyInstruction(MI, ErrorInfo)) 784 report(ErrorInfo.data(), MI); 785} 786 787void 788MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { 789 const MachineInstr *MI = MO->getParent(); 790 const MCInstrDesc &MCID = MI->getDesc(); 791 792 // The first MCID.NumDefs operands must be explicit register defines 793 if (MONum < MCID.getNumDefs()) { 794 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; 795 if (!MO->isReg()) 796 report("Explicit definition must be a register", MO, MONum); 797 else if (!MO->isDef() && !MCOI.isOptionalDef()) 798 report("Explicit definition marked as use", MO, MONum); 799 else if (MO->isImplicit()) 800 report("Explicit definition marked as implicit", MO, MONum); 801 } else if (MONum < MCID.getNumOperands()) { 802 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; 803 // Don't check if it's the last operand in a variadic instruction. See, 804 // e.g., LDM_RET in the arm back end. 805 if (MO->isReg() && 806 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) { 807 if (MO->isDef() && !MCOI.isOptionalDef()) 808 report("Explicit operand marked as def", MO, MONum); 809 if (MO->isImplicit()) 810 report("Explicit operand marked as implicit", MO, MONum); 811 } 812 813 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO); 814 if (TiedTo != -1) { 815 if (!MO->isReg()) 816 report("Tied use must be a register", MO, MONum); 817 else if (!MO->isTied()) 818 report("Operand should be tied", MO, MONum); 819 else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum)) 820 report("Tied def doesn't match MCInstrDesc", MO, MONum); 821 } else if (MO->isReg() && MO->isTied()) 822 report("Explicit operand should not be tied", MO, MONum); 823 } else { 824 // ARM adds %reg0 operands to indicate predicates. We'll allow that. 825 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg()) 826 report("Extra explicit operand on non-variadic instruction", MO, MONum); 827 } 828 829 switch (MO->getType()) { 830 case MachineOperand::MO_Register: { 831 const unsigned Reg = MO->getReg(); 832 if (!Reg) 833 return; 834 if (MRI->tracksLiveness() && !MI->isDebugValue()) 835 checkLiveness(MO, MONum); 836 837 // Verify the consistency of tied operands. 838 if (MO->isTied()) { 839 unsigned OtherIdx = MI->findTiedOperandIdx(MONum); 840 const MachineOperand &OtherMO = MI->getOperand(OtherIdx); 841 if (!OtherMO.isReg()) 842 report("Must be tied to a register", MO, MONum); 843 if (!OtherMO.isTied()) 844 report("Missing tie flags on tied operand", MO, MONum); 845 if (MI->findTiedOperandIdx(OtherIdx) != MONum) 846 report("Inconsistent tie links", MO, MONum); 847 if (MONum < MCID.getNumDefs()) { 848 if (OtherIdx < MCID.getNumOperands()) { 849 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO)) 850 report("Explicit def tied to explicit use without tie constraint", 851 MO, MONum); 852 } else { 853 if (!OtherMO.isImplicit()) 854 report("Explicit def should be tied to implicit use", MO, MONum); 855 } 856 } 857 } 858 859 // Verify two-address constraints after leaving SSA form. 860 unsigned DefIdx; 861 if (!MRI->isSSA() && MO->isUse() && 862 MI->isRegTiedToDefOperand(MONum, &DefIdx) && 863 Reg != MI->getOperand(DefIdx).getReg()) 864 report("Two-address instruction operands must be identical", MO, MONum); 865 866 // Check register classes. 867 if (MONum < MCID.getNumOperands() && !MO->isImplicit()) { 868 unsigned SubIdx = MO->getSubReg(); 869 870 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 871 if (SubIdx) { 872 report("Illegal subregister index for physical register", MO, MONum); 873 return; 874 } 875 if (const TargetRegisterClass *DRC = 876 TII->getRegClass(MCID, MONum, TRI, *MF)) { 877 if (!DRC->contains(Reg)) { 878 report("Illegal physical register for instruction", MO, MONum); 879 *OS << TRI->getName(Reg) << " is not a " 880 << DRC->getName() << " register.\n"; 881 } 882 } 883 } else { 884 // Virtual register. 885 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 886 if (SubIdx) { 887 const TargetRegisterClass *SRC = 888 TRI->getSubClassWithSubReg(RC, SubIdx); 889 if (!SRC) { 890 report("Invalid subregister index for virtual register", MO, MONum); 891 *OS << "Register class " << RC->getName() 892 << " does not support subreg index " << SubIdx << "\n"; 893 return; 894 } 895 if (RC != SRC) { 896 report("Invalid register class for subregister index", MO, MONum); 897 *OS << "Register class " << RC->getName() 898 << " does not fully support subreg index " << SubIdx << "\n"; 899 return; 900 } 901 } 902 if (const TargetRegisterClass *DRC = 903 TII->getRegClass(MCID, MONum, TRI, *MF)) { 904 if (SubIdx) { 905 const TargetRegisterClass *SuperRC = 906 TRI->getLargestLegalSuperClass(RC); 907 if (!SuperRC) { 908 report("No largest legal super class exists.", MO, MONum); 909 return; 910 } 911 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); 912 if (!DRC) { 913 report("No matching super-reg register class.", MO, MONum); 914 return; 915 } 916 } 917 if (!RC->hasSuperClassEq(DRC)) { 918 report("Illegal virtual register for instruction", MO, MONum); 919 *OS << "Expected a " << DRC->getName() << " register, but got a " 920 << RC->getName() << " register\n"; 921 } 922 } 923 } 924 } 925 break; 926 } 927 928 case MachineOperand::MO_RegisterMask: 929 regMasks.push_back(MO->getRegMask()); 930 break; 931 932 case MachineOperand::MO_MachineBasicBlock: 933 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent())) 934 report("PHI operand is not in the CFG", MO, MONum); 935 break; 936 937 case MachineOperand::MO_FrameIndex: 938 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) && 939 LiveInts && !LiveInts->isNotInMIMap(MI)) { 940 LiveInterval &LI = LiveStks->getInterval(MO->getIndex()); 941 SlotIndex Idx = LiveInts->getInstructionIndex(MI); 942 if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) { 943 report("Instruction loads from dead spill slot", MO, MONum); 944 *OS << "Live stack: " << LI << '\n'; 945 } 946 if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) { 947 report("Instruction stores to dead spill slot", MO, MONum); 948 *OS << "Live stack: " << LI << '\n'; 949 } 950 } 951 break; 952 953 default: 954 break; 955 } 956} 957 958void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) { 959 const MachineInstr *MI = MO->getParent(); 960 const unsigned Reg = MO->getReg(); 961 962 // Both use and def operands can read a register. 963 if (MO->readsReg()) { 964 regsLiveInButUnused.erase(Reg); 965 966 if (MO->isKill()) 967 addRegWithSubRegs(regsKilled, Reg); 968 969 // Check that LiveVars knows this kill. 970 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) && 971 MO->isKill()) { 972 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg); 973 if (std::find(VI.Kills.begin(), VI.Kills.end(), MI) == VI.Kills.end()) 974 report("Kill missing from LiveVariables", MO, MONum); 975 } 976 977 // Check LiveInts liveness and kill. 978 if (LiveInts && !LiveInts->isNotInMIMap(MI)) { 979 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI); 980 // Check the cached regunit intervals. 981 if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) { 982 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) { 983 if (const LiveInterval *LI = LiveInts->getCachedRegUnit(*Units)) { 984 LiveRangeQuery LRQ(*LI, UseIdx); 985 if (!LRQ.valueIn()) { 986 report("No live range at use", MO, MONum); 987 *OS << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI) 988 << ' ' << *LI << '\n'; 989 } 990 if (MO->isKill() && !LRQ.isKill()) { 991 report("Live range continues after kill flag", MO, MONum); 992 *OS << PrintRegUnit(*Units, TRI) << ' ' << *LI << '\n'; 993 } 994 } 995 } 996 } 997 998 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 999 if (LiveInts->hasInterval(Reg)) { 1000 // This is a virtual register interval. 1001 const LiveInterval &LI = LiveInts->getInterval(Reg); 1002 LiveRangeQuery LRQ(LI, UseIdx); 1003 if (!LRQ.valueIn()) { 1004 report("No live range at use", MO, MONum); 1005 *OS << UseIdx << " is not live in " << LI << '\n'; 1006 } 1007 // Check for extra kill flags. 1008 // Note that we allow missing kill flags for now. 1009 if (MO->isKill() && !LRQ.isKill()) { 1010 report("Live range continues after kill flag", MO, MONum); 1011 *OS << "Live range: " << LI << '\n'; 1012 } 1013 } else { 1014 report("Virtual register has no live interval", MO, MONum); 1015 } 1016 } 1017 } 1018 1019 // Use of a dead register. 1020 if (!regsLive.count(Reg)) { 1021 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 1022 // Reserved registers may be used even when 'dead'. 1023 if (!isReserved(Reg)) 1024 report("Using an undefined physical register", MO, MONum); 1025 } else if (MRI->def_empty(Reg)) { 1026 report("Reading virtual register without a def", MO, MONum); 1027 } else { 1028 BBInfo &MInfo = MBBInfoMap[MI->getParent()]; 1029 // We don't know which virtual registers are live in, so only complain 1030 // if vreg was killed in this MBB. Otherwise keep track of vregs that 1031 // must be live in. PHI instructions are handled separately. 1032 if (MInfo.regsKilled.count(Reg)) 1033 report("Using a killed virtual register", MO, MONum); 1034 else if (!MI->isPHI()) 1035 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI)); 1036 } 1037 } 1038 } 1039 1040 if (MO->isDef()) { 1041 // Register defined. 1042 // TODO: verify that earlyclobber ops are not used. 1043 if (MO->isDead()) 1044 addRegWithSubRegs(regsDead, Reg); 1045 else 1046 addRegWithSubRegs(regsDefined, Reg); 1047 1048 // Verify SSA form. 1049 if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) && 1050 llvm::next(MRI->def_begin(Reg)) != MRI->def_end()) 1051 report("Multiple virtual register defs in SSA form", MO, MONum); 1052 1053 // Check LiveInts for a live range, but only for virtual registers. 1054 if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) && 1055 !LiveInts->isNotInMIMap(MI)) { 1056 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI); 1057 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber()); 1058 if (LiveInts->hasInterval(Reg)) { 1059 const LiveInterval &LI = LiveInts->getInterval(Reg); 1060 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) { 1061 assert(VNI && "NULL valno is not allowed"); 1062 if (VNI->def != DefIdx) { 1063 report("Inconsistent valno->def", MO, MONum); 1064 *OS << "Valno " << VNI->id << " is not defined at " 1065 << DefIdx << " in " << LI << '\n'; 1066 } 1067 } else { 1068 report("No live range at def", MO, MONum); 1069 *OS << DefIdx << " is not live in " << LI << '\n'; 1070 } 1071 } else { 1072 report("Virtual register has no Live interval", MO, MONum); 1073 } 1074 } 1075 } 1076} 1077 1078void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) { 1079} 1080 1081// This function gets called after visiting all instructions in a bundle. The 1082// argument points to the bundle header. 1083// Normal stand-alone instructions are also considered 'bundles', and this 1084// function is called for all of them. 1085void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) { 1086 BBInfo &MInfo = MBBInfoMap[MI->getParent()]; 1087 set_union(MInfo.regsKilled, regsKilled); 1088 set_subtract(regsLive, regsKilled); regsKilled.clear(); 1089 // Kill any masked registers. 1090 while (!regMasks.empty()) { 1091 const uint32_t *Mask = regMasks.pop_back_val(); 1092 for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I) 1093 if (TargetRegisterInfo::isPhysicalRegister(*I) && 1094 MachineOperand::clobbersPhysReg(Mask, *I)) 1095 regsDead.push_back(*I); 1096 } 1097 set_subtract(regsLive, regsDead); regsDead.clear(); 1098 set_union(regsLive, regsDefined); regsDefined.clear(); 1099} 1100 1101void 1102MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) { 1103 MBBInfoMap[MBB].regsLiveOut = regsLive; 1104 regsLive.clear(); 1105 1106 if (Indexes) { 1107 SlotIndex stop = Indexes->getMBBEndIdx(MBB); 1108 if (!(stop > lastIndex)) { 1109 report("Block ends before last instruction index", MBB); 1110 *OS << "Block ends at " << stop 1111 << " last instruction was at " << lastIndex << '\n'; 1112 } 1113 lastIndex = stop; 1114 } 1115} 1116 1117// Calculate the largest possible vregsPassed sets. These are the registers that 1118// can pass through an MBB live, but may not be live every time. It is assumed 1119// that all vregsPassed sets are empty before the call. 1120void MachineVerifier::calcRegsPassed() { 1121 // First push live-out regs to successors' vregsPassed. Remember the MBBs that 1122 // have any vregsPassed. 1123 SmallPtrSet<const MachineBasicBlock*, 8> todo; 1124 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 1125 MFI != MFE; ++MFI) { 1126 const MachineBasicBlock &MBB(*MFI); 1127 BBInfo &MInfo = MBBInfoMap[&MBB]; 1128 if (!MInfo.reachable) 1129 continue; 1130 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(), 1131 SuE = MBB.succ_end(); SuI != SuE; ++SuI) { 1132 BBInfo &SInfo = MBBInfoMap[*SuI]; 1133 if (SInfo.addPassed(MInfo.regsLiveOut)) 1134 todo.insert(*SuI); 1135 } 1136 } 1137 1138 // Iteratively push vregsPassed to successors. This will converge to the same 1139 // final state regardless of DenseSet iteration order. 1140 while (!todo.empty()) { 1141 const MachineBasicBlock *MBB = *todo.begin(); 1142 todo.erase(MBB); 1143 BBInfo &MInfo = MBBInfoMap[MBB]; 1144 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(), 1145 SuE = MBB->succ_end(); SuI != SuE; ++SuI) { 1146 if (*SuI == MBB) 1147 continue; 1148 BBInfo &SInfo = MBBInfoMap[*SuI]; 1149 if (SInfo.addPassed(MInfo.vregsPassed)) 1150 todo.insert(*SuI); 1151 } 1152 } 1153} 1154 1155// Calculate the set of virtual registers that must be passed through each basic 1156// block in order to satisfy the requirements of successor blocks. This is very 1157// similar to calcRegsPassed, only backwards. 1158void MachineVerifier::calcRegsRequired() { 1159 // First push live-in regs to predecessors' vregsRequired. 1160 SmallPtrSet<const MachineBasicBlock*, 8> todo; 1161 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 1162 MFI != MFE; ++MFI) { 1163 const MachineBasicBlock &MBB(*MFI); 1164 BBInfo &MInfo = MBBInfoMap[&MBB]; 1165 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(), 1166 PrE = MBB.pred_end(); PrI != PrE; ++PrI) { 1167 BBInfo &PInfo = MBBInfoMap[*PrI]; 1168 if (PInfo.addRequired(MInfo.vregsLiveIn)) 1169 todo.insert(*PrI); 1170 } 1171 } 1172 1173 // Iteratively push vregsRequired to predecessors. This will converge to the 1174 // same final state regardless of DenseSet iteration order. 1175 while (!todo.empty()) { 1176 const MachineBasicBlock *MBB = *todo.begin(); 1177 todo.erase(MBB); 1178 BBInfo &MInfo = MBBInfoMap[MBB]; 1179 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(), 1180 PrE = MBB->pred_end(); PrI != PrE; ++PrI) { 1181 if (*PrI == MBB) 1182 continue; 1183 BBInfo &SInfo = MBBInfoMap[*PrI]; 1184 if (SInfo.addRequired(MInfo.vregsRequired)) 1185 todo.insert(*PrI); 1186 } 1187 } 1188} 1189 1190// Check PHI instructions at the beginning of MBB. It is assumed that 1191// calcRegsPassed has been run so BBInfo::isLiveOut is valid. 1192void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) { 1193 SmallPtrSet<const MachineBasicBlock*, 8> seen; 1194 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end(); 1195 BBI != BBE && BBI->isPHI(); ++BBI) { 1196 seen.clear(); 1197 1198 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) { 1199 unsigned Reg = BBI->getOperand(i).getReg(); 1200 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB(); 1201 if (!Pre->isSuccessor(MBB)) 1202 continue; 1203 seen.insert(Pre); 1204 BBInfo &PrInfo = MBBInfoMap[Pre]; 1205 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg)) 1206 report("PHI operand is not live-out from predecessor", 1207 &BBI->getOperand(i), i); 1208 } 1209 1210 // Did we see all predecessors? 1211 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(), 1212 PrE = MBB->pred_end(); PrI != PrE; ++PrI) { 1213 if (!seen.count(*PrI)) { 1214 report("Missing PHI operand", BBI); 1215 *OS << "BB#" << (*PrI)->getNumber() 1216 << " is a predecessor according to the CFG.\n"; 1217 } 1218 } 1219 } 1220} 1221 1222void MachineVerifier::visitMachineFunctionAfter() { 1223 calcRegsPassed(); 1224 1225 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 1226 MFI != MFE; ++MFI) { 1227 BBInfo &MInfo = MBBInfoMap[MFI]; 1228 1229 // Skip unreachable MBBs. 1230 if (!MInfo.reachable) 1231 continue; 1232 1233 checkPHIOps(MFI); 1234 } 1235 1236 // Now check liveness info if available 1237 calcRegsRequired(); 1238 1239 // Check for killed virtual registers that should be live out. 1240 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 1241 MFI != MFE; ++MFI) { 1242 BBInfo &MInfo = MBBInfoMap[MFI]; 1243 for (RegSet::iterator 1244 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E; 1245 ++I) 1246 if (MInfo.regsKilled.count(*I)) { 1247 report("Virtual register killed in block, but needed live out.", MFI); 1248 *OS << "Virtual register " << PrintReg(*I) 1249 << " is used after the block.\n"; 1250 } 1251 } 1252 1253 if (!MF->empty()) { 1254 BBInfo &MInfo = MBBInfoMap[&MF->front()]; 1255 for (RegSet::iterator 1256 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E; 1257 ++I) 1258 report("Virtual register def doesn't dominate all uses.", 1259 MRI->getVRegDef(*I)); 1260 } 1261 1262 if (LiveVars) 1263 verifyLiveVariables(); 1264 if (LiveInts) 1265 verifyLiveIntervals(); 1266} 1267 1268void MachineVerifier::verifyLiveVariables() { 1269 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars"); 1270 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { 1271 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 1272 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg); 1273 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 1274 MFI != MFE; ++MFI) { 1275 BBInfo &MInfo = MBBInfoMap[MFI]; 1276 1277 // Our vregsRequired should be identical to LiveVariables' AliveBlocks 1278 if (MInfo.vregsRequired.count(Reg)) { 1279 if (!VI.AliveBlocks.test(MFI->getNumber())) { 1280 report("LiveVariables: Block missing from AliveBlocks", MFI); 1281 *OS << "Virtual register " << PrintReg(Reg) 1282 << " must be live through the block.\n"; 1283 } 1284 } else { 1285 if (VI.AliveBlocks.test(MFI->getNumber())) { 1286 report("LiveVariables: Block should not be in AliveBlocks", MFI); 1287 *OS << "Virtual register " << PrintReg(Reg) 1288 << " is not needed live through the block.\n"; 1289 } 1290 } 1291 } 1292 } 1293} 1294 1295void MachineVerifier::verifyLiveIntervals() { 1296 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts"); 1297 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { 1298 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 1299 1300 // Spilling and splitting may leave unused registers around. Skip them. 1301 if (MRI->reg_nodbg_empty(Reg)) 1302 continue; 1303 1304 if (!LiveInts->hasInterval(Reg)) { 1305 report("Missing live interval for virtual register", MF); 1306 *OS << PrintReg(Reg, TRI) << " still has defs or uses\n"; 1307 continue; 1308 } 1309 1310 const LiveInterval &LI = LiveInts->getInterval(Reg); 1311 assert(Reg == LI.reg && "Invalid reg to interval mapping"); 1312 verifyLiveInterval(LI); 1313 } 1314 1315 // Verify all the cached regunit intervals. 1316 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i) 1317 if (const LiveInterval *LI = LiveInts->getCachedRegUnit(i)) 1318 verifyLiveInterval(*LI); 1319} 1320 1321void MachineVerifier::verifyLiveIntervalValue(const LiveInterval &LI, 1322 VNInfo *VNI) { 1323 if (VNI->isUnused()) 1324 return; 1325 1326 const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def); 1327 1328 if (!DefVNI) { 1329 report("Valno not live at def and not marked unused", MF, LI); 1330 *OS << "Valno #" << VNI->id << '\n'; 1331 return; 1332 } 1333 1334 if (DefVNI != VNI) { 1335 report("Live range at def has different valno", MF, LI); 1336 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def 1337 << " where valno #" << DefVNI->id << " is live\n"; 1338 return; 1339 } 1340 1341 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def); 1342 if (!MBB) { 1343 report("Invalid definition index", MF, LI); 1344 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def 1345 << " in " << LI << '\n'; 1346 return; 1347 } 1348 1349 if (VNI->isPHIDef()) { 1350 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) { 1351 report("PHIDef value is not defined at MBB start", MBB, LI); 1352 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def 1353 << ", not at the beginning of BB#" << MBB->getNumber() << '\n'; 1354 } 1355 return; 1356 } 1357 1358 // Non-PHI def. 1359 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def); 1360 if (!MI) { 1361 report("No instruction at def index", MBB, LI); 1362 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n'; 1363 return; 1364 } 1365 1366 bool hasDef = false; 1367 bool isEarlyClobber = false; 1368 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) { 1369 if (!MOI->isReg() || !MOI->isDef()) 1370 continue; 1371 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { 1372 if (MOI->getReg() != LI.reg) 1373 continue; 1374 } else { 1375 if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) || 1376 !TRI->hasRegUnit(MOI->getReg(), LI.reg)) 1377 continue; 1378 } 1379 hasDef = true; 1380 if (MOI->isEarlyClobber()) 1381 isEarlyClobber = true; 1382 } 1383 1384 if (!hasDef) { 1385 report("Defining instruction does not modify register", MI); 1386 *OS << "Valno #" << VNI->id << " in " << LI << '\n'; 1387 } 1388 1389 // Early clobber defs begin at USE slots, but other defs must begin at 1390 // DEF slots. 1391 if (isEarlyClobber) { 1392 if (!VNI->def.isEarlyClobber()) { 1393 report("Early clobber def must be at an early-clobber slot", MBB, LI); 1394 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n'; 1395 } 1396 } else if (!VNI->def.isRegister()) { 1397 report("Non-PHI, non-early clobber def must be at a register slot", 1398 MBB, LI); 1399 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n'; 1400 } 1401} 1402 1403void 1404MachineVerifier::verifyLiveIntervalSegment(const LiveInterval &LI, 1405 LiveInterval::const_iterator I) { 1406 const VNInfo *VNI = I->valno; 1407 assert(VNI && "Live range has no valno"); 1408 1409 if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) { 1410 report("Foreign valno in live range", MF, LI); 1411 *OS << *I << " has a bad valno\n"; 1412 } 1413 1414 if (VNI->isUnused()) { 1415 report("Live range valno is marked unused", MF, LI); 1416 *OS << *I << '\n'; 1417 } 1418 1419 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start); 1420 if (!MBB) { 1421 report("Bad start of live segment, no basic block", MF, LI); 1422 *OS << *I << '\n'; 1423 return; 1424 } 1425 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB); 1426 if (I->start != MBBStartIdx && I->start != VNI->def) { 1427 report("Live segment must begin at MBB entry or valno def", MBB, LI); 1428 *OS << *I << '\n'; 1429 } 1430 1431 const MachineBasicBlock *EndMBB = 1432 LiveInts->getMBBFromIndex(I->end.getPrevSlot()); 1433 if (!EndMBB) { 1434 report("Bad end of live segment, no basic block", MF, LI); 1435 *OS << *I << '\n'; 1436 return; 1437 } 1438 1439 // No more checks for live-out segments. 1440 if (I->end == LiveInts->getMBBEndIdx(EndMBB)) 1441 return; 1442 1443 // RegUnit intervals are allowed dead phis. 1444 if (!TargetRegisterInfo::isVirtualRegister(LI.reg) && VNI->isPHIDef() && 1445 I->start == VNI->def && I->end == VNI->def.getDeadSlot()) 1446 return; 1447 1448 // The live segment is ending inside EndMBB 1449 const MachineInstr *MI = 1450 LiveInts->getInstructionFromIndex(I->end.getPrevSlot()); 1451 if (!MI) { 1452 report("Live segment doesn't end at a valid instruction", EndMBB, LI); 1453 *OS << *I << '\n'; 1454 return; 1455 } 1456 1457 // The block slot must refer to a basic block boundary. 1458 if (I->end.isBlock()) { 1459 report("Live segment ends at B slot of an instruction", EndMBB, LI); 1460 *OS << *I << '\n'; 1461 } 1462 1463 if (I->end.isDead()) { 1464 // Segment ends on the dead slot. 1465 // That means there must be a dead def. 1466 if (!SlotIndex::isSameInstr(I->start, I->end)) { 1467 report("Live segment ending at dead slot spans instructions", EndMBB, LI); 1468 *OS << *I << '\n'; 1469 } 1470 } 1471 1472 // A live segment can only end at an early-clobber slot if it is being 1473 // redefined by an early-clobber def. 1474 if (I->end.isEarlyClobber()) { 1475 if (I+1 == LI.end() || (I+1)->start != I->end) { 1476 report("Live segment ending at early clobber slot must be " 1477 "redefined by an EC def in the same instruction", EndMBB, LI); 1478 *OS << *I << '\n'; 1479 } 1480 } 1481 1482 // The following checks only apply to virtual registers. Physreg liveness 1483 // is too weird to check. 1484 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { 1485 // A live range can end with either a redefinition, a kill flag on a 1486 // use, or a dead flag on a def. 1487 bool hasRead = false; 1488 bool hasDeadDef = false; 1489 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) { 1490 if (!MOI->isReg() || MOI->getReg() != LI.reg) 1491 continue; 1492 if (MOI->readsReg()) 1493 hasRead = true; 1494 if (MOI->isDef() && MOI->isDead()) 1495 hasDeadDef = true; 1496 } 1497 1498 if (I->end.isDead()) { 1499 if (!hasDeadDef) { 1500 report("Instruction doesn't have a dead def operand", MI); 1501 I->print(*OS); 1502 *OS << " in " << LI << '\n'; 1503 } 1504 } else { 1505 if (!hasRead) { 1506 report("Instruction ending live range doesn't read the register", MI); 1507 *OS << *I << " in " << LI << '\n'; 1508 } 1509 } 1510 } 1511 1512 // Now check all the basic blocks in this live segment. 1513 MachineFunction::const_iterator MFI = MBB; 1514 // Is this live range the beginning of a non-PHIDef VN? 1515 if (I->start == VNI->def && !VNI->isPHIDef()) { 1516 // Not live-in to any blocks. 1517 if (MBB == EndMBB) 1518 return; 1519 // Skip this block. 1520 ++MFI; 1521 } 1522 for (;;) { 1523 assert(LiveInts->isLiveInToMBB(LI, MFI)); 1524 // We don't know how to track physregs into a landing pad. 1525 if (!TargetRegisterInfo::isVirtualRegister(LI.reg) && 1526 MFI->isLandingPad()) { 1527 if (&*MFI == EndMBB) 1528 break; 1529 ++MFI; 1530 continue; 1531 } 1532 1533 // Is VNI a PHI-def in the current block? 1534 bool IsPHI = VNI->isPHIDef() && 1535 VNI->def == LiveInts->getMBBStartIdx(MFI); 1536 1537 // Check that VNI is live-out of all predecessors. 1538 for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(), 1539 PE = MFI->pred_end(); PI != PE; ++PI) { 1540 SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI); 1541 const VNInfo *PVNI = LI.getVNInfoBefore(PEnd); 1542 1543 // All predecessors must have a live-out value. 1544 if (!PVNI) { 1545 report("Register not marked live out of predecessor", *PI, LI); 1546 *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber() 1547 << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before " 1548 << PEnd << '\n'; 1549 continue; 1550 } 1551 1552 // Only PHI-defs can take different predecessor values. 1553 if (!IsPHI && PVNI != VNI) { 1554 report("Different value live out of predecessor", *PI, LI); 1555 *OS << "Valno #" << PVNI->id << " live out of BB#" 1556 << (*PI)->getNumber() << '@' << PEnd 1557 << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber() 1558 << '@' << LiveInts->getMBBStartIdx(MFI) << '\n'; 1559 } 1560 } 1561 if (&*MFI == EndMBB) 1562 break; 1563 ++MFI; 1564 } 1565} 1566 1567void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) { 1568 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end(); 1569 I!=E; ++I) 1570 verifyLiveIntervalValue(LI, *I); 1571 1572 for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I) 1573 verifyLiveIntervalSegment(LI, I); 1574 1575 // Check the LI only has one connected component. 1576 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { 1577 ConnectedVNInfoEqClasses ConEQ(*LiveInts); 1578 unsigned NumComp = ConEQ.Classify(&LI); 1579 if (NumComp > 1) { 1580 report("Multiple connected components in live interval", MF, LI); 1581 for (unsigned comp = 0; comp != NumComp; ++comp) { 1582 *OS << comp << ": valnos"; 1583 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), 1584 E = LI.vni_end(); I!=E; ++I) 1585 if (comp == ConEQ.getEqClass(*I)) 1586 *OS << ' ' << (*I)->id; 1587 *OS << '\n'; 1588 } 1589 } 1590 } 1591} 1592