1/* Opcode table header for m680[01234]0/m6888[12]/m68851. 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001, 3 2003, 2004, 2006 Free Software Foundation, Inc. 4 5 This file is part of GDB, GAS, and the GNU binutils. 6 7 GDB, GAS, and the GNU binutils are free software; you can redistribute 8 them and/or modify them under the terms of the GNU General Public 9 License as published by the Free Software Foundation; either version 10 1, or (at your option) any later version. 11 12 GDB, GAS, and the GNU binutils are distributed in the hope that they 13 will be useful, but WITHOUT ANY WARRANTY; without even the implied 14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 15 the GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this file; see the file COPYING. If not, write to the Free 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 20 02110-1301, USA. */ 21 22/* These are used as bit flags for the arch field in the m68k_opcode 23 structure. */ 24#define _m68k_undef 0 25#define m68000 0x001 26#define m68010 0x002 27#define m68020 0x004 28#define m68030 0x008 29#define m68040 0x010 30#define m68060 0x020 31#define m68881 0x040 32#define m68851 0x080 33#define cpu32 0x100 /* e.g., 68332 */ 34#define fido_a 0x200 35#define m68k_mask 0x3ff 36 37#define mcfmac 0x400 /* ColdFire MAC. */ 38#define mcfemac 0x800 /* ColdFire EMAC. */ 39#define cfloat 0x1000 /* ColdFire FPU. */ 40#define mcfhwdiv 0x2000 /* ColdFire hardware divide. */ 41 42#define mcfisa_a 0x4000 /* ColdFire ISA_A. */ 43#define mcfisa_aa 0x8000 /* ColdFire ISA_A+. */ 44#define mcfisa_b 0x10000 /* ColdFire ISA_B. */ 45#define mcfusp 0x20000 /* ColdFire USP instructions. */ 46#define mcf_mask 0x3e400 47 48/* Handy aliases. */ 49#define m68040up (m68040 | m68060) 50#define m68030up (m68030 | m68040up) 51#define m68020up (m68020 | m68030up) 52#define m68010up (m68010 | cpu32 | fido_a | m68020up) 53#define m68000up (m68000 | m68010up) 54 55#define mfloat (m68881 | m68040 | m68060) 56#define mmmu (m68851 | m68030 | m68040 | m68060) 57 58/* The structure used to hold information for an opcode. */ 59 60struct m68k_opcode 61{ 62 /* The opcode name. */ 63 const char *name; 64 /* The pseudo-size of the instruction(in bytes). Used to determine 65 number of bytes necessary to disassemble the instruction. */ 66 unsigned int size; 67 /* The opcode itself. */ 68 unsigned long opcode; 69 /* The mask used by the disassembler. */ 70 unsigned long match; 71 /* The arguments. */ 72 const char *args; 73 /* The architectures which support this opcode. */ 74 unsigned int arch; 75}; 76 77/* The structure used to hold information for an opcode alias. */ 78 79struct m68k_opcode_alias 80{ 81 /* The alias name. */ 82 const char *alias; 83 /* The instruction for which this is an alias. */ 84 const char *primary; 85}; 86 87/* We store four bytes of opcode for all opcodes because that is the 88 most any of them need. The actual length of an instruction is 89 always at least 2 bytes, and is as much longer as necessary to hold 90 the operands it has. 91 92 The match field is a mask saying which bits must match particular 93 opcode in order for an instruction to be an instance of that 94 opcode. 95 96 The args field is a string containing two characters for each 97 operand of the instruction. The first specifies the kind of 98 operand; the second, the place it is stored. */ 99 100/* Kinds of operands: 101 Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+- 102 103 D data register only. Stored as 3 bits. 104 A address register only. Stored as 3 bits. 105 a address register indirect only. Stored as 3 bits. 106 R either kind of register. Stored as 4 bits. 107 r either kind of register indirect only. Stored as 4 bits. 108 At the moment, used only for cas2 instruction. 109 F floating point coprocessor register only. Stored as 3 bits. 110 O an offset (or width): immediate data 0-31 or data register. 111 Stored as 6 bits in special format for BF... insns. 112 + autoincrement only. Stored as 3 bits (number of the address register). 113 - autodecrement only. Stored as 3 bits (number of the address register). 114 Q quick immediate data. Stored as 3 bits. 115 This matches an immediate operand only when value is in range 1 .. 8. 116 M moveq immediate data. Stored as 8 bits. 117 This matches an immediate operand only when value is in range -128..127 118 T trap vector immediate data. Stored as 4 bits. 119 120 k K-factor for fmove.p instruction. Stored as a 7-bit constant or 121 a three bit register offset, depending on the field type. 122 123 # immediate data. Stored in special places (b, w or l) 124 which say how many bits to store. 125 ^ immediate data for floating point instructions. Special places 126 are offset by 2 bytes from '#'... 127 B pc-relative address, converted to an offset 128 that is treated as immediate data. 129 d displacement and register. Stores the register as 3 bits 130 and stores the displacement in the entire second word. 131 132 C the CCR. No need to store it; this is just for filtering validity. 133 S the SR. No need to store, just as with CCR. 134 U the USP. No need to store, just as with CCR. 135 E the MAC ACC. No need to store, just as with CCR. 136 e the EMAC ACC[0123]. 137 G the MAC/EMAC MACSR. No need to store, just as with CCR. 138 g the EMAC ACCEXT{01,23}. 139 H the MASK. No need to store, just as with CCR. 140 i the MAC/EMAC scale factor. 141 142 I Coprocessor ID. Not printed if 1. The Coprocessor ID is always 143 extracted from the 'd' field of word one, which means that an extended 144 coprocessor opcode can be skipped using the 'i' place, if needed. 145 146 s System Control register for the floating point coprocessor. 147 148 J Misc register for movec instruction, stored in 'j' format. 149 Possible values: 150 0x000 SFC Source Function Code reg [60, 40, 30, 20, 10] 151 0x001 DFC Data Function Code reg [60, 40, 30, 20, 10] 152 0x002 CACR Cache Control Register [60, 40, 30, 20, mcf] 153 0x003 TC MMU Translation Control [60, 40] 154 0x004 ITT0 Instruction Transparent 155 Translation reg 0 [60, 40] 156 0x005 ITT1 Instruction Transparent 157 Translation reg 1 [60, 40] 158 0x006 DTT0 Data Transparent 159 Translation reg 0 [60, 40] 160 0x007 DTT1 Data Transparent 161 Translation reg 1 [60, 40] 162 0x008 BUSCR Bus Control Register [60] 163 0x800 USP User Stack Pointer [60, 40, 30, 20, 10] 164 0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf] 165 0x802 CAAR Cache Address Register [ 30, 20] 166 0x803 MSP Master Stack Pointer [ 40, 30, 20] 167 0x804 ISP Interrupt Stack Pointer [ 40, 30, 20] 168 0x805 MMUSR MMU Status reg [ 40] 169 0x806 URP User Root Pointer [60, 40] 170 0x807 SRP Supervisor Root Pointer [60, 40] 171 0x808 PCR Processor Configuration reg [60] 172 0xC00 ROMBAR ROM Base Address Register [520X] 173 0xC04 RAMBAR0 RAM Base Address Register 0 [520X] 174 0xC05 RAMBAR1 RAM Base Address Register 0 [520X] 175 0xC0F MBAR0 RAM Base Address Register 0 [520X] 176 0xC04 FLASHBAR FLASH Base Address Register [mcf528x] 177 0xC05 RAMBAR Static RAM Base Address Register [mcf528x] 178 179 L Register list of the type d0-d7/a0-a7 etc. 180 (New! Improved! Can also hold fp0-fp7, as well!) 181 The assembler tries to see if the registers match the insn by 182 looking at where the insn wants them stored. 183 184 l Register list like L, but with all the bits reversed. 185 Used for going the other way. . . 186 187 c cache identifier which may be "nc" for no cache, "ic" 188 for instruction cache, "dc" for data cache, or "bc" 189 for both caches. Used in cinv and cpush. Always 190 stored in position "d". 191 192 u Any register, with ``upper'' or ``lower'' specification. Used 193 in the mac instructions with size word. 194 195 The remainder are all stored as 6 bits using an address mode and a 196 register number; they differ in which addressing modes they match. 197 198 * all (modes 0-6,7.0-4) 199 ~ alterable memory (modes 2-6,7.0,7.1) 200 (not 0,1,7.2-4) 201 % alterable (modes 0-6,7.0,7.1) 202 (not 7.2-4) 203 ; data (modes 0,2-6,7.0-4) 204 (not 1) 205 @ data, but not immediate (modes 0,2-6,7.0-3) 206 (not 1,7.4) 207 ! control (modes 2,5,6,7.0-3) 208 (not 0,1,3,4,7.4) 209 & alterable control (modes 2,5,6,7.0,7.1) 210 (not 0,1,3,4,7.2-4) 211 $ alterable data (modes 0,2-6,7.0,7.1) 212 (not 1,7.2-4) 213 ? alterable control, or data register (modes 0,2,5,6,7.0,7.1) 214 (not 1,3,4,7.2-4) 215 / control, or data register (modes 0,2,5,6,7.0-3) 216 (not 1,3,4,7.4) 217 > *save operands (modes 2,4,5,6,7.0,7.1) 218 (not 0,1,3,7.2-4) 219 < *restore operands (modes 2,3,5,6,7.0-3) 220 (not 0,1,4,7.4) 221 222 coldfire move operands: 223 m (modes 0-4) 224 n (modes 5,7.2) 225 o (modes 6,7.0,7.1,7.3,7.4) 226 p (modes 0-5) 227 228 coldfire bset/bclr/btst/mulsl/mulul operands: 229 q (modes 0,2-5) 230 v (modes 0,2-5,7.0,7.1) 231 b (modes 0,2-5,7.2) 232 w (modes 2-5,7.2) 233 y (modes 2,5) 234 z (modes 2,5,7.2) 235 x mov3q immediate operand. 236 4 (modes 2,3,4,5) 237 */ 238 239/* For the 68851: */ 240/* I didn't use much imagination in choosing the 241 following codes, so many of them aren't very 242 mnemonic. -rab 243 244 0 32 bit pmmu register 245 Possible values: 246 000 TC Translation Control Register (68030, 68851) 247 248 1 16 bit pmmu register 249 111 AC Access Control (68851) 250 251 2 8 bit pmmu register 252 100 CAL Current Access Level (68851) 253 101 VAL Validate Access Level (68851) 254 110 SCC Stack Change Control (68851) 255 256 3 68030-only pmmu registers (32 bit) 257 010 TT0 Transparent Translation reg 0 258 (aka Access Control reg 0 -- AC0 -- on 68ec030) 259 011 TT1 Transparent Translation reg 1 260 (aka Access Control reg 1 -- AC1 -- on 68ec030) 261 262 W wide pmmu registers 263 Possible values: 264 001 DRP Dma Root Pointer (68851) 265 010 SRP Supervisor Root Pointer (68030, 68851) 266 011 CRP Cpu Root Pointer (68030, 68851) 267 268 f function code register (68030, 68851) 269 0 SFC 270 1 DFC 271 272 V VAL register only (68851) 273 274 X BADx, BACx (16 bit) 275 100 BAD Breakpoint Acknowledge Data (68851) 276 101 BAC Breakpoint Acknowledge Control (68851) 277 278 Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030) 279 Z PCSR (68851) 280 281 | memory (modes 2-6, 7.*) 282 283 t address test level (68030 only) 284 Stored as 3 bits, range 0-7. 285 Also used for breakpoint instruction now. 286 287*/ 288 289/* Places to put an operand, for non-general operands: 290 Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/ 291 292 s source, low bits of first word. 293 d dest, shifted 9 in first word 294 1 second word, shifted 12 295 2 second word, shifted 6 296 3 second word, shifted 0 297 4 third word, shifted 12 298 5 third word, shifted 6 299 6 third word, shifted 0 300 7 second word, shifted 7 301 8 second word, shifted 10 302 9 second word, shifted 5 303 D store in both place 1 and place 3; for divul and divsl. 304 B first word, low byte, for branch displacements 305 W second word (entire), for branch displacements 306 L second and third words (entire), for branch displacements 307 (also overloaded for move16) 308 b second word, low byte 309 w second word (entire) [variable word/long branch offset for dbra] 310 W second word (entire) (must be signed 16 bit value) 311 l second and third word (entire) 312 g variable branch offset for bra and similar instructions. 313 The place to store depends on the magnitude of offset. 314 t store in both place 7 and place 8; for floating point operations 315 c branch offset for cpBcc operations. 316 The place to store is word two if bit six of word one is zero, 317 and words two and three if bit six of word one is one. 318 i Increment by two, to skip over coprocessor extended operands. Only 319 works with the 'I' format. 320 k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number. 321 Also used for dynamic fmovem instruction. 322 C floating point coprocessor constant - 7 bits. Also used for static 323 K-factors... 324 j Movec register #, stored in 12 low bits of second word. 325 m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word 326 and remaining 3 bits of register shifted 9 bits in first word. 327 Indicate upper/lower in 1 bit shifted 7 bits in second word. 328 Use with `R' or `u' format. 329 n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split 330 with MSB shifted 6 bits in first word and remaining 3 bits of 331 register shifted 9 bits in first word. No upper/lower 332 indication is done.) Use with `R' or `u' format. 333 o For M[S]ACw; 4 bits shifted 12 in second word (like `1'). 334 Indicate upper/lower in 1 bit shifted 7 bits in second word. 335 Use with `R' or `u' format. 336 M For M[S]ACw; 4 bits in low bits of first word. Indicate 337 upper/lower in 1 bit shifted 6 bits in second word. Use with 338 `R' or `u' format. 339 N For M[S]ACw; 4 bits in low bits of second word. Indicate 340 upper/lower in 1 bit shifted 6 bits in second word. Use with 341 `R' or `u' format. 342 h shift indicator (scale factor), 1 bit shifted 10 in second word 343 344 Places to put operand, for general operands: 345 d destination, shifted 6 bits in first word 346 b source, at low bit of first word, and immediate uses one byte 347 w source, at low bit of first word, and immediate uses two bytes 348 l source, at low bit of first word, and immediate uses four bytes 349 s source, at low bit of first word. 350 Used sometimes in contexts where immediate is not allowed anyway. 351 f single precision float, low bit of 1st word, immediate uses 4 bytes 352 F double precision float, low bit of 1st word, immediate uses 8 bytes 353 x extended precision float, low bit of 1st word, immediate uses 12 bytes 354 p packed float, low bit of 1st word, immediate uses 12 bytes 355 G EMAC accumulator, load (bit 4 2nd word, !bit8 first word) 356 H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word) 357 F EMAC ACCx 358 f EMAC ACCy 359 I MAC/EMAC scale factor 360 / Like 's', but set 2nd word, bit 5 if trailing_ampersand set 361 ] first word, bit 10 362*/ 363 364extern const struct m68k_opcode m68k_opcodes[]; 365extern const struct m68k_opcode_alias m68k_opcode_aliases[]; 366 367extern const int m68k_numopcodes, m68k_numaliases; 368 369/* end of m68k-opcode.h */ 370