1/* d30v.h -- Header file for D30V opcode table 2 Copyright 1997, 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. 3 Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions 4 5This file is part of GDB, GAS, and the GNU binutils. 6 7GDB, GAS, and the GNU binutils are free software; you can redistribute 8them and/or modify them under the terms of the GNU General Public 9License as published by the Free Software Foundation; either version 101, or (at your option) any later version. 11 12GDB, GAS, and the GNU binutils are distributed in the hope that they 13will be useful, but WITHOUT ANY WARRANTY; without even the implied 14warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 15the GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with this file; see the file COPYING. If not, write to the Free 19Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 20 21#ifndef D30V_H 22#define D30V_H 23 24#define NOP 0x00F00000 25 26/* Structure to hold information about predefined registers. */ 27struct pd_reg 28{ 29 char *name; /* name to recognize */ 30 char *pname; /* name to print for this register */ 31 int value; 32}; 33 34extern const struct pd_reg pre_defined_registers[]; 35int reg_name_cnt (void); 36 37/* the number of control registers */ 38#define MAX_CONTROL_REG 64 39 40/* define the format specifiers */ 41#define FM00 0 42#define FM01 0x80000000 43#define FM10 0x8000000000000000LL 44#define FM11 0x8000000080000000LL 45 46/* define the opcode classes */ 47#define BRA 0 48#define LOGIC 1 49#define IMEM 2 50#define IALU1 4 51#define IALU2 5 52 53/* define the execution condition codes */ 54#define ECC_AL 0 /* ALways (default) */ 55#define ECC_TX 1 /* F0=True, F1=Don't care */ 56#define ECC_FX 2 /* F0=False, F1=Don't care */ 57#define ECC_XT 3 /* F0=Don't care, F1=True */ 58#define ECC_XF 4 /* F0=Don't care, F1=False */ 59#define ECC_TT 5 /* F0=True, F1=True */ 60#define ECC_TF 6 /* F0=True, F1=False */ 61#define ECC_RESERVED 7 /* reserved */ 62#define ECC_MAX ECC_RESERVED 63 64extern const char *d30v_ecc_names[]; 65 66/* condition code table for CMP and CMPU */ 67extern const char *d30v_cc_names[]; 68 69/* The opcode table is an array of struct d30v_opcode. */ 70struct d30v_opcode 71{ 72 /* The opcode name. */ 73 const char *name; 74 75 /* the opcode */ 76 int op1; /* first part, "IALU1" for example */ 77 int op2; /* the rest of the opcode */ 78 79 /* opcode format(s). These numbers correspond to entries */ 80 /* in the d30v_format_table */ 81 unsigned char format[4]; 82 83#define SHORT_M 1 84#define SHORT_M2 5 /* for ld2w and st2w */ 85#define SHORT_A 9 86#define SHORT_B1 11 87#define SHORT_B2 12 88#define SHORT_B2r 13 89#define SHORT_B3 14 90#define SHORT_B3r 16 91#define SHORT_B3b 18 92#define SHORT_B3br 20 93#define SHORT_D1r 22 94#define SHORT_D2 24 95#define SHORT_D2r 26 96#define SHORT_D2Br 28 97#define SHORT_U 30 /* unary SHORT_A. ABS for example */ 98#define SHORT_F 31 /* SHORT_A with flag registers */ 99#define SHORT_AF 33 /* SHORT_A with only the first register a flag register */ 100#define SHORT_T 35 /* for trap instruction */ 101#define SHORT_A5 36 /* SHORT_A with a 5-bit immediate instead of 6 */ 102#define SHORT_CMP 38 /* special form for CMPcc */ 103#define SHORT_CMPU 40 /* special form for CMPUcc */ 104#define SHORT_A1 42 /* special form of SHORT_A for MACa opcodes where a=1 */ 105#define SHORT_AA 44 /* SHORT_A with the first register an accumulator */ 106#define SHORT_RA 46 /* SHORT_A with the second register an accumulator */ 107#define SHORT_MODINC 48 108#define SHORT_MODDEC 49 109#define SHORT_C1 50 110#define SHORT_C2 51 111#define SHORT_UF 52 112#define SHORT_A2 53 113#define SHORT_NONE 55 /* no operands */ 114#define SHORT_AR 56 /* like SHORT_AA but only accept register as third parameter */ 115#define LONG 57 116#define LONG_U 58 /* unary LONG */ 117#define LONG_Ur 59 /* LONG pc-relative */ 118#define LONG_CMP 60 /* special form for CMPcc and CMPUcc */ 119#define LONG_M 61 /* Memory long for ldb, stb */ 120#define LONG_M2 62 /* Memory long for ld2w, st2w */ 121#define LONG_2 63 /* LONG with 2 operands; jmptnz */ 122#define LONG_2r 64 /* LONG with 2 operands; bratnz */ 123#define LONG_2b 65 /* LONG_2 with modifier of 3 */ 124#define LONG_2br 66 /* LONG_2r with modifier of 3 */ 125#define LONG_D 67 /* for DJMPI */ 126#define LONG_Dr 68 /* for DBRAI */ 127#define LONG_Dbr 69 /* for repeati */ 128 129 /* the execution unit(s) used */ 130 int unit; 131#define EITHER 0 132#define IU 1 133#define MU 2 134#define EITHER_BUT_PREFER_MU 3 135 136 /* this field is used to decide if two instructions */ 137 /* can be executed in parallel */ 138 long flags_used; 139 long flags_set; 140#define FLAG_0 (1L<<0) 141#define FLAG_1 (1L<<1) 142#define FLAG_2 (1L<<2) 143#define FLAG_3 (1L<<3) 144#define FLAG_4 (1L<<4) /* S (saturation) */ 145#define FLAG_5 (1L<<5) /* V (overflow) */ 146#define FLAG_6 (1L<<6) /* VA (accumulated overflow) */ 147#define FLAG_7 (1L<<7) /* C (carry/borrow) */ 148#define FLAG_SM (1L<<8) /* SM (stack mode) */ 149#define FLAG_RP (1L<<9) /* RP (repeat enable) */ 150#define FLAG_CONTROL (1L<<10) /* control registers */ 151#define FLAG_A0 (1L<<11) /* A0 */ 152#define FLAG_A1 (1L<<12) /* A1 */ 153#define FLAG_JMP (1L<<13) /* instruction is a branch */ 154#define FLAG_JSR (1L<<14) /* subroutine call. must be aligned */ 155#define FLAG_MEM (1L<<15) /* reads/writes memory */ 156#define FLAG_NOT_WITH_ADDSUBppp (1L<<16) /* Old meaning: a 2 word 4 byter operation 157 New meaning: operation cannot be 158 combined in parallel with ADD/SUBppp. */ 159#define FLAG_MUL16 (1L<<17) /* 16 bit multiply */ 160#define FLAG_MUL32 (1L<<18) /* 32 bit multiply */ 161#define FLAG_ADDSUBppp (1L<<19) /* ADDppp or SUBppp */ 162#define FLAG_DELAY (1L<<20) /* This is a delayed branch or jump */ 163#define FLAG_LKR (1L<<21) /* insn in left slot kills right slot */ 164#define FLAG_CVVA (FLAG_5|FLAG_6|FLAG_7) 165#define FLAG_C FLAG_7 166#define FLAG_ALL (FLAG_0 | \ 167 FLAG_1 | \ 168 FLAG_2 | \ 169 FLAG_3 | \ 170 FLAG_4 | \ 171 FLAG_5 | \ 172 FLAG_6 | \ 173 FLAG_7 | \ 174 FLAG_SM | \ 175 FLAG_RP | \ 176 FLAG_CONTROL) 177 178 int reloc_flag; 179#define RELOC_PCREL 1 180#define RELOC_ABS 2 181}; 182 183extern const struct d30v_opcode d30v_opcode_table[]; 184extern const int d30v_num_opcodes; 185 186/* The operands table is an array of struct d30v_operand. */ 187struct d30v_operand 188{ 189 /* the length of the field */ 190 int length; 191 192 /* The number of significant bits in the operand. */ 193 int bits; 194 195 /* position relative to Ra */ 196 int position; 197 198 /* syntax flags. */ 199 long flags; 200}; 201extern const struct d30v_operand d30v_operand_table[]; 202 203/* Values defined for the flags field of a struct d30v_operand. */ 204 205/* this is the destination register; it will be modified */ 206/* this is used by the optimizer */ 207#define OPERAND_DEST (1) 208 209/* number or symbol */ 210#define OPERAND_NUM (2) 211 212/* address or label */ 213#define OPERAND_ADDR (4) 214 215/* register */ 216#define OPERAND_REG (8) 217 218/* postincrement + */ 219#define OPERAND_PLUS (0x10) 220 221/* postdecrement - */ 222#define OPERAND_MINUS (0x20) 223 224/* signed number */ 225#define OPERAND_SIGNED (0x40) 226 227/* this operand must be shifted left by 3 */ 228#define OPERAND_SHIFT (0x80) 229 230/* flag register */ 231#define OPERAND_FLAG (0x100) 232 233/* control register */ 234#define OPERAND_CONTROL (0x200) 235 236/* accumulator */ 237#define OPERAND_ACC (0x400) 238 239/* @ */ 240#define OPERAND_ATSIGN (0x800) 241 242/* @( */ 243#define OPERAND_ATPAR (0x1000) 244 245/* predecrement mode '@-sp' */ 246#define OPERAND_ATMINUS (0x2000) 247 248/* this operand changes the instruction name */ 249/* for example, CPMcc, CMPUcc */ 250#define OPERAND_NAME (0x4000) 251 252/* fake operand for mvtsys and mvfsys */ 253#define OPERAND_SPECIAL (0x8000) 254 255/* let the optimizer know that two registers are affected */ 256#define OPERAND_2REG (0x10000) 257 258/* This operand is pc-relative. Note that repeati can have two immediate 259 operands, one of which is pcrel, the other (the IMM6U one) is not. */ 260#define OPERAND_PCREL (0x20000) 261 262/* The format table is an array of struct d30v_format. */ 263struct d30v_format 264{ 265 int form; /* SHORT_A, LONG, etc */ 266 int modifier; /* two bit modifier following opcode */ 267 unsigned char operands[5]; 268}; 269extern const struct d30v_format d30v_format_table[]; 270 271 272/* an instruction is defined by an opcode and a format */ 273/* for example, "add" has one opcode, but three different */ 274/* formats, 2 SHORT_A forms and a LONG form. */ 275struct d30v_insn 276{ 277 struct d30v_opcode *op; /* pointer to an entry in the opcode table */ 278 struct d30v_format *form; /* pointer to an entry in the format table */ 279 int ecc; /* execution condition code */ 280}; 281 282/* an expressionS only has one register type, so we fake it */ 283/* by setting high bits to indicate type */ 284#define REGISTER_MASK 0xFF 285 286#endif /* D30V_H */ 287