1" Vim syntax file
2" Language:	Verilog
3" Maintainer:	Mun Johl <Mun.Johl@emulex.com>
4" Last Update:  Fri Oct 13 11:44:32 PDT 2006
5
6" For version 5.x: Clear all syntax items
7" For version 6.x: Quit when a syntax file was already loaded
8if version < 600
9   syntax clear
10elseif exists("b:current_syntax")
11   finish
12endif
13
14" Set the local value of the 'iskeyword' option
15if version >= 600
16   setlocal iskeyword=@,48-57,_,192-255
17else
18   set iskeyword=@,48-57,_,192-255
19endif
20
21" A bunch of useful Verilog keywords
22
23syn keyword verilogStatement   always and assign automatic buf
24syn keyword verilogStatement   bufif0 bufif1 cell cmos
25syn keyword verilogStatement   config deassign defparam design
26syn keyword verilogStatement   disable edge endconfig
27syn keyword verilogStatement   endfunction endgenerate endmodule
28syn keyword verilogStatement   endprimitive endspecify endtable endtask
29syn keyword verilogStatement   event force function
30syn keyword verilogStatement   generate genvar highz0 highz1 ifnone
31syn keyword verilogStatement   incdir include initial inout input
32syn keyword verilogStatement   instance integer large liblist
33syn keyword verilogStatement   library localparam macromodule medium
34syn keyword verilogStatement   module nand negedge nmos nor
35syn keyword verilogStatement   noshowcancelled not notif0 notif1 or
36syn keyword verilogStatement   output parameter pmos posedge primitive
37syn keyword verilogStatement   pull0 pull1 pulldown pullup
38syn keyword verilogStatement   pulsestyle_onevent pulsestyle_ondetect
39syn keyword verilogStatement   rcmos real realtime reg release
40syn keyword verilogStatement   rnmos rpmos rtran rtranif0 rtranif1
41syn keyword verilogStatement   scalared showcancelled signed small
42syn keyword verilogStatement   specify specparam strong0 strong1
43syn keyword verilogStatement   supply0 supply1 table task time tran
44syn keyword verilogStatement   tranif0 tranif1 tri tri0 tri1 triand
45syn keyword verilogStatement   trior trireg unsigned use vectored wait
46syn keyword verilogStatement   wand weak0 weak1 wire wor xnor xor
47syn keyword verilogLabel       begin end fork join
48syn keyword verilogConditional if else case casex casez default endcase
49syn keyword verilogRepeat      forever repeat while for
50
51syn keyword verilogTodo contained TODO
52
53syn match   verilogOperator "[&|~><!)(*#%@+/=?:;}{,.\^\-\[\]]"
54
55syn region  verilogComment start="/\*" end="\*/" contains=verilogTodo,@Spell
56syn match   verilogComment "//.*" contains=verilogTodo,@Spell
57
58"syn match   verilogGlobal "`[a-zA-Z0-9_]\+\>"
59syn match verilogGlobal "`celldefine"
60syn match verilogGlobal "`default_nettype"
61syn match verilogGlobal "`define"
62syn match verilogGlobal "`else"
63syn match verilogGlobal "`elsif"
64syn match verilogGlobal "`endcelldefine"
65syn match verilogGlobal "`endif"
66syn match verilogGlobal "`ifdef"
67syn match verilogGlobal "`ifndef"
68syn match verilogGlobal "`include"
69syn match verilogGlobal "`line"
70syn match verilogGlobal "`nounconnected_drive"
71syn match verilogGlobal "`resetall"
72syn match verilogGlobal "`timescale"
73syn match verilogGlobal "`unconnected_drive"
74syn match verilogGlobal "`undef"
75syn match   verilogGlobal "$[a-zA-Z0-9_]\+\>"
76
77syn match   verilogConstant "\<[A-Z][A-Z0-9_]\+\>"
78
79syn match   verilogNumber "\(\<\d\+\|\)'[sS]\?[bB]\s*[0-1_xXzZ?]\+\>"
80syn match   verilogNumber "\(\<\d\+\|\)'[sS]\?[oO]\s*[0-7_xXzZ?]\+\>"
81syn match   verilogNumber "\(\<\d\+\|\)'[sS]\?[dD]\s*[0-9_xXzZ?]\+\>"
82syn match   verilogNumber "\(\<\d\+\|\)'[sS]\?[hH]\s*[0-9a-fA-F_xXzZ?]\+\>"
83syn match   verilogNumber "\<[+-]\=[0-9_]\+\(\.[0-9_]*\|\)\(e[0-9_]*\|\)\>"
84
85syn region  verilogString start=+"+ skip=+\\"+ end=+"+ contains=verilogEscape,@Spell
86syn match   verilogEscape +\\[nt"\\]+ contained
87syn match   verilogEscape "\\\o\o\=\o\=" contained
88
89" Directives
90syn match   verilogDirective   "//\s*synopsys\>.*$"
91syn region  verilogDirective   start="/\*\s*synopsys\>" end="\*/"
92syn region  verilogDirective   start="//\s*synopsys dc_script_begin\>" end="//\s*synopsys dc_script_end\>"
93
94syn match   verilogDirective   "//\s*\$s\>.*$"
95syn region  verilogDirective   start="/\*\s*\$s\>" end="\*/"
96syn region  verilogDirective   start="//\s*\$s dc_script_begin\>" end="//\s*\$s dc_script_end\>"
97
98"Modify the following as needed.  The trade-off is performance versus
99"functionality.
100syn sync minlines=50
101
102" Define the default highlighting.
103" For version 5.7 and earlier: only when not done already
104" For version 5.8 and later: only when an item doesn't have highlighting yet
105if version >= 508 || !exists("did_verilog_syn_inits")
106   if version < 508
107      let did_verilog_syn_inits = 1
108      command -nargs=+ HiLink hi link <args>
109   else
110      command -nargs=+ HiLink hi def link <args>
111   endif
112
113   " The default highlighting.
114   HiLink verilogCharacter       Character
115   HiLink verilogConditional     Conditional
116   HiLink verilogRepeat		 Repeat
117   HiLink verilogString		 String
118   HiLink verilogTodo		 Todo
119   HiLink verilogComment	 Comment
120   HiLink verilogConstant	 Constant
121   HiLink verilogLabel		 Label
122   HiLink verilogNumber		 Number
123   HiLink verilogOperator	 Special
124   HiLink verilogStatement	 Statement
125   HiLink verilogGlobal		 Define
126   HiLink verilogDirective	 SpecialComment
127   HiLink verilogEscape		 Special
128
129   delcommand HiLink
130endif
131
132let b:current_syntax = "verilog"
133
134" vim: ts=8
135