1//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the X86 specific subclass of TargetMachine. 11// 12//===----------------------------------------------------------------------===// 13 14#include "X86TargetMachine.h" 15#include "X86.h" 16#include "llvm/PassManager.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/Passes.h" 19#include "llvm/Support/CommandLine.h" 20#include "llvm/Support/FormattedStream.h" 21#include "llvm/Target/TargetOptions.h" 22#include "llvm/Support/TargetRegistry.h" 23using namespace llvm; 24 25extern "C" void LLVMInitializeX86Target() { 26 // Register the target. 27 RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target); 28 RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target); 29} 30 31void X86_32TargetMachine::anchor() { } 32 33X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT, 34 StringRef CPU, StringRef FS, 35 const TargetOptions &Options, 36 Reloc::Model RM, CodeModel::Model CM, 37 CodeGenOpt::Level OL) 38 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false), 39 DataLayout(getSubtargetImpl()->isTargetDarwin() ? 40 "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-" 41 "n8:16:32-S128" : 42 (getSubtargetImpl()->isTargetCygMing() || 43 getSubtargetImpl()->isTargetWindows()) ? 44 "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-" 45 "n8:16:32-S32" : 46 "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-" 47 "n8:16:32-S128"), 48 InstrInfo(*this), 49 TSInfo(*this), 50 TLInfo(*this), 51 JITInfo(*this) { 52} 53 54void X86_64TargetMachine::anchor() { } 55 56X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT, 57 StringRef CPU, StringRef FS, 58 const TargetOptions &Options, 59 Reloc::Model RM, CodeModel::Model CM, 60 CodeGenOpt::Level OL) 61 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true), 62 DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-" 63 "n8:16:32:64-S128"), 64 InstrInfo(*this), 65 TSInfo(*this), 66 TLInfo(*this), 67 JITInfo(*this) { 68} 69 70/// X86TargetMachine ctor - Create an X86 target. 71/// 72X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, 73 StringRef CPU, StringRef FS, 74 const TargetOptions &Options, 75 Reloc::Model RM, CodeModel::Model CM, 76 CodeGenOpt::Level OL, 77 bool is64Bit) 78 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 79 Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit), 80 FrameLowering(*this, Subtarget), 81 ELFWriterInfo(is64Bit, true), 82 InstrItins(Subtarget.getInstrItineraryData()){ 83 // Determine the PICStyle based on the target selected. 84 if (getRelocationModel() == Reloc::Static) { 85 // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None. 86 Subtarget.setPICStyle(PICStyles::None); 87 } else if (Subtarget.is64Bit()) { 88 // PIC in 64 bit mode is always rip-rel. 89 Subtarget.setPICStyle(PICStyles::RIPRel); 90 } else if (Subtarget.isTargetCygMing()) { 91 Subtarget.setPICStyle(PICStyles::None); 92 } else if (Subtarget.isTargetDarwin()) { 93 if (getRelocationModel() == Reloc::PIC_) 94 Subtarget.setPICStyle(PICStyles::StubPIC); 95 else { 96 assert(getRelocationModel() == Reloc::DynamicNoPIC); 97 Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC); 98 } 99 } else if (Subtarget.isTargetELF()) { 100 Subtarget.setPICStyle(PICStyles::GOT); 101 } 102 103 // default to hard float ABI 104 if (Options.FloatABIType == FloatABI::Default) 105 this->Options.FloatABIType = FloatABI::Hard; 106} 107 108//===----------------------------------------------------------------------===// 109// Command line options for x86 110//===----------------------------------------------------------------------===// 111static cl::opt<bool> 112UseVZeroUpper("x86-use-vzeroupper", 113 cl::desc("Minimize AVX to SSE transition penalty"), 114 cl::init(true)); 115 116// Temporary option to control early if-conversion for x86 while adding machine 117// models. 118static cl::opt<bool> 119X86EarlyIfConv("x86-early-ifcvt", 120 cl::desc("Enable early if-conversion on X86")); 121 122//===----------------------------------------------------------------------===// 123// Pass Pipeline Configuration 124//===----------------------------------------------------------------------===// 125 126namespace { 127/// X86 Code Generator Pass Configuration Options. 128class X86PassConfig : public TargetPassConfig { 129public: 130 X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM) 131 : TargetPassConfig(TM, PM) {} 132 133 X86TargetMachine &getX86TargetMachine() const { 134 return getTM<X86TargetMachine>(); 135 } 136 137 const X86Subtarget &getX86Subtarget() const { 138 return *getX86TargetMachine().getSubtargetImpl(); 139 } 140 141 virtual bool addInstSelector(); 142 virtual bool addPreRegAlloc(); 143 virtual bool addPostRegAlloc(); 144 virtual bool addPreEmitPass(); 145}; 146} // namespace 147 148TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) { 149 X86PassConfig *PC = new X86PassConfig(this, PM); 150 151 if (X86EarlyIfConv && Subtarget.hasCMov()) 152 PC->enablePass(&EarlyIfConverterID); 153 154 return PC; 155} 156 157bool X86PassConfig::addInstSelector() { 158 // Install an instruction selector. 159 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel())); 160 161 // For ELF, cleanup any local-dynamic TLS accesses. 162 if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None) 163 addPass(createCleanupLocalDynamicTLSPass()); 164 165 // For 32-bit, prepend instructions to set the "global base reg" for PIC. 166 if (!getX86Subtarget().is64Bit()) 167 addPass(createGlobalBaseRegPass()); 168 169 return false; 170} 171 172bool X86PassConfig::addPreRegAlloc() { 173 addPass(createX86MaxStackAlignmentHeuristicPass()); 174 return false; // -print-machineinstr shouldn't print after this. 175} 176 177bool X86PassConfig::addPostRegAlloc() { 178 addPass(createX86FloatingPointStackifierPass()); 179 return true; // -print-machineinstr should print after this. 180} 181 182bool X86PassConfig::addPreEmitPass() { 183 bool ShouldPrint = false; 184 if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) { 185 addPass(createExecutionDependencyFixPass(&X86::VR128RegClass)); 186 ShouldPrint = true; 187 } 188 189 if (getX86Subtarget().hasAVX() && UseVZeroUpper) { 190 addPass(createX86IssueVZeroUpperPass()); 191 ShouldPrint = true; 192 } 193 194 return ShouldPrint; 195} 196 197bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, 198 JITCodeEmitter &JCE) { 199 PM.add(createX86JITCodeEmitterPass(*this, JCE)); 200 201 return false; 202} 203