1//===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Instruction Itinerary classes used for X86 12def IIC_DEFAULT : InstrItinClass; 13def IIC_ALU_MEM : InstrItinClass; 14def IIC_ALU_NONMEM : InstrItinClass; 15def IIC_LEA : InstrItinClass; 16def IIC_LEA_16 : InstrItinClass; 17def IIC_MUL8 : InstrItinClass; 18def IIC_MUL16_MEM : InstrItinClass; 19def IIC_MUL16_REG : InstrItinClass; 20def IIC_MUL32_MEM : InstrItinClass; 21def IIC_MUL32_REG : InstrItinClass; 22def IIC_MUL64 : InstrItinClass; 23// imul by al, ax, eax, tax 24def IIC_IMUL8 : InstrItinClass; 25def IIC_IMUL16_MEM : InstrItinClass; 26def IIC_IMUL16_REG : InstrItinClass; 27def IIC_IMUL32_MEM : InstrItinClass; 28def IIC_IMUL32_REG : InstrItinClass; 29def IIC_IMUL64 : InstrItinClass; 30// imul reg by reg|mem 31def IIC_IMUL16_RM : InstrItinClass; 32def IIC_IMUL16_RR : InstrItinClass; 33def IIC_IMUL32_RM : InstrItinClass; 34def IIC_IMUL32_RR : InstrItinClass; 35def IIC_IMUL64_RM : InstrItinClass; 36def IIC_IMUL64_RR : InstrItinClass; 37// imul reg = reg/mem * imm 38def IIC_IMUL16_RMI : InstrItinClass; 39def IIC_IMUL16_RRI : InstrItinClass; 40def IIC_IMUL32_RMI : InstrItinClass; 41def IIC_IMUL32_RRI : InstrItinClass; 42def IIC_IMUL64_RMI : InstrItinClass; 43def IIC_IMUL64_RRI : InstrItinClass; 44// div 45def IIC_DIV8_MEM : InstrItinClass; 46def IIC_DIV8_REG : InstrItinClass; 47def IIC_DIV16 : InstrItinClass; 48def IIC_DIV32 : InstrItinClass; 49def IIC_DIV64 : InstrItinClass; 50// idiv 51def IIC_IDIV8 : InstrItinClass; 52def IIC_IDIV16 : InstrItinClass; 53def IIC_IDIV32 : InstrItinClass; 54def IIC_IDIV64 : InstrItinClass; 55// neg/not/inc/dec 56def IIC_UNARY_REG : InstrItinClass; 57def IIC_UNARY_MEM : InstrItinClass; 58// add/sub/and/or/xor/adc/sbc/cmp/test 59def IIC_BIN_MEM : InstrItinClass; 60def IIC_BIN_NONMEM : InstrItinClass; 61// shift/rotate 62def IIC_SR : InstrItinClass; 63// shift double 64def IIC_SHD16_REG_IM : InstrItinClass; 65def IIC_SHD16_REG_CL : InstrItinClass; 66def IIC_SHD16_MEM_IM : InstrItinClass; 67def IIC_SHD16_MEM_CL : InstrItinClass; 68def IIC_SHD32_REG_IM : InstrItinClass; 69def IIC_SHD32_REG_CL : InstrItinClass; 70def IIC_SHD32_MEM_IM : InstrItinClass; 71def IIC_SHD32_MEM_CL : InstrItinClass; 72def IIC_SHD64_REG_IM : InstrItinClass; 73def IIC_SHD64_REG_CL : InstrItinClass; 74def IIC_SHD64_MEM_IM : InstrItinClass; 75def IIC_SHD64_MEM_CL : InstrItinClass; 76// cmov 77def IIC_CMOV16_RM : InstrItinClass; 78def IIC_CMOV16_RR : InstrItinClass; 79def IIC_CMOV32_RM : InstrItinClass; 80def IIC_CMOV32_RR : InstrItinClass; 81def IIC_CMOV64_RM : InstrItinClass; 82def IIC_CMOV64_RR : InstrItinClass; 83// set 84def IIC_SET_R : InstrItinClass; 85def IIC_SET_M : InstrItinClass; 86// jmp/jcc/jcxz 87def IIC_Jcc : InstrItinClass; 88def IIC_JCXZ : InstrItinClass; 89def IIC_JMP_REL : InstrItinClass; 90def IIC_JMP_REG : InstrItinClass; 91def IIC_JMP_MEM : InstrItinClass; 92def IIC_JMP_FAR_MEM : InstrItinClass; 93def IIC_JMP_FAR_PTR : InstrItinClass; 94// loop 95def IIC_LOOP : InstrItinClass; 96def IIC_LOOPE : InstrItinClass; 97def IIC_LOOPNE : InstrItinClass; 98// call 99def IIC_CALL_RI : InstrItinClass; 100def IIC_CALL_MEM : InstrItinClass; 101def IIC_CALL_FAR_MEM : InstrItinClass; 102def IIC_CALL_FAR_PTR : InstrItinClass; 103// ret 104def IIC_RET : InstrItinClass; 105def IIC_RET_IMM : InstrItinClass; 106//sign extension movs 107def IIC_MOVSX : InstrItinClass; 108def IIC_MOVSX_R16_R8 : InstrItinClass; 109def IIC_MOVSX_R16_M8 : InstrItinClass; 110def IIC_MOVSX_R16_R16 : InstrItinClass; 111def IIC_MOVSX_R32_R32 : InstrItinClass; 112//zero extension movs 113def IIC_MOVZX : InstrItinClass; 114def IIC_MOVZX_R16_R8 : InstrItinClass; 115def IIC_MOVZX_R16_M8 : InstrItinClass; 116 117def IIC_REP_MOVS : InstrItinClass; 118def IIC_REP_STOS : InstrItinClass; 119 120// SSE scalar/parallel binary operations 121def IIC_SSE_ALU_F32S_RR : InstrItinClass; 122def IIC_SSE_ALU_F32S_RM : InstrItinClass; 123def IIC_SSE_ALU_F64S_RR : InstrItinClass; 124def IIC_SSE_ALU_F64S_RM : InstrItinClass; 125def IIC_SSE_MUL_F32S_RR : InstrItinClass; 126def IIC_SSE_MUL_F32S_RM : InstrItinClass; 127def IIC_SSE_MUL_F64S_RR : InstrItinClass; 128def IIC_SSE_MUL_F64S_RM : InstrItinClass; 129def IIC_SSE_DIV_F32S_RR : InstrItinClass; 130def IIC_SSE_DIV_F32S_RM : InstrItinClass; 131def IIC_SSE_DIV_F64S_RR : InstrItinClass; 132def IIC_SSE_DIV_F64S_RM : InstrItinClass; 133def IIC_SSE_ALU_F32P_RR : InstrItinClass; 134def IIC_SSE_ALU_F32P_RM : InstrItinClass; 135def IIC_SSE_ALU_F64P_RR : InstrItinClass; 136def IIC_SSE_ALU_F64P_RM : InstrItinClass; 137def IIC_SSE_MUL_F32P_RR : InstrItinClass; 138def IIC_SSE_MUL_F32P_RM : InstrItinClass; 139def IIC_SSE_MUL_F64P_RR : InstrItinClass; 140def IIC_SSE_MUL_F64P_RM : InstrItinClass; 141def IIC_SSE_DIV_F32P_RR : InstrItinClass; 142def IIC_SSE_DIV_F32P_RM : InstrItinClass; 143def IIC_SSE_DIV_F64P_RR : InstrItinClass; 144def IIC_SSE_DIV_F64P_RM : InstrItinClass; 145 146def IIC_SSE_COMIS_RR : InstrItinClass; 147def IIC_SSE_COMIS_RM : InstrItinClass; 148 149def IIC_SSE_HADDSUB_RR : InstrItinClass; 150def IIC_SSE_HADDSUB_RM : InstrItinClass; 151 152def IIC_SSE_BIT_P_RR : InstrItinClass; 153def IIC_SSE_BIT_P_RM : InstrItinClass; 154 155def IIC_SSE_INTALU_P_RR : InstrItinClass; 156def IIC_SSE_INTALU_P_RM : InstrItinClass; 157def IIC_SSE_INTALUQ_P_RR : InstrItinClass; 158def IIC_SSE_INTALUQ_P_RM : InstrItinClass; 159 160def IIC_SSE_INTMUL_P_RR : InstrItinClass; 161def IIC_SSE_INTMUL_P_RM : InstrItinClass; 162 163def IIC_SSE_INTSH_P_RR : InstrItinClass; 164def IIC_SSE_INTSH_P_RM : InstrItinClass; 165def IIC_SSE_INTSH_P_RI : InstrItinClass; 166 167def IIC_SSE_CMPP_RR : InstrItinClass; 168def IIC_SSE_CMPP_RM : InstrItinClass; 169 170def IIC_SSE_SHUFP : InstrItinClass; 171def IIC_SSE_PSHUF : InstrItinClass; 172 173def IIC_SSE_UNPCK : InstrItinClass; 174 175def IIC_SSE_MOVMSK : InstrItinClass; 176def IIC_SSE_MASKMOV : InstrItinClass; 177 178def IIC_SSE_PEXTRW : InstrItinClass; 179def IIC_SSE_PINSRW : InstrItinClass; 180 181def IIC_SSE_PABS_RR : InstrItinClass; 182def IIC_SSE_PABS_RM : InstrItinClass; 183 184def IIC_SSE_SQRTP_RR : InstrItinClass; 185def IIC_SSE_SQRTP_RM : InstrItinClass; 186def IIC_SSE_SQRTS_RR : InstrItinClass; 187def IIC_SSE_SQRTS_RM : InstrItinClass; 188 189def IIC_SSE_RCPP_RR : InstrItinClass; 190def IIC_SSE_RCPP_RM : InstrItinClass; 191def IIC_SSE_RCPS_RR : InstrItinClass; 192def IIC_SSE_RCPS_RM : InstrItinClass; 193 194def IIC_SSE_MOV_S_RR : InstrItinClass; 195def IIC_SSE_MOV_S_RM : InstrItinClass; 196def IIC_SSE_MOV_S_MR : InstrItinClass; 197 198def IIC_SSE_MOVA_P_RR : InstrItinClass; 199def IIC_SSE_MOVA_P_RM : InstrItinClass; 200def IIC_SSE_MOVA_P_MR : InstrItinClass; 201 202def IIC_SSE_MOVU_P_RR : InstrItinClass; 203def IIC_SSE_MOVU_P_RM : InstrItinClass; 204def IIC_SSE_MOVU_P_MR : InstrItinClass; 205 206def IIC_SSE_MOVDQ : InstrItinClass; 207def IIC_SSE_MOVD_ToGP : InstrItinClass; 208def IIC_SSE_MOVQ_RR : InstrItinClass; 209 210def IIC_SSE_MOV_LH : InstrItinClass; 211 212def IIC_SSE_LDDQU : InstrItinClass; 213 214def IIC_SSE_MOVNT : InstrItinClass; 215 216def IIC_SSE_PHADDSUBD_RR : InstrItinClass; 217def IIC_SSE_PHADDSUBD_RM : InstrItinClass; 218def IIC_SSE_PHADDSUBSW_RR : InstrItinClass; 219def IIC_SSE_PHADDSUBSW_RM : InstrItinClass; 220def IIC_SSE_PHADDSUBW_RR : InstrItinClass; 221def IIC_SSE_PHADDSUBW_RM : InstrItinClass; 222def IIC_SSE_PSHUFB_RR : InstrItinClass; 223def IIC_SSE_PSHUFB_RM : InstrItinClass; 224def IIC_SSE_PSIGN_RR : InstrItinClass; 225def IIC_SSE_PSIGN_RM : InstrItinClass; 226 227def IIC_SSE_PMADD : InstrItinClass; 228def IIC_SSE_PMULHRSW : InstrItinClass; 229def IIC_SSE_PALIGNR : InstrItinClass; 230def IIC_SSE_MWAIT : InstrItinClass; 231def IIC_SSE_MONITOR : InstrItinClass; 232 233def IIC_SSE_PREFETCH : InstrItinClass; 234def IIC_SSE_PAUSE : InstrItinClass; 235def IIC_SSE_LFENCE : InstrItinClass; 236def IIC_SSE_MFENCE : InstrItinClass; 237def IIC_SSE_SFENCE : InstrItinClass; 238def IIC_SSE_LDMXCSR : InstrItinClass; 239def IIC_SSE_STMXCSR : InstrItinClass; 240 241def IIC_SSE_CVT_PD_RR : InstrItinClass; 242def IIC_SSE_CVT_PD_RM : InstrItinClass; 243def IIC_SSE_CVT_PS_RR : InstrItinClass; 244def IIC_SSE_CVT_PS_RM : InstrItinClass; 245def IIC_SSE_CVT_PI2PS_RR : InstrItinClass; 246def IIC_SSE_CVT_PI2PS_RM : InstrItinClass; 247def IIC_SSE_CVT_Scalar_RR : InstrItinClass; 248def IIC_SSE_CVT_Scalar_RM : InstrItinClass; 249def IIC_SSE_CVT_SS2SI32_RM : InstrItinClass; 250def IIC_SSE_CVT_SS2SI32_RR : InstrItinClass; 251def IIC_SSE_CVT_SS2SI64_RM : InstrItinClass; 252def IIC_SSE_CVT_SS2SI64_RR : InstrItinClass; 253def IIC_SSE_CVT_SD2SI_RM : InstrItinClass; 254def IIC_SSE_CVT_SD2SI_RR : InstrItinClass; 255 256// MMX 257def IIC_MMX_MOV_MM_RM : InstrItinClass; 258def IIC_MMX_MOV_REG_MM : InstrItinClass; 259def IIC_MMX_MOVQ_RM : InstrItinClass; 260def IIC_MMX_MOVQ_RR : InstrItinClass; 261 262def IIC_MMX_ALU_RM : InstrItinClass; 263def IIC_MMX_ALU_RR : InstrItinClass; 264def IIC_MMX_ALUQ_RM : InstrItinClass; 265def IIC_MMX_ALUQ_RR : InstrItinClass; 266def IIC_MMX_PHADDSUBW_RM : InstrItinClass; 267def IIC_MMX_PHADDSUBW_RR : InstrItinClass; 268def IIC_MMX_PHADDSUBD_RM : InstrItinClass; 269def IIC_MMX_PHADDSUBD_RR : InstrItinClass; 270def IIC_MMX_PMUL : InstrItinClass; 271def IIC_MMX_MISC_FUNC_MEM : InstrItinClass; 272def IIC_MMX_MISC_FUNC_REG : InstrItinClass; 273def IIC_MMX_PSADBW : InstrItinClass; 274def IIC_MMX_SHIFT_RI : InstrItinClass; 275def IIC_MMX_SHIFT_RM : InstrItinClass; 276def IIC_MMX_SHIFT_RR : InstrItinClass; 277def IIC_MMX_UNPCK_H_RM : InstrItinClass; 278def IIC_MMX_UNPCK_H_RR : InstrItinClass; 279def IIC_MMX_UNPCK_L : InstrItinClass; 280def IIC_MMX_PCK_RM : InstrItinClass; 281def IIC_MMX_PCK_RR : InstrItinClass; 282def IIC_MMX_PSHUF : InstrItinClass; 283def IIC_MMX_PEXTR : InstrItinClass; 284def IIC_MMX_PINSRW : InstrItinClass; 285def IIC_MMX_MASKMOV : InstrItinClass; 286 287def IIC_MMX_CVT_PD_RR : InstrItinClass; 288def IIC_MMX_CVT_PD_RM : InstrItinClass; 289def IIC_MMX_CVT_PS_RR : InstrItinClass; 290def IIC_MMX_CVT_PS_RM : InstrItinClass; 291 292def IIC_CMPX_LOCK : InstrItinClass; 293def IIC_CMPX_LOCK_8 : InstrItinClass; 294def IIC_CMPX_LOCK_8B : InstrItinClass; 295def IIC_CMPX_LOCK_16B : InstrItinClass; 296 297def IIC_XADD_LOCK_MEM : InstrItinClass; 298def IIC_XADD_LOCK_MEM8 : InstrItinClass; 299 300def IIC_FILD : InstrItinClass; 301def IIC_FLD : InstrItinClass; 302def IIC_FLD80 : InstrItinClass; 303def IIC_FST : InstrItinClass; 304def IIC_FST80 : InstrItinClass; 305def IIC_FIST : InstrItinClass; 306def IIC_FLDZ : InstrItinClass; 307def IIC_FUCOM : InstrItinClass; 308def IIC_FUCOMI : InstrItinClass; 309def IIC_FCOMI : InstrItinClass; 310def IIC_FNSTSW : InstrItinClass; 311def IIC_FNSTCW : InstrItinClass; 312def IIC_FLDCW : InstrItinClass; 313def IIC_FNINIT : InstrItinClass; 314def IIC_FFREE : InstrItinClass; 315def IIC_FNCLEX : InstrItinClass; 316def IIC_WAIT : InstrItinClass; 317def IIC_FXAM : InstrItinClass; 318def IIC_FNOP : InstrItinClass; 319def IIC_FLDL : InstrItinClass; 320def IIC_F2XM1 : InstrItinClass; 321def IIC_FYL2X : InstrItinClass; 322def IIC_FPTAN : InstrItinClass; 323def IIC_FPATAN : InstrItinClass; 324def IIC_FXTRACT : InstrItinClass; 325def IIC_FPREM1 : InstrItinClass; 326def IIC_FPSTP : InstrItinClass; 327def IIC_FPREM : InstrItinClass; 328def IIC_FYL2XP1 : InstrItinClass; 329def IIC_FSINCOS : InstrItinClass; 330def IIC_FRNDINT : InstrItinClass; 331def IIC_FSCALE : InstrItinClass; 332def IIC_FCOMPP : InstrItinClass; 333def IIC_FXSAVE : InstrItinClass; 334def IIC_FXRSTOR : InstrItinClass; 335 336def IIC_FXCH : InstrItinClass; 337 338// System instructions 339def IIC_CPUID : InstrItinClass; 340def IIC_INT : InstrItinClass; 341def IIC_INT3 : InstrItinClass; 342def IIC_INVD : InstrItinClass; 343def IIC_INVLPG : InstrItinClass; 344def IIC_IRET : InstrItinClass; 345def IIC_HLT : InstrItinClass; 346def IIC_LXS : InstrItinClass; 347def IIC_LTR : InstrItinClass; 348def IIC_RDTSC : InstrItinClass; 349def IIC_RSM : InstrItinClass; 350def IIC_SIDT : InstrItinClass; 351def IIC_SGDT : InstrItinClass; 352def IIC_SLDT : InstrItinClass; 353def IIC_STR : InstrItinClass; 354def IIC_SWAPGS : InstrItinClass; 355def IIC_SYSCALL : InstrItinClass; 356def IIC_SYS_ENTER_EXIT : InstrItinClass; 357def IIC_IN_RR : InstrItinClass; 358def IIC_IN_RI : InstrItinClass; 359def IIC_OUT_RR : InstrItinClass; 360def IIC_OUT_IR : InstrItinClass; 361def IIC_INS : InstrItinClass; 362def IIC_MOV_REG_DR : InstrItinClass; 363def IIC_MOV_DR_REG : InstrItinClass; 364def IIC_MOV_REG_CR : InstrItinClass; 365def IIC_MOV_CR_REG : InstrItinClass; 366def IIC_MOV_REG_SR : InstrItinClass; 367def IIC_MOV_MEM_SR : InstrItinClass; 368def IIC_MOV_SR_REG : InstrItinClass; 369def IIC_MOV_SR_MEM : InstrItinClass; 370def IIC_LAR_RM : InstrItinClass; 371def IIC_LAR_RR : InstrItinClass; 372def IIC_LSL_RM : InstrItinClass; 373def IIC_LSL_RR : InstrItinClass; 374def IIC_LGDT : InstrItinClass; 375def IIC_LIDT : InstrItinClass; 376def IIC_LLDT_REG : InstrItinClass; 377def IIC_LLDT_MEM : InstrItinClass; 378def IIC_PUSH_CS : InstrItinClass; 379def IIC_PUSH_SR : InstrItinClass; 380def IIC_POP_SR : InstrItinClass; 381def IIC_POP_SR_SS : InstrItinClass; 382def IIC_VERR : InstrItinClass; 383def IIC_VERW_REG : InstrItinClass; 384def IIC_VERW_MEM : InstrItinClass; 385def IIC_WRMSR : InstrItinClass; 386def IIC_RDMSR : InstrItinClass; 387def IIC_RDPMC : InstrItinClass; 388def IIC_SMSW : InstrItinClass; 389def IIC_LMSW_REG : InstrItinClass; 390def IIC_LMSW_MEM : InstrItinClass; 391def IIC_ENTER : InstrItinClass; 392def IIC_LEAVE : InstrItinClass; 393def IIC_POP_MEM : InstrItinClass; 394def IIC_POP_REG16 : InstrItinClass; 395def IIC_POP_REG : InstrItinClass; 396def IIC_POP_F : InstrItinClass; 397def IIC_POP_FD : InstrItinClass; 398def IIC_POP_A : InstrItinClass; 399def IIC_PUSH_IMM : InstrItinClass; 400def IIC_PUSH_MEM : InstrItinClass; 401def IIC_PUSH_REG : InstrItinClass; 402def IIC_PUSH_F : InstrItinClass; 403def IIC_PUSH_A : InstrItinClass; 404def IIC_BSWAP : InstrItinClass; 405def IIC_BSF : InstrItinClass; 406def IIC_BSR : InstrItinClass; 407def IIC_MOVS : InstrItinClass; 408def IIC_STOS : InstrItinClass; 409def IIC_SCAS : InstrItinClass; 410def IIC_CMPS : InstrItinClass; 411def IIC_MOV : InstrItinClass; 412def IIC_MOV_MEM : InstrItinClass; 413def IIC_AHF : InstrItinClass; 414def IIC_BT_MI : InstrItinClass; 415def IIC_BT_MR : InstrItinClass; 416def IIC_BT_RI : InstrItinClass; 417def IIC_BT_RR : InstrItinClass; 418def IIC_BTX_MI : InstrItinClass; 419def IIC_BTX_MR : InstrItinClass; 420def IIC_BTX_RI : InstrItinClass; 421def IIC_BTX_RR : InstrItinClass; 422def IIC_XCHG_REG : InstrItinClass; 423def IIC_XCHG_MEM : InstrItinClass; 424def IIC_XADD_REG : InstrItinClass; 425def IIC_XADD_MEM : InstrItinClass; 426def IIC_CMPXCHG_MEM : InstrItinClass; 427def IIC_CMPXCHG_REG : InstrItinClass; 428def IIC_CMPXCHG_MEM8 : InstrItinClass; 429def IIC_CMPXCHG_REG8 : InstrItinClass; 430def IIC_CMPXCHG_8B : InstrItinClass; 431def IIC_CMPXCHG_16B : InstrItinClass; 432def IIC_LODS : InstrItinClass; 433def IIC_OUTS : InstrItinClass; 434def IIC_CLC : InstrItinClass; 435def IIC_CLD : InstrItinClass; 436def IIC_CLI : InstrItinClass; 437def IIC_CMC : InstrItinClass; 438def IIC_CLTS : InstrItinClass; 439def IIC_STC : InstrItinClass; 440def IIC_STI : InstrItinClass; 441def IIC_STD : InstrItinClass; 442def IIC_XLAT : InstrItinClass; 443def IIC_AAA : InstrItinClass; 444def IIC_AAD : InstrItinClass; 445def IIC_AAM : InstrItinClass; 446def IIC_AAS : InstrItinClass; 447def IIC_DAA : InstrItinClass; 448def IIC_DAS : InstrItinClass; 449def IIC_BOUND : InstrItinClass; 450def IIC_ARPL_REG : InstrItinClass; 451def IIC_ARPL_MEM : InstrItinClass; 452def IIC_MOVBE : InstrItinClass; 453 454def IIC_NOP : InstrItinClass; 455 456//===----------------------------------------------------------------------===// 457// Processor instruction itineraries. 458 459// IssueWidth is analagous to the number of decode units. Core and its 460// descendents, including Nehalem and SandyBridge have 4 decoders. 461// Resources beyond the decoder operate on micro-ops and are bufferred 462// so adjacent micro-ops don't directly compete. 463// 464// MinLatency=0 indicates that RAW dependencies can be decoded in the 465// same cycle. 466// 467// HighLatency=10 is optimistic. X86InstrInfo::isHighLatencyDef 468// indicates high latency opcodes. Alternatively, InstrItinData 469// entries may be included here to define specific operand 470// latencies. Since these latencies are not used for pipeline hazards, 471// they do not need to be exact. 472// 473// The GenericModel contains no instruciton itineraries. 474def GenericModel : SchedMachineModel { 475 let IssueWidth = 4; 476 let MinLatency = 0; 477 let LoadLatency = 4; 478 let HighLatency = 10; 479} 480 481include "X86ScheduleAtom.td" 482