1//===-- X86InstrXOP.td - XOP Instruction Set ---------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes XOP (eXtended OPerations)
11//
12//===----------------------------------------------------------------------===//
13
14multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
15  def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
16           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
17           [(set VR128:$dst, (Int VR128:$src))]>, VEX;
18  def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
19           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
20           [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, VEX;
21}
22
23let isAsmParserOnly = 1 in {
24  defm VPHSUBWD  : xop2op<0xE2, "vphsubwd", int_x86_xop_vphsubwd, memopv2i64>;
25  defm VPHSUBDQ  : xop2op<0xE3, "vphsubdq", int_x86_xop_vphsubdq, memopv2i64>;
26  defm VPHSUBBW  : xop2op<0xE1, "vphsubbw", int_x86_xop_vphsubbw, memopv2i64>;
27  defm VPHADDWQ  : xop2op<0xC7, "vphaddwq", int_x86_xop_vphaddwq, memopv2i64>;
28  defm VPHADDWD  : xop2op<0xC6, "vphaddwd", int_x86_xop_vphaddwd, memopv2i64>;
29  defm VPHADDUWQ : xop2op<0xD7, "vphadduwq", int_x86_xop_vphadduwq, memopv2i64>;
30  defm VPHADDUWD : xop2op<0xD6, "vphadduwd", int_x86_xop_vphadduwd, memopv2i64>;
31  defm VPHADDUDQ : xop2op<0xDB, "vphaddudq", int_x86_xop_vphaddudq, memopv2i64>;
32  defm VPHADDUBW : xop2op<0xD1, "vphaddubw", int_x86_xop_vphaddubw, memopv2i64>;
33  defm VPHADDUBQ : xop2op<0xD3, "vphaddubq", int_x86_xop_vphaddubq, memopv2i64>;
34  defm VPHADDUBD : xop2op<0xD2, "vphaddubd", int_x86_xop_vphaddubd, memopv2i64>;
35  defm VPHADDDQ  : xop2op<0xCB, "vphadddq", int_x86_xop_vphadddq, memopv2i64>;
36  defm VPHADDBW  : xop2op<0xC1, "vphaddbw", int_x86_xop_vphaddbw, memopv2i64>;
37  defm VPHADDBQ  : xop2op<0xC3, "vphaddbq", int_x86_xop_vphaddbq, memopv2i64>;
38  defm VPHADDBD  : xop2op<0xC2, "vphaddbd", int_x86_xop_vphaddbd, memopv2i64>;
39}
40
41// Scalar load 2 addr operand instructions
42multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int,
43                     Operand memop, ComplexPattern mem_cpat> {
44  def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
45           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
46           [(set VR128:$dst, (Int VR128:$src))]>, VEX;
47  def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
48           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
49           [(set VR128:$dst, (Int (bitconvert mem_cpat:$src)))]>, VEX;
50}
51
52let isAsmParserOnly = 1 in {
53  defm VFRCZSS   : xop2opsld<0x82, "vfrczss", int_x86_xop_vfrcz_ss,
54                   ssmem, sse_load_f32>;
55  defm VFRCZSD   : xop2opsld<0x83, "vfrczsd", int_x86_xop_vfrcz_sd,
56                   sdmem, sse_load_f64>;
57}
58
59multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int,
60                     PatFrag memop> {
61  def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
62           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
63           [(set VR128:$dst, (Int VR128:$src))]>, VEX;
64  def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
65           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
66           [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, VEX;
67}
68
69let isAsmParserOnly = 1 in {
70  defm VFRCZPS : xop2op128<0x80, "vfrczps", int_x86_xop_vfrcz_ps, memopv4f32>;
71  defm VFRCZPD : xop2op128<0x81, "vfrczpd", int_x86_xop_vfrcz_pd, memopv2f64>;
72}
73
74multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int,
75                     PatFrag memop> {
76  def rrY : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
77           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
78           [(set VR256:$dst, (Int VR256:$src))]>, VEX, VEX_L;
79  def rmY : IXOP<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
80           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
81           [(set VR256:$dst, (Int (bitconvert (memop addr:$src))))]>, VEX, VEX_L;
82}
83
84let isAsmParserOnly = 1 in {
85  defm VFRCZPS : xop2op256<0x80, "vfrczps", int_x86_xop_vfrcz_ps_256,
86                           memopv8f32>;
87  defm VFRCZPD : xop2op256<0x81, "vfrczpd", int_x86_xop_vfrcz_pd_256,
88                           memopv4f64>;
89}
90
91multiclass xop3op<bits<8> opc, string OpcodeStr, Intrinsic Int> {
92  def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
93           (ins VR128:$src1, VR128:$src2),
94           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
95           [(set VR128:$dst, (Int VR128:$src1, VR128:$src2))]>, VEX_4VOp3;
96  def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
97           (ins VR128:$src1, i128mem:$src2),
98           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
99           [(set VR128:$dst,
100              (Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))]>,
101           VEX_4V, VEX_W;
102  def mr : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
103           (ins i128mem:$src1, VR128:$src2),
104           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
105           [(set VR128:$dst,
106              (Int (bitconvert (memopv2i64 addr:$src1)), VR128:$src2))]>,
107             VEX_4VOp3;
108}
109
110let isAsmParserOnly = 1 in {
111  defm VPSHLW : xop3op<0x95, "vpshlw", int_x86_xop_vpshlw>;
112  defm VPSHLQ : xop3op<0x97, "vpshlq", int_x86_xop_vpshlq>;
113  defm VPSHLD : xop3op<0x96, "vpshld", int_x86_xop_vpshld>;
114  defm VPSHLB : xop3op<0x94, "vpshlb", int_x86_xop_vpshlb>;
115  defm VPSHAW : xop3op<0x99, "vpshaw", int_x86_xop_vpshaw>;
116  defm VPSHAQ : xop3op<0x9B, "vpshaq", int_x86_xop_vpshaq>;
117  defm VPSHAD : xop3op<0x9A, "vpshad", int_x86_xop_vpshad>;
118  defm VPSHAB : xop3op<0x98, "vpshab", int_x86_xop_vpshab>;
119  defm VPROTW : xop3op<0x91, "vprotw", int_x86_xop_vprotw>;
120  defm VPROTQ : xop3op<0x93, "vprotq", int_x86_xop_vprotq>;
121  defm VPROTD : xop3op<0x92, "vprotd", int_x86_xop_vprotd>;
122  defm VPROTB : xop3op<0x90, "vprotb", int_x86_xop_vprotb>;
123}
124
125multiclass xop3opimm<bits<8> opc, string OpcodeStr, Intrinsic Int> {
126  def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
127           (ins VR128:$src1, i8imm:$src2),
128           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
129           [(set VR128:$dst, (Int VR128:$src1, imm:$src2))]>, VEX;
130  def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
131           (ins i128mem:$src1, i8imm:$src2),
132           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
133           [(set VR128:$dst,
134             (Int (bitconvert (memopv2i64 addr:$src1)), imm:$src2))]>, VEX;
135}
136
137let isAsmParserOnly = 1 in {
138  defm VPROTW : xop3opimm<0xC1, "vprotw", int_x86_xop_vprotwi>;
139  defm VPROTQ : xop3opimm<0xC3, "vprotq", int_x86_xop_vprotqi>;
140  defm VPROTD : xop3opimm<0xC2, "vprotd", int_x86_xop_vprotdi>;
141  defm VPROTB : xop3opimm<0xC0, "vprotb", int_x86_xop_vprotbi>;
142}
143
144// Instruction where second source can be memory, but third must be register
145multiclass xop4opm2<bits<8> opc, string OpcodeStr, Intrinsic Int> {
146  def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
147           (ins VR128:$src1, VR128:$src2, VR128:$src3),
148           !strconcat(OpcodeStr,
149           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
150           [(set VR128:$dst,
151              (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_4V, VEX_I8IMM;
152  def rm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
153           (ins VR128:$src1, i128mem:$src2, VR128:$src3),
154           !strconcat(OpcodeStr,
155           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
156           [(set VR128:$dst,
157              (Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2)),
158              VR128:$src3))]>, VEX_4V, VEX_I8IMM;
159}
160
161let isAsmParserOnly = 1 in {
162  defm VPMADCSWD  : xop4opm2<0xB6, "vpmadcswd", int_x86_xop_vpmadcswd>;
163  defm VPMADCSSWD : xop4opm2<0xA6, "vpmadcsswd", int_x86_xop_vpmadcsswd>;
164  defm VPMACSWW   : xop4opm2<0x95, "vpmacsww", int_x86_xop_vpmacsww>;
165  defm VPMACSWD   : xop4opm2<0x96, "vpmacswd", int_x86_xop_vpmacswd>;
166  defm VPMACSSWW  : xop4opm2<0x85, "vpmacssww", int_x86_xop_vpmacssww>;
167  defm VPMACSSWD  : xop4opm2<0x86, "vpmacsswd", int_x86_xop_vpmacsswd>;
168  defm VPMACSSDQL : xop4opm2<0x87, "vpmacssdql", int_x86_xop_vpmacssdql>;
169  defm VPMACSSDQH : xop4opm2<0x8F, "vpmacssdqh", int_x86_xop_vpmacssdqh>;
170  defm VPMACSSDD  : xop4opm2<0x8E, "vpmacssdd", int_x86_xop_vpmacssdd>;
171  defm VPMACSDQL  : xop4opm2<0x97, "vpmacsdql", int_x86_xop_vpmacsdql>;
172  defm VPMACSDQH  : xop4opm2<0x9F, "vpmacsdqh", int_x86_xop_vpmacsdqh>;
173  defm VPMACSDD   : xop4opm2<0x9E, "vpmacsdd", int_x86_xop_vpmacsdd>;
174}
175
176// Instruction where second source can be memory, third must be imm8
177multiclass xop4opimm<bits<8> opc, string OpcodeStr, Intrinsic Int> {
178  def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
179           (ins VR128:$src1, VR128:$src2, i8imm:$src3),
180           !strconcat(OpcodeStr,
181           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
182           [(set VR128:$dst, (Int VR128:$src1, VR128:$src2, imm:$src3))]>,
183           VEX_4V;
184  def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
185           (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
186           !strconcat(OpcodeStr,
187           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
188           [(set VR128:$dst,
189             (Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2)),
190              imm:$src3))]>, VEX_4V;
191}
192
193let isAsmParserOnly = 1 in {
194  defm VPCOMB  : xop4opimm<0xCC, "vpcomb", int_x86_xop_vpcomb>;
195  defm VPCOMW  : xop4opimm<0xCD, "vpcomw", int_x86_xop_vpcomw>;
196  defm VPCOMD  : xop4opimm<0xCE, "vpcomd", int_x86_xop_vpcomd>;
197  defm VPCOMQ  : xop4opimm<0xCF, "vpcomq", int_x86_xop_vpcomq>;
198  defm VPCOMUB : xop4opimm<0xEC, "vpcomub", int_x86_xop_vpcomub>;
199  defm VPCOMUW : xop4opimm<0xED, "vpcomuw", int_x86_xop_vpcomuw>;
200  defm VPCOMUD : xop4opimm<0xEE, "vpcomud", int_x86_xop_vpcomud>;
201  defm VPCOMUQ : xop4opimm<0xEF, "vpcomuq", int_x86_xop_vpcomuq>;
202}
203
204// Instruction where either second or third source can be memory
205multiclass xop4op<bits<8> opc, string OpcodeStr, Intrinsic Int> {
206  def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
207           (ins VR128:$src1, VR128:$src2, VR128:$src3),
208           !strconcat(OpcodeStr,
209           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
210           [(set VR128:$dst, (Int VR128:$src1, VR128:$src2, VR128:$src3))]>,
211           VEX_4V, VEX_I8IMM;
212  def rm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
213           (ins VR128:$src1, VR128:$src2, i128mem:$src3),
214           !strconcat(OpcodeStr,
215           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
216           [(set VR128:$dst,
217             (Int VR128:$src1, VR128:$src2,
218              (bitconvert (memopv2i64 addr:$src3))))]>,
219           VEX_4V, VEX_I8IMM, VEX_W, MemOp4;
220  def mr : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
221           (ins VR128:$src1, i128mem:$src2, VR128:$src3),
222           !strconcat(OpcodeStr,
223           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
224           [(set VR128:$dst,
225             (Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2)),
226              VR128:$src3))]>,
227           VEX_4V, VEX_I8IMM;
228}
229
230let isAsmParserOnly = 1 in {
231  defm VPPERM : xop4op<0xA3, "vpperm", int_x86_xop_vpperm>;
232  defm VPCMOV : xop4op<0xA2, "vpcmov", int_x86_xop_vpcmov>;
233}
234
235multiclass xop4op256<bits<8> opc, string OpcodeStr, Intrinsic Int> {
236  def rrY : IXOPi8<opc, MRMSrcReg, (outs VR256:$dst),
237           (ins VR256:$src1, VR256:$src2, VR256:$src3),
238           !strconcat(OpcodeStr,
239           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
240           [(set VR256:$dst, (Int VR256:$src1, VR256:$src2, VR256:$src3))]>,
241           VEX_4V, VEX_I8IMM, VEX_L;
242  def rmY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
243           (ins VR256:$src1, VR256:$src2, i256mem:$src3),
244           !strconcat(OpcodeStr,
245           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
246           [(set VR256:$dst,
247             (Int VR256:$src1, VR256:$src2,
248              (bitconvert (memopv4i64 addr:$src3))))]>,
249           VEX_4V, VEX_I8IMM, VEX_W, MemOp4, VEX_L;
250  def mrY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
251           (ins VR256:$src1, f256mem:$src2, VR256:$src3),
252           !strconcat(OpcodeStr,
253           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
254           [(set VR256:$dst,
255             (Int VR256:$src1, (bitconvert (memopv4i64 addr:$src2)),
256              VR256:$src3))]>,
257           VEX_4V, VEX_I8IMM, VEX_L;
258}
259
260let isAsmParserOnly = 1 in {
261  defm VPCMOV : xop4op256<0xA2, "vpcmov", int_x86_xop_vpcmov_256>;
262}
263
264multiclass xop5op<bits<8> opc, string OpcodeStr, Intrinsic Int128,
265                  Intrinsic Int256, PatFrag ld_128, PatFrag ld_256> {
266  def rr : IXOP5<opc, MRMSrcReg, (outs VR128:$dst),
267        (ins VR128:$src1, VR128:$src2, VR128:$src3, i8imm:$src4),
268        !strconcat(OpcodeStr,
269        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
270        [(set VR128:$dst,
271           (Int128 VR128:$src1, VR128:$src2, VR128:$src3, imm:$src4))]>;
272  def rm : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
273        (ins VR128:$src1, VR128:$src2, f128mem:$src3, i8imm:$src4),
274        !strconcat(OpcodeStr,
275        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
276        [(set VR128:$dst,
277           (Int128 VR128:$src1, VR128:$src2, (ld_128 addr:$src3), imm:$src4))]>,
278        VEX_W, MemOp4;
279  def mr : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
280        (ins VR128:$src1, f128mem:$src2, VR128:$src3, i8imm:$src4),
281        !strconcat(OpcodeStr,
282        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
283        [(set VR128:$dst,
284           (Int128 VR128:$src1, (ld_128 addr:$src2), VR128:$src3, imm:$src4))]>;
285  def rrY : IXOP5<opc, MRMSrcReg, (outs VR256:$dst),
286        (ins VR256:$src1, VR256:$src2, VR256:$src3, i8imm:$src4),
287        !strconcat(OpcodeStr,
288        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
289        [(set VR256:$dst,
290          (Int256 VR256:$src1, VR256:$src2, VR256:$src3, imm:$src4))]>, VEX_L;
291  def rmY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
292        (ins VR256:$src1, VR256:$src2, f256mem:$src3, i8imm:$src4),
293        !strconcat(OpcodeStr,
294        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
295        [(set VR256:$dst,
296          (Int256 VR256:$src1, VR256:$src2, (ld_256 addr:$src3), imm:$src4))]>,
297        VEX_W, MemOp4, VEX_L;
298  def mrY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
299        (ins VR256:$src1, f256mem:$src2, VR256:$src3, i8imm:$src4),
300        !strconcat(OpcodeStr,
301        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
302        [(set VR256:$dst,
303           (Int256 VR256:$src1, (ld_256 addr:$src2), VR256:$src3, imm:$src4))]>,
304        VEX_L;
305}
306
307defm VPERMIL2PD : xop5op<0x49, "vpermil2pd", int_x86_xop_vpermil2pd,
308                         int_x86_xop_vpermil2pd_256, memopv2f64, memopv4f64>;
309defm VPERMIL2PS : xop5op<0x48, "vpermil2ps", int_x86_xop_vpermil2ps,
310                         int_x86_xop_vpermil2ps_256, memopv4f32, memopv8f32>;
311
312