1//===-- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 MMX instruction set, defining the instructions,
11// and properties of the instructions which are needed for code generation,
12// machine code emission, and analysis.
13//
14// All instructions that use MMX should be in this file, even if they also use
15// SSE.
16//
17//===----------------------------------------------------------------------===//
18
19//===----------------------------------------------------------------------===//
20// MMX Multiclasses
21//===----------------------------------------------------------------------===//
22
23def MMX_INTALU_ITINS : OpndItins<
24  IIC_MMX_ALU_RR, IIC_MMX_ALU_RM
25>;
26
27def MMX_INTALUQ_ITINS : OpndItins<
28  IIC_MMX_ALUQ_RR, IIC_MMX_ALUQ_RM
29>;
30
31def MMX_PHADDSUBW : OpndItins<
32  IIC_MMX_PHADDSUBW_RR, IIC_MMX_PHADDSUBW_RM
33>;
34
35def MMX_PHADDSUBD : OpndItins<
36  IIC_MMX_PHADDSUBD_RR, IIC_MMX_PHADDSUBD_RM
37>;
38
39def MMX_PMUL_ITINS : OpndItins<
40  IIC_MMX_PMUL, IIC_MMX_PMUL
41>;
42
43def MMX_PSADBW_ITINS : OpndItins<
44  IIC_MMX_PSADBW, IIC_MMX_PSADBW
45>;
46
47def MMX_MISC_FUNC_ITINS : OpndItins<
48  IIC_MMX_MISC_FUNC_MEM, IIC_MMX_MISC_FUNC_REG
49>;
50
51def MMX_SHIFT_ITINS : ShiftOpndItins<
52  IIC_MMX_SHIFT_RR, IIC_MMX_SHIFT_RM, IIC_MMX_SHIFT_RI
53>;
54
55def MMX_UNPCK_H_ITINS : OpndItins<
56  IIC_MMX_UNPCK_H_RR, IIC_MMX_UNPCK_H_RM
57>;
58
59def MMX_UNPCK_L_ITINS : OpndItins<
60  IIC_MMX_UNPCK_L, IIC_MMX_UNPCK_L
61>;
62
63def MMX_PCK_ITINS : OpndItins<
64  IIC_MMX_PCK_RR, IIC_MMX_PCK_RM
65>;
66
67def MMX_PSHUF_ITINS : OpndItins<
68  IIC_MMX_PSHUF, IIC_MMX_PSHUF
69>;
70
71def MMX_CVT_PD_ITINS : OpndItins<
72  IIC_MMX_CVT_PD_RR, IIC_MMX_CVT_PD_RM
73>;
74
75def MMX_CVT_PS_ITINS : OpndItins<
76  IIC_MMX_CVT_PS_RR, IIC_MMX_CVT_PS_RM
77>;
78
79let Constraints = "$src1 = $dst" in {
80  // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic.
81  // When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp.
82  multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
83                               OpndItins itins, bit Commutable = 0> {
84    def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
85                 (ins VR64:$src1, VR64:$src2),
86                 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
87                 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))], itins.rr> {
88      let isCommutable = Commutable;
89    }
90    def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
91                 (ins VR64:$src1, i64mem:$src2),
92                 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93                 [(set VR64:$dst, (IntId VR64:$src1,
94                                   (bitconvert (load_mmx addr:$src2))))],
95                 itins.rm>;
96  }
97
98  multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
99                                string OpcodeStr, Intrinsic IntId,
100                                Intrinsic IntId2, ShiftOpndItins itins> {
101    def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
102                                  (ins VR64:$src1, VR64:$src2),
103                  !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
104                  [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))], itins.rr>;
105    def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
106                                  (ins VR64:$src1, i64mem:$src2),
107                  !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
108                  [(set VR64:$dst, (IntId VR64:$src1,
109                                    (bitconvert (load_mmx addr:$src2))))],
110                  itins.rm>;
111    def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
112                                   (ins VR64:$src1, i32i8imm:$src2),
113                    !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
114           [(set VR64:$dst, (IntId2 VR64:$src1, (i32 imm:$src2)))], itins.ri>;
115  }
116}
117
118/// Unary MMX instructions requiring SSSE3.
119multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,
120                               Intrinsic IntId64, OpndItins itins> {
121  def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
122                   !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
123                   [(set VR64:$dst, (IntId64 VR64:$src))], itins.rr>;
124
125  def rm64 : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
126                   !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
127                   [(set VR64:$dst,
128                     (IntId64 (bitconvert (memopmmx addr:$src))))],
129                   itins.rm>;
130}
131
132/// Binary MMX instructions requiring SSSE3.
133let ImmT = NoImm, Constraints = "$src1 = $dst" in {
134multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,
135                             Intrinsic IntId64, OpndItins itins> {
136  let isCommutable = 0 in
137  def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst),
138       (ins VR64:$src1, VR64:$src2),
139        !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
140       [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))], itins.rr>;
141  def rm64 : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst),
142       (ins VR64:$src1, i64mem:$src2),
143        !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
144       [(set VR64:$dst,
145         (IntId64 VR64:$src1,
146          (bitconvert (memopmmx addr:$src2))))], itins.rm>;
147}
148}
149
150/// PALIGN MMX instructions (require SSSE3).
151multiclass ssse3_palign_mm<string asm, Intrinsic IntId> {
152  def R64irr  : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
153      (ins VR64:$src1, VR64:$src2, i8imm:$src3),
154      !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 
155      [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>;
156  def R64irm  : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
157      (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
158      !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
159      [(set VR64:$dst, (IntId VR64:$src1,
160                       (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>;
161}
162
163multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
164                         Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
165                         string asm, OpndItins itins, Domain d> {
166  def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
167                  [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr, d>;
168  def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
169                  [(set DstRC:$dst, (Int (ld_frag addr:$src)))], itins.rm, d>;
170}
171
172multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
173                    RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
174                    PatFrag ld_frag, string asm, Domain d> {
175  def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst),(ins DstRC:$src1, SrcRC:$src2),
176              asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], 
177              IIC_DEFAULT, d>;
178  def irm : PI<opc, MRMSrcMem, (outs DstRC:$dst),
179                   (ins DstRC:$src1, x86memop:$src2), asm,
180              [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], 
181              IIC_DEFAULT, d>;
182}
183
184//===----------------------------------------------------------------------===//
185// MMX EMMS Instruction
186//===----------------------------------------------------------------------===//
187
188def MMX_EMMS  : MMXI<0x77, RawFrm, (outs), (ins), "emms",
189                     [(int_x86_mmx_emms)]>;
190
191//===----------------------------------------------------------------------===//
192// MMX Scalar Instructions
193//===----------------------------------------------------------------------===//
194
195// Data Transfer Instructions
196def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
197                        "movd\t{$src, $dst|$dst, $src}",
198                        [(set VR64:$dst, 
199                         (x86mmx (scalar_to_vector GR32:$src)))],
200                        IIC_MMX_MOV_MM_RM>;
201let canFoldAsLoad = 1 in
202def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
203                        "movd\t{$src, $dst|$dst, $src}",
204                        [(set VR64:$dst,
205                        (x86mmx (scalar_to_vector (loadi32 addr:$src))))],
206                        IIC_MMX_MOV_MM_RM>;
207let mayStore = 1 in
208def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
209                        "movd\t{$src, $dst|$dst, $src}", [], IIC_MMX_MOV_MM_RM>;
210def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs), (ins GR32:$dst, VR64:$src),
211                        "movd\t{$src, $dst|$dst, $src}", [], IIC_MMX_MOV_REG_MM>;
212
213let neverHasSideEffects = 1 in
214def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
215                             "movd\t{$src, $dst|$dst, $src}",
216                             [], IIC_MMX_MOV_MM_RM>;
217
218// These are 64 bit moves, but since the OS X assembler doesn't
219// recognize a register-register movq, we write them as
220// movd.
221def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
222                               (outs GR64:$dst), (ins VR64:$src),
223                               "movd\t{$src, $dst|$dst, $src}", 
224                             [(set GR64:$dst,
225                              (bitconvert VR64:$src))], IIC_MMX_MOV_REG_MM>;
226def MMX_MOVD64rrv164 : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
227                             "movd\t{$src, $dst|$dst, $src}",
228                             [(set VR64:$dst,
229                              (bitconvert GR64:$src))], IIC_MMX_MOV_MM_RM>;
230let neverHasSideEffects = 1 in
231def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
232                        "movq\t{$src, $dst|$dst, $src}", [],
233                        IIC_MMX_MOVQ_RR>;
234let canFoldAsLoad = 1 in
235def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
236                        "movq\t{$src, $dst|$dst, $src}",
237                        [(set VR64:$dst, (load_mmx addr:$src))],
238                        IIC_MMX_MOVQ_RM>;
239def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
240                        "movq\t{$src, $dst|$dst, $src}",
241                        [(store (x86mmx VR64:$src), addr:$dst)],
242                        IIC_MMX_MOVQ_RM>;
243
244def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
245                             (ins VR128:$src), "movdq2q\t{$src, $dst|$dst, $src}",
246                             [(set VR64:$dst,
247                               (x86mmx (bitconvert
248                               (i64 (vector_extract (v2i64 VR128:$src),
249                                     (iPTR 0))))))],
250                             IIC_MMX_MOVQ_RR>;
251
252def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst),
253                              (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}",
254                              [(set VR128:$dst,
255                                (v2i64
256                                  (scalar_to_vector
257                                    (i64 (bitconvert (x86mmx VR64:$src))))))],
258                              IIC_MMX_MOVQ_RR>;
259
260let neverHasSideEffects = 1 in
261def MMX_MOVQ2FR64rr: MMXS2SIi8<0xD6, MRMSrcReg, (outs FR64:$dst),
262                               (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}",
263                               [], IIC_MMX_MOVQ_RR>;
264
265def MMX_MOVFR642Qrr: MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
266                              (ins FR64:$src), "movdq2q\t{$src, $dst|$dst, $src}",
267                              [], IIC_MMX_MOVQ_RR>;
268
269def MMX_MOVNTQmr  : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
270                         "movntq\t{$src, $dst|$dst, $src}",
271                         [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)],
272                         IIC_MMX_MOVQ_RM>;
273
274let AddedComplexity = 15 in
275// movd to MMX register zero-extends
276def MMX_MOVZDI2PDIrr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
277                             "movd\t{$src, $dst|$dst, $src}",
278              [(set VR64:$dst,
279                    (x86mmx (X86vzmovl (x86mmx (scalar_to_vector GR32:$src)))))],
280                            IIC_MMX_MOV_MM_RM>;
281let AddedComplexity = 20 in
282def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst),
283                           (ins i32mem:$src),
284                             "movd\t{$src, $dst|$dst, $src}",
285          [(set VR64:$dst,
286                (x86mmx (X86vzmovl (x86mmx
287                                   (scalar_to_vector (loadi32 addr:$src))))))],
288                            IIC_MMX_MOV_MM_RM>;
289
290// Arithmetic Instructions
291defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", int_x86_ssse3_pabs_b,
292                                     MMX_INTALU_ITINS>;
293defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", int_x86_ssse3_pabs_w,
294                                     MMX_INTALU_ITINS>;
295defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", int_x86_ssse3_pabs_d,
296                                     MMX_INTALU_ITINS>;
297// -- Addition
298defm MMX_PADDB : MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b,
299                                   MMX_INTALU_ITINS, 1>;
300defm MMX_PADDW : MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w,
301                                   MMX_INTALU_ITINS, 1>;
302defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d,
303                                   MMX_INTALU_ITINS, 1>;
304defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q,
305                                   MMX_INTALUQ_ITINS, 1>;
306defm MMX_PADDSB  : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b,
307                                   MMX_INTALU_ITINS, 1>;
308defm MMX_PADDSW  : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w,
309                                   MMX_INTALU_ITINS, 1>;
310
311defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b,
312                                   MMX_INTALU_ITINS, 1>;
313defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w,
314                                   MMX_INTALU_ITINS, 1>;
315
316defm MMX_PHADDW  : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w,
317                                   MMX_PHADDSUBW>;
318defm MMX_PHADD   : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d,
319                                   MMX_PHADDSUBD>;
320defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw,
321                                   MMX_PHADDSUBW>;
322
323
324// -- Subtraction
325defm MMX_PSUBB : MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b,
326                                   MMX_INTALU_ITINS>;
327defm MMX_PSUBW : MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w,
328                                   MMX_INTALU_ITINS, 1>;
329defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d,
330                                   MMX_INTALU_ITINS, 1>;
331defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q,
332                                   MMX_INTALUQ_ITINS, 1>;
333
334defm MMX_PSUBSB  : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b,
335                                   MMX_INTALU_ITINS, 1>;
336defm MMX_PSUBSW  : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w,
337                                   MMX_INTALU_ITINS, 1>;
338
339defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b,
340                                   MMX_INTALU_ITINS, 1>;
341defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w,
342                                   MMX_INTALU_ITINS, 1>;
343
344defm MMX_PHSUBW  : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w,
345                                   MMX_PHADDSUBW>;
346defm MMX_PHSUBD  : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d,
347                                   MMX_PHADDSUBD>;
348defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw,
349                                   MMX_PHADDSUBW>;
350
351// -- Multiplication
352defm MMX_PMULLW  : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w,
353                                     MMX_PMUL_ITINS, 1>;
354
355defm MMX_PMULHW  : MMXI_binop_rm_int<0xE5, "pmulhw",  int_x86_mmx_pmulh_w,
356                                     MMX_PMUL_ITINS, 1>;
357defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w,
358                                     MMX_PMUL_ITINS, 1>;
359defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq,
360                                     MMX_PMUL_ITINS, 1>;
361let isCommutable = 1 in
362defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw",
363                                     int_x86_ssse3_pmul_hr_sw, MMX_PMUL_ITINS>;
364
365// -- Miscellanea
366defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd,
367                                     MMX_PMUL_ITINS, 1>;
368
369defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw",
370                                     int_x86_ssse3_pmadd_ub_sw, MMX_PMUL_ITINS>;
371defm MMX_PAVGB   : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b,
372                                     MMX_MISC_FUNC_ITINS, 1>;
373defm MMX_PAVGW   : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w,
374                                     MMX_MISC_FUNC_ITINS, 1>;
375
376defm MMX_PMINUB  : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b,
377                                     MMX_MISC_FUNC_ITINS, 1>;
378defm MMX_PMINSW  : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w,
379                                     MMX_MISC_FUNC_ITINS, 1>;
380
381defm MMX_PMAXUB  : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b,
382                                     MMX_MISC_FUNC_ITINS, 1>;
383defm MMX_PMAXSW  : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w,
384                                     MMX_MISC_FUNC_ITINS, 1>;
385
386defm MMX_PSADBW  : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw,
387                                     MMX_PSADBW_ITINS, 1>;
388
389defm MMX_PSIGNB :  SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b,
390                                        MMX_MISC_FUNC_ITINS>;
391defm MMX_PSIGNW :  SS3I_binop_rm_int_mm<0x09, "psignw", int_x86_ssse3_psign_w,
392                                        MMX_MISC_FUNC_ITINS>;
393defm MMX_PSIGND :  SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d,
394                                        MMX_MISC_FUNC_ITINS>;
395let Constraints = "$src1 = $dst" in
396  defm MMX_PALIGN : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>;
397
398// Logical Instructions
399defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand,
400                                  MMX_INTALU_ITINS, 1>;
401defm MMX_POR  : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por,
402                                  MMX_INTALU_ITINS, 1>;
403defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor,
404                                  MMX_INTALU_ITINS, 1>;
405defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn,
406                                  MMX_INTALU_ITINS>;
407
408// Shift Instructions
409defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
410                                    int_x86_mmx_psrl_w, int_x86_mmx_psrli_w,
411                                    MMX_SHIFT_ITINS>;
412defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
413                                    int_x86_mmx_psrl_d, int_x86_mmx_psrli_d,
414                                    MMX_SHIFT_ITINS>;
415defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
416                                    int_x86_mmx_psrl_q, int_x86_mmx_psrli_q,
417                                    MMX_SHIFT_ITINS>;
418
419defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
420                                    int_x86_mmx_psll_w, int_x86_mmx_pslli_w,
421                                    MMX_SHIFT_ITINS>;
422defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
423                                    int_x86_mmx_psll_d, int_x86_mmx_pslli_d,
424                                    MMX_SHIFT_ITINS>;
425defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
426                                    int_x86_mmx_psll_q, int_x86_mmx_pslli_q,
427                                    MMX_SHIFT_ITINS>;
428
429defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
430                                    int_x86_mmx_psra_w, int_x86_mmx_psrai_w,
431                                    MMX_SHIFT_ITINS>;
432defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
433                                    int_x86_mmx_psra_d, int_x86_mmx_psrai_d,
434                                    MMX_SHIFT_ITINS>;
435
436// Comparison Instructions
437defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b,
438                                     MMX_INTALU_ITINS>;
439defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w,
440                                     MMX_INTALU_ITINS>;
441defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d,
442                                     MMX_INTALU_ITINS>;
443
444defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b,
445                                     MMX_INTALU_ITINS>;
446defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w,
447                                     MMX_INTALU_ITINS>;
448defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d,
449                                     MMX_INTALU_ITINS>;
450
451// -- Unpack Instructions
452defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw", 
453                                       int_x86_mmx_punpckhbw,
454                                       MMX_UNPCK_H_ITINS>;
455defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd", 
456                                       int_x86_mmx_punpckhwd,
457                                       MMX_UNPCK_H_ITINS>;
458defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq", 
459                                       int_x86_mmx_punpckhdq,
460                                       MMX_UNPCK_H_ITINS>;
461defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw", 
462                                       int_x86_mmx_punpcklbw,
463                                       MMX_UNPCK_L_ITINS>;
464defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd", 
465                                       int_x86_mmx_punpcklwd,
466                                       MMX_UNPCK_L_ITINS>;
467defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq",
468                                       int_x86_mmx_punpckldq,
469                                       MMX_UNPCK_L_ITINS>;
470
471// -- Pack Instructions
472defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb,
473                                      MMX_PCK_ITINS>;
474defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw,
475                                      MMX_PCK_ITINS>;
476defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb,
477                                      MMX_PCK_ITINS>;
478
479// -- Shuffle Instructions
480defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b,
481                                       MMX_PSHUF_ITINS>;
482
483def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
484                          (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
485                          "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
486                          [(set VR64:$dst,
487                             (int_x86_sse_pshuf_w VR64:$src1, imm:$src2))],
488                          IIC_MMX_PSHUF>;
489def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
490                          (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
491                          "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
492                          [(set VR64:$dst,
493                             (int_x86_sse_pshuf_w (load_mmx addr:$src1),
494                                                   imm:$src2))],
495                          IIC_MMX_PSHUF>;
496
497
498
499
500// -- Conversion Instructions
501defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
502                      f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
503                      MMX_CVT_PS_ITINS, SSEPackedSingle>, TB;
504defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
505                      f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
506                      MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
507defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
508                       f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
509                       MMX_CVT_PS_ITINS, SSEPackedSingle>, TB;
510defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
511                       f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
512                       MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
513defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
514                         i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
515                         MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
516let Constraints = "$src1 = $dst" in {
517  defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
518                         int_x86_sse_cvtpi2ps,
519                         i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
520                          SSEPackedSingle>, TB;
521}
522
523// Extract / Insert
524def MMX_PEXTRWirri: MMXIi8<0xC5, MRMSrcReg,
525                           (outs GR32:$dst), (ins VR64:$src1, i32i8imm:$src2),
526                           "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
527                           [(set GR32:$dst, (int_x86_mmx_pextr_w VR64:$src1,
528                                             (iPTR imm:$src2)))],
529                           IIC_MMX_PEXTR>;
530let Constraints = "$src1 = $dst" in {
531  def MMX_PINSRWirri : MMXIi8<0xC4, MRMSrcReg,
532                      (outs VR64:$dst), 
533                      (ins VR64:$src1, GR32:$src2, i32i8imm:$src3),
534                      "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
535                      [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
536                                        GR32:$src2, (iPTR imm:$src3)))],
537                      IIC_MMX_PINSRW>;
538
539  def MMX_PINSRWirmi : MMXIi8<0xC4, MRMSrcMem,
540                     (outs VR64:$dst),
541                     (ins VR64:$src1, i16mem:$src2, i32i8imm:$src3),
542                     "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
543                     [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
544                                         (i32 (anyext (loadi16 addr:$src2))),
545                                       (iPTR imm:$src3)))],
546                     IIC_MMX_PINSRW>;
547}
548
549// Mask creation
550def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
551                          "pmovmskb\t{$src, $dst|$dst, $src}",
552                          [(set GR32:$dst, 
553                                (int_x86_mmx_pmovmskb VR64:$src))]>;
554
555
556// Low word of XMM to MMX.
557def MMX_X86movdq2q : SDNode<"X86ISD::MOVDQ2Q", SDTypeProfile<1, 1,
558                            [SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>;
559
560def : Pat<(x86mmx (MMX_X86movdq2q VR128:$src)),
561          (x86mmx (MMX_MOVDQ2Qrr VR128:$src))>;
562
563def : Pat<(x86mmx (MMX_X86movdq2q (loadv2i64 addr:$src))),
564          (x86mmx (MMX_MOVQ64rm addr:$src))>;
565
566// Misc.
567let Uses = [EDI] in
568def MMX_MASKMOVQ : MMXI<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
569                        "maskmovq\t{$mask, $src|$src, $mask}",
570                        [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)],
571                        IIC_MMX_MASKMOV>;
572let Uses = [RDI] in
573def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
574                           "maskmovq\t{$mask, $src|$src, $mask}",
575                           [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)],
576                           IIC_MMX_MASKMOV>;
577
578// 64-bit bit convert.
579let Predicates = [HasSSE2] in {
580def : Pat<(x86mmx (bitconvert (i64 GR64:$src))),
581          (MMX_MOVD64to64rr GR64:$src)>;
582def : Pat<(i64 (bitconvert (x86mmx VR64:$src))),
583          (MMX_MOVD64from64rr VR64:$src)>;
584def : Pat<(f64 (bitconvert (x86mmx VR64:$src))),
585          (MMX_MOVQ2FR64rr VR64:$src)>;
586def : Pat<(x86mmx (bitconvert (f64 FR64:$src))),
587          (MMX_MOVFR642Qrr FR64:$src)>;
588}
589
590
591