1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PPCInstrFormats.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC specific type constraints. 19// 20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22]>; 23def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 24def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 25 SDTCisVT<1, i32> ]>; 26def SDT_PPCvperm : SDTypeProfile<1, 3, [ 27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 28]>; 29 30def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 32]>; 33 34def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 36]>; 37 38def SDT_PPClbrx : SDTypeProfile<1, 2, [ 39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 40]>; 41def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 43]>; 44 45def SDT_PPClarx : SDTypeProfile<1, 1, [ 46 SDTCisInt<0>, SDTCisPtrTy<1> 47]>; 48def SDT_PPCstcx : SDTypeProfile<0, 2, [ 49 SDTCisInt<0>, SDTCisPtrTy<1> 50]>; 51 52def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 53 SDTCisPtrTy<0>, SDTCisVT<1, i32> 54]>; 55 56def SDT_PPCnop : SDTypeProfile<0, 0, []>; 57 58//===----------------------------------------------------------------------===// 59// PowerPC specific DAG Nodes. 60// 61 62def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>; 63def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 64def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 65def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 66 [SDNPHasChain, SDNPMayStore]>; 67 68// This sequence is used for long double->int conversions. It changes the 69// bits in the FPSCR which is not modelled. 70def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 71 [SDNPOutGlue]>; 72def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 73 [SDNPInGlue, SDNPOutGlue]>; 74def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 75 [SDNPInGlue, SDNPOutGlue]>; 76def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, 77 [SDNPInGlue, SDNPOutGlue]>; 78def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3, 79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>, 80 SDTCisVT<3, f64>]>, 81 [SDNPInGlue]>; 82 83def PPCfsel : SDNode<"PPCISD::FSEL", 84 // Type constraint for fsel. 85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 87 88def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 89def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 90def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>; 91def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 92def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 93 94def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 95 96// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 97// amounts. These nodes are generated by the multi-precision shift code. 98def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 99def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 100def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 101 102def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>; 103def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, 104 [SDNPHasChain, SDNPMayStore]>; 105 106// These are target-independent nodes, but have target-specific formats. 107def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 108 [SDNPHasChain, SDNPOutGlue]>; 109def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 111 112def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 113def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall, 114 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 115 SDNPVariadic]>; 116def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall, 117 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 118 SDNPVariadic]>; 119def PPCcall_nop_SVR4 : SDNode<"PPCISD::CALL_NOP_SVR4", SDT_PPCCall, 120 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 121 SDNPVariadic]>; 122def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInGlue, SDNPOutGlue]>; 123def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>, 124 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 125def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>, 126 [SDNPHasChain, SDNPSideEffect, 127 SDNPInGlue, SDNPOutGlue]>; 128def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>, 129 [SDNPHasChain, SDNPSideEffect, 130 SDNPInGlue, SDNPOutGlue]>; 131def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 133def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone, 134 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 135 SDNPVariadic]>; 136 137def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone, 138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 139 SDNPVariadic]>; 140 141def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 142 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 143 144def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 145 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 146 147def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 148def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>; 149 150def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 151 [SDNPHasChain, SDNPOptInGlue]>; 152 153def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 154 [SDNPHasChain, SDNPMayLoad]>; 155def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 156 [SDNPHasChain, SDNPMayStore]>; 157 158// Instructions to set/unset CR bit 6 for SVR4 vararg calls 159def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 160 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 161def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 162 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 163 164// Instructions to support atomic operations 165def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx, 166 [SDNPHasChain, SDNPMayLoad]>; 167def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx, 168 [SDNPHasChain, SDNPMayStore]>; 169 170// Instructions to support dynamic alloca. 171def SDTDynOp : SDTypeProfile<1, 2, []>; 172def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 173 174//===----------------------------------------------------------------------===// 175// PowerPC specific transformation functions and pattern fragments. 176// 177 178def SHL32 : SDNodeXForm<imm, [{ 179 // Transformation function: 31 - imm 180 return getI32Imm(31 - N->getZExtValue()); 181}]>; 182 183def SRL32 : SDNodeXForm<imm, [{ 184 // Transformation function: 32 - imm 185 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0); 186}]>; 187 188def LO16 : SDNodeXForm<imm, [{ 189 // Transformation function: get the low 16 bits. 190 return getI32Imm((unsigned short)N->getZExtValue()); 191}]>; 192 193def HI16 : SDNodeXForm<imm, [{ 194 // Transformation function: shift the immediate value down into the low bits. 195 return getI32Imm((unsigned)N->getZExtValue() >> 16); 196}]>; 197 198def HA16 : SDNodeXForm<imm, [{ 199 // Transformation function: shift the immediate value down into the low bits. 200 signed int Val = N->getZExtValue(); 201 return getI32Imm((Val - (signed short)Val) >> 16); 202}]>; 203def MB : SDNodeXForm<imm, [{ 204 // Transformation function: get the start bit of a mask 205 unsigned mb = 0, me; 206 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 207 return getI32Imm(mb); 208}]>; 209 210def ME : SDNodeXForm<imm, [{ 211 // Transformation function: get the end bit of a mask 212 unsigned mb, me = 0; 213 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 214 return getI32Imm(me); 215}]>; 216def maskimm32 : PatLeaf<(imm), [{ 217 // maskImm predicate - True if immediate is a run of ones. 218 unsigned mb, me; 219 if (N->getValueType(0) == MVT::i32) 220 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 221 else 222 return false; 223}]>; 224 225def immSExt16 : PatLeaf<(imm), [{ 226 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended 227 // field. Used by instructions like 'addi'. 228 if (N->getValueType(0) == MVT::i32) 229 return (int32_t)N->getZExtValue() == (short)N->getZExtValue(); 230 else 231 return (int64_t)N->getZExtValue() == (short)N->getZExtValue(); 232}]>; 233def immZExt16 : PatLeaf<(imm), [{ 234 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 235 // field. Used by instructions like 'ori'. 236 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 237}], LO16>; 238 239// imm16Shifted* - These match immediates where the low 16-bits are zero. There 240// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 241// identical in 32-bit mode, but in 64-bit mode, they return true if the 242// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 243// clear). 244def imm16ShiftedZExt : PatLeaf<(imm), [{ 245 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 246 // immediate are set. Used by instructions like 'xoris'. 247 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 248}], HI16>; 249 250def imm16ShiftedSExt : PatLeaf<(imm), [{ 251 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 252 // immediate are set. Used by instructions like 'addis'. Identical to 253 // imm16ShiftedZExt in 32-bit mode. 254 if (N->getZExtValue() & 0xFFFF) return false; 255 if (N->getValueType(0) == MVT::i32) 256 return true; 257 // For 64-bit, make sure it is sext right. 258 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 259}], HI16>; 260 261 262//===----------------------------------------------------------------------===// 263// PowerPC Flag Definitions. 264 265class isPPC64 { bit PPC64 = 1; } 266class isDOT { 267 list<Register> Defs = [CR0]; 268 bit RC = 1; 269} 270 271class RegConstraint<string C> { 272 string Constraints = C; 273} 274class NoEncode<string E> { 275 string DisableEncoding = E; 276} 277 278 279//===----------------------------------------------------------------------===// 280// PowerPC Operand Definitions. 281 282def s5imm : Operand<i32> { 283 let PrintMethod = "printS5ImmOperand"; 284} 285def u5imm : Operand<i32> { 286 let PrintMethod = "printU5ImmOperand"; 287} 288def u6imm : Operand<i32> { 289 let PrintMethod = "printU6ImmOperand"; 290} 291def s16imm : Operand<i32> { 292 let PrintMethod = "printS16ImmOperand"; 293} 294def u16imm : Operand<i32> { 295 let PrintMethod = "printU16ImmOperand"; 296} 297def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing. 298 let PrintMethod = "printS16X4ImmOperand"; 299} 300def directbrtarget : Operand<OtherVT> { 301 let PrintMethod = "printBranchOperand"; 302 let EncoderMethod = "getDirectBrEncoding"; 303} 304def condbrtarget : Operand<OtherVT> { 305 let PrintMethod = "printBranchOperand"; 306 let EncoderMethod = "getCondBrEncoding"; 307} 308def calltarget : Operand<iPTR> { 309 let EncoderMethod = "getDirectBrEncoding"; 310} 311def aaddr : Operand<iPTR> { 312 let PrintMethod = "printAbsAddrOperand"; 313} 314def symbolHi: Operand<i32> { 315 let PrintMethod = "printSymbolHi"; 316 let EncoderMethod = "getHA16Encoding"; 317} 318def symbolLo: Operand<i32> { 319 let PrintMethod = "printSymbolLo"; 320 let EncoderMethod = "getLO16Encoding"; 321} 322def crbitm: Operand<i8> { 323 let PrintMethod = "printcrbitm"; 324 let EncoderMethod = "get_crbitm_encoding"; 325} 326// Address operands 327def memri : Operand<iPTR> { 328 let PrintMethod = "printMemRegImm"; 329 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 330 let EncoderMethod = "getMemRIEncoding"; 331} 332def memrr : Operand<iPTR> { 333 let PrintMethod = "printMemRegReg"; 334 let MIOperandInfo = (ops ptr_rc:$offreg, ptr_rc:$ptrreg); 335} 336def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits. 337 let PrintMethod = "printMemRegImmShifted"; 338 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 339 let EncoderMethod = "getMemRIXEncoding"; 340} 341 342// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg 343// that doesn't matter. 344def pred : PredicateOperand<OtherVT, (ops imm, CRRC), 345 (ops (i32 20), (i32 zero_reg))> { 346 let PrintMethod = "printPredicateOperand"; 347} 348 349// Define PowerPC specific addressing mode. 350def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; 351def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; 352def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 353def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std" 354 355/// This is just the offset part of iaddr, used for preinc. 356def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 357def xaddroff : ComplexPattern<iPTR, 1, "SelectAddrIdxOffs", [], []>; 358 359//===----------------------------------------------------------------------===// 360// PowerPC Instruction Predicate Definitions. 361def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">; 362def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">; 363def IsBookE : Predicate<"PPCSubTarget.isBookE()">; 364 365//===----------------------------------------------------------------------===// 366// PowerPC Instruction Definitions. 367 368// Pseudo-instructions: 369 370let hasCtrlDep = 1 in { 371let Defs = [R1], Uses = [R1] in { 372def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "", 373 [(callseq_start timm:$amt)]>; 374def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "", 375 [(callseq_end timm:$amt1, timm:$amt2)]>; 376} 377 378def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS), 379 "UPDATE_VRSAVE $rD, $rS", []>; 380} 381 382let Defs = [R1], Uses = [R1] in 383def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "", 384 [(set GPRC:$result, 385 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>; 386 387// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 388// instruction selection into a branch sequence. 389let usesCustomInserter = 1, // Expanded after instruction selection. 390 PPC970_Single = 1 in { 391 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F, 392 i32imm:$BROPC), "", 393 []>; 394 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F, 395 i32imm:$BROPC), "", 396 []>; 397 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F, 398 i32imm:$BROPC), "", 399 []>; 400 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F, 401 i32imm:$BROPC), "", 402 []>; 403 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F, 404 i32imm:$BROPC), "", 405 []>; 406} 407 408// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 409// scavenge a register for it. 410let mayStore = 1 in 411def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F), 412 "", []>; 413 414// RESTORE_CR - Indicate that we're restoring the CR register (previously 415// spilled), so we'll need to scavenge a register for it. 416let mayLoad = 1 in 417def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F), 418 "", []>; 419 420let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 421 let isReturn = 1, Uses = [LR, RM] in 422 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p), 423 "b${p:cc}lr ${p:reg}", BrB, 424 [(retflag)]>; 425 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in 426 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; 427} 428 429let Defs = [LR] in 430 def MovePCtoLR : Pseudo<(outs), (ins), "", []>, 431 PPC970_Unit_BRU; 432 433let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 434 let isBarrier = 1 in { 435 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), 436 "b $dst", BrB, 437 [(br bb:$dst)]>; 438 } 439 440 // BCC represents an arbitrary conditional branch on a predicate. 441 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 442 // a two-value operand where a dag node expects two operands. :( 443 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), 444 "b${cond:cc} ${cond:reg}, $dst" 445 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>; 446 447 let Defs = [CTR], Uses = [CTR] in { 448 def BDZ : IForm_ext<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 449 "bdz $dst", BrB, []>; 450 def BDNZ : IForm_ext<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 451 "bdnz $dst", BrB, []>; 452 } 453} 454 455// Darwin ABI Calls. 456let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 457 // Convenient aliases for call instructions 458 let Uses = [RM] in { 459 def BL_Darwin : IForm<18, 0, 1, 460 (outs), (ins calltarget:$func), 461 "bl $func", BrB, []>; // See Pat patterns below. 462 def BLA_Darwin : IForm<18, 1, 1, 463 (outs), (ins aaddr:$func), 464 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>; 465 } 466 let Uses = [CTR, RM] in { 467 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 468 (outs), (ins), 469 "bctrl", BrB, 470 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>; 471 } 472} 473 474// SVR4 ABI Calls. 475let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 476 // Convenient aliases for call instructions 477 let Uses = [RM] in { 478 def BL_SVR4 : IForm<18, 0, 1, 479 (outs), (ins calltarget:$func), 480 "bl $func", BrB, []>; // See Pat patterns below. 481 def BLA_SVR4 : IForm<18, 1, 1, 482 (outs), (ins aaddr:$func), 483 "bla $func", BrB, 484 [(PPCcall_SVR4 (i32 imm:$func))]>; 485 } 486 let Uses = [CTR, RM] in { 487 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1, 488 (outs), (ins), 489 "bctrl", BrB, 490 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>; 491 } 492} 493 494 495let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 496def TCRETURNdi :Pseudo< (outs), 497 (ins calltarget:$dst, i32imm:$offset), 498 "#TC_RETURNd $dst $offset", 499 []>; 500 501 502let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 503def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset), 504 "#TC_RETURNa $func $offset", 505 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 506 507let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 508def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 509 "#TC_RETURNr $dst $offset", 510 []>; 511 512 513let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 514 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 515def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 516 Requires<[In32BitMode]>; 517 518 519 520let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 521 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 522def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 523 "b $dst", BrB, 524 []>; 525 526 527let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 528 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 529def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 530 "ba $dst", BrB, 531 []>; 532 533 534// DCB* instructions. 535def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), 536 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 537 PPC970_DGroup_Single; 538def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), 539 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, 540 PPC970_DGroup_Single; 541def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), 542 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 543 PPC970_DGroup_Single; 544def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), 545 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 546 PPC970_DGroup_Single; 547def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), 548 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>, 549 PPC970_DGroup_Single; 550def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), 551 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>, 552 PPC970_DGroup_Single; 553def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), 554 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 555 PPC970_DGroup_Single; 556def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), 557 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 558 PPC970_DGroup_Single; 559 560def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), 561 (DCBT xoaddr:$dst)>; 562 563// Atomic operations 564let usesCustomInserter = 1 in { 565 let Defs = [CR0] in { 566 def ATOMIC_LOAD_ADD_I8 : Pseudo< 567 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 568 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>; 569 def ATOMIC_LOAD_SUB_I8 : Pseudo< 570 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 571 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>; 572 def ATOMIC_LOAD_AND_I8 : Pseudo< 573 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 574 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>; 575 def ATOMIC_LOAD_OR_I8 : Pseudo< 576 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 577 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>; 578 def ATOMIC_LOAD_XOR_I8 : Pseudo< 579 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 580 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>; 581 def ATOMIC_LOAD_NAND_I8 : Pseudo< 582 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 583 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>; 584 def ATOMIC_LOAD_ADD_I16 : Pseudo< 585 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 586 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>; 587 def ATOMIC_LOAD_SUB_I16 : Pseudo< 588 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 589 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>; 590 def ATOMIC_LOAD_AND_I16 : Pseudo< 591 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 592 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>; 593 def ATOMIC_LOAD_OR_I16 : Pseudo< 594 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 595 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>; 596 def ATOMIC_LOAD_XOR_I16 : Pseudo< 597 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 598 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>; 599 def ATOMIC_LOAD_NAND_I16 : Pseudo< 600 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 601 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>; 602 def ATOMIC_LOAD_ADD_I32 : Pseudo< 603 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 604 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>; 605 def ATOMIC_LOAD_SUB_I32 : Pseudo< 606 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 607 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>; 608 def ATOMIC_LOAD_AND_I32 : Pseudo< 609 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 610 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>; 611 def ATOMIC_LOAD_OR_I32 : Pseudo< 612 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 613 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>; 614 def ATOMIC_LOAD_XOR_I32 : Pseudo< 615 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 616 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>; 617 def ATOMIC_LOAD_NAND_I32 : Pseudo< 618 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 619 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>; 620 621 def ATOMIC_CMP_SWAP_I8 : Pseudo< 622 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "", 623 [(set GPRC:$dst, 624 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 625 def ATOMIC_CMP_SWAP_I16 : Pseudo< 626 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "", 627 [(set GPRC:$dst, 628 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 629 def ATOMIC_CMP_SWAP_I32 : Pseudo< 630 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "", 631 [(set GPRC:$dst, 632 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 633 634 def ATOMIC_SWAP_I8 : Pseudo< 635 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "", 636 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>; 637 def ATOMIC_SWAP_I16 : Pseudo< 638 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "", 639 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>; 640 def ATOMIC_SWAP_I32 : Pseudo< 641 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "", 642 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>; 643 } 644} 645 646// Instructions to support atomic operations 647def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src), 648 "lwarx $rD, $src", LdStLWARX, 649 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>; 650 651let Defs = [CR0] in 652def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst), 653 "stwcx. $rS, $dst", LdStSTWCX, 654 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>, 655 isDOT; 656 657let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 658def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>; 659 660//===----------------------------------------------------------------------===// 661// PPC32 Load Instructions. 662// 663 664// Unindexed (r+i) Loads. 665let canFoldAsLoad = 1, PPC970_Unit = 2 in { 666def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src), 667 "lbz $rD, $src", LdStLoad, 668 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; 669def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src), 670 "lha $rD, $src", LdStLHA, 671 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>, 672 PPC970_DGroup_Cracked; 673def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src), 674 "lhz $rD, $src", LdStLoad, 675 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>; 676def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src), 677 "lwz $rD, $src", LdStLoad, 678 [(set GPRC:$rD, (load iaddr:$src))]>; 679 680def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src), 681 "lfs $rD, $src", LdStLFD, 682 [(set F4RC:$rD, (load iaddr:$src))]>; 683def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src), 684 "lfd $rD, $src", LdStLFD, 685 [(set F8RC:$rD, (load iaddr:$src))]>; 686 687 688// Unindexed (r+i) Loads with Update (preinc). 689let mayLoad = 1 in { 690def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 691 "lbzu $rD, $addr", LdStLoadUpd, 692 []>, RegConstraint<"$addr.reg = $ea_result">, 693 NoEncode<"$ea_result">; 694 695def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 696 "lhau $rD, $addr", LdStLHAU, 697 []>, RegConstraint<"$addr.reg = $ea_result">, 698 NoEncode<"$ea_result">; 699 700def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 701 "lhzu $rD, $addr", LdStLoadUpd, 702 []>, RegConstraint<"$addr.reg = $ea_result">, 703 NoEncode<"$ea_result">; 704 705def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 706 "lwzu $rD, $addr", LdStLoadUpd, 707 []>, RegConstraint<"$addr.reg = $ea_result">, 708 NoEncode<"$ea_result">; 709 710def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 711 "lfsu $rD, $addr", LdStLFDU, 712 []>, RegConstraint<"$addr.reg = $ea_result">, 713 NoEncode<"$ea_result">; 714 715def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 716 "lfdu $rD, $addr", LdStLFDU, 717 []>, RegConstraint<"$addr.reg = $ea_result">, 718 NoEncode<"$ea_result">; 719 720 721// Indexed (r+r) Loads with Update (preinc). 722def LBZUX : XForm_1<31, 119, (outs GPRC:$rD, ptr_rc:$ea_result), 723 (ins memrr:$addr), 724 "lbzux $rD, $addr", LdStLoadUpd, 725 []>, RegConstraint<"$addr.offreg = $ea_result">, 726 NoEncode<"$ea_result">; 727 728def LHAUX : XForm_1<31, 375, (outs GPRC:$rD, ptr_rc:$ea_result), 729 (ins memrr:$addr), 730 "lhaux $rD, $addr", LdStLHAU, 731 []>, RegConstraint<"$addr.offreg = $ea_result">, 732 NoEncode<"$ea_result">; 733 734def LHZUX : XForm_1<31, 331, (outs GPRC:$rD, ptr_rc:$ea_result), 735 (ins memrr:$addr), 736 "lhzux $rD, $addr", LdStLoadUpd, 737 []>, RegConstraint<"$addr.offreg = $ea_result">, 738 NoEncode<"$ea_result">; 739 740def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc:$ea_result), 741 (ins memrr:$addr), 742 "lwzux $rD, $addr", LdStLoadUpd, 743 []>, RegConstraint<"$addr.offreg = $ea_result">, 744 NoEncode<"$ea_result">; 745 746def LFSUX : XForm_1<31, 567, (outs F4RC:$rD, ptr_rc:$ea_result), 747 (ins memrr:$addr), 748 "lfsux $rD, $addr", LdStLFDU, 749 []>, RegConstraint<"$addr.offreg = $ea_result">, 750 NoEncode<"$ea_result">; 751 752def LFDUX : XForm_1<31, 631, (outs F8RC:$rD, ptr_rc:$ea_result), 753 (ins memrr:$addr), 754 "lfdux $rD, $addr", LdStLFDU, 755 []>, RegConstraint<"$addr.offreg = $ea_result">, 756 NoEncode<"$ea_result">; 757} 758} 759 760// Indexed (r+r) Loads. 761// 762let canFoldAsLoad = 1, PPC970_Unit = 2 in { 763def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src), 764 "lbzx $rD, $src", LdStLoad, 765 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>; 766def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src), 767 "lhax $rD, $src", LdStLHA, 768 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>, 769 PPC970_DGroup_Cracked; 770def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src), 771 "lhzx $rD, $src", LdStLoad, 772 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>; 773def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src), 774 "lwzx $rD, $src", LdStLoad, 775 [(set GPRC:$rD, (load xaddr:$src))]>; 776 777 778def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src), 779 "lhbrx $rD, $src", LdStLoad, 780 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>; 781def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src), 782 "lwbrx $rD, $src", LdStLoad, 783 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>; 784 785def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src), 786 "lfsx $frD, $src", LdStLFD, 787 [(set F4RC:$frD, (load xaddr:$src))]>; 788def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src), 789 "lfdx $frD, $src", LdStLFD, 790 [(set F8RC:$frD, (load xaddr:$src))]>; 791} 792 793//===----------------------------------------------------------------------===// 794// PPC32 Store Instructions. 795// 796 797// Unindexed (r+i) Stores. 798let PPC970_Unit = 2 in { 799def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src), 800 "stb $rS, $src", LdStStore, 801 [(truncstorei8 GPRC:$rS, iaddr:$src)]>; 802def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src), 803 "sth $rS, $src", LdStStore, 804 [(truncstorei16 GPRC:$rS, iaddr:$src)]>; 805def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src), 806 "stw $rS, $src", LdStStore, 807 [(store GPRC:$rS, iaddr:$src)]>; 808def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst), 809 "stfs $rS, $dst", LdStSTFD, 810 [(store F4RC:$rS, iaddr:$dst)]>; 811def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst), 812 "stfd $rS, $dst", LdStSTFD, 813 [(store F8RC:$rS, iaddr:$dst)]>; 814} 815 816// Unindexed (r+i) Stores with Update (preinc). 817let PPC970_Unit = 2 in { 818def STBU : DForm_1a<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 819 symbolLo:$ptroff, ptr_rc:$ptrreg), 820 "stbu $rS, $ptroff($ptrreg)", LdStStoreUpd, 821 [(set ptr_rc:$ea_res, 822 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg, 823 iaddroff:$ptroff))]>, 824 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 825def STHU : DForm_1a<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 826 symbolLo:$ptroff, ptr_rc:$ptrreg), 827 "sthu $rS, $ptroff($ptrreg)", LdStStoreUpd, 828 [(set ptr_rc:$ea_res, 829 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg, 830 iaddroff:$ptroff))]>, 831 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 832def STWU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 833 symbolLo:$ptroff, ptr_rc:$ptrreg), 834 "stwu $rS, $ptroff($ptrreg)", LdStStoreUpd, 835 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg, 836 iaddroff:$ptroff))]>, 837 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 838def STFSU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS, 839 symbolLo:$ptroff, ptr_rc:$ptrreg), 840 "stfsu $rS, $ptroff($ptrreg)", LdStSTFDU, 841 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg, 842 iaddroff:$ptroff))]>, 843 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 844def STFDU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS, 845 symbolLo:$ptroff, ptr_rc:$ptrreg), 846 "stfdu $rS, $ptroff($ptrreg)", LdStSTFDU, 847 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg, 848 iaddroff:$ptroff))]>, 849 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 850} 851 852 853// Indexed (r+r) Stores. 854// 855let PPC970_Unit = 2 in { 856def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst), 857 "stbx $rS, $dst", LdStStore, 858 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>, 859 PPC970_DGroup_Cracked; 860def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst), 861 "sthx $rS, $dst", LdStStore, 862 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>, 863 PPC970_DGroup_Cracked; 864def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst), 865 "stwx $rS, $dst", LdStStore, 866 [(store GPRC:$rS, xaddr:$dst)]>, 867 PPC970_DGroup_Cracked; 868 869def STBUX : XForm_8<31, 247, (outs ptr_rc:$ea_res), 870 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 871 "stbux $rS, $ptroff, $ptrreg", LdStStoreUpd, 872 [(set ptr_rc:$ea_res, 873 (pre_truncsti8 GPRC:$rS, 874 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 875 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 876 PPC970_DGroup_Cracked; 877 878def STHUX : XForm_8<31, 439, (outs ptr_rc:$ea_res), 879 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 880 "sthux $rS, $ptroff, $ptrreg", LdStStoreUpd, 881 [(set ptr_rc:$ea_res, 882 (pre_truncsti16 GPRC:$rS, 883 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 884 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 885 PPC970_DGroup_Cracked; 886 887def STWUX : XForm_8<31, 183, (outs ptr_rc:$ea_res), 888 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 889 "stwux $rS, $ptroff, $ptrreg", LdStStoreUpd, 890 [(set ptr_rc:$ea_res, 891 (pre_store GPRC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 892 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 893 PPC970_DGroup_Cracked; 894 895def STFSUX : XForm_8<31, 695, (outs ptr_rc:$ea_res), 896 (ins F4RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 897 "stfsux $rS, $ptroff, $ptrreg", LdStSTFDU, 898 [(set ptr_rc:$ea_res, 899 (pre_store F4RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 900 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 901 PPC970_DGroup_Cracked; 902 903def STFDUX : XForm_8<31, 759, (outs ptr_rc:$ea_res), 904 (ins F8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 905 "stfdux $rS, $ptroff, $ptrreg", LdStSTFDU, 906 [(set ptr_rc:$ea_res, 907 (pre_store F8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 908 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 909 PPC970_DGroup_Cracked; 910 911def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst), 912 "sthbrx $rS, $dst", LdStStore, 913 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>, 914 PPC970_DGroup_Cracked; 915def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst), 916 "stwbrx $rS, $dst", LdStStore, 917 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>, 918 PPC970_DGroup_Cracked; 919 920def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst), 921 "stfiwx $frS, $dst", LdStSTFD, 922 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>; 923 924def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst), 925 "stfsx $frS, $dst", LdStSTFD, 926 [(store F4RC:$frS, xaddr:$dst)]>; 927def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst), 928 "stfdx $frS, $dst", LdStSTFD, 929 [(store F8RC:$frS, xaddr:$dst)]>; 930} 931 932def SYNC : XForm_24_sync<31, 598, (outs), (ins), 933 "sync", LdStSync, 934 [(int_ppc_sync)]>; 935 936//===----------------------------------------------------------------------===// 937// PPC32 Arithmetic Instructions. 938// 939 940let PPC970_Unit = 1 in { // FXU Operations. 941def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 942 "addi $rD, $rA, $imm", IntSimple, 943 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; 944def ADDIL : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$imm), 945 "addi $rD, $rA, $imm", IntSimple, 946 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; 947let Defs = [CARRY] in { 948def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 949 "addic $rD, $rA, $imm", IntGeneral, 950 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>, 951 PPC970_DGroup_Cracked; 952def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 953 "addic. $rD, $rA, $imm", IntGeneral, 954 []>; 955} 956def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm), 957 "addis $rD, $rA, $imm", IntSimple, 958 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>; 959def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym), 960 "la $rD, $sym($rA)", IntGeneral, 961 [(set GPRC:$rD, (add GPRC:$rA, 962 (PPClo tglobaladdr:$sym, 0)))]>; 963def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 964 "mulli $rD, $rA, $imm", IntMulLI, 965 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; 966let Defs = [CARRY] in { 967def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 968 "subfic $rD, $rA, $imm", IntGeneral, 969 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>; 970} 971 972let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 973 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm), 974 "li $rD, $imm", IntSimple, 975 [(set GPRC:$rD, immSExt16:$imm)]>; 976 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm), 977 "lis $rD, $imm", IntSimple, 978 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>; 979} 980} 981 982let PPC970_Unit = 1 in { // FXU Operations. 983def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 984 "andi. $dst, $src1, $src2", IntGeneral, 985 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>, 986 isDOT; 987def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 988 "andis. $dst, $src1, $src2", IntGeneral, 989 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>, 990 isDOT; 991def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 992 "ori $dst, $src1, $src2", IntSimple, 993 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; 994def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 995 "oris $dst, $src1, $src2", IntSimple, 996 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>; 997def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 998 "xori $dst, $src1, $src2", IntSimple, 999 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; 1000def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1001 "xoris $dst, $src1, $src2", IntSimple, 1002 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>; 1003def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple, 1004 []>; 1005def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm), 1006 "cmpwi $crD, $rA, $imm", IntCompare>; 1007def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1008 "cmplwi $dst, $src1, $src2", IntCompare>; 1009} 1010 1011 1012let PPC970_Unit = 1 in { // FXU Operations. 1013def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1014 "nand $rA, $rS, $rB", IntSimple, 1015 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; 1016def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1017 "and $rA, $rS, $rB", IntSimple, 1018 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; 1019def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1020 "andc $rA, $rS, $rB", IntSimple, 1021 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; 1022def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1023 "or $rA, $rS, $rB", IntSimple, 1024 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; 1025def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1026 "nor $rA, $rS, $rB", IntSimple, 1027 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>; 1028def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1029 "orc $rA, $rS, $rB", IntSimple, 1030 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>; 1031def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1032 "eqv $rA, $rS, $rB", IntSimple, 1033 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>; 1034def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1035 "xor $rA, $rS, $rB", IntSimple, 1036 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>; 1037def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1038 "slw $rA, $rS, $rB", IntGeneral, 1039 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>; 1040def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1041 "srw $rA, $rS, $rB", IntGeneral, 1042 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>; 1043let Defs = [CARRY] in { 1044def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1045 "sraw $rA, $rS, $rB", IntShift, 1046 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>; 1047} 1048} 1049 1050let PPC970_Unit = 1 in { // FXU Operations. 1051let Defs = [CARRY] in { 1052def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH), 1053 "srawi $rA, $rS, $SH", IntShift, 1054 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>; 1055} 1056def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS), 1057 "cntlzw $rA, $rS", IntGeneral, 1058 [(set GPRC:$rA, (ctlz GPRC:$rS))]>; 1059def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS), 1060 "extsb $rA, $rS", IntSimple, 1061 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>; 1062def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS), 1063 "extsh $rA, $rS", IntSimple, 1064 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>; 1065 1066def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 1067 "cmpw $crD, $rA, $rB", IntCompare>; 1068def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 1069 "cmplw $crD, $rA, $rB", IntCompare>; 1070} 1071let PPC970_Unit = 3 in { // FPU Operations. 1072//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), 1073// "fcmpo $crD, $fA, $fB", FPCompare>; 1074def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB), 1075 "fcmpu $crD, $fA, $fB", FPCompare>; 1076def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB), 1077 "fcmpu $crD, $fA, $fB", FPCompare>; 1078 1079let Uses = [RM] in { 1080 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB), 1081 "fctiwz $frD, $frB", FPGeneral, 1082 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>; 1083 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB), 1084 "frsp $frD, $frB", FPGeneral, 1085 [(set F4RC:$frD, (fround F8RC:$frB))]>; 1086 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB), 1087 "fsqrt $frD, $frB", FPSqrt, 1088 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>; 1089 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB), 1090 "fsqrts $frD, $frB", FPSqrt, 1091 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>; 1092 } 1093} 1094 1095/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 1096/// often coalesced away and we don't want the dispatch group builder to think 1097/// that they will fill slots (which could cause the load of a LSU reject to 1098/// sneak into a d-group with a store). 1099def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB), 1100 "fmr $frD, $frB", FPGeneral, 1101 []>, // (set F4RC:$frD, F4RC:$frB) 1102 PPC970_Unit_Pseudo; 1103 1104let PPC970_Unit = 3 in { // FPU Operations. 1105// These are artificially split into two different forms, for 4/8 byte FP. 1106def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB), 1107 "fabs $frD, $frB", FPGeneral, 1108 [(set F4RC:$frD, (fabs F4RC:$frB))]>; 1109def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB), 1110 "fabs $frD, $frB", FPGeneral, 1111 [(set F8RC:$frD, (fabs F8RC:$frB))]>; 1112def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB), 1113 "fnabs $frD, $frB", FPGeneral, 1114 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>; 1115def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB), 1116 "fnabs $frD, $frB", FPGeneral, 1117 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>; 1118def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB), 1119 "fneg $frD, $frB", FPGeneral, 1120 [(set F4RC:$frD, (fneg F4RC:$frB))]>; 1121def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB), 1122 "fneg $frD, $frB", FPGeneral, 1123 [(set F8RC:$frD, (fneg F8RC:$frB))]>; 1124} 1125 1126 1127// XL-Form instructions. condition register logical ops. 1128// 1129def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA), 1130 "mcrf $BF, $BFA", BrMCR>, 1131 PPC970_DGroup_First, PPC970_Unit_CRU; 1132 1133def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD), 1134 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1135 "creqv $CRD, $CRA, $CRB", BrCR, 1136 []>; 1137 1138def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD), 1139 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1140 "cror $CRD, $CRA, $CRB", BrCR, 1141 []>; 1142 1143def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins), 1144 "creqv $dst, $dst, $dst", BrCR, 1145 []>; 1146 1147def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins), 1148 "crxor $dst, $dst, $dst", BrCR, 1149 []>; 1150 1151let Defs = [CR1EQ], CRD = 6 in { 1152def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 1153 "creqv 6, 6, 6", BrCR, 1154 [(PPCcr6set)]>; 1155 1156def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 1157 "crxor 6, 6, 6", BrCR, 1158 [(PPCcr6unset)]>; 1159} 1160 1161// XFX-Form instructions. Instructions that deal with SPRs. 1162// 1163let Uses = [CTR] in { 1164def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins), 1165 "mfctr $rT", SprMFSPR>, 1166 PPC970_DGroup_First, PPC970_Unit_FXU; 1167} 1168let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in { 1169def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS), 1170 "mtctr $rS", SprMTSPR>, 1171 PPC970_DGroup_First, PPC970_Unit_FXU; 1172} 1173 1174let Defs = [LR] in { 1175def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS), 1176 "mtlr $rS", SprMTSPR>, 1177 PPC970_DGroup_First, PPC970_Unit_FXU; 1178} 1179let Uses = [LR] in { 1180def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins), 1181 "mflr $rT", SprMFSPR>, 1182 PPC970_DGroup_First, PPC970_Unit_FXU; 1183} 1184 1185// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like 1186// a GPR on the PPC970. As such, copies in and out have the same performance 1187// characteristics as an OR instruction. 1188def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS), 1189 "mtspr 256, $rS", IntGeneral>, 1190 PPC970_DGroup_Single, PPC970_Unit_FXU; 1191def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins), 1192 "mfspr $rT, 256", IntGeneral>, 1193 PPC970_DGroup_First, PPC970_Unit_FXU; 1194 1195def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS), 1196 "mtcrf $FXM, $rS", BrMCRX>, 1197 PPC970_MicroCode, PPC970_Unit_CRU; 1198 1199// This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters; 1200// declaring that here gives the local register allocator problems with this: 1201// vreg = MCRF CR0 1202// MFCR <kill of whatever preg got assigned to vreg> 1203// while not declaring it breaks DeadMachineInstructionElimination. 1204// As it turns out, in all cases where we currently use this, 1205// we're only interested in one subregister of it. Represent this in the 1206// instruction to keep the register allocator from becoming confused. 1207// 1208// FIXME: Make this a real Pseudo instruction when the JIT switches to MC. 1209def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), 1210 "", SprMFCR>, 1211 PPC970_MicroCode, PPC970_Unit_CRU; 1212 1213def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), 1214 "mfcr $rT", SprMFCR>, 1215 PPC970_MicroCode, PPC970_Unit_CRU; 1216 1217def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), 1218 "mfocrf $rT, $FXM", SprMFCR>, 1219 PPC970_DGroup_First, PPC970_Unit_CRU; 1220 1221// Instructions to manipulate FPSCR. Only long double handling uses these. 1222// FPSCR is not modelled; we use the SDNode Flag to keep things in order. 1223 1224let Uses = [RM], Defs = [RM] in { 1225 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 1226 "mtfsb0 $FM", IntMTFSB0, 1227 [(PPCmtfsb0 (i32 imm:$FM))]>, 1228 PPC970_DGroup_Single, PPC970_Unit_FPU; 1229 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 1230 "mtfsb1 $FM", IntMTFSB0, 1231 [(PPCmtfsb1 (i32 imm:$FM))]>, 1232 PPC970_DGroup_Single, PPC970_Unit_FPU; 1233 // MTFSF does not actually produce an FP result. We pretend it copies 1234 // input reg B to the output. If we didn't do this it would look like the 1235 // instruction had no outputs (because we aren't modelling the FPSCR) and 1236 // it would be deleted. 1237 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA), 1238 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB), 1239 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0, 1240 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM), 1241 F8RC:$rT, F8RC:$FRB))]>, 1242 PPC970_DGroup_Single, PPC970_Unit_FPU; 1243} 1244let Uses = [RM] in { 1245 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins), 1246 "mffs $rT", IntMFFS, 1247 [(set F8RC:$rT, (PPCmffs))]>, 1248 PPC970_DGroup_Single, PPC970_Unit_FPU; 1249 def FADDrtz: AForm_2<63, 21, 1250 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1251 "fadd $FRT, $FRA, $FRB", FPAddSub, 1252 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>, 1253 PPC970_DGroup_Single, PPC970_Unit_FPU; 1254} 1255 1256 1257let PPC970_Unit = 1 in { // FXU Operations. 1258 1259// XO-Form instructions. Arithmetic instructions that can set overflow bit 1260// 1261def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1262 "add $rT, $rA, $rB", IntSimple, 1263 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>; 1264let Defs = [CARRY] in { 1265def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1266 "addc $rT, $rA, $rB", IntGeneral, 1267 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>, 1268 PPC970_DGroup_Cracked; 1269} 1270def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1271 "divw $rT, $rA, $rB", IntDivW, 1272 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>, 1273 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1274def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1275 "divwu $rT, $rA, $rB", IntDivW, 1276 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>, 1277 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1278def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1279 "mulhw $rT, $rA, $rB", IntMulHW, 1280 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>; 1281def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1282 "mulhwu $rT, $rA, $rB", IntMulHWU, 1283 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>; 1284def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1285 "mullw $rT, $rA, $rB", IntMulHW, 1286 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>; 1287def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1288 "subf $rT, $rA, $rB", IntGeneral, 1289 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>; 1290let Defs = [CARRY] in { 1291def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1292 "subfc $rT, $rA, $rB", IntGeneral, 1293 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>, 1294 PPC970_DGroup_Cracked; 1295} 1296def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1297 "neg $rT, $rA", IntSimple, 1298 [(set GPRC:$rT, (ineg GPRC:$rA))]>; 1299let Uses = [CARRY], Defs = [CARRY] in { 1300def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1301 "adde $rT, $rA, $rB", IntGeneral, 1302 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>; 1303def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1304 "addme $rT, $rA", IntGeneral, 1305 [(set GPRC:$rT, (adde GPRC:$rA, -1))]>; 1306def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1307 "addze $rT, $rA", IntGeneral, 1308 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>; 1309def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1310 "subfe $rT, $rA, $rB", IntGeneral, 1311 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>; 1312def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1313 "subfme $rT, $rA", IntGeneral, 1314 [(set GPRC:$rT, (sube -1, GPRC:$rA))]>; 1315def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1316 "subfze $rT, $rA", IntGeneral, 1317 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>; 1318} 1319} 1320 1321// A-Form instructions. Most of the instructions executed in the FPU are of 1322// this type. 1323// 1324let PPC970_Unit = 3 in { // FPU Operations. 1325let Uses = [RM] in { 1326 def FMADD : AForm_1<63, 29, 1327 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1328 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1329 [(set F8RC:$FRT, 1330 (fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB))]>; 1331 def FMADDS : AForm_1<59, 29, 1332 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1333 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1334 [(set F4RC:$FRT, 1335 (fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB))]>; 1336 def FMSUB : AForm_1<63, 28, 1337 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1338 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1339 [(set F8RC:$FRT, 1340 (fma F8RC:$FRA, F8RC:$FRC, (fneg F8RC:$FRB)))]>; 1341 def FMSUBS : AForm_1<59, 28, 1342 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1343 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1344 [(set F4RC:$FRT, 1345 (fma F4RC:$FRA, F4RC:$FRC, (fneg F4RC:$FRB)))]>; 1346 def FNMADD : AForm_1<63, 31, 1347 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1348 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1349 [(set F8RC:$FRT, 1350 (fneg (fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB)))]>; 1351 def FNMADDS : AForm_1<59, 31, 1352 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1353 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1354 [(set F4RC:$FRT, 1355 (fneg (fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB)))]>; 1356 def FNMSUB : AForm_1<63, 30, 1357 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1358 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1359 [(set F8RC:$FRT, (fneg (fma F8RC:$FRA, F8RC:$FRC, 1360 (fneg F8RC:$FRB))))]>; 1361 def FNMSUBS : AForm_1<59, 30, 1362 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1363 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1364 [(set F4RC:$FRT, (fneg (fma F4RC:$FRA, F4RC:$FRC, 1365 (fneg F4RC:$FRB))))]>; 1366} 1367// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 1368// having 4 of these, force the comparison to always be an 8-byte double (code 1369// should use an FMRSD if the input comparison value really wants to be a float) 1370// and 4/8 byte forms for the result and operand type.. 1371def FSELD : AForm_1<63, 23, 1372 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1373 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1374 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>; 1375def FSELS : AForm_1<63, 23, 1376 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1377 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1378 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>; 1379let Uses = [RM] in { 1380 def FADD : AForm_2<63, 21, 1381 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1382 "fadd $FRT, $FRA, $FRB", FPAddSub, 1383 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>; 1384 def FADDS : AForm_2<59, 21, 1385 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1386 "fadds $FRT, $FRA, $FRB", FPGeneral, 1387 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; 1388 def FDIV : AForm_2<63, 18, 1389 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1390 "fdiv $FRT, $FRA, $FRB", FPDivD, 1391 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>; 1392 def FDIVS : AForm_2<59, 18, 1393 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1394 "fdivs $FRT, $FRA, $FRB", FPDivS, 1395 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>; 1396 def FMUL : AForm_3<63, 25, 1397 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1398 "fmul $FRT, $FRA, $FRB", FPFused, 1399 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>; 1400 def FMULS : AForm_3<59, 25, 1401 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1402 "fmuls $FRT, $FRA, $FRB", FPGeneral, 1403 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>; 1404 def FSUB : AForm_2<63, 20, 1405 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1406 "fsub $FRT, $FRA, $FRB", FPAddSub, 1407 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>; 1408 def FSUBS : AForm_2<59, 20, 1409 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1410 "fsubs $FRT, $FRA, $FRB", FPGeneral, 1411 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; 1412 } 1413} 1414 1415let PPC970_Unit = 1 in { // FXU Operations. 1416 def ISEL : AForm_1<31, 15, 1417 (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB, pred:$cond), 1418 "isel $rT, $rA, $rB, $cond", IntGeneral, 1419 []>; 1420} 1421 1422let PPC970_Unit = 1 in { // FXU Operations. 1423// M-Form instructions. rotate and mask instructions. 1424// 1425let isCommutable = 1 in { 1426// RLWIMI can be commuted if the rotate amount is zero. 1427def RLWIMI : MForm_2<20, 1428 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 1429 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate, 1430 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">, 1431 NoEncode<"$rSi">; 1432} 1433def RLWINM : MForm_2<21, 1434 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1435 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 1436 []>; 1437def RLWINMo : MForm_2<21, 1438 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1439 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, 1440 []>, isDOT, PPC970_DGroup_Cracked; 1441def RLWNM : MForm_2<23, 1442 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), 1443 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral, 1444 []>; 1445} 1446 1447 1448//===----------------------------------------------------------------------===// 1449// PowerPC Instruction Patterns 1450// 1451 1452// Arbitrary immediate support. Implement in terms of LIS/ORI. 1453def : Pat<(i32 imm:$imm), 1454 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 1455 1456// Implement the 'not' operation with the NOR instruction. 1457def NOT : Pat<(not GPRC:$in), 1458 (NOR GPRC:$in, GPRC:$in)>; 1459 1460// ADD an arbitrary immediate. 1461def : Pat<(add GPRC:$in, imm:$imm), 1462 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 1463// OR an arbitrary immediate. 1464def : Pat<(or GPRC:$in, imm:$imm), 1465 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1466// XOR an arbitrary immediate. 1467def : Pat<(xor GPRC:$in, imm:$imm), 1468 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1469// SUBFIC 1470def : Pat<(sub immSExt16:$imm, GPRC:$in), 1471 (SUBFIC GPRC:$in, imm:$imm)>; 1472 1473// SHL/SRL 1474def : Pat<(shl GPRC:$in, (i32 imm:$imm)), 1475 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>; 1476def : Pat<(srl GPRC:$in, (i32 imm:$imm)), 1477 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>; 1478 1479// ROTL 1480def : Pat<(rotl GPRC:$in, GPRC:$sh), 1481 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>; 1482def : Pat<(rotl GPRC:$in, (i32 imm:$imm)), 1483 (RLWINM GPRC:$in, imm:$imm, 0, 31)>; 1484 1485// RLWNM 1486def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm), 1487 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 1488 1489// Calls 1490def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)), 1491 (BL_Darwin tglobaladdr:$dst)>; 1492def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)), 1493 (BL_Darwin texternalsym:$dst)>; 1494def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)), 1495 (BL_SVR4 tglobaladdr:$dst)>; 1496def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)), 1497 (BL_SVR4 texternalsym:$dst)>; 1498 1499 1500def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 1501 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 1502 1503def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 1504 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 1505 1506def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 1507 (TCRETURNri CTRRC:$dst, imm:$imm)>; 1508 1509 1510 1511// Hi and Lo for Darwin Global Addresses. 1512def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 1513def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 1514def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 1515def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 1516def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 1517def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 1518def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 1519def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 1520def : Pat<(PPChi tglobaltlsaddr:$g, GPRC:$in), 1521 (ADDIS GPRC:$in, tglobaltlsaddr:$g)>; 1522def : Pat<(PPClo tglobaltlsaddr:$g, GPRC:$in), 1523 (ADDIL GPRC:$in, tglobaltlsaddr:$g)>; 1524def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)), 1525 (ADDIS GPRC:$in, tglobaladdr:$g)>; 1526def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)), 1527 (ADDIS GPRC:$in, tconstpool:$g)>; 1528def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)), 1529 (ADDIS GPRC:$in, tjumptable:$g)>; 1530def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)), 1531 (ADDIS GPRC:$in, tblockaddress:$g)>; 1532 1533// Standard shifts. These are represented separately from the real shifts above 1534// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 1535// amounts. 1536def : Pat<(sra GPRC:$rS, GPRC:$rB), 1537 (SRAW GPRC:$rS, GPRC:$rB)>; 1538def : Pat<(srl GPRC:$rS, GPRC:$rB), 1539 (SRW GPRC:$rS, GPRC:$rB)>; 1540def : Pat<(shl GPRC:$rS, GPRC:$rB), 1541 (SLW GPRC:$rS, GPRC:$rB)>; 1542 1543def : Pat<(zextloadi1 iaddr:$src), 1544 (LBZ iaddr:$src)>; 1545def : Pat<(zextloadi1 xaddr:$src), 1546 (LBZX xaddr:$src)>; 1547def : Pat<(extloadi1 iaddr:$src), 1548 (LBZ iaddr:$src)>; 1549def : Pat<(extloadi1 xaddr:$src), 1550 (LBZX xaddr:$src)>; 1551def : Pat<(extloadi8 iaddr:$src), 1552 (LBZ iaddr:$src)>; 1553def : Pat<(extloadi8 xaddr:$src), 1554 (LBZX xaddr:$src)>; 1555def : Pat<(extloadi16 iaddr:$src), 1556 (LHZ iaddr:$src)>; 1557def : Pat<(extloadi16 xaddr:$src), 1558 (LHZX xaddr:$src)>; 1559def : Pat<(f64 (extloadf32 iaddr:$src)), 1560 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>; 1561def : Pat<(f64 (extloadf32 xaddr:$src)), 1562 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>; 1563 1564def : Pat<(f64 (fextend F4RC:$src)), 1565 (COPY_TO_REGCLASS F4RC:$src, F8RC)>; 1566 1567// Memory barriers 1568def : Pat<(membarrier (i32 imm /*ll*/), 1569 (i32 imm /*ls*/), 1570 (i32 imm /*sl*/), 1571 (i32 imm /*ss*/), 1572 (i32 imm /*device*/)), 1573 (SYNC)>; 1574 1575def : Pat<(atomic_fence (imm), (imm)), (SYNC)>; 1576 1577include "PPCInstrAltivec.td" 1578include "PPCInstr64Bit.td" 1579