1//===-- SPUISelLowering.h - Cell SPU DAG Lowering Interface -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Cell SPU uses to lower LLVM code into
11// a selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef SPU_ISELLOWERING_H
16#define SPU_ISELLOWERING_H
17
18#include "SPU.h"
19#include "llvm/Target/TargetLowering.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21
22namespace llvm {
23  namespace SPUISD {
24    enum NodeType {
25      // Start the numbering where the builting ops and target ops leave off.
26      FIRST_NUMBER = ISD::BUILTIN_OP_END,
27
28      // Pseudo instructions:
29      RET_FLAG,                 ///< Return with flag, matched by bi instruction
30
31      Hi,                       ///< High address component (upper 16)
32      Lo,                       ///< Low address component (lower 16)
33      PCRelAddr,                ///< Program counter relative address
34      AFormAddr,                ///< A-form address (local store)
35      IndirectAddr,             ///< D-Form "imm($r)" and X-form "$r($r)"
36
37      LDRESULT,                 ///< Load result (value, chain)
38      CALL,                     ///< CALL instruction
39      SHUFB,                    ///< Vector shuffle (permute)
40      SHUFFLE_MASK,             ///< Shuffle mask
41      CNTB,                     ///< Count leading ones in bytes
42      PREFSLOT2VEC,             ///< Promote scalar->vector
43      VEC2PREFSLOT,             ///< Extract element 0
44      SHL_BITS,                 ///< Shift quad left, by bits
45      SHL_BYTES,                ///< Shift quad left, by bytes
46      SRL_BYTES,                ///< Shift quad right, by bytes. Insert zeros.
47      VEC_ROTL,                 ///< Vector rotate left
48      VEC_ROTR,                 ///< Vector rotate right
49      ROTBYTES_LEFT,            ///< Rotate bytes (loads -> ROTQBYI)
50      ROTBYTES_LEFT_BITS,       ///< Rotate bytes left by bit shift count
51      SELECT_MASK,              ///< Select Mask (FSM, FSMB, FSMH, FSMBI)
52      SELB,                     ///< Select bits -> (b & mask) | (a & ~mask)
53      // Markers: These aren't used to generate target-dependent nodes, but
54      // are used during instruction selection.
55      ADD64_MARKER,             ///< i64 addition marker
56      SUB64_MARKER,             ///< i64 subtraction marker
57      MUL64_MARKER,             ///< i64 multiply marker
58      LAST_SPUISD               ///< Last user-defined instruction
59    };
60  }
61
62  //! Utility functions specific to CellSPU:
63  namespace SPU {
64    SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
65                             EVT ValueType);
66    SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
67                             EVT ValueType);
68    SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
69                             EVT ValueType);
70    SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
71                            EVT ValueType);
72    SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
73                              EVT ValueType);
74    SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
75    SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
76
77    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG,
78                              const SPUTargetMachine &TM);
79    //! Simplify a EVT::v2i64 constant splat to CellSPU-ready form
80    SDValue LowerV2I64Splat(EVT OpVT, SelectionDAG &DAG, uint64_t splat,
81                             DebugLoc dl);
82  }
83
84  class SPUTargetMachine;            // forward dec'l.
85
86  class SPUTargetLowering :
87    public TargetLowering
88  {
89    SPUTargetMachine &SPUTM;
90
91  public:
92    //! The venerable constructor
93    /*!
94     This is where the CellSPU backend sets operation handling (i.e., legal,
95     custom, expand or promote.)
96     */
97    SPUTargetLowering(SPUTargetMachine &TM);
98
99    //! Get the target machine
100    SPUTargetMachine &getSPUTargetMachine() {
101      return SPUTM;
102    }
103
104    /// getTargetNodeName() - This method returns the name of a target specific
105    /// DAG node.
106    virtual const char *getTargetNodeName(unsigned Opcode) const;
107
108    /// getSetCCResultType - Return the ValueType for ISD::SETCC
109    virtual EVT getSetCCResultType(EVT VT) const;
110
111    virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
112
113    //! Custom lowering hooks
114    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
115
116    //! Custom lowering hook for nodes with illegal result types.
117    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
118                                    SelectionDAG &DAG) const;
119
120    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
121
122    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
123                                                APInt &KnownZero,
124                                                APInt &KnownOne,
125                                                const SelectionDAG &DAG,
126                                                unsigned Depth = 0) const;
127
128    virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
129                                                   unsigned Depth = 0) const;
130
131    ConstraintType getConstraintType(const std::string &ConstraintLetter) const;
132
133    /// Examine constraint string and operand type and determine a weight value.
134    /// The operand object must already have been set up with the operand type.
135    ConstraintWeight getSingleConstraintMatchWeight(
136      AsmOperandInfo &info, const char *constraint) const;
137
138    std::pair<unsigned, const TargetRegisterClass*>
139      getRegForInlineAsmConstraint(const std::string &Constraint,
140                                   EVT VT) const;
141
142    void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
143                                      std::vector<SDValue> &Ops,
144                                      SelectionDAG &DAG) const;
145
146    /// isLegalAddressImmediate - Return true if the integer value can be used
147    /// as the offset of the target addressing mode.
148    virtual bool isLegalAddressImmediate(int64_t V, Type *Ty) const;
149    virtual bool isLegalAddressImmediate(GlobalValue *) const;
150
151    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
152
153    virtual SDValue
154      LowerFormalArguments(SDValue Chain,
155                           CallingConv::ID CallConv, bool isVarArg,
156                           const SmallVectorImpl<ISD::InputArg> &Ins,
157                           DebugLoc dl, SelectionDAG &DAG,
158                           SmallVectorImpl<SDValue> &InVals) const;
159
160    virtual SDValue
161      LowerCall(TargetLowering::CallLoweringInfo &CLI,
162                SmallVectorImpl<SDValue> &InVals) const;
163
164    virtual SDValue
165      LowerReturn(SDValue Chain,
166                  CallingConv::ID CallConv, bool isVarArg,
167                  const SmallVectorImpl<ISD::OutputArg> &Outs,
168                  const SmallVectorImpl<SDValue> &OutVals,
169                  DebugLoc dl, SelectionDAG &DAG) const;
170
171    virtual bool isLegalICmpImmediate(int64_t Imm) const;
172
173    virtual bool isLegalAddressingMode(const AddrMode &AM,
174                                       Type *Ty) const;
175  };
176}
177
178#endif
179