1//===-- SPUHazardRecognizers.cpp - Cell Hazard Recognizer Impls -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements hazard recognizers for scheduling on Cell SPU 11// processors. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "sched" 16 17#include "SPUHazardRecognizers.h" 18#include "SPU.h" 19#include "SPUInstrInfo.h" 20#include "llvm/CodeGen/ScheduleDAG.h" 21#include "llvm/CodeGen/SelectionDAGNodes.h" 22#include "llvm/Support/Debug.h" 23#include "llvm/Support/raw_ostream.h" 24using namespace llvm; 25 26//===----------------------------------------------------------------------===// 27// Cell SPU hazard recognizer 28// 29// This is the pipeline hazard recognizer for the Cell SPU processor. It does 30// very little right now. 31//===----------------------------------------------------------------------===// 32 33/// Return the pipeline hazard type encountered or generated by this 34/// instruction. Currently returns NoHazard. 35/// 36/// \return NoHazard 37ScheduleHazardRecognizer::HazardType 38SPUHazardRecognizer::getHazardType(SUnit *SU, int Stalls) 39{ 40 // Initial thoughts on how to do this, but this code cannot work unless the 41 // function's prolog and epilog code are also being scheduled so that we can 42 // accurately determine which pipeline is being scheduled. 43#if 0 44 assert(Stalls == 0 && "SPU hazards don't yet support scoreboard lookahead"); 45 46 const SDNode *Node = SU->getNode()->getFlaggedMachineNode(); 47 ScheduleHazardRecognizer::HazardType retval = NoHazard; 48 bool mustBeOdd = false; 49 50 switch (Node->getOpcode()) { 51 case SPU::LQDv16i8: 52 case SPU::LQDv8i16: 53 case SPU::LQDv4i32: 54 case SPU::LQDv4f32: 55 case SPU::LQDv2f64: 56 case SPU::LQDr128: 57 case SPU::LQDr64: 58 case SPU::LQDr32: 59 case SPU::LQDr16: 60 case SPU::LQAv16i8: 61 case SPU::LQAv8i16: 62 case SPU::LQAv4i32: 63 case SPU::LQAv4f32: 64 case SPU::LQAv2f64: 65 case SPU::LQAr128: 66 case SPU::LQAr64: 67 case SPU::LQAr32: 68 case SPU::LQXv4i32: 69 case SPU::LQXr128: 70 case SPU::LQXr64: 71 case SPU::LQXr32: 72 case SPU::LQXr16: 73 case SPU::STQDv16i8: 74 case SPU::STQDv8i16: 75 case SPU::STQDv4i32: 76 case SPU::STQDv4f32: 77 case SPU::STQDv2f64: 78 case SPU::STQDr128: 79 case SPU::STQDr64: 80 case SPU::STQDr32: 81 case SPU::STQDr16: 82 case SPU::STQDr8: 83 case SPU::STQAv16i8: 84 case SPU::STQAv8i16: 85 case SPU::STQAv4i32: 86 case SPU::STQAv4f32: 87 case SPU::STQAv2f64: 88 case SPU::STQAr128: 89 case SPU::STQAr64: 90 case SPU::STQAr32: 91 case SPU::STQAr16: 92 case SPU::STQAr8: 93 case SPU::STQXv16i8: 94 case SPU::STQXv8i16: 95 case SPU::STQXv4i32: 96 case SPU::STQXv4f32: 97 case SPU::STQXv2f64: 98 case SPU::STQXr128: 99 case SPU::STQXr64: 100 case SPU::STQXr32: 101 case SPU::STQXr16: 102 case SPU::STQXr8: 103 case SPU::RET: 104 mustBeOdd = true; 105 break; 106 default: 107 // Assume that this instruction can be on the even pipe 108 break; 109 } 110 111 if (mustBeOdd && !EvenOdd) 112 retval = Hazard; 113 114 DEBUG(errs() << "SPUHazardRecognizer EvenOdd " << EvenOdd << " Hazard " 115 << retval << "\n"); 116 EvenOdd ^= 1; 117 return retval; 118#else 119 return NoHazard; 120#endif 121} 122 123void SPUHazardRecognizer::EmitInstruction(SUnit *SU) 124{ 125} 126 127void SPUHazardRecognizer::AdvanceCycle() 128{ 129 DEBUG(errs() << "SPUHazardRecognizer::AdvanceCycle\n"); 130} 131 132void SPUHazardRecognizer::EmitNoop() 133{ 134 AdvanceCycle(); 135} 136