1//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This class prints an ARM MCInst to a .s file. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "asm-printer" 15#include "ARMInstPrinter.h" 16#include "MCTargetDesc/ARMBaseInfo.h" 17#include "MCTargetDesc/ARMAddressingModes.h" 18#include "llvm/MC/MCInst.h" 19#include "llvm/MC/MCAsmInfo.h" 20#include "llvm/MC/MCExpr.h" 21#include "llvm/MC/MCInstrInfo.h" 22#include "llvm/MC/MCRegisterInfo.h" 23#include "llvm/Support/raw_ostream.h" 24using namespace llvm; 25 26#include "ARMGenAsmWriter.inc" 27 28/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing. 29/// 30/// getSORegOffset returns an integer from 0-31, representing '32' as 0. 31static unsigned translateShiftImm(unsigned imm) { 32 // lsr #32 and asr #32 exist, but should be encoded as a 0. 33 assert((imm & ~0x1f) == 0 && "Invalid shift encoding"); 34 35 if (imm == 0) 36 return 32; 37 return imm; 38} 39 40/// Prints the shift value with an immediate value. 41static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, 42 unsigned ShImm) { 43 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) 44 return; 45 O << ", "; 46 47 assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0"); 48 O << getShiftOpcStr(ShOpc); 49 50 if (ShOpc != ARM_AM::rrx) 51 O << " #" << translateShiftImm(ShImm); 52} 53 54ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI, 55 const MCInstrInfo &MII, 56 const MCRegisterInfo &MRI, 57 const MCSubtargetInfo &STI) : 58 MCInstPrinter(MAI, MII, MRI) { 59 // Initialize the set of available features. 60 setAvailableFeatures(STI.getFeatureBits()); 61} 62 63void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { 64 OS << getRegisterName(RegNo); 65} 66 67void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, 68 StringRef Annot) { 69 unsigned Opcode = MI->getOpcode(); 70 71 // Check for HINT instructions w/ canonical names. 72 if (Opcode == ARM::HINT || Opcode == ARM::t2HINT) { 73 switch (MI->getOperand(0).getImm()) { 74 case 0: O << "\tnop"; break; 75 case 1: O << "\tyield"; break; 76 case 2: O << "\twfe"; break; 77 case 3: O << "\twfi"; break; 78 case 4: O << "\tsev"; break; 79 default: 80 // Anything else should just print normally. 81 printInstruction(MI, O); 82 printAnnotation(O, Annot); 83 return; 84 } 85 printPredicateOperand(MI, 1, O); 86 if (Opcode == ARM::t2HINT) 87 O << ".w"; 88 printAnnotation(O, Annot); 89 return; 90 } 91 92 // Check for MOVs and print canonical forms, instead. 93 if (Opcode == ARM::MOVsr) { 94 // FIXME: Thumb variants? 95 const MCOperand &Dst = MI->getOperand(0); 96 const MCOperand &MO1 = MI->getOperand(1); 97 const MCOperand &MO2 = MI->getOperand(2); 98 const MCOperand &MO3 = MI->getOperand(3); 99 100 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); 101 printSBitModifierOperand(MI, 6, O); 102 printPredicateOperand(MI, 4, O); 103 104 O << '\t' << getRegisterName(Dst.getReg()) 105 << ", " << getRegisterName(MO1.getReg()); 106 107 O << ", " << getRegisterName(MO2.getReg()); 108 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); 109 printAnnotation(O, Annot); 110 return; 111 } 112 113 if (Opcode == ARM::MOVsi) { 114 // FIXME: Thumb variants? 115 const MCOperand &Dst = MI->getOperand(0); 116 const MCOperand &MO1 = MI->getOperand(1); 117 const MCOperand &MO2 = MI->getOperand(2); 118 119 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); 120 printSBitModifierOperand(MI, 5, O); 121 printPredicateOperand(MI, 3, O); 122 123 O << '\t' << getRegisterName(Dst.getReg()) 124 << ", " << getRegisterName(MO1.getReg()); 125 126 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { 127 printAnnotation(O, Annot); 128 return; 129 } 130 131 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); 132 printAnnotation(O, Annot); 133 return; 134 } 135 136 137 // A8.6.123 PUSH 138 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) && 139 MI->getOperand(0).getReg() == ARM::SP && 140 MI->getNumOperands() > 5) { 141 // Should only print PUSH if there are at least two registers in the list. 142 O << '\t' << "push"; 143 printPredicateOperand(MI, 2, O); 144 if (Opcode == ARM::t2STMDB_UPD) 145 O << ".w"; 146 O << '\t'; 147 printRegisterList(MI, 4, O); 148 printAnnotation(O, Annot); 149 return; 150 } 151 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP && 152 MI->getOperand(3).getImm() == -4) { 153 O << '\t' << "push"; 154 printPredicateOperand(MI, 4, O); 155 O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}"; 156 printAnnotation(O, Annot); 157 return; 158 } 159 160 // A8.6.122 POP 161 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) && 162 MI->getOperand(0).getReg() == ARM::SP && 163 MI->getNumOperands() > 5) { 164 // Should only print POP if there are at least two registers in the list. 165 O << '\t' << "pop"; 166 printPredicateOperand(MI, 2, O); 167 if (Opcode == ARM::t2LDMIA_UPD) 168 O << ".w"; 169 O << '\t'; 170 printRegisterList(MI, 4, O); 171 printAnnotation(O, Annot); 172 return; 173 } 174 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP && 175 MI->getOperand(4).getImm() == 4) { 176 O << '\t' << "pop"; 177 printPredicateOperand(MI, 5, O); 178 O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}"; 179 printAnnotation(O, Annot); 180 return; 181 } 182 183 184 // A8.6.355 VPUSH 185 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) && 186 MI->getOperand(0).getReg() == ARM::SP) { 187 O << '\t' << "vpush"; 188 printPredicateOperand(MI, 2, O); 189 O << '\t'; 190 printRegisterList(MI, 4, O); 191 printAnnotation(O, Annot); 192 return; 193 } 194 195 // A8.6.354 VPOP 196 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) && 197 MI->getOperand(0).getReg() == ARM::SP) { 198 O << '\t' << "vpop"; 199 printPredicateOperand(MI, 2, O); 200 O << '\t'; 201 printRegisterList(MI, 4, O); 202 printAnnotation(O, Annot); 203 return; 204 } 205 206 if (Opcode == ARM::tLDMIA) { 207 bool Writeback = true; 208 unsigned BaseReg = MI->getOperand(0).getReg(); 209 for (unsigned i = 3; i < MI->getNumOperands(); ++i) { 210 if (MI->getOperand(i).getReg() == BaseReg) 211 Writeback = false; 212 } 213 214 O << "\tldm"; 215 216 printPredicateOperand(MI, 1, O); 217 O << '\t' << getRegisterName(BaseReg); 218 if (Writeback) O << "!"; 219 O << ", "; 220 printRegisterList(MI, 3, O); 221 printAnnotation(O, Annot); 222 return; 223 } 224 225 // Thumb1 NOP 226 if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 && 227 MI->getOperand(1).getReg() == ARM::R8) { 228 O << "\tnop"; 229 printPredicateOperand(MI, 2, O); 230 printAnnotation(O, Annot); 231 return; 232 } 233 234 printInstruction(MI, O); 235 printAnnotation(O, Annot); 236} 237 238void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 239 raw_ostream &O) { 240 const MCOperand &Op = MI->getOperand(OpNo); 241 if (Op.isReg()) { 242 unsigned Reg = Op.getReg(); 243 O << getRegisterName(Reg); 244 } else if (Op.isImm()) { 245 O << '#' << Op.getImm(); 246 } else { 247 assert(Op.isExpr() && "unknown operand kind in printOperand"); 248 // If a symbolic branch target was added as a constant expression then print 249 // that address in hex. And only print 32 unsigned bits for the address. 250 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr()); 251 int64_t Address; 252 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) { 253 O << "0x"; 254 O.write_hex((uint32_t)Address); 255 } 256 else { 257 // Otherwise, just print the expression. 258 O << *Op.getExpr(); 259 } 260 } 261} 262 263void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, 264 raw_ostream &O) { 265 const MCOperand &MO1 = MI->getOperand(OpNum); 266 if (MO1.isExpr()) 267 O << *MO1.getExpr(); 268 else if (MO1.isImm()) 269 O << "[pc, #" << MO1.getImm() << "]"; 270 else 271 llvm_unreachable("Unknown LDR label operand?"); 272} 273 274// so_reg is a 4-operand unit corresponding to register forms of the A5.1 275// "Addressing Mode 1 - Data-processing operands" forms. This includes: 276// REG 0 0 - e.g. R5 277// REG REG 0,SH_OPC - e.g. R5, ROR R3 278// REG 0 IMM,SH_OPC - e.g. R5, LSL #3 279void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum, 280 raw_ostream &O) { 281 const MCOperand &MO1 = MI->getOperand(OpNum); 282 const MCOperand &MO2 = MI->getOperand(OpNum+1); 283 const MCOperand &MO3 = MI->getOperand(OpNum+2); 284 285 O << getRegisterName(MO1.getReg()); 286 287 // Print the shift opc. 288 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); 289 O << ", " << ARM_AM::getShiftOpcStr(ShOpc); 290 if (ShOpc == ARM_AM::rrx) 291 return; 292 293 O << ' ' << getRegisterName(MO2.getReg()); 294 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); 295} 296 297void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum, 298 raw_ostream &O) { 299 const MCOperand &MO1 = MI->getOperand(OpNum); 300 const MCOperand &MO2 = MI->getOperand(OpNum+1); 301 302 O << getRegisterName(MO1.getReg()); 303 304 // Print the shift opc. 305 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()), 306 ARM_AM::getSORegOffset(MO2.getImm())); 307} 308 309 310//===--------------------------------------------------------------------===// 311// Addressing Mode #2 312//===--------------------------------------------------------------------===// 313 314void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, 315 raw_ostream &O) { 316 const MCOperand &MO1 = MI->getOperand(Op); 317 const MCOperand &MO2 = MI->getOperand(Op+1); 318 const MCOperand &MO3 = MI->getOperand(Op+2); 319 320 O << "[" << getRegisterName(MO1.getReg()); 321 322 if (!MO2.getReg()) { 323 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0. 324 O << ", #" 325 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())) 326 << ARM_AM::getAM2Offset(MO3.getImm()); 327 O << "]"; 328 return; 329 } 330 331 O << ", " 332 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())) 333 << getRegisterName(MO2.getReg()); 334 335 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()), 336 ARM_AM::getAM2Offset(MO3.getImm())); 337 O << "]"; 338} 339 340void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op, 341 raw_ostream &O) { 342 const MCOperand &MO1 = MI->getOperand(Op); 343 const MCOperand &MO2 = MI->getOperand(Op+1); 344 O << "[" << getRegisterName(MO1.getReg()) << ", " 345 << getRegisterName(MO2.getReg()) << "]"; 346} 347 348void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op, 349 raw_ostream &O) { 350 const MCOperand &MO1 = MI->getOperand(Op); 351 const MCOperand &MO2 = MI->getOperand(Op+1); 352 O << "[" << getRegisterName(MO1.getReg()) << ", " 353 << getRegisterName(MO2.getReg()) << ", lsl #1]"; 354} 355 356void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op, 357 raw_ostream &O) { 358 const MCOperand &MO1 = MI->getOperand(Op); 359 360 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 361 printOperand(MI, Op, O); 362 return; 363 } 364 365#ifndef NDEBUG 366 const MCOperand &MO3 = MI->getOperand(Op+2); 367 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm()); 368 assert(IdxMode != ARMII::IndexModePost && 369 "Should be pre or offset index op"); 370#endif 371 372 printAM2PreOrOffsetIndexOp(MI, Op, O); 373} 374 375void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI, 376 unsigned OpNum, 377 raw_ostream &O) { 378 const MCOperand &MO1 = MI->getOperand(OpNum); 379 const MCOperand &MO2 = MI->getOperand(OpNum+1); 380 381 if (!MO1.getReg()) { 382 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm()); 383 O << '#' 384 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) 385 << ImmOffs; 386 return; 387 } 388 389 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) 390 << getRegisterName(MO1.getReg()); 391 392 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()), 393 ARM_AM::getAM2Offset(MO2.getImm())); 394} 395 396//===--------------------------------------------------------------------===// 397// Addressing Mode #3 398//===--------------------------------------------------------------------===// 399 400void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op, 401 raw_ostream &O) { 402 const MCOperand &MO1 = MI->getOperand(Op); 403 const MCOperand &MO2 = MI->getOperand(Op+1); 404 const MCOperand &MO3 = MI->getOperand(Op+2); 405 406 O << "[" << getRegisterName(MO1.getReg()) << "], "; 407 408 if (MO2.getReg()) { 409 O << (char)ARM_AM::getAM3Op(MO3.getImm()) 410 << getRegisterName(MO2.getReg()); 411 return; 412 } 413 414 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()); 415 O << '#' 416 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm())) 417 << ImmOffs; 418} 419 420void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, 421 raw_ostream &O) { 422 const MCOperand &MO1 = MI->getOperand(Op); 423 const MCOperand &MO2 = MI->getOperand(Op+1); 424 const MCOperand &MO3 = MI->getOperand(Op+2); 425 426 O << '[' << getRegisterName(MO1.getReg()); 427 428 if (MO2.getReg()) { 429 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm())) 430 << getRegisterName(MO2.getReg()) << ']'; 431 return; 432 } 433 434 //If the op is sub we have to print the immediate even if it is 0 435 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()); 436 ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm()); 437 438 if (ImmOffs || (op == ARM_AM::sub)) 439 O << ", #" 440 << ARM_AM::getAddrOpcStr(op) 441 << ImmOffs; 442 O << ']'; 443} 444 445void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op, 446 raw_ostream &O) { 447 const MCOperand &MO1 = MI->getOperand(Op); 448 if (!MO1.isReg()) { // For label symbolic references. 449 printOperand(MI, Op, O); 450 return; 451 } 452 453 const MCOperand &MO3 = MI->getOperand(Op+2); 454 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm()); 455 456 if (IdxMode == ARMII::IndexModePost) { 457 printAM3PostIndexOp(MI, Op, O); 458 return; 459 } 460 printAM3PreOrOffsetIndexOp(MI, Op, O); 461} 462 463void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI, 464 unsigned OpNum, 465 raw_ostream &O) { 466 const MCOperand &MO1 = MI->getOperand(OpNum); 467 const MCOperand &MO2 = MI->getOperand(OpNum+1); 468 469 if (MO1.getReg()) { 470 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) 471 << getRegisterName(MO1.getReg()); 472 return; 473 } 474 475 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm()); 476 O << '#' 477 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) 478 << ImmOffs; 479} 480 481void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, 482 unsigned OpNum, 483 raw_ostream &O) { 484 const MCOperand &MO = MI->getOperand(OpNum); 485 unsigned Imm = MO.getImm(); 486 O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff); 487} 488 489void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, 490 raw_ostream &O) { 491 const MCOperand &MO1 = MI->getOperand(OpNum); 492 const MCOperand &MO2 = MI->getOperand(OpNum+1); 493 494 O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg()); 495} 496 497void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, 498 unsigned OpNum, 499 raw_ostream &O) { 500 const MCOperand &MO = MI->getOperand(OpNum); 501 unsigned Imm = MO.getImm(); 502 O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2); 503} 504 505 506void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum, 507 raw_ostream &O) { 508 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum) 509 .getImm()); 510 O << ARM_AM::getAMSubModeStr(Mode); 511} 512 513void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum, 514 raw_ostream &O) { 515 const MCOperand &MO1 = MI->getOperand(OpNum); 516 const MCOperand &MO2 = MI->getOperand(OpNum+1); 517 518 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 519 printOperand(MI, OpNum, O); 520 return; 521 } 522 523 O << "[" << getRegisterName(MO1.getReg()); 524 525 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm()); 526 unsigned Op = ARM_AM::getAM5Op(MO2.getImm()); 527 if (ImmOffs || Op == ARM_AM::sub) { 528 O << ", #" 529 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm())) 530 << ImmOffs * 4; 531 } 532 O << "]"; 533} 534 535void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum, 536 raw_ostream &O) { 537 const MCOperand &MO1 = MI->getOperand(OpNum); 538 const MCOperand &MO2 = MI->getOperand(OpNum+1); 539 540 O << "[" << getRegisterName(MO1.getReg()); 541 if (MO2.getImm()) { 542 // FIXME: Both darwin as and GNU as violate ARM docs here. 543 O << ", :" << (MO2.getImm() << 3); 544 } 545 O << "]"; 546} 547 548void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum, 549 raw_ostream &O) { 550 const MCOperand &MO1 = MI->getOperand(OpNum); 551 O << "[" << getRegisterName(MO1.getReg()) << "]"; 552} 553 554void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI, 555 unsigned OpNum, 556 raw_ostream &O) { 557 const MCOperand &MO = MI->getOperand(OpNum); 558 if (MO.getReg() == 0) 559 O << "!"; 560 else 561 O << ", " << getRegisterName(MO.getReg()); 562} 563 564void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI, 565 unsigned OpNum, 566 raw_ostream &O) { 567 const MCOperand &MO = MI->getOperand(OpNum); 568 uint32_t v = ~MO.getImm(); 569 int32_t lsb = CountTrailingZeros_32(v); 570 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb; 571 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); 572 O << '#' << lsb << ", #" << width; 573} 574 575void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum, 576 raw_ostream &O) { 577 unsigned val = MI->getOperand(OpNum).getImm(); 578 O << ARM_MB::MemBOptToString(val); 579} 580 581void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum, 582 raw_ostream &O) { 583 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); 584 bool isASR = (ShiftOp & (1 << 5)) != 0; 585 unsigned Amt = ShiftOp & 0x1f; 586 if (isASR) 587 O << ", asr #" << (Amt == 0 ? 32 : Amt); 588 else if (Amt) 589 O << ", lsl #" << Amt; 590} 591 592void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, 593 raw_ostream &O) { 594 unsigned Imm = MI->getOperand(OpNum).getImm(); 595 if (Imm == 0) 596 return; 597 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!"); 598 O << ", lsl #" << Imm; 599} 600 601void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, 602 raw_ostream &O) { 603 unsigned Imm = MI->getOperand(OpNum).getImm(); 604 // A shift amount of 32 is encoded as 0. 605 if (Imm == 0) 606 Imm = 32; 607 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!"); 608 O << ", asr #" << Imm; 609} 610 611void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum, 612 raw_ostream &O) { 613 O << "{"; 614 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) { 615 if (i != OpNum) O << ", "; 616 O << getRegisterName(MI->getOperand(i).getReg()); 617 } 618 O << "}"; 619} 620 621void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum, 622 raw_ostream &O) { 623 const MCOperand &Op = MI->getOperand(OpNum); 624 if (Op.getImm()) 625 O << "be"; 626 else 627 O << "le"; 628} 629 630void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum, 631 raw_ostream &O) { 632 const MCOperand &Op = MI->getOperand(OpNum); 633 O << ARM_PROC::IModToString(Op.getImm()); 634} 635 636void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum, 637 raw_ostream &O) { 638 const MCOperand &Op = MI->getOperand(OpNum); 639 unsigned IFlags = Op.getImm(); 640 for (int i=2; i >= 0; --i) 641 if (IFlags & (1 << i)) 642 O << ARM_PROC::IFlagsToString(1 << i); 643 644 if (IFlags == 0) 645 O << "none"; 646} 647 648void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum, 649 raw_ostream &O) { 650 const MCOperand &Op = MI->getOperand(OpNum); 651 unsigned SpecRegRBit = Op.getImm() >> 4; 652 unsigned Mask = Op.getImm() & 0xf; 653 654 if (getAvailableFeatures() & ARM::FeatureMClass) { 655 unsigned SYSm = Op.getImm(); 656 unsigned Opcode = MI->getOpcode(); 657 // For reads of the special registers ignore the "mask encoding" bits 658 // which are only for writes. 659 if (Opcode == ARM::t2MRS_M) 660 SYSm &= 0xff; 661 switch (SYSm) { 662 default: llvm_unreachable("Unexpected mask value!"); 663 case 0: 664 case 0x800: O << "apsr"; return; // with _nzcvq bits is an alias for aspr 665 case 0x400: O << "apsr_g"; return; 666 case 0xc00: O << "apsr_nzcvqg"; return; 667 case 1: 668 case 0x801: O << "iapsr"; return; // with _nzcvq bits is an alias for iapsr 669 case 0x401: O << "iapsr_g"; return; 670 case 0xc01: O << "iapsr_nzcvqg"; return; 671 case 2: 672 case 0x802: O << "eapsr"; return; // with _nzcvq bits is an alias for eapsr 673 case 0x402: O << "eapsr_g"; return; 674 case 0xc02: O << "eapsr_nzcvqg"; return; 675 case 3: 676 case 0x803: O << "xpsr"; return; // with _nzcvq bits is an alias for xpsr 677 case 0x403: O << "xpsr_g"; return; 678 case 0xc03: O << "xpsr_nzcvqg"; return; 679 case 5: 680 case 0x805: O << "ipsr"; return; 681 case 6: 682 case 0x806: O << "epsr"; return; 683 case 7: 684 case 0x807: O << "iepsr"; return; 685 case 8: 686 case 0x808: O << "msp"; return; 687 case 9: 688 case 0x809: O << "psp"; return; 689 case 0x10: 690 case 0x810: O << "primask"; return; 691 case 0x11: 692 case 0x811: O << "basepri"; return; 693 case 0x12: 694 case 0x812: O << "basepri_max"; return; 695 case 0x13: 696 case 0x813: O << "faultmask"; return; 697 case 0x14: 698 case 0x814: O << "control"; return; 699 } 700 } 701 702 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as 703 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively. 704 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) { 705 O << "APSR_"; 706 switch (Mask) { 707 default: llvm_unreachable("Unexpected mask value!"); 708 case 4: O << "g"; return; 709 case 8: O << "nzcvq"; return; 710 case 12: O << "nzcvqg"; return; 711 } 712 } 713 714 if (SpecRegRBit) 715 O << "SPSR"; 716 else 717 O << "CPSR"; 718 719 if (Mask) { 720 O << '_'; 721 if (Mask & 8) O << 'f'; 722 if (Mask & 4) O << 's'; 723 if (Mask & 2) O << 'x'; 724 if (Mask & 1) O << 'c'; 725 } 726} 727 728void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum, 729 raw_ostream &O) { 730 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); 731 // Handle the undefined 15 CC value here for printing so we don't abort(). 732 if ((unsigned)CC == 15) 733 O << "<und>"; 734 else if (CC != ARMCC::AL) 735 O << ARMCondCodeToString(CC); 736} 737 738void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI, 739 unsigned OpNum, 740 raw_ostream &O) { 741 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); 742 O << ARMCondCodeToString(CC); 743} 744 745void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum, 746 raw_ostream &O) { 747 if (MI->getOperand(OpNum).getReg()) { 748 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR && 749 "Expect ARM CPSR register!"); 750 O << 's'; 751 } 752} 753 754void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum, 755 raw_ostream &O) { 756 O << MI->getOperand(OpNum).getImm(); 757} 758 759void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum, 760 raw_ostream &O) { 761 O << "p" << MI->getOperand(OpNum).getImm(); 762} 763 764void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum, 765 raw_ostream &O) { 766 O << "c" << MI->getOperand(OpNum).getImm(); 767} 768 769void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum, 770 raw_ostream &O) { 771 O << "{" << MI->getOperand(OpNum).getImm() << "}"; 772} 773 774void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum, 775 raw_ostream &O) { 776 llvm_unreachable("Unhandled PC-relative pseudo-instruction!"); 777} 778 779void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum, 780 raw_ostream &O) { 781 const MCOperand &MO = MI->getOperand(OpNum); 782 783 if (MO.isExpr()) { 784 O << *MO.getExpr(); 785 return; 786 } 787 788 int32_t OffImm = (int32_t)MO.getImm(); 789 790 if (OffImm == INT32_MIN) 791 O << "#-0"; 792 else if (OffImm < 0) 793 O << "#-" << -OffImm; 794 else 795 O << "#" << OffImm; 796} 797 798void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, 799 raw_ostream &O) { 800 O << "#" << MI->getOperand(OpNum).getImm() * 4; 801} 802 803void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum, 804 raw_ostream &O) { 805 unsigned Imm = MI->getOperand(OpNum).getImm(); 806 O << "#" << (Imm == 0 ? 32 : Imm); 807} 808 809void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum, 810 raw_ostream &O) { 811 // (3 - the number of trailing zeros) is the number of then / else. 812 unsigned Mask = MI->getOperand(OpNum).getImm(); 813 unsigned Firstcond = MI->getOperand(OpNum-1).getImm(); 814 unsigned CondBit0 = Firstcond & 1; 815 unsigned NumTZ = CountTrailingZeros_32(Mask); 816 assert(NumTZ <= 3 && "Invalid IT mask!"); 817 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 818 bool T = ((Mask >> Pos) & 1) == CondBit0; 819 if (T) 820 O << 't'; 821 else 822 O << 'e'; 823 } 824} 825 826void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op, 827 raw_ostream &O) { 828 const MCOperand &MO1 = MI->getOperand(Op); 829 const MCOperand &MO2 = MI->getOperand(Op + 1); 830 831 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 832 printOperand(MI, Op, O); 833 return; 834 } 835 836 O << "[" << getRegisterName(MO1.getReg()); 837 if (unsigned RegNum = MO2.getReg()) 838 O << ", " << getRegisterName(RegNum); 839 O << "]"; 840} 841 842void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI, 843 unsigned Op, 844 raw_ostream &O, 845 unsigned Scale) { 846 const MCOperand &MO1 = MI->getOperand(Op); 847 const MCOperand &MO2 = MI->getOperand(Op + 1); 848 849 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 850 printOperand(MI, Op, O); 851 return; 852 } 853 854 O << "[" << getRegisterName(MO1.getReg()); 855 if (unsigned ImmOffs = MO2.getImm()) 856 O << ", #" << ImmOffs * Scale; 857 O << "]"; 858} 859 860void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI, 861 unsigned Op, 862 raw_ostream &O) { 863 printThumbAddrModeImm5SOperand(MI, Op, O, 1); 864} 865 866void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI, 867 unsigned Op, 868 raw_ostream &O) { 869 printThumbAddrModeImm5SOperand(MI, Op, O, 2); 870} 871 872void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI, 873 unsigned Op, 874 raw_ostream &O) { 875 printThumbAddrModeImm5SOperand(MI, Op, O, 4); 876} 877 878void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op, 879 raw_ostream &O) { 880 printThumbAddrModeImm5SOperand(MI, Op, O, 4); 881} 882 883// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2 884// register with shift forms. 885// REG 0 0 - e.g. R5 886// REG IMM, SH_OPC - e.g. R5, LSL #3 887void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum, 888 raw_ostream &O) { 889 const MCOperand &MO1 = MI->getOperand(OpNum); 890 const MCOperand &MO2 = MI->getOperand(OpNum+1); 891 892 unsigned Reg = MO1.getReg(); 893 O << getRegisterName(Reg); 894 895 // Print the shift opc. 896 assert(MO2.isImm() && "Not a valid t2_so_reg value!"); 897 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()), 898 ARM_AM::getSORegOffset(MO2.getImm())); 899} 900 901void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, 902 raw_ostream &O) { 903 const MCOperand &MO1 = MI->getOperand(OpNum); 904 const MCOperand &MO2 = MI->getOperand(OpNum+1); 905 906 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 907 printOperand(MI, OpNum, O); 908 return; 909 } 910 911 O << "[" << getRegisterName(MO1.getReg()); 912 913 int32_t OffImm = (int32_t)MO2.getImm(); 914 bool isSub = OffImm < 0; 915 // Special value for #-0. All others are normal. 916 if (OffImm == INT32_MIN) 917 OffImm = 0; 918 if (isSub) 919 O << ", #-" << -OffImm; 920 else if (OffImm > 0) 921 O << ", #" << OffImm; 922 O << "]"; 923} 924 925void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI, 926 unsigned OpNum, 927 raw_ostream &O) { 928 const MCOperand &MO1 = MI->getOperand(OpNum); 929 const MCOperand &MO2 = MI->getOperand(OpNum+1); 930 931 O << "[" << getRegisterName(MO1.getReg()); 932 933 int32_t OffImm = (int32_t)MO2.getImm(); 934 // Don't print +0. 935 if (OffImm == INT32_MIN) 936 O << ", #-0"; 937 else if (OffImm < 0) 938 O << ", #-" << -OffImm; 939 else if (OffImm > 0) 940 O << ", #" << OffImm; 941 O << "]"; 942} 943 944void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI, 945 unsigned OpNum, 946 raw_ostream &O) { 947 const MCOperand &MO1 = MI->getOperand(OpNum); 948 const MCOperand &MO2 = MI->getOperand(OpNum+1); 949 950 if (!MO1.isReg()) { // For label symbolic references. 951 printOperand(MI, OpNum, O); 952 return; 953 } 954 955 O << "[" << getRegisterName(MO1.getReg()); 956 957 int32_t OffImm = (int32_t)MO2.getImm(); 958 959 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); 960 961 // Don't print +0. 962 if (OffImm == INT32_MIN) 963 O << ", #-0"; 964 else if (OffImm < 0) 965 O << ", #-" << -OffImm; 966 else if (OffImm > 0) 967 O << ", #" << OffImm; 968 O << "]"; 969} 970 971void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI, 972 unsigned OpNum, 973 raw_ostream &O) { 974 const MCOperand &MO1 = MI->getOperand(OpNum); 975 const MCOperand &MO2 = MI->getOperand(OpNum+1); 976 977 O << "[" << getRegisterName(MO1.getReg()); 978 if (MO2.getImm()) 979 O << ", #" << MO2.getImm() * 4; 980 O << "]"; 981} 982 983void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI, 984 unsigned OpNum, 985 raw_ostream &O) { 986 const MCOperand &MO1 = MI->getOperand(OpNum); 987 int32_t OffImm = (int32_t)MO1.getImm(); 988 // Don't print +0. 989 if (OffImm < 0) 990 O << ", #-" << -OffImm; 991 else 992 O << ", #" << OffImm; 993} 994 995void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, 996 unsigned OpNum, 997 raw_ostream &O) { 998 const MCOperand &MO1 = MI->getOperand(OpNum); 999 int32_t OffImm = (int32_t)MO1.getImm(); 1000 1001 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); 1002 1003 // Don't print +0. 1004 if (OffImm == INT32_MIN) 1005 O << ", #-0"; 1006 else if (OffImm < 0) 1007 O << ", #-" << -OffImm; 1008 else if (OffImm > 0) 1009 O << ", #" << OffImm; 1010} 1011 1012void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI, 1013 unsigned OpNum, 1014 raw_ostream &O) { 1015 const MCOperand &MO1 = MI->getOperand(OpNum); 1016 const MCOperand &MO2 = MI->getOperand(OpNum+1); 1017 const MCOperand &MO3 = MI->getOperand(OpNum+2); 1018 1019 O << "[" << getRegisterName(MO1.getReg()); 1020 1021 assert(MO2.getReg() && "Invalid so_reg load / store address!"); 1022 O << ", " << getRegisterName(MO2.getReg()); 1023 1024 unsigned ShAmt = MO3.getImm(); 1025 if (ShAmt) { 1026 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!"); 1027 O << ", lsl #" << ShAmt; 1028 } 1029 O << "]"; 1030} 1031 1032void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum, 1033 raw_ostream &O) { 1034 const MCOperand &MO = MI->getOperand(OpNum); 1035 O << '#' << ARM_AM::getFPImmFloat(MO.getImm()); 1036} 1037 1038void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum, 1039 raw_ostream &O) { 1040 unsigned EncodedImm = MI->getOperand(OpNum).getImm(); 1041 unsigned EltBits; 1042 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits); 1043 O << "#0x"; 1044 O.write_hex(Val); 1045} 1046 1047void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, 1048 raw_ostream &O) { 1049 unsigned Imm = MI->getOperand(OpNum).getImm(); 1050 O << "#" << Imm + 1; 1051} 1052 1053void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum, 1054 raw_ostream &O) { 1055 unsigned Imm = MI->getOperand(OpNum).getImm(); 1056 if (Imm == 0) 1057 return; 1058 O << ", ror #"; 1059 switch (Imm) { 1060 default: assert (0 && "illegal ror immediate!"); 1061 case 1: O << "8"; break; 1062 case 2: O << "16"; break; 1063 case 3: O << "24"; break; 1064 } 1065} 1066 1067void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum, 1068 raw_ostream &O) { 1069 O << "#" << 16 - MI->getOperand(OpNum).getImm(); 1070} 1071 1072void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum, 1073 raw_ostream &O) { 1074 O << "#" << 32 - MI->getOperand(OpNum).getImm(); 1075} 1076 1077void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum, 1078 raw_ostream &O) { 1079 O << "[" << MI->getOperand(OpNum).getImm() << "]"; 1080} 1081 1082void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum, 1083 raw_ostream &O) { 1084 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "}"; 1085} 1086 1087void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum, 1088 raw_ostream &O) { 1089 unsigned Reg = MI->getOperand(OpNum).getReg(); 1090 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 1091 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); 1092 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}"; 1093} 1094 1095void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, 1096 unsigned OpNum, 1097 raw_ostream &O) { 1098 unsigned Reg = MI->getOperand(OpNum).getReg(); 1099 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 1100 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); 1101 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}"; 1102} 1103 1104void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum, 1105 raw_ostream &O) { 1106 // Normally, it's not safe to use register enum values directly with 1107 // addition to get the next register, but for VFP registers, the 1108 // sort order is guaranteed because they're all of the form D<n>. 1109 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", " 1110 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", " 1111 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}"; 1112} 1113 1114void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum, 1115 raw_ostream &O) { 1116 // Normally, it's not safe to use register enum values directly with 1117 // addition to get the next register, but for VFP registers, the 1118 // sort order is guaranteed because they're all of the form D<n>. 1119 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", " 1120 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", " 1121 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", " 1122 << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "}"; 1123} 1124 1125void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI, 1126 unsigned OpNum, 1127 raw_ostream &O) { 1128 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[]}"; 1129} 1130 1131void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI, 1132 unsigned OpNum, 1133 raw_ostream &O) { 1134 unsigned Reg = MI->getOperand(OpNum).getReg(); 1135 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 1136 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); 1137 O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}"; 1138} 1139 1140void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI, 1141 unsigned OpNum, 1142 raw_ostream &O) { 1143 // Normally, it's not safe to use register enum values directly with 1144 // addition to get the next register, but for VFP registers, the 1145 // sort order is guaranteed because they're all of the form D<n>. 1146 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], " 1147 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], " 1148 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}"; 1149} 1150 1151void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI, 1152 unsigned OpNum, 1153 raw_ostream &O) { 1154 // Normally, it's not safe to use register enum values directly with 1155 // addition to get the next register, but for VFP registers, the 1156 // sort order is guaranteed because they're all of the form D<n>. 1157 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], " 1158 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], " 1159 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], " 1160 << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "[]}"; 1161} 1162 1163void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI, 1164 unsigned OpNum, 1165 raw_ostream &O) { 1166 unsigned Reg = MI->getOperand(OpNum).getReg(); 1167 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 1168 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); 1169 O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}"; 1170} 1171 1172void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI, 1173 unsigned OpNum, 1174 raw_ostream &O) { 1175 // Normally, it's not safe to use register enum values directly with 1176 // addition to get the next register, but for VFP registers, the 1177 // sort order is guaranteed because they're all of the form D<n>. 1178 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], " 1179 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], " 1180 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[]}"; 1181} 1182 1183void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI, 1184 unsigned OpNum, 1185 raw_ostream &O) { 1186 // Normally, it's not safe to use register enum values directly with 1187 // addition to get the next register, but for VFP registers, the 1188 // sort order is guaranteed because they're all of the form D<n>. 1189 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], " 1190 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], " 1191 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[], " 1192 << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "[]}"; 1193} 1194 1195void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI, 1196 unsigned OpNum, 1197 raw_ostream &O) { 1198 // Normally, it's not safe to use register enum values directly with 1199 // addition to get the next register, but for VFP registers, the 1200 // sort order is guaranteed because they're all of the form D<n>. 1201 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", " 1202 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", " 1203 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "}"; 1204} 1205 1206void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI, 1207 unsigned OpNum, 1208 raw_ostream &O) { 1209 // Normally, it's not safe to use register enum values directly with 1210 // addition to get the next register, but for VFP registers, the 1211 // sort order is guaranteed because they're all of the form D<n>. 1212 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", " 1213 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", " 1214 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << ", " 1215 << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "}"; 1216} 1217