1/* Definitions for opcode table for the sparc. 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002, 3 2003, 2005 Free Software Foundation, Inc. 4 5 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and 6 the GNU Binutils. 7 8 GAS/GDB is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2, or (at your option) 11 any later version. 12 13 GAS/GDB is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GAS or GDB; see the file COPYING. If not, write to 20 the Free Software Foundation, 51 Franklin Street - Fifth Floor, 21 Boston, MA 02110-1301, USA. */ 22 23#include "ansidecl.h" 24 25/* The SPARC opcode table (and other related data) is defined in 26 the opcodes library in sparc-opc.c. If you change anything here, make 27 sure you fix up that file, and vice versa. */ 28 29 /* FIXME-someday: perhaps the ,a's and such should be embedded in the 30 instruction's name rather than the args. This would make gas faster, pinsn 31 slower, but would mess up some macros a bit. xoxorich. */ 32 33/* List of instruction sets variations. 34 These values are such that each element is either a superset of a 35 preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P 36 returns non-zero. 37 The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. 38 Don't change this without updating sparc-opc.c. */ 39 40enum sparc_opcode_arch_val 41{ 42 SPARC_OPCODE_ARCH_V6 = 0, 43 SPARC_OPCODE_ARCH_V7, 44 SPARC_OPCODE_ARCH_V8, 45 SPARC_OPCODE_ARCH_SPARCLET, 46 SPARC_OPCODE_ARCH_SPARCLITE, 47 /* V9 variants must appear last. */ 48 SPARC_OPCODE_ARCH_V9, 49 SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */ 50 SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */ 51 SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */ 52}; 53 54/* The highest architecture in the table. */ 55#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1) 56 57/* Given an enum sparc_opcode_arch_val, return the bitmask to use in 58 insn encoding/decoding. */ 59#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch)) 60 61/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */ 62#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9) 63 64/* Table of cpu variants. */ 65 66typedef struct sparc_opcode_arch 67{ 68 const char *name; 69 /* Mask of sparc_opcode_arch_val's supported. 70 EG: For v7 this would be 71 (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). 72 These are short's because sparc_opcode.architecture is. */ 73 short supported; 74} sparc_opcode_arch; 75 76extern const struct sparc_opcode_arch sparc_opcode_archs[]; 77 78/* Given architecture name, look up it's sparc_opcode_arch_val value. */ 79extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *); 80 81/* Return the bitmask of supported architectures for ARCH. */ 82#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported) 83 84/* Non-zero if ARCH1 conflicts with ARCH2. 85 IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */ 86#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ 87 (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ 88 != SPARC_OPCODE_SUPPORTED (ARCH1)) \ 89 && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ 90 != SPARC_OPCODE_SUPPORTED (ARCH2))) 91 92/* Structure of an opcode table entry. */ 93 94typedef struct sparc_opcode 95{ 96 const char *name; 97 unsigned long match; /* Bits that must be set. */ 98 unsigned long lose; /* Bits that must not be set. */ 99 const char *args; 100 /* This was called "delayed" in versions before the flags. */ 101 char flags; 102 short architecture; /* Bitmask of sparc_opcode_arch_val's. */ 103} sparc_opcode; 104 105#define F_DELAYED 1 /* Delayed branch. */ 106#define F_ALIAS 2 /* Alias for a "real" instruction. */ 107#define F_UNBR 4 /* Unconditional branch. */ 108#define F_CONDBR 8 /* Conditional branch. */ 109#define F_JSR 16 /* Subroutine call. */ 110#define F_FLOAT 32 /* Floating point instruction (not a branch). */ 111#define F_FBR 64 /* Floating point branch. */ 112/* FIXME: Add F_ANACHRONISTIC flag for v9. */ 113 114/* All sparc opcodes are 32 bits, except for the `set' instruction (really a 115 macro), which is 64 bits. It is handled as a special case. 116 117 The match component is a mask saying which bits must match a particular 118 opcode in order for an instruction to be an instance of that opcode. 119 120 The args component is a string containing one character for each operand of the 121 instruction. 122 123 Kinds of operands: 124 # Number used by optimizer. It is ignored. 125 1 rs1 register. 126 2 rs2 register. 127 d rd register. 128 e frs1 floating point register. 129 v frs1 floating point register (double/even). 130 V frs1 floating point register (quad/multiple of 4). 131 f frs2 floating point register. 132 B frs2 floating point register (double/even). 133 R frs2 floating point register (quad/multiple of 4). 134 g frsd floating point register. 135 H frsd floating point register (double/even). 136 J frsd floating point register (quad/multiple of 4). 137 b crs1 coprocessor register 138 c crs2 coprocessor register 139 D crsd coprocessor register 140 m alternate space register (asr) in rd 141 M alternate space register (asr) in rs1 142 h 22 high bits. 143 X 5 bit unsigned immediate 144 Y 6 bit unsigned immediate 145 3 SIAM mode (3 bits). (v9b) 146 K MEMBAR mask (7 bits). (v9) 147 j 10 bit Immediate. (v9) 148 I 11 bit Immediate. (v9) 149 i 13 bit Immediate. 150 n 22 bit immediate. 151 k 2+14 bit PC relative immediate. (v9) 152 G 19 bit PC relative immediate. (v9) 153 l 22 bit PC relative immediate. 154 L 30 bit PC relative immediate. 155 a Annul. The annul bit is set. 156 A Alternate address space. Stored as 8 bits. 157 C Coprocessor state register. 158 F floating point state register. 159 p Processor state register. 160 N Branch predict clear ",pn" (v9) 161 T Branch predict set ",pt" (v9) 162 z %icc. (v9) 163 Z %xcc. (v9) 164 q Floating point queue. 165 r Single register that is both rs1 and rd. 166 O Single register that is both rs2 and rd. 167 Q Coprocessor queue. 168 S Special case. 169 t Trap base register. 170 w Window invalid mask register. 171 y Y register. 172 u sparclet coprocessor registers in rd position 173 U sparclet coprocessor registers in rs1 position 174 E %ccr. (v9) 175 s %fprs. (v9) 176 P %pc. (v9) 177 W %tick. (v9) 178 o %asi. (v9) 179 6 %fcc0. (v9) 180 7 %fcc1. (v9) 181 8 %fcc2. (v9) 182 9 %fcc3. (v9) 183 ! Privileged Register in rd (v9) 184 ? Privileged Register in rs1 (v9) 185 * Prefetch function constant. (v9) 186 x OPF field (v9 impdep). 187 0 32/64 bit immediate for set or setx (v9) insns 188 _ Ancillary state register in rd (v9a) 189 / Ancillary state register in rs1 (v9a) 190 191 The following chars are unused: (note: ,[] are used as punctuation) 192 [45]. */ 193 194#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ 195#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */ 196#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */ 197#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */ 198#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */ 199#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */ 200#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */ 201#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */ 202#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */ 203#define F1(x) (OP (x)) 204#define DISP30(x) ((x) & 0x3fffffff) 205#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */ 206#define RS2(x) ((x) & 0x1f) /* Rs2 field. */ 207#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */ 208#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */ 209#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ 210#define ASI_RS2(x) (SIMM13 (x)) 211#define MEMBAR(x) ((x) & 0x7f) 212#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */ 213 214#define ANNUL (1 << 29) 215#define BPRED (1 << 19) /* V9. */ 216#define IMMED F3I (1) 217#define RD_G0 RD (~0) 218#define RS1_G0 RS1 (~0) 219#define RS2_G0 RS2 (~0) 220 221extern const struct sparc_opcode sparc_opcodes[]; 222extern const int sparc_num_opcodes; 223 224extern int sparc_encode_asi (const char *); 225extern const char *sparc_decode_asi (int); 226extern int sparc_encode_membar (const char *); 227extern const char *sparc_decode_membar (int); 228extern int sparc_encode_prefetch (const char *); 229extern const char *sparc_decode_prefetch (int); 230extern int sparc_encode_sparclet_cpreg (const char *); 231extern const char *sparc_decode_sparclet_cpreg (int); 232 233/* Local Variables: 234 fill-column: 131 235 comment-column: 0 236 End: */ 237 238