1/* cris.h -- Header file for CRIS opcode and register tables.
2   Copyright (C) 2000, 2001, 2004 Free Software Foundation, Inc.
3   Contributed by Axis Communications AB, Lund, Sweden.
4   Originally written for GAS 1.38.1 by Mikael Asker.
5   Updated, BFDized and GNUified by Hans-Peter Nilsson.
6
7This file is part of GAS, GDB and the GNU binutils.
8
9GAS, GDB, and GNU binutils is free software; you can redistribute it
10and/or modify it under the terms of the GNU General Public License as
11published by the Free Software Foundation; either version 2, or (at your
12option) any later version.
13
14GAS, GDB, and GNU binutils are distributed in the hope that they will be
15useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
20along with this program; if not, write to the Free Software
21Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
22
23#ifndef __CRIS_H_INCLUDED_
24#define __CRIS_H_INCLUDED_
25
26#if !defined(__STDC__) && !defined(const)
27#define const
28#endif
29
30
31/* Registers.  */
32#define MAX_REG (15)
33#define REG_SP (14)
34#define REG_PC (15)
35
36/* CPU version control of disassembly and assembly of instructions.
37   May affect how the instruction is assembled, at least the size of
38   immediate operands.  */
39enum cris_insn_version_usage
40{
41  /* Any version.  */
42  cris_ver_version_all=0,
43
44  /* Indeterminate (intended for disassembly only, or obsolete).  */
45  cris_ver_warning,
46
47  /* Only for v0..3 (Etrax 1..4).  */
48  cris_ver_v0_3,
49
50  /* Only for v3 or higher (ETRAX 4 and beyond).  */
51  cris_ver_v3p,
52
53  /* Only for v8 (Etrax 100).  */
54  cris_ver_v8,
55
56  /* Only for v8 or higher (ETRAX 100, ETRAX 100 LX).  */
57  cris_ver_v8p,
58
59  /* Only for v0..10.  FIXME: Not sure what to do with this.  */
60  cris_ver_sim_v0_10,
61
62  /* Only for v0..10.  */
63  cris_ver_v0_10,
64
65  /* Only for v3..10.  (ETRAX 4, ETRAX 100 and ETRAX 100 LX).  */
66  cris_ver_v3_10,
67
68  /* Only for v8..10 (ETRAX 100 and ETRAX 100 LX).  */
69  cris_ver_v8_10,
70
71  /* Only for v10 (ETRAX 100 LX) and same series.  */
72  cris_ver_v10,
73
74  /* Only for v10 (ETRAX 100 LX) and same series.  */
75  cris_ver_v10p,
76
77  /* Only for v32 or higher (codename GUINNESS).
78     Of course some or all these of may change to cris_ver_v32p if/when
79     there's a new revision. */
80  cris_ver_v32p
81};
82
83
84/* Special registers.  */
85struct cris_spec_reg
86{
87  const char *const name;
88  unsigned int number;
89
90  /* The size of the register.  */
91  unsigned int reg_size;
92
93  /* What CPU version the special register of that name is implemented
94     in.  If cris_ver_warning, emit an unimplemented-warning.  */
95  enum cris_insn_version_usage applicable_version;
96
97  /* There might be a specific warning for using a special register
98     here.  */
99  const char *const warning;
100};
101extern const struct cris_spec_reg cris_spec_regs[];
102
103
104/* Support registers (kind of special too, but not named as such).  */
105struct cris_support_reg
106{
107  const char *const name;
108  unsigned int number;
109};
110extern const struct cris_support_reg cris_support_regs[];
111
112struct cris_cond15
113{
114  /* The name of the condition.  */
115  const char *const name;
116
117  /* What CPU version this condition name applies to.  */
118  enum cris_insn_version_usage applicable_version;
119};
120extern const struct cris_cond15 cris_conds15[];
121
122/* Opcode-dependent constants.  */
123#define AUTOINCR_BIT (0x04)
124
125/* Prefixes.  */
126#define BDAP_QUICK_OPCODE (0x0100)
127#define BDAP_QUICK_Z_BITS (0x0e00)
128
129#define BIAP_OPCODE	  (0x0540)
130#define BIAP_Z_BITS	  (0x0a80)
131
132#define DIP_OPCODE	  (0x0970)
133#define DIP_Z_BITS	  (0xf280)
134
135#define BDAP_INDIR_LOW	  (0x40)
136#define BDAP_INDIR_LOW_Z  (0x80)
137#define BDAP_INDIR_HIGH	  (0x09)
138#define BDAP_INDIR_HIGH_Z (0x02)
139
140#define BDAP_INDIR_OPCODE (BDAP_INDIR_HIGH * 0x0100 + BDAP_INDIR_LOW)
141#define BDAP_INDIR_Z_BITS (BDAP_INDIR_HIGH_Z * 0x100 + BDAP_INDIR_LOW_Z)
142#define BDAP_PC_LOW	  (BDAP_INDIR_LOW + REG_PC)
143#define BDAP_INCR_HIGH	  (BDAP_INDIR_HIGH + AUTOINCR_BIT)
144
145/* No prefix must have this code for its "match" bits in the
146   opcode-table.  "BCC .+2" will do nicely.  */
147#define NO_CRIS_PREFIX 0
148
149/* Definitions for condition codes.  */
150#define CC_CC  0x0
151#define CC_HS  0x0
152#define CC_CS  0x1
153#define CC_LO  0x1
154#define CC_NE  0x2
155#define CC_EQ  0x3
156#define CC_VC  0x4
157#define CC_VS  0x5
158#define CC_PL  0x6
159#define CC_MI  0x7
160#define CC_LS  0x8
161#define CC_HI  0x9
162#define CC_GE  0xA
163#define CC_LT  0xB
164#define CC_GT  0xC
165#define CC_LE  0xD
166#define CC_A   0xE
167#define CC_EXT 0xF
168
169/* A table of strings "cc", "cs"... indexed with condition code
170   values as above.  */
171extern const char *const cris_cc_strings[];
172
173/* Bcc quick.  */
174#define BRANCH_QUICK_LOW  (0)
175#define BRANCH_QUICK_HIGH (0)
176#define BRANCH_QUICK_OPCODE (BRANCH_QUICK_HIGH * 0x0100 + BRANCH_QUICK_LOW)
177#define BRANCH_QUICK_Z_BITS (0x0F00)
178
179/* BA quick.  */
180#define BA_QUICK_HIGH (BRANCH_QUICK_HIGH + CC_A * 0x10)
181#define BA_QUICK_OPCODE (BA_QUICK_HIGH * 0x100 + BRANCH_QUICK_LOW)
182
183/* Bcc [PC+].  */
184#define BRANCH_PC_LOW	 (0xFF)
185#define BRANCH_INCR_HIGH (0x0D)
186#define BA_PC_INCR_OPCODE \
187 ((BRANCH_INCR_HIGH + CC_A * 0x10) * 0x0100 + BRANCH_PC_LOW)
188
189/* Jump.  */
190/* Note that old versions generated special register 8 (in high bits)
191   and not-that-old versions recognized it as a jump-instruction.
192   That opcode now belongs to JUMPU.  */
193#define JUMP_INDIR_OPCODE (0x0930)
194#define JUMP_INDIR_Z_BITS (0xf2c0)
195#define JUMP_PC_INCR_OPCODE \
196 (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + REG_PC)
197
198#define MOVE_M_TO_PREG_OPCODE 0x0a30
199#define MOVE_M_TO_PREG_ZBITS 0x01c0
200
201/* BDAP.D N,PC.  */
202#define MOVE_PC_INCR_OPCODE_PREFIX \
203 (((BDAP_INCR_HIGH | (REG_PC << 4)) << 8) | BDAP_PC_LOW | (2 << 4))
204#define MOVE_PC_INCR_OPCODE_SUFFIX \
205 (MOVE_M_TO_PREG_OPCODE | REG_PC | (AUTOINCR_BIT << 8))
206
207#define JUMP_PC_INCR_OPCODE_V32 (0x0DBF)
208
209/* BA DWORD (V32).  */
210#define BA_DWORD_OPCODE (0x0EBF)
211
212/* Nop.  */
213#define NOP_OPCODE (0x050F)
214#define NOP_Z_BITS (0xFFFF ^ NOP_OPCODE)
215
216#define NOP_OPCODE_V32 (0x05B0)
217#define NOP_Z_BITS_V32 (0xFFFF ^ NOP_OPCODE_V32)
218
219/* For the compatibility mode, let's use "MOVE R0,P0".  Doesn't affect
220   registers or flags.  Unfortunately shuts off interrupts for one cycle
221   for < v32, but there doesn't seem to be any alternative without that
222   effect.  */
223#define NOP_OPCODE_COMMON (0x630)
224#define NOP_OPCODE_ZBITS_COMMON (0xffff & ~NOP_OPCODE_COMMON)
225
226/* LAPC.D  */
227#define LAPC_DWORD_OPCODE (0x0D7F)
228#define LAPC_DWORD_Z_BITS (0x0fff & ~LAPC_DWORD_OPCODE)
229
230/* Structure of an opcode table entry.  */
231enum cris_imm_oprnd_size_type
232{
233  /* No size is applicable.  */
234  SIZE_NONE,
235
236  /* Always 32 bits.  */
237  SIZE_FIX_32,
238
239  /* Indicated by size of special register.  */
240  SIZE_SPEC_REG,
241
242  /* Indicated by size field, signed.  */
243  SIZE_FIELD_SIGNED,
244
245  /* Indicated by size field, unsigned.  */
246  SIZE_FIELD_UNSIGNED,
247
248  /* Indicated by size field, no sign implied.  */
249  SIZE_FIELD
250};
251
252/* For GDB.  FIXME: Is this the best way to handle opcode
253   interpretation?  */
254enum cris_op_type
255{
256  cris_not_implemented_op = 0,
257  cris_abs_op,
258  cris_addi_op,
259  cris_asr_op,
260  cris_asrq_op,
261  cris_ax_ei_setf_op,
262  cris_bdap_prefix,
263  cris_biap_prefix,
264  cris_break_op,
265  cris_btst_nop_op,
266  cris_clearf_di_op,
267  cris_dip_prefix,
268  cris_dstep_logshift_mstep_neg_not_op,
269  cris_eight_bit_offset_branch_op,
270  cris_move_mem_to_reg_movem_op,
271  cris_move_reg_to_mem_movem_op,
272  cris_move_to_preg_op,
273  cris_muls_op,
274  cris_mulu_op,
275  cris_none_reg_mode_add_sub_cmp_and_or_move_op,
276  cris_none_reg_mode_clear_test_op,
277  cris_none_reg_mode_jump_op,
278  cris_none_reg_mode_move_from_preg_op,
279  cris_quick_mode_add_sub_op,
280  cris_quick_mode_and_cmp_move_or_op,
281  cris_quick_mode_bdap_prefix,
282  cris_reg_mode_add_sub_cmp_and_or_move_op,
283  cris_reg_mode_clear_op,
284  cris_reg_mode_jump_op,
285  cris_reg_mode_move_from_preg_op,
286  cris_reg_mode_test_op,
287  cris_scc_op,
288  cris_sixteen_bit_offset_branch_op,
289  cris_three_operand_add_sub_cmp_and_or_op,
290  cris_three_operand_bound_op,
291  cris_two_operand_bound_op,
292  cris_xor_op
293};
294
295struct cris_opcode
296{
297  /* The name of the insn.  */
298  const char *name;
299
300  /* Bits that must be 1 for a match.  */
301  unsigned int match;
302
303  /* Bits that must be 0 for a match.  */
304  unsigned int lose;
305
306  /* See the table in "opcodes/cris-opc.c".  */
307  const char *args;
308
309  /* Nonzero if this is a delayed branch instruction.  */
310  char delayed;
311
312  /* Size of immediate operands.  */
313  enum cris_imm_oprnd_size_type imm_oprnd_size;
314
315  /* Indicates which version this insn was first implemented in.  */
316  enum cris_insn_version_usage applicable_version;
317
318  /* What kind of operation this is.  */
319  enum cris_op_type op;
320};
321extern const struct cris_opcode cris_opcodes[];
322
323
324/* These macros are for the target-specific flags in disassemble_info
325   used at disassembly.  */
326
327/* This insn accesses memory.  This flag is more trustworthy than
328   checking insn_type for "dis_dref" which does not work for
329   e.g. "JSR [foo]".  */
330#define CRIS_DIS_FLAG_MEMREF (1 << 0)
331
332/* The "target" field holds a register number.  */
333#define CRIS_DIS_FLAG_MEM_TARGET_IS_REG (1 << 1)
334
335/* The "target2" field holds a register number; add it to "target".  */
336#define CRIS_DIS_FLAG_MEM_TARGET2_IS_REG (1 << 2)
337
338/* Yet another add-on: the register in "target2" must be multiplied
339   by 2 before adding to "target".  */
340#define CRIS_DIS_FLAG_MEM_TARGET2_MULT2 (1 << 3)
341
342/* Yet another add-on: the register in "target2" must be multiplied
343   by 4 (mutually exclusive with .._MULT2).  */
344#define CRIS_DIS_FLAG_MEM_TARGET2_MULT4 (1 << 4)
345
346/* The register in "target2" is an indirect memory reference (of the
347   register there), add to "target".  Assumed size is dword (mutually
348   exclusive with .._MULT[24]).  */
349#define CRIS_DIS_FLAG_MEM_TARGET2_MEM (1 << 5)
350
351/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "byte";
352   sign-extended before adding to "target".  */
353#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE (1 << 6)
354
355/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "word";
356   sign-extended before adding to "target".  */
357#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD (1 << 7)
358
359#endif /* __CRIS_H_INCLUDED_ */
360
361/*
362 * Local variables:
363 * eval: (c-set-style "gnu")
364 * indent-tabs-mode: t
365 * End:
366 */
367