1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * KVM_SET_SREGS tests 4 * 5 * Copyright (C) 2018, Google LLC. 6 * 7 * This is a regression test for the bug fixed by the following commit: 8 * d3802286fa0f ("kvm: x86: Disallow illegal IA32_APIC_BASE MSR values") 9 * 10 * That bug allowed a user-mode program that called the KVM_SET_SREGS 11 * ioctl to put a VCPU's local APIC into an invalid state. 12 */ 13#define _GNU_SOURCE /* for program_invocation_short_name */ 14#include <fcntl.h> 15#include <stdio.h> 16#include <stdlib.h> 17#include <string.h> 18#include <sys/ioctl.h> 19 20#include "test_util.h" 21 22#include "kvm_util.h" 23#include "processor.h" 24 25#define TEST_INVALID_CR_BIT(vcpu, cr, orig, bit) \ 26do { \ 27 struct kvm_sregs new; \ 28 int rc; \ 29 \ 30 /* Skip the sub-test, the feature/bit is supported. */ \ 31 if (orig.cr & bit) \ 32 break; \ 33 \ 34 memcpy(&new, &orig, sizeof(sregs)); \ 35 new.cr |= bit; \ 36 \ 37 rc = _vcpu_sregs_set(vcpu, &new); \ 38 TEST_ASSERT(rc, "KVM allowed invalid " #cr " bit (0x%lx)", bit); \ 39 \ 40 /* Sanity check that KVM didn't change anything. */ \ 41 vcpu_sregs_get(vcpu, &new); \ 42 TEST_ASSERT(!memcmp(&new, &orig, sizeof(new)), "KVM modified sregs"); \ 43} while (0) 44 45static uint64_t calc_supported_cr4_feature_bits(void) 46{ 47 uint64_t cr4; 48 49 cr4 = X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE | 50 X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE | X86_CR4_PGE | 51 X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_OSXMMEXCPT; 52 if (kvm_cpu_has(X86_FEATURE_UMIP)) 53 cr4 |= X86_CR4_UMIP; 54 if (kvm_cpu_has(X86_FEATURE_LA57)) 55 cr4 |= X86_CR4_LA57; 56 if (kvm_cpu_has(X86_FEATURE_VMX)) 57 cr4 |= X86_CR4_VMXE; 58 if (kvm_cpu_has(X86_FEATURE_SMX)) 59 cr4 |= X86_CR4_SMXE; 60 if (kvm_cpu_has(X86_FEATURE_FSGSBASE)) 61 cr4 |= X86_CR4_FSGSBASE; 62 if (kvm_cpu_has(X86_FEATURE_PCID)) 63 cr4 |= X86_CR4_PCIDE; 64 if (kvm_cpu_has(X86_FEATURE_XSAVE)) 65 cr4 |= X86_CR4_OSXSAVE; 66 if (kvm_cpu_has(X86_FEATURE_SMEP)) 67 cr4 |= X86_CR4_SMEP; 68 if (kvm_cpu_has(X86_FEATURE_SMAP)) 69 cr4 |= X86_CR4_SMAP; 70 if (kvm_cpu_has(X86_FEATURE_PKU)) 71 cr4 |= X86_CR4_PKE; 72 73 return cr4; 74} 75 76int main(int argc, char *argv[]) 77{ 78 struct kvm_sregs sregs; 79 struct kvm_vcpu *vcpu; 80 struct kvm_vm *vm; 81 uint64_t cr4; 82 int rc, i; 83 84 /* 85 * Create a dummy VM, specifically to avoid doing KVM_SET_CPUID2, and 86 * use it to verify all supported CR4 bits can be set prior to defining 87 * the vCPU model, i.e. without doing KVM_SET_CPUID2. 88 */ 89 vm = vm_create_barebones(); 90 vcpu = __vm_vcpu_add(vm, 0); 91 92 vcpu_sregs_get(vcpu, &sregs); 93 94 sregs.cr0 = 0; 95 sregs.cr4 |= calc_supported_cr4_feature_bits(); 96 cr4 = sregs.cr4; 97 98 rc = _vcpu_sregs_set(vcpu, &sregs); 99 TEST_ASSERT(!rc, "Failed to set supported CR4 bits (0x%lx)", cr4); 100 101 vcpu_sregs_get(vcpu, &sregs); 102 TEST_ASSERT(sregs.cr4 == cr4, "sregs.CR4 (0x%llx) != CR4 (0x%lx)", 103 sregs.cr4, cr4); 104 105 /* Verify all unsupported features are rejected by KVM. */ 106 TEST_INVALID_CR_BIT(vcpu, cr4, sregs, X86_CR4_UMIP); 107 TEST_INVALID_CR_BIT(vcpu, cr4, sregs, X86_CR4_LA57); 108 TEST_INVALID_CR_BIT(vcpu, cr4, sregs, X86_CR4_VMXE); 109 TEST_INVALID_CR_BIT(vcpu, cr4, sregs, X86_CR4_SMXE); 110 TEST_INVALID_CR_BIT(vcpu, cr4, sregs, X86_CR4_FSGSBASE); 111 TEST_INVALID_CR_BIT(vcpu, cr4, sregs, X86_CR4_PCIDE); 112 TEST_INVALID_CR_BIT(vcpu, cr4, sregs, X86_CR4_OSXSAVE); 113 TEST_INVALID_CR_BIT(vcpu, cr4, sregs, X86_CR4_SMEP); 114 TEST_INVALID_CR_BIT(vcpu, cr4, sregs, X86_CR4_SMAP); 115 TEST_INVALID_CR_BIT(vcpu, cr4, sregs, X86_CR4_PKE); 116 117 for (i = 32; i < 64; i++) 118 TEST_INVALID_CR_BIT(vcpu, cr0, sregs, BIT(i)); 119 120 /* NW without CD is illegal, as is PG without PE. */ 121 TEST_INVALID_CR_BIT(vcpu, cr0, sregs, X86_CR0_NW); 122 TEST_INVALID_CR_BIT(vcpu, cr0, sregs, X86_CR0_PG); 123 124 kvm_vm_free(vm); 125 126 /* Create a "real" VM and verify APIC_BASE can be set. */ 127 vm = vm_create_with_one_vcpu(&vcpu, NULL); 128 129 vcpu_sregs_get(vcpu, &sregs); 130 sregs.apic_base = 1 << 10; 131 rc = _vcpu_sregs_set(vcpu, &sregs); 132 TEST_ASSERT(rc, "Set IA32_APIC_BASE to %llx (invalid)", 133 sregs.apic_base); 134 sregs.apic_base = 1 << 11; 135 rc = _vcpu_sregs_set(vcpu, &sregs); 136 TEST_ASSERT(!rc, "Couldn't set IA32_APIC_BASE to %llx (valid)", 137 sregs.apic_base); 138 139 kvm_vm_free(vm); 140 141 return 0; 142} 143