1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * set_id_regs - Test for setting ID register from usersapce. 4 * 5 * Copyright (c) 2023 Google LLC. 6 * 7 * 8 * Test that KVM supports setting ID registers from userspace and handles the 9 * feature set correctly. 10 */ 11 12#include <stdint.h> 13#include "kvm_util.h" 14#include "processor.h" 15#include "test_util.h" 16#include <linux/bitfield.h> 17 18enum ftr_type { 19 FTR_EXACT, /* Use a predefined safe value */ 20 FTR_LOWER_SAFE, /* Smaller value is safe */ 21 FTR_HIGHER_SAFE, /* Bigger value is safe */ 22 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */ 23 FTR_END, /* Mark the last ftr bits */ 24}; 25 26#define FTR_SIGNED true /* Value should be treated as signed */ 27#define FTR_UNSIGNED false /* Value should be treated as unsigned */ 28 29struct reg_ftr_bits { 30 char *name; 31 bool sign; 32 enum ftr_type type; 33 uint8_t shift; 34 uint64_t mask; 35 /* 36 * For FTR_EXACT, safe_val is used as the exact safe value. 37 * For FTR_LOWER_SAFE, safe_val is used as the minimal safe value. 38 */ 39 int64_t safe_val; 40}; 41 42struct test_feature_reg { 43 uint32_t reg; 44 const struct reg_ftr_bits *ftr_bits; 45}; 46 47#define __REG_FTR_BITS(NAME, SIGNED, TYPE, SHIFT, MASK, SAFE_VAL) \ 48 { \ 49 .name = #NAME, \ 50 .sign = SIGNED, \ 51 .type = TYPE, \ 52 .shift = SHIFT, \ 53 .mask = MASK, \ 54 .safe_val = SAFE_VAL, \ 55 } 56 57#define REG_FTR_BITS(type, reg, field, safe_val) \ 58 __REG_FTR_BITS(reg##_##field, FTR_UNSIGNED, type, reg##_##field##_SHIFT, \ 59 reg##_##field##_MASK, safe_val) 60 61#define S_REG_FTR_BITS(type, reg, field, safe_val) \ 62 __REG_FTR_BITS(reg##_##field, FTR_SIGNED, type, reg##_##field##_SHIFT, \ 63 reg##_##field##_MASK, safe_val) 64 65#define REG_FTR_END \ 66 { \ 67 .type = FTR_END, \ 68 } 69 70static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = { 71 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0), 72 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, ID_AA64DFR0_EL1_DebugVer_IMP), 73 REG_FTR_END, 74}; 75 76static const struct reg_ftr_bits ftr_id_dfr0_el1[] = { 77 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, PerfMon, ID_DFR0_EL1_PerfMon_PMUv3), 78 REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, CopDbg, ID_DFR0_EL1_CopDbg_Armv8), 79 REG_FTR_END, 80}; 81 82static const struct reg_ftr_bits ftr_id_aa64isar0_el1[] = { 83 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RNDR, 0), 84 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TLB, 0), 85 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TS, 0), 86 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, FHM, 0), 87 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, DP, 0), 88 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM4, 0), 89 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM3, 0), 90 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA3, 0), 91 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RDM, 0), 92 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TME, 0), 93 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, ATOMIC, 0), 94 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, CRC32, 0), 95 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA2, 0), 96 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA1, 0), 97 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, AES, 0), 98 REG_FTR_END, 99}; 100 101static const struct reg_ftr_bits ftr_id_aa64isar1_el1[] = { 102 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LS64, 0), 103 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, XS, 0), 104 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, I8MM, 0), 105 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DGH, 0), 106 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, BF16, 0), 107 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SPECRES, 0), 108 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SB, 0), 109 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FRINTTS, 0), 110 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LRCPC, 0), 111 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FCMA, 0), 112 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, JSCVT, 0), 113 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DPB, 0), 114 REG_FTR_END, 115}; 116 117static const struct reg_ftr_bits ftr_id_aa64isar2_el1[] = { 118 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, BC, 0), 119 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, RPRES, 0), 120 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, WFxT, 0), 121 REG_FTR_END, 122}; 123 124static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = { 125 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV3, 0), 126 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV2, 0), 127 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, DIT, 0), 128 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, SEL2, 0), 129 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL3, 0), 130 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL2, 0), 131 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL1, 0), 132 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL0, 0), 133 REG_FTR_END, 134}; 135 136static const struct reg_ftr_bits ftr_id_aa64mmfr0_el1[] = { 137 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ECV, 0), 138 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, EXS, 0), 139 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN4, 0), 140 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN64, 0), 141 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN16, 0), 142 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGENDEL0, 0), 143 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, SNSMEM, 0), 144 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGEND, 0), 145 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ASIDBITS, 0), 146 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, PARANGE, 0), 147 REG_FTR_END, 148}; 149 150static const struct reg_ftr_bits ftr_id_aa64mmfr1_el1[] = { 151 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, TIDCP1, 0), 152 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, AFP, 0), 153 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, ETS, 0), 154 REG_FTR_BITS(FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1, SpecSEI, 0), 155 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, PAN, 0), 156 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, LO, 0), 157 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HPDS, 0), 158 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HAFDBS, 0), 159 REG_FTR_END, 160}; 161 162static const struct reg_ftr_bits ftr_id_aa64mmfr2_el1[] = { 163 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, E0PD, 0), 164 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, BBM, 0), 165 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, TTL, 0), 166 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, AT, 0), 167 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, ST, 0), 168 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, VARange, 0), 169 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, IESB, 0), 170 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, LSM, 0), 171 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, UAO, 0), 172 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, CnP, 0), 173 REG_FTR_END, 174}; 175 176static const struct reg_ftr_bits ftr_id_aa64zfr0_el1[] = { 177 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F64MM, 0), 178 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F32MM, 0), 179 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, I8MM, 0), 180 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SM4, 0), 181 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SHA3, 0), 182 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BF16, 0), 183 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BitPerm, 0), 184 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, AES, 0), 185 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SVEver, 0), 186 REG_FTR_END, 187}; 188 189#define TEST_REG(id, table) \ 190 { \ 191 .reg = id, \ 192 .ftr_bits = &((table)[0]), \ 193 } 194 195static struct test_feature_reg test_regs[] = { 196 TEST_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0_el1), 197 TEST_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0_el1), 198 TEST_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0_el1), 199 TEST_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1_el1), 200 TEST_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2_el1), 201 TEST_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0_el1), 202 TEST_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0_el1), 203 TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1), 204 TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1), 205 TEST_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1), 206}; 207 208#define GUEST_REG_SYNC(id) GUEST_SYNC_ARGS(0, id, read_sysreg_s(id), 0, 0); 209 210static void guest_code(void) 211{ 212 GUEST_REG_SYNC(SYS_ID_AA64DFR0_EL1); 213 GUEST_REG_SYNC(SYS_ID_DFR0_EL1); 214 GUEST_REG_SYNC(SYS_ID_AA64ISAR0_EL1); 215 GUEST_REG_SYNC(SYS_ID_AA64ISAR1_EL1); 216 GUEST_REG_SYNC(SYS_ID_AA64ISAR2_EL1); 217 GUEST_REG_SYNC(SYS_ID_AA64PFR0_EL1); 218 GUEST_REG_SYNC(SYS_ID_AA64MMFR0_EL1); 219 GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1); 220 GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1); 221 GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1); 222 223 GUEST_DONE(); 224} 225 226/* Return a safe value to a given ftr_bits an ftr value */ 227uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr) 228{ 229 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0); 230 231 if (ftr_bits->sign == FTR_UNSIGNED) { 232 switch (ftr_bits->type) { 233 case FTR_EXACT: 234 ftr = ftr_bits->safe_val; 235 break; 236 case FTR_LOWER_SAFE: 237 if (ftr > ftr_bits->safe_val) 238 ftr--; 239 break; 240 case FTR_HIGHER_SAFE: 241 if (ftr < ftr_max) 242 ftr++; 243 break; 244 case FTR_HIGHER_OR_ZERO_SAFE: 245 if (ftr == ftr_max) 246 ftr = 0; 247 else if (ftr != 0) 248 ftr++; 249 break; 250 default: 251 break; 252 } 253 } else if (ftr != ftr_max) { 254 switch (ftr_bits->type) { 255 case FTR_EXACT: 256 ftr = ftr_bits->safe_val; 257 break; 258 case FTR_LOWER_SAFE: 259 if (ftr > ftr_bits->safe_val) 260 ftr--; 261 break; 262 case FTR_HIGHER_SAFE: 263 if (ftr < ftr_max - 1) 264 ftr++; 265 break; 266 case FTR_HIGHER_OR_ZERO_SAFE: 267 if (ftr != 0 && ftr != ftr_max - 1) 268 ftr++; 269 break; 270 default: 271 break; 272 } 273 } 274 275 return ftr; 276} 277 278/* Return an invalid value to a given ftr_bits an ftr value */ 279uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr) 280{ 281 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0); 282 283 if (ftr_bits->sign == FTR_UNSIGNED) { 284 switch (ftr_bits->type) { 285 case FTR_EXACT: 286 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1); 287 break; 288 case FTR_LOWER_SAFE: 289 ftr++; 290 break; 291 case FTR_HIGHER_SAFE: 292 ftr--; 293 break; 294 case FTR_HIGHER_OR_ZERO_SAFE: 295 if (ftr == 0) 296 ftr = ftr_max; 297 else 298 ftr--; 299 break; 300 default: 301 break; 302 } 303 } else if (ftr != ftr_max) { 304 switch (ftr_bits->type) { 305 case FTR_EXACT: 306 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1); 307 break; 308 case FTR_LOWER_SAFE: 309 ftr++; 310 break; 311 case FTR_HIGHER_SAFE: 312 ftr--; 313 break; 314 case FTR_HIGHER_OR_ZERO_SAFE: 315 if (ftr == 0) 316 ftr = ftr_max - 1; 317 else 318 ftr--; 319 break; 320 default: 321 break; 322 } 323 } else { 324 ftr = 0; 325 } 326 327 return ftr; 328} 329 330static void test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg, 331 const struct reg_ftr_bits *ftr_bits) 332{ 333 uint8_t shift = ftr_bits->shift; 334 uint64_t mask = ftr_bits->mask; 335 uint64_t val, new_val, ftr; 336 337 vcpu_get_reg(vcpu, reg, &val); 338 ftr = (val & mask) >> shift; 339 340 ftr = get_safe_value(ftr_bits, ftr); 341 342 ftr <<= shift; 343 val &= ~mask; 344 val |= ftr; 345 346 vcpu_set_reg(vcpu, reg, val); 347 vcpu_get_reg(vcpu, reg, &new_val); 348 TEST_ASSERT_EQ(new_val, val); 349} 350 351static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg, 352 const struct reg_ftr_bits *ftr_bits) 353{ 354 uint8_t shift = ftr_bits->shift; 355 uint64_t mask = ftr_bits->mask; 356 uint64_t val, old_val, ftr; 357 int r; 358 359 vcpu_get_reg(vcpu, reg, &val); 360 ftr = (val & mask) >> shift; 361 362 ftr = get_invalid_value(ftr_bits, ftr); 363 364 old_val = val; 365 ftr <<= shift; 366 val &= ~mask; 367 val |= ftr; 368 369 r = __vcpu_set_reg(vcpu, reg, val); 370 TEST_ASSERT(r < 0 && errno == EINVAL, 371 "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno); 372 373 vcpu_get_reg(vcpu, reg, &val); 374 TEST_ASSERT_EQ(val, old_val); 375} 376 377static void test_user_set_reg(struct kvm_vcpu *vcpu, bool aarch64_only) 378{ 379 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE]; 380 struct reg_mask_range range = { 381 .addr = (__u64)masks, 382 }; 383 int ret; 384 385 /* KVM should return error when reserved field is not zero */ 386 range.reserved[0] = 1; 387 ret = __vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range); 388 TEST_ASSERT(ret, "KVM doesn't check invalid parameters."); 389 390 /* Get writable masks for feature ID registers */ 391 memset(range.reserved, 0, sizeof(range.reserved)); 392 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range); 393 394 for (int i = 0; i < ARRAY_SIZE(test_regs); i++) { 395 const struct reg_ftr_bits *ftr_bits = test_regs[i].ftr_bits; 396 uint32_t reg_id = test_regs[i].reg; 397 uint64_t reg = KVM_ARM64_SYS_REG(reg_id); 398 int idx; 399 400 /* Get the index to masks array for the idreg */ 401 idx = KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(reg_id), sys_reg_Op1(reg_id), 402 sys_reg_CRn(reg_id), sys_reg_CRm(reg_id), 403 sys_reg_Op2(reg_id)); 404 405 for (int j = 0; ftr_bits[j].type != FTR_END; j++) { 406 /* Skip aarch32 reg on aarch64 only system, since they are RAZ/WI. */ 407 if (aarch64_only && sys_reg_CRm(reg_id) < 4) { 408 ksft_test_result_skip("%s on AARCH64 only system\n", 409 ftr_bits[j].name); 410 continue; 411 } 412 413 /* Make sure the feature field is writable */ 414 TEST_ASSERT_EQ(masks[idx] & ftr_bits[j].mask, ftr_bits[j].mask); 415 416 test_reg_set_fail(vcpu, reg, &ftr_bits[j]); 417 test_reg_set_success(vcpu, reg, &ftr_bits[j]); 418 419 ksft_test_result_pass("%s\n", ftr_bits[j].name); 420 } 421 } 422} 423 424static void test_guest_reg_read(struct kvm_vcpu *vcpu) 425{ 426 bool done = false; 427 struct ucall uc; 428 uint64_t val; 429 430 while (!done) { 431 vcpu_run(vcpu); 432 433 switch (get_ucall(vcpu, &uc)) { 434 case UCALL_ABORT: 435 REPORT_GUEST_ASSERT(uc); 436 break; 437 case UCALL_SYNC: 438 /* Make sure the written values are seen by guest */ 439 vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(uc.args[2]), &val); 440 TEST_ASSERT_EQ(val, uc.args[3]); 441 break; 442 case UCALL_DONE: 443 done = true; 444 break; 445 default: 446 TEST_FAIL("Unexpected ucall: %lu", uc.cmd); 447 } 448 } 449} 450 451int main(void) 452{ 453 struct kvm_vcpu *vcpu; 454 struct kvm_vm *vm; 455 bool aarch64_only; 456 uint64_t val, el0; 457 int ftr_cnt; 458 459 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES)); 460 461 vm = vm_create_with_one_vcpu(&vcpu, guest_code); 462 463 /* Check for AARCH64 only system */ 464 vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), &val); 465 el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val); 466 aarch64_only = (el0 == ID_AA64PFR0_EL1_ELx_64BIT_ONLY); 467 468 ksft_print_header(); 469 470 ftr_cnt = ARRAY_SIZE(ftr_id_aa64dfr0_el1) + ARRAY_SIZE(ftr_id_dfr0_el1) + 471 ARRAY_SIZE(ftr_id_aa64isar0_el1) + ARRAY_SIZE(ftr_id_aa64isar1_el1) + 472 ARRAY_SIZE(ftr_id_aa64isar2_el1) + ARRAY_SIZE(ftr_id_aa64pfr0_el1) + 473 ARRAY_SIZE(ftr_id_aa64mmfr0_el1) + ARRAY_SIZE(ftr_id_aa64mmfr1_el1) + 474 ARRAY_SIZE(ftr_id_aa64mmfr2_el1) + ARRAY_SIZE(ftr_id_aa64zfr0_el1) - 475 ARRAY_SIZE(test_regs); 476 477 ksft_set_plan(ftr_cnt); 478 479 test_user_set_reg(vcpu, aarch64_only); 480 test_guest_reg_read(vcpu); 481 482 kvm_vm_free(vm); 483 484 ksft_finished(); 485} 486