1{
2	"add+sub+mul",
3	.insns = {
4	BPF_MOV64_IMM(BPF_REG_1, 1),
5	BPF_ALU64_IMM(BPF_ADD, BPF_REG_1, 2),
6	BPF_MOV64_IMM(BPF_REG_2, 3),
7	BPF_ALU64_REG(BPF_SUB, BPF_REG_1, BPF_REG_2),
8	BPF_ALU64_IMM(BPF_ADD, BPF_REG_1, -1),
9	BPF_ALU64_IMM(BPF_MUL, BPF_REG_1, 3),
10	BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
11	BPF_EXIT_INSN(),
12	},
13	.result = ACCEPT,
14	.retval = -3,
15},
16{
17	"xor32 zero extend check",
18	.insns = {
19	BPF_MOV32_IMM(BPF_REG_2, -1),
20	BPF_ALU64_IMM(BPF_LSH, BPF_REG_2, 32),
21	BPF_ALU64_IMM(BPF_OR, BPF_REG_2, 0xffff),
22	BPF_ALU32_REG(BPF_XOR, BPF_REG_2, BPF_REG_2),
23	BPF_MOV32_IMM(BPF_REG_0, 2),
24	BPF_JMP_IMM(BPF_JNE, BPF_REG_2, 0, 1),
25	BPF_MOV32_IMM(BPF_REG_0, 1),
26	BPF_EXIT_INSN(),
27	},
28	.prog_type = BPF_PROG_TYPE_SCHED_CLS,
29	.result = ACCEPT,
30	.retval = 1,
31},
32{
33	"arsh32 on imm",
34	.insns = {
35	BPF_MOV64_IMM(BPF_REG_0, 1),
36	BPF_ALU32_IMM(BPF_ARSH, BPF_REG_0, 5),
37	BPF_EXIT_INSN(),
38	},
39	.result = ACCEPT,
40	.retval = 0,
41},
42{
43	"arsh32 on imm 2",
44	.insns = {
45	BPF_LD_IMM64(BPF_REG_0, 0x1122334485667788),
46	BPF_ALU32_IMM(BPF_ARSH, BPF_REG_0, 7),
47	BPF_EXIT_INSN(),
48	},
49	.result = ACCEPT,
50	.retval = -16069393,
51},
52{
53	"arsh32 on reg",
54	.insns = {
55	BPF_MOV64_IMM(BPF_REG_0, 1),
56	BPF_MOV64_IMM(BPF_REG_1, 5),
57	BPF_ALU32_REG(BPF_ARSH, BPF_REG_0, BPF_REG_1),
58	BPF_EXIT_INSN(),
59	},
60	.result = ACCEPT,
61	.retval = 0,
62},
63{
64	"arsh32 on reg 2",
65	.insns = {
66	BPF_LD_IMM64(BPF_REG_0, 0xffff55667788),
67	BPF_MOV64_IMM(BPF_REG_1, 15),
68	BPF_ALU32_REG(BPF_ARSH, BPF_REG_0, BPF_REG_1),
69	BPF_EXIT_INSN(),
70	},
71	.result = ACCEPT,
72	.retval = 43724,
73},
74{
75	"arsh64 on imm",
76	.insns = {
77	BPF_MOV64_IMM(BPF_REG_0, 1),
78	BPF_ALU64_IMM(BPF_ARSH, BPF_REG_0, 5),
79	BPF_EXIT_INSN(),
80	},
81	.result = ACCEPT,
82},
83{
84	"arsh64 on reg",
85	.insns = {
86	BPF_MOV64_IMM(BPF_REG_0, 1),
87	BPF_MOV64_IMM(BPF_REG_1, 5),
88	BPF_ALU64_REG(BPF_ARSH, BPF_REG_0, BPF_REG_1),
89	BPF_EXIT_INSN(),
90	},
91	.result = ACCEPT,
92},
93{
94	"lsh64 by 0 imm",
95	.insns = {
96	BPF_LD_IMM64(BPF_REG_0, 1),
97	BPF_LD_IMM64(BPF_REG_1, 1),
98	BPF_ALU64_IMM(BPF_LSH, BPF_REG_1, 0),
99	BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 1, 1),
100	BPF_MOV64_IMM(BPF_REG_0, 2),
101	BPF_EXIT_INSN(),
102	},
103	.result = ACCEPT,
104	.retval = 1,
105},
106{
107	"rsh64 by 0 imm",
108	.insns = {
109	BPF_LD_IMM64(BPF_REG_0, 1),
110	BPF_LD_IMM64(BPF_REG_1, 0x100000000LL),
111	BPF_ALU64_REG(BPF_MOV, BPF_REG_2, BPF_REG_1),
112	BPF_ALU64_IMM(BPF_RSH, BPF_REG_1, 0),
113	BPF_JMP_REG(BPF_JEQ, BPF_REG_1, BPF_REG_2, 1),
114	BPF_MOV64_IMM(BPF_REG_0, 2),
115	BPF_EXIT_INSN(),
116	},
117	.result = ACCEPT,
118	.retval = 1,
119},
120{
121	"arsh64 by 0 imm",
122	.insns = {
123	BPF_LD_IMM64(BPF_REG_0, 1),
124	BPF_LD_IMM64(BPF_REG_1, 0x100000000LL),
125	BPF_ALU64_REG(BPF_MOV, BPF_REG_2, BPF_REG_1),
126	BPF_ALU64_IMM(BPF_ARSH, BPF_REG_1, 0),
127	BPF_JMP_REG(BPF_JEQ, BPF_REG_1, BPF_REG_2, 1),
128	BPF_MOV64_IMM(BPF_REG_0, 2),
129	BPF_EXIT_INSN(),
130	},
131	.result = ACCEPT,
132	.retval = 1,
133},
134{
135	"lsh64 by 0 reg",
136	.insns = {
137	BPF_LD_IMM64(BPF_REG_0, 1),
138	BPF_LD_IMM64(BPF_REG_1, 1),
139	BPF_LD_IMM64(BPF_REG_2, 0),
140	BPF_ALU64_REG(BPF_LSH, BPF_REG_1, BPF_REG_2),
141	BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 1, 1),
142	BPF_MOV64_IMM(BPF_REG_0, 2),
143	BPF_EXIT_INSN(),
144	},
145	.result = ACCEPT,
146	.retval = 1,
147},
148{
149	"rsh64 by 0 reg",
150	.insns = {
151	BPF_LD_IMM64(BPF_REG_0, 1),
152	BPF_LD_IMM64(BPF_REG_1, 0x100000000LL),
153	BPF_ALU64_REG(BPF_MOV, BPF_REG_2, BPF_REG_1),
154	BPF_LD_IMM64(BPF_REG_3, 0),
155	BPF_ALU64_REG(BPF_RSH, BPF_REG_1, BPF_REG_3),
156	BPF_JMP_REG(BPF_JEQ, BPF_REG_1, BPF_REG_2, 1),
157	BPF_MOV64_IMM(BPF_REG_0, 2),
158	BPF_EXIT_INSN(),
159	},
160	.result = ACCEPT,
161	.retval = 1,
162},
163{
164	"arsh64 by 0 reg",
165	.insns = {
166	BPF_LD_IMM64(BPF_REG_0, 1),
167	BPF_LD_IMM64(BPF_REG_1, 0x100000000LL),
168	BPF_ALU64_REG(BPF_MOV, BPF_REG_2, BPF_REG_1),
169	BPF_LD_IMM64(BPF_REG_3, 0),
170	BPF_ALU64_REG(BPF_ARSH, BPF_REG_1, BPF_REG_3),
171	BPF_JMP_REG(BPF_JEQ, BPF_REG_1, BPF_REG_2, 1),
172	BPF_MOV64_IMM(BPF_REG_0, 2),
173	BPF_EXIT_INSN(),
174	},
175	.result = ACCEPT,
176	.retval = 1,
177},
178{
179	"invalid 64-bit BPF_END with BPF_TO_BE",
180	.insns = {
181	BPF_MOV32_IMM(BPF_REG_0, 0),
182	{
183		.code  = BPF_ALU64 | BPF_END | BPF_TO_BE,
184		.dst_reg = BPF_REG_0,
185		.src_reg = 0,
186		.off   = 0,
187		.imm   = 32,
188	},
189	BPF_EXIT_INSN(),
190	},
191	.errstr = "unknown opcode df",
192	.result = REJECT,
193},
194{
195	"mov64 src == dst",
196	.insns = {
197	BPF_MOV64_IMM(BPF_REG_2, 0),
198	BPF_MOV64_REG(BPF_REG_2, BPF_REG_2),
199	// Check bounds are OK
200	BPF_ALU64_REG(BPF_ADD, BPF_REG_1, BPF_REG_2),
201	BPF_MOV64_IMM(BPF_REG_0, 0),
202	BPF_EXIT_INSN(),
203	},
204	.prog_type = BPF_PROG_TYPE_SCHED_CLS,
205	.result = ACCEPT,
206},
207{
208	"mov64 src != dst",
209	.insns = {
210	BPF_MOV64_IMM(BPF_REG_3, 0),
211	BPF_MOV64_REG(BPF_REG_2, BPF_REG_3),
212	// Check bounds are OK
213	BPF_ALU64_REG(BPF_ADD, BPF_REG_1, BPF_REG_2),
214	BPF_MOV64_IMM(BPF_REG_0, 0),
215	BPF_EXIT_INSN(),
216	},
217	.prog_type = BPF_PROG_TYPE_SCHED_CLS,
218	.result = ACCEPT,
219},
220