1[ 2 { 3 "BriefDescription": "Counts the number of lfclk ticks", 4 "EventCode": "0x01", 5 "EventName": "UNC_CXLCM_CLOCKTICKS", 6 "PerPkg": "1", 7 "UMask": "0x2", 8 "Unit": "CXLCM" 9 }, 10 { 11 "BriefDescription": "Number of Allocation to Mem Rxx AGF 0", 12 "EventCode": "0x43", 13 "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_DATA", 14 "PerPkg": "1", 15 "UMask": "0x8", 16 "Unit": "CXLCM" 17 }, 18 { 19 "BriefDescription": "Number of Allocation to Cache Req AGF0", 20 "EventCode": "0x43", 21 "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_REQ0", 22 "PerPkg": "1", 23 "UMask": "0x1", 24 "Unit": "CXLCM" 25 }, 26 { 27 "BriefDescription": "Number of Allocation to Cache Rsp AGF", 28 "EventCode": "0x43", 29 "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_REQ1", 30 "PerPkg": "1", 31 "UMask": "0x2", 32 "Unit": "CXLCM" 33 }, 34 { 35 "BriefDescription": "Number of Allocation to Cache Data AGF", 36 "EventCode": "0x43", 37 "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_RSP0", 38 "PerPkg": "1", 39 "UMask": "0x4", 40 "Unit": "CXLCM" 41 }, 42 { 43 "BriefDescription": "Number of Allocation to Cache Rsp AGF", 44 "EventCode": "0x43", 45 "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_RSP1", 46 "PerPkg": "1", 47 "UMask": "0x40", 48 "Unit": "CXLCM" 49 }, 50 { 51 "BriefDescription": "Number of Allocation to Cache Req AGF 1", 52 "EventCode": "0x43", 53 "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.MEM_DATA", 54 "PerPkg": "1", 55 "UMask": "0x20", 56 "Unit": "CXLCM" 57 }, 58 { 59 "BriefDescription": "Number of Allocation to Mem Data AGF", 60 "EventCode": "0x43", 61 "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.MEM_REQ", 62 "PerPkg": "1", 63 "UMask": "0x10", 64 "Unit": "CXLCM" 65 }, 66 { 67 "BriefDescription": "Count the number of Flits with AK set", 68 "EventCode": "0x4b", 69 "EventName": "UNC_CXLCM_RxC_FLITS.AK_HDR", 70 "PerPkg": "1", 71 "UMask": "0x10", 72 "Unit": "CXLCM" 73 }, 74 { 75 "BriefDescription": "Count the number of Flits with BE set", 76 "EventCode": "0x4b", 77 "EventName": "UNC_CXLCM_RxC_FLITS.BE_HDR", 78 "PerPkg": "1", 79 "UMask": "0x20", 80 "Unit": "CXLCM" 81 }, 82 { 83 "BriefDescription": "Count the number of control flits received", 84 "EventCode": "0x4b", 85 "EventName": "UNC_CXLCM_RxC_FLITS.CTRL", 86 "PerPkg": "1", 87 "UMask": "0x4", 88 "Unit": "CXLCM" 89 }, 90 { 91 "BriefDescription": "Count the number of Headerless flits received", 92 "EventCode": "0x4b", 93 "EventName": "UNC_CXLCM_RxC_FLITS.NO_HDR", 94 "PerPkg": "1", 95 "UMask": "0x8", 96 "Unit": "CXLCM" 97 }, 98 { 99 "BriefDescription": "Count the number of protocol flits received", 100 "EventCode": "0x4b", 101 "EventName": "UNC_CXLCM_RxC_FLITS.PROT", 102 "PerPkg": "1", 103 "UMask": "0x2", 104 "Unit": "CXLCM" 105 }, 106 { 107 "BriefDescription": "Count the number of Flits with SZ set", 108 "EventCode": "0x4b", 109 "EventName": "UNC_CXLCM_RxC_FLITS.SZ_HDR", 110 "PerPkg": "1", 111 "UMask": "0x40", 112 "Unit": "CXLCM" 113 }, 114 { 115 "BriefDescription": "Count the number of flits received", 116 "EventCode": "0x4b", 117 "EventName": "UNC_CXLCM_RxC_FLITS.VALID", 118 "PerPkg": "1", 119 "UMask": "0x1", 120 "Unit": "CXLCM" 121 }, 122 { 123 "BriefDescription": "Count the number of valid messages in the flit", 124 "EventCode": "0x4b", 125 "EventName": "UNC_CXLCM_RxC_FLITS.VALID_MSG", 126 "PerPkg": "1", 127 "UMask": "0x80", 128 "Unit": "CXLCM" 129 }, 130 { 131 "BriefDescription": "Count the number of CRC errors detected", 132 "EventCode": "0x40", 133 "EventName": "UNC_CXLCM_RxC_MISC.CRC_ERRORS", 134 "PerPkg": "1", 135 "UMask": "0x8", 136 "Unit": "CXLCM" 137 }, 138 { 139 "BriefDescription": "Count the number of Init flits sent", 140 "EventCode": "0x40", 141 "EventName": "UNC_CXLCM_RxC_MISC.INIT", 142 "PerPkg": "1", 143 "UMask": "0x4", 144 "Unit": "CXLCM" 145 }, 146 { 147 "BriefDescription": "Count the number of LLCRD flits sent", 148 "EventCode": "0x40", 149 "EventName": "UNC_CXLCM_RxC_MISC.LLCRD", 150 "PerPkg": "1", 151 "UMask": "0x1", 152 "Unit": "CXLCM" 153 }, 154 { 155 "BriefDescription": "Count the number of Retry flits sent", 156 "EventCode": "0x40", 157 "EventName": "UNC_CXLCM_RxC_MISC.RETRY", 158 "PerPkg": "1", 159 "UMask": "0x2", 160 "Unit": "CXLCM" 161 }, 162 { 163 "BriefDescription": "Number of cycles the Packing Buffer is Full", 164 "EventCode": "0x52", 165 "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_DATA", 166 "PerPkg": "1", 167 "UMask": "0x4", 168 "Unit": "CXLCM" 169 }, 170 { 171 "BriefDescription": "Number of cycles the Packing Buffer is Full", 172 "EventCode": "0x52", 173 "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_REQ", 174 "PerPkg": "1", 175 "UMask": "0x1", 176 "Unit": "CXLCM" 177 }, 178 { 179 "BriefDescription": "Number of cycles the Packing Buffer is Full", 180 "EventCode": "0x52", 181 "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_RSP", 182 "PerPkg": "1", 183 "UMask": "0x2", 184 "Unit": "CXLCM" 185 }, 186 { 187 "BriefDescription": "Number of cycles the Packing Buffer is Full", 188 "EventCode": "0x52", 189 "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.MEM_DATA", 190 "PerPkg": "1", 191 "UMask": "0x10", 192 "Unit": "CXLCM" 193 }, 194 { 195 "BriefDescription": "Number of cycles the Packing Buffer is Full", 196 "EventCode": "0x52", 197 "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.MEM_REQ", 198 "PerPkg": "1", 199 "UMask": "0x8", 200 "Unit": "CXLCM" 201 }, 202 { 203 "BriefDescription": "Number of Allocation to Cache Data Packing buffer", 204 "EventCode": "0x41", 205 "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_DATA", 206 "PerPkg": "1", 207 "UMask": "0x4", 208 "Unit": "CXLCM" 209 }, 210 { 211 "BriefDescription": "Number of Allocation to Cache Req Packing buffer", 212 "EventCode": "0x41", 213 "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_REQ", 214 "PerPkg": "1", 215 "UMask": "0x1", 216 "Unit": "CXLCM" 217 }, 218 { 219 "BriefDescription": "Number of Allocation to Cache Rsp Packing buffer", 220 "EventCode": "0x41", 221 "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_RSP", 222 "PerPkg": "1", 223 "UMask": "0x2", 224 "Unit": "CXLCM" 225 }, 226 { 227 "BriefDescription": "Number of Allocation to Mem Data Packing buffer", 228 "EventCode": "0x41", 229 "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA", 230 "PerPkg": "1", 231 "UMask": "0x10", 232 "Unit": "CXLCM" 233 }, 234 { 235 "BriefDescription": "Number of Allocation to Mem Rxx Packing buffer", 236 "EventCode": "0x41", 237 "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_REQ", 238 "PerPkg": "1", 239 "UMask": "0x8", 240 "Unit": "CXLCM" 241 }, 242 { 243 "BriefDescription": "Number of cycles of Not Empty for Cache Data Packing buffer", 244 "EventCode": "0x42", 245 "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_DATA", 246 "PerPkg": "1", 247 "UMask": "0x4", 248 "Unit": "CXLCM" 249 }, 250 { 251 "BriefDescription": "Number of cycles of Not Empty for Cache Req Packing buffer", 252 "EventCode": "0x42", 253 "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_REQ", 254 "PerPkg": "1", 255 "UMask": "0x1", 256 "Unit": "CXLCM" 257 }, 258 { 259 "BriefDescription": "Number of cycles of Not Empty for Cache Rsp Packing buffer", 260 "EventCode": "0x42", 261 "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_RSP", 262 "PerPkg": "1", 263 "UMask": "0x2", 264 "Unit": "CXLCM" 265 }, 266 { 267 "BriefDescription": "Number of cycles of Not Empty for Mem Data Packing buffer", 268 "EventCode": "0x42", 269 "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.MEM_DATA", 270 "PerPkg": "1", 271 "UMask": "0x10", 272 "Unit": "CXLCM" 273 }, 274 { 275 "BriefDescription": "Number of cycles of Not Empty for Mem Rxx Packing buffer", 276 "EventCode": "0x42", 277 "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.MEM_REQ", 278 "PerPkg": "1", 279 "UMask": "0x8", 280 "Unit": "CXLCM" 281 }, 282 { 283 "BriefDescription": "Count the number of Flits with AK set", 284 "EventCode": "0x05", 285 "EventName": "UNC_CXLCM_TxC_FLITS.AK_HDR", 286 "PerPkg": "1", 287 "UMask": "0x10", 288 "Unit": "CXLCM" 289 }, 290 { 291 "BriefDescription": "Count the number of Flits with BE set", 292 "EventCode": "0x05", 293 "EventName": "UNC_CXLCM_TxC_FLITS.BE_HDR", 294 "PerPkg": "1", 295 "UMask": "0x20", 296 "Unit": "CXLCM" 297 }, 298 { 299 "BriefDescription": "Count the number of control flits packed", 300 "EventCode": "0x05", 301 "EventName": "UNC_CXLCM_TxC_FLITS.CTRL", 302 "PerPkg": "1", 303 "UMask": "0x4", 304 "Unit": "CXLCM" 305 }, 306 { 307 "BriefDescription": "Count the number of Headerless flits packed", 308 "EventCode": "0x05", 309 "EventName": "UNC_CXLCM_TxC_FLITS.NO_HDR", 310 "PerPkg": "1", 311 "UMask": "0x8", 312 "Unit": "CXLCM" 313 }, 314 { 315 "BriefDescription": "Count the number of protocol flits packed", 316 "EventCode": "0x05", 317 "EventName": "UNC_CXLCM_TxC_FLITS.PROT", 318 "PerPkg": "1", 319 "UMask": "0x2", 320 "Unit": "CXLCM" 321 }, 322 { 323 "BriefDescription": "Count the number of Flits with SZ set", 324 "EventCode": "0x05", 325 "EventName": "UNC_CXLCM_TxC_FLITS.SZ_HDR", 326 "PerPkg": "1", 327 "UMask": "0x40", 328 "Unit": "CXLCM" 329 }, 330 { 331 "BriefDescription": "Count the number of flits packed", 332 "EventCode": "0x05", 333 "EventName": "UNC_CXLCM_TxC_FLITS.VALID", 334 "PerPkg": "1", 335 "UMask": "0x1", 336 "Unit": "CXLCM" 337 }, 338 { 339 "BriefDescription": "Number of Allocation to Cache Data Packing buffer", 340 "EventCode": "0x02", 341 "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_DATA", 342 "PerPkg": "1", 343 "UMask": "0x4", 344 "Unit": "CXLCM" 345 }, 346 { 347 "BriefDescription": "Number of Allocation to Cache Req Packing buffer", 348 "EventCode": "0x02", 349 "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_REQ0", 350 "PerPkg": "1", 351 "UMask": "0x1", 352 "Unit": "CXLCM" 353 }, 354 { 355 "BriefDescription": "Number of Allocation to Cache Rsp1 Packing buffer", 356 "EventCode": "0x02", 357 "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_REQ1", 358 "PerPkg": "1", 359 "UMask": "0x40", 360 "Unit": "CXLCM" 361 }, 362 { 363 "BriefDescription": "Number of Allocation to Cache Rsp0 Packing buffer", 364 "EventCode": "0x02", 365 "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_RSP0", 366 "PerPkg": "1", 367 "UMask": "0x2", 368 "Unit": "CXLCM" 369 }, 370 { 371 "BriefDescription": "Number of Allocation to Cache Req Packing buffer", 372 "EventCode": "0x02", 373 "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_RSP1", 374 "PerPkg": "1", 375 "UMask": "0x20", 376 "Unit": "CXLCM" 377 }, 378 { 379 "BriefDescription": "Number of Allocation to Mem Data Packing buffer", 380 "EventCode": "0x02", 381 "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.MEM_DATA", 382 "PerPkg": "1", 383 "UMask": "0x10", 384 "Unit": "CXLCM" 385 }, 386 { 387 "BriefDescription": "Number of Allocation to Mem Rxx Packing buffer", 388 "EventCode": "0x02", 389 "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.MEM_REQ", 390 "PerPkg": "1", 391 "UMask": "0x8", 392 "Unit": "CXLCM" 393 }, 394 { 395 "BriefDescription": "Counts the number of uclk ticks", 396 "EventCode": "0x01", 397 "EventName": "UNC_CXLDP_CLOCKTICKS", 398 "PerPkg": "1", 399 "UMask": "0x1", 400 "Unit": "CXLDP" 401 }, 402 { 403 "BriefDescription": "Number of Allocation to M2S Data AGF", 404 "EventCode": "0x02", 405 "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_DATA", 406 "PerPkg": "1", 407 "UMask": "0x20", 408 "Unit": "CXLDP" 409 }, 410 { 411 "BriefDescription": "Number of Allocation to M2S Req AGF", 412 "EventCode": "0x02", 413 "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_REQ", 414 "PerPkg": "1", 415 "UMask": "0x10", 416 "Unit": "CXLDP" 417 }, 418 { 419 "BriefDescription": "Number of Allocation to U2C Data AGF", 420 "EventCode": "0x02", 421 "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_DATA", 422 "PerPkg": "1", 423 "UMask": "0x8", 424 "Unit": "CXLDP" 425 }, 426 { 427 "BriefDescription": "Number of Allocation to U2C Req AGF", 428 "EventCode": "0x02", 429 "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_REQ", 430 "PerPkg": "1", 431 "UMask": "0x1", 432 "Unit": "CXLDP" 433 }, 434 { 435 "BriefDescription": "Number of Allocation to U2C Rsp AGF 0", 436 "EventCode": "0x02", 437 "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_RSP0", 438 "PerPkg": "1", 439 "UMask": "0x2", 440 "Unit": "CXLDP" 441 }, 442 { 443 "BriefDescription": "Number of Allocation to U2C Rsp AGF 1", 444 "EventCode": "0x02", 445 "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_RSP1", 446 "PerPkg": "1", 447 "UMask": "0x4", 448 "Unit": "CXLDP" 449 } 450] 451