1[
2    {
3        "BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
4        "EventCode": "0x5C",
5        "EventName": "CPL_CYCLES.RING0",
6        "SampleAfterValue": "2000003",
7        "UMask": "0x1"
8    },
9    {
10        "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
11        "CounterMask": "1",
12        "EdgeDetect": "1",
13        "EventCode": "0x5C",
14        "EventName": "CPL_CYCLES.RING0_TRANS",
15        "SampleAfterValue": "100007",
16        "UMask": "0x1"
17    },
18    {
19        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
20        "EventCode": "0x5C",
21        "EventName": "CPL_CYCLES.RING123",
22        "SampleAfterValue": "2000003",
23        "UMask": "0x2"
24    },
25    {
26        "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
27        "EventCode": "0x4E",
28        "EventName": "HW_PRE_REQ.DL1_MISS",
29        "SampleAfterValue": "2000003",
30        "UMask": "0x2"
31    },
32    {
33        "BriefDescription": "Valid instructions written to IQ per cycle.",
34        "EventCode": "0x17",
35        "EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
36        "SampleAfterValue": "2000003",
37        "UMask": "0x1"
38    },
39    {
40        "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
41        "EventCode": "0x63",
42        "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
43        "SampleAfterValue": "2000003",
44        "UMask": "0x1"
45    }
46]
47